1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __CLK_STARFIVE_JH71X0_H
3 #define __CLK_STARFIVE_JH71X0_H
5 #include <linux/bits.h>
6 #include <linux/clk-provider.h>
7 #include <linux/device.h>
8 #include <linux/spinlock.h>
11 #define JH71X0_CLK_ENABLE BIT(31)
12 #define JH71X0_CLK_INVERT BIT(30)
13 #define JH71X0_CLK_MUX_MASK GENMASK(27, 24)
14 #define JH71X0_CLK_MUX_SHIFT 24
15 #define JH71X0_CLK_DIV_MASK GENMASK(23, 0)
16 #define JH71X0_CLK_FRAC_MASK GENMASK(15, 8)
17 #define JH71X0_CLK_FRAC_SHIFT 8
18 #define JH71X0_CLK_INT_MASK GENMASK(7, 0)
20 /* fractional divider min/max */
21 #define JH71X0_CLK_FRAC_MIN 100UL
22 #define JH71X0_CLK_FRAC_MAX 25599UL
25 struct jh71x0_clk_data {
32 #define JH71X0_GATE(_idx, _name, _flags, _parent) \
35 .flags = CLK_SET_RATE_PARENT | (_flags), \
36 .max = JH71X0_CLK_ENABLE, \
37 .parents = { [0] = _parent }, \
40 #define JH71X0__DIV(_idx, _name, _max, _parent) \
45 .parents = { [0] = _parent }, \
48 #define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \
52 .max = JH71X0_CLK_ENABLE | (_max), \
53 .parents = { [0] = _parent }, \
56 #define JH71X0_FDIV(_idx, _name, _parent) \
60 .max = JH71X0_CLK_FRAC_MAX, \
61 .parents = { [0] = _parent }, \
64 #define JH71X0__MUX(_idx, _name, _nparents, ...) \
68 .max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT, \
69 .parents = { __VA_ARGS__ }, \
72 #define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) \
76 .max = JH71X0_CLK_ENABLE | \
77 (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT), \
78 .parents = { __VA_ARGS__ }, \
81 #define JH71X0_MDIV(_idx, _name, _max, _nparents, ...) \
85 .max = (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
86 .parents = { __VA_ARGS__ }, \
89 #define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) \
93 .max = JH71X0_CLK_ENABLE | \
94 (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
95 .parents = { __VA_ARGS__ }, \
98 #define JH71X0__INV(_idx, _name, _parent) \
101 .flags = CLK_SET_RATE_PARENT, \
102 .max = JH71X0_CLK_INVERT, \
103 .parents = { [0] = _parent }, \
109 unsigned int max_div;
112 struct jh71x0_clk_priv {
113 /* protect clk enable and set rate/parent from happening at the same time */
117 struct clk_hw *pll[3];
118 struct jh71x0_clk reg[];
121 const struct clk_ops *starfive_jh71x0_clk_ops(u32 max);