1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * common clks module for all SiRF SoCs
5 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
12 #define MHZ (KHZ * KHZ)
14 static void __iomem *sirfsoc_clk_vbase;
15 static void __iomem *sirfsoc_rsc_vbase;
16 static struct clk_onecell_data clk_data;
19 * SiRFprimaII clock controller
20 * - 2 oscillators: osc-26MHz, rtc-32.768KHz
21 * - 3 standard configurable plls: pll1, pll2 & pll3
22 * - 2 exclusive plls: usb phy pll and sata phy pll
23 * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
25 * Each clock domain can select its own clock source from five clock sources,
26 * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
27 * clock of the group clock.
28 * - dsp domain: gps, mf
29 * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
30 * - sys domain: security
35 unsigned short regofs; /* register offset */
38 #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
42 signed char enable_bit; /* enable bit: 0 ~ 63 */
43 unsigned short regofs; /* register offset */
46 #define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
50 signed char enable_bit; /* enable bit: 0 ~ 63 */
53 #define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
55 static int std_clk_is_enabled(struct clk_hw *hw);
56 static int std_clk_enable(struct clk_hw *hw);
57 static void std_clk_disable(struct clk_hw *hw);
59 static inline unsigned long clkc_readl(unsigned reg)
61 return readl(sirfsoc_clk_vbase + reg);
64 static inline void clkc_writel(u32 val, unsigned reg)
66 writel(val, sirfsoc_clk_vbase + reg);
73 static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
74 unsigned long parent_rate)
76 unsigned long fin = parent_rate;
77 struct clk_pll *clk = to_pllclk(hw);
78 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
79 SIRFSOC_CLKC_PLL1_CFG0;
81 if (clkc_readl(regcfg2) & BIT(2)) {
85 /* fout = fin * nf / nr / od */
86 u32 cfg0 = clkc_readl(clk->regofs);
87 u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
88 u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
89 u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
91 return fin / MHZ * nf / nr / od * MHZ;
95 static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
96 unsigned long *parent_rate)
98 unsigned long fin, nf, nr, od;
102 * fout = fin * nf / (nr * od);
103 * set od = 1, nr = fin/MHz, so fout = nf * MHz
105 rate = rate - rate % MHZ;
120 dividend = (u64)fin * nf;
121 do_div(dividend, nr * od);
123 return (long)dividend;
126 static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
127 unsigned long parent_rate)
129 struct clk_pll *clk = to_pllclk(hw);
130 unsigned long fin, nf, nr, od, reg;
133 * fout = fin * nf / (nr * od);
134 * set od = 1, nr = fin/MHz, so fout = nf * MHz
138 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
145 BUG_ON((fin % MHZ) || nr > BIT(6));
149 reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
150 clkc_writel(reg, clk->regofs);
152 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
153 clkc_writel((nf >> 1) - 1, reg);
155 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
156 while (!(clkc_readl(reg) & BIT(6)))
162 static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
163 unsigned long *parent_rate)
166 * SiRF SoC has not cpu clock control,
167 * So bypass to it's parent pll.
169 struct clk_hw *parent_clk = clk_hw_get_parent(hw);
170 struct clk_hw *pll_parent_clk = clk_hw_get_parent(parent_clk);
171 unsigned long pll_parent_rate = clk_hw_get_rate(pll_parent_clk);
172 return pll_clk_round_rate(parent_clk, rate, &pll_parent_rate);
175 static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw,
176 unsigned long parent_rate)
179 * SiRF SoC has not cpu clock control,
180 * So return the parent pll rate.
182 struct clk_hw *parent_clk = clk_hw_get_parent(hw);
183 return clk_hw_get_rate(parent_clk);
186 static const struct clk_ops std_pll_ops = {
187 .recalc_rate = pll_clk_recalc_rate,
188 .round_rate = pll_clk_round_rate,
189 .set_rate = pll_clk_set_rate,
192 static const char * const pll_clk_parents[] = {
196 static const struct clk_init_data clk_pll1_init = {
199 .parent_names = pll_clk_parents,
200 .num_parents = ARRAY_SIZE(pll_clk_parents),
203 static const struct clk_init_data clk_pll2_init = {
206 .parent_names = pll_clk_parents,
207 .num_parents = ARRAY_SIZE(pll_clk_parents),
210 static const struct clk_init_data clk_pll3_init = {
213 .parent_names = pll_clk_parents,
214 .num_parents = ARRAY_SIZE(pll_clk_parents),
217 static struct clk_pll clk_pll1 = {
218 .regofs = SIRFSOC_CLKC_PLL1_CFG0,
220 .init = &clk_pll1_init,
224 static struct clk_pll clk_pll2 = {
225 .regofs = SIRFSOC_CLKC_PLL2_CFG0,
227 .init = &clk_pll2_init,
231 static struct clk_pll clk_pll3 = {
232 .regofs = SIRFSOC_CLKC_PLL3_CFG0,
234 .init = &clk_pll3_init,
239 * usb uses specified pll
242 static int usb_pll_clk_enable(struct clk_hw *hw)
244 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
245 reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
246 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
247 while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
248 SIRFSOC_USBPHY_PLL_LOCK))
254 static void usb_pll_clk_disable(struct clk_hw *clk)
256 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
257 reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
258 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
261 static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
263 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
264 return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
267 static const struct clk_ops usb_pll_ops = {
268 .enable = usb_pll_clk_enable,
269 .disable = usb_pll_clk_disable,
270 .recalc_rate = usb_pll_clk_recalc_rate,
273 static const struct clk_init_data clk_usb_pll_init = {
276 .parent_names = pll_clk_parents,
277 .num_parents = ARRAY_SIZE(pll_clk_parents),
280 static struct clk_hw usb_pll_clk_hw = {
281 .init = &clk_usb_pll_init,
285 * clock domains - cpu, mem, sys/io, dsp, gfx
288 static const char * const dmn_clk_parents[] = {
296 static u8 dmn_clk_get_parent(struct clk_hw *hw)
298 struct clk_dmn *clk = to_dmnclk(hw);
299 u32 cfg = clkc_readl(clk->regofs);
301 /* parent of io domain can only be pll3 */
302 if (strcmp(hw->init->name, "io") == 0)
305 WARN_ON((cfg & (BIT(3) - 1)) > 4);
307 return cfg & (BIT(3) - 1);
310 static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
312 struct clk_dmn *clk = to_dmnclk(hw);
313 u32 cfg = clkc_readl(clk->regofs);
315 /* parent of io domain can only be pll3 */
316 if (strcmp(hw->init->name, "io") == 0)
319 cfg &= ~(BIT(3) - 1);
320 clkc_writel(cfg | parent, clk->regofs);
321 /* BIT(3) - switching status: 1 - busy, 0 - done */
322 while (clkc_readl(clk->regofs) & BIT(3))
328 static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
329 unsigned long parent_rate)
332 unsigned long fin = parent_rate;
333 struct clk_dmn *clk = to_dmnclk(hw);
335 u32 cfg = clkc_readl(clk->regofs);
338 /* fcd bypass mode */
342 * wait count: bit[19:16], hold count: bit[23:20]
344 u32 wait = (cfg >> 16) & (BIT(4) - 1);
345 u32 hold = (cfg >> 20) & (BIT(4) - 1);
347 return fin / (wait + hold + 2);
351 static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
352 unsigned long *parent_rate)
355 unsigned ratio, wait, hold;
356 unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
363 if (ratio > BIT(bits + 1))
364 ratio = BIT(bits + 1);
366 wait = (ratio >> 1) - 1;
367 hold = ratio - wait - 2;
369 return fin / (wait + hold + 2);
372 static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
373 unsigned long parent_rate)
375 struct clk_dmn *clk = to_dmnclk(hw);
377 unsigned ratio, wait, hold, reg;
378 unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
383 if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
388 wait = (ratio >> 1) - 1;
389 hold = ratio - wait - 2;
391 reg = clkc_readl(clk->regofs);
392 reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
393 reg |= (wait << 16) | (hold << 20) | BIT(25);
394 clkc_writel(reg, clk->regofs);
396 /* waiting FCD been effective */
397 while (clkc_readl(clk->regofs) & BIT(25))
403 static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
404 unsigned long parent_rate)
407 struct clk *cur_parent;
409 if (rate == clk_get_rate(clk_pll1.hw.clk)) {
410 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
414 if (rate == clk_get_rate(clk_pll2.hw.clk)) {
415 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
419 if (rate == clk_get_rate(clk_pll3.hw.clk)) {
420 ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk);
424 cur_parent = clk_get_parent(hw->clk);
426 /* switch to tmp pll before setting parent clock's rate */
427 if (cur_parent == clk_pll1.hw.clk) {
428 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
432 ret2 = clk_set_rate(clk_pll1.hw.clk, rate);
434 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
436 return ret2 ? ret2 : ret1;
439 static const struct clk_ops msi_ops = {
440 .set_rate = dmn_clk_set_rate,
441 .round_rate = dmn_clk_round_rate,
442 .recalc_rate = dmn_clk_recalc_rate,
443 .set_parent = dmn_clk_set_parent,
444 .get_parent = dmn_clk_get_parent,
447 static const struct clk_init_data clk_mem_init = {
450 .parent_names = dmn_clk_parents,
451 .num_parents = ARRAY_SIZE(dmn_clk_parents),
454 static struct clk_dmn clk_mem = {
455 .regofs = SIRFSOC_CLKC_MEM_CFG,
457 .init = &clk_mem_init,
461 static const struct clk_init_data clk_sys_init = {
464 .parent_names = dmn_clk_parents,
465 .num_parents = ARRAY_SIZE(dmn_clk_parents),
466 .flags = CLK_SET_RATE_GATE,
469 static struct clk_dmn clk_sys = {
470 .regofs = SIRFSOC_CLKC_SYS_CFG,
472 .init = &clk_sys_init,
476 static const struct clk_init_data clk_io_init = {
479 .parent_names = dmn_clk_parents,
480 .num_parents = ARRAY_SIZE(dmn_clk_parents),
483 static struct clk_dmn clk_io = {
484 .regofs = SIRFSOC_CLKC_IO_CFG,
486 .init = &clk_io_init,
490 static const struct clk_ops cpu_ops = {
491 .set_parent = dmn_clk_set_parent,
492 .get_parent = dmn_clk_get_parent,
493 .set_rate = cpu_clk_set_rate,
494 .round_rate = cpu_clk_round_rate,
495 .recalc_rate = cpu_clk_recalc_rate,
498 static const struct clk_init_data clk_cpu_init = {
501 .parent_names = dmn_clk_parents,
502 .num_parents = ARRAY_SIZE(dmn_clk_parents),
503 .flags = CLK_SET_RATE_PARENT,
506 static struct clk_dmn clk_cpu = {
507 .regofs = SIRFSOC_CLKC_CPU_CFG,
509 .init = &clk_cpu_init,
513 static const struct clk_ops dmn_ops = {
514 .is_enabled = std_clk_is_enabled,
515 .enable = std_clk_enable,
516 .disable = std_clk_disable,
517 .set_rate = dmn_clk_set_rate,
518 .round_rate = dmn_clk_round_rate,
519 .recalc_rate = dmn_clk_recalc_rate,
520 .set_parent = dmn_clk_set_parent,
521 .get_parent = dmn_clk_get_parent,
524 /* dsp, gfx, mm, lcd and vpp domain */
526 static const struct clk_init_data clk_dsp_init = {
529 .parent_names = dmn_clk_parents,
530 .num_parents = ARRAY_SIZE(dmn_clk_parents),
533 static struct clk_dmn clk_dsp = {
534 .regofs = SIRFSOC_CLKC_DSP_CFG,
537 .init = &clk_dsp_init,
541 static const struct clk_init_data clk_gfx_init = {
544 .parent_names = dmn_clk_parents,
545 .num_parents = ARRAY_SIZE(dmn_clk_parents),
548 static struct clk_dmn clk_gfx = {
549 .regofs = SIRFSOC_CLKC_GFX_CFG,
552 .init = &clk_gfx_init,
556 static const struct clk_init_data clk_mm_init = {
559 .parent_names = dmn_clk_parents,
560 .num_parents = ARRAY_SIZE(dmn_clk_parents),
563 static struct clk_dmn clk_mm = {
564 .regofs = SIRFSOC_CLKC_MM_CFG,
567 .init = &clk_mm_init,
572 * for atlas6, gfx2d holds the bit of prima2's clk_mm
574 #define clk_gfx2d clk_mm
576 static const struct clk_init_data clk_lcd_init = {
579 .parent_names = dmn_clk_parents,
580 .num_parents = ARRAY_SIZE(dmn_clk_parents),
583 static struct clk_dmn clk_lcd = {
584 .regofs = SIRFSOC_CLKC_LCD_CFG,
587 .init = &clk_lcd_init,
591 static const struct clk_init_data clk_vpp_init = {
594 .parent_names = dmn_clk_parents,
595 .num_parents = ARRAY_SIZE(dmn_clk_parents),
598 static struct clk_dmn clk_vpp = {
599 .regofs = SIRFSOC_CLKC_LCD_CFG,
602 .init = &clk_vpp_init,
606 static const struct clk_init_data clk_mmc01_init = {
609 .parent_names = dmn_clk_parents,
610 .num_parents = ARRAY_SIZE(dmn_clk_parents),
613 static const struct clk_init_data clk_mmc23_init = {
616 .parent_names = dmn_clk_parents,
617 .num_parents = ARRAY_SIZE(dmn_clk_parents),
620 static const struct clk_init_data clk_mmc45_init = {
623 .parent_names = dmn_clk_parents,
624 .num_parents = ARRAY_SIZE(dmn_clk_parents),
628 * peripheral controllers in io domain
631 static int std_clk_is_enabled(struct clk_hw *hw)
635 struct clk_std *clk = to_stdclk(hw);
637 bit = clk->enable_bit % 32;
638 reg = clk->enable_bit / 32;
639 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
641 return !!(clkc_readl(reg) & BIT(bit));
644 static int std_clk_enable(struct clk_hw *hw)
648 struct clk_std *clk = to_stdclk(hw);
650 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
652 bit = clk->enable_bit % 32;
653 reg = clk->enable_bit / 32;
654 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
656 val = clkc_readl(reg) | BIT(bit);
657 clkc_writel(val, reg);
661 static void std_clk_disable(struct clk_hw *hw)
665 struct clk_std *clk = to_stdclk(hw);
667 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
669 bit = clk->enable_bit % 32;
670 reg = clk->enable_bit / 32;
671 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
673 val = clkc_readl(reg) & ~BIT(bit);
674 clkc_writel(val, reg);
677 static const char * const std_clk_io_parents[] = {
681 static const struct clk_ops ios_ops = {
682 .is_enabled = std_clk_is_enabled,
683 .enable = std_clk_enable,
684 .disable = std_clk_disable,
687 static const struct clk_init_data clk_cphif_init = {
690 .parent_names = std_clk_io_parents,
691 .num_parents = ARRAY_SIZE(std_clk_io_parents),
694 static struct clk_std clk_cphif = {
697 .init = &clk_cphif_init,
701 static const struct clk_init_data clk_dmac0_init = {
704 .parent_names = std_clk_io_parents,
705 .num_parents = ARRAY_SIZE(std_clk_io_parents),
708 static struct clk_std clk_dmac0 = {
711 .init = &clk_dmac0_init,
715 static const struct clk_init_data clk_dmac1_init = {
718 .parent_names = std_clk_io_parents,
719 .num_parents = ARRAY_SIZE(std_clk_io_parents),
722 static struct clk_std clk_dmac1 = {
725 .init = &clk_dmac1_init,
729 static const struct clk_init_data clk_audio_init = {
732 .parent_names = std_clk_io_parents,
733 .num_parents = ARRAY_SIZE(std_clk_io_parents),
736 static struct clk_std clk_audio = {
739 .init = &clk_audio_init,
743 static const struct clk_init_data clk_uart0_init = {
746 .parent_names = std_clk_io_parents,
747 .num_parents = ARRAY_SIZE(std_clk_io_parents),
750 static struct clk_std clk_uart0 = {
753 .init = &clk_uart0_init,
757 static const struct clk_init_data clk_uart1_init = {
760 .parent_names = std_clk_io_parents,
761 .num_parents = ARRAY_SIZE(std_clk_io_parents),
764 static struct clk_std clk_uart1 = {
767 .init = &clk_uart1_init,
771 static const struct clk_init_data clk_uart2_init = {
774 .parent_names = std_clk_io_parents,
775 .num_parents = ARRAY_SIZE(std_clk_io_parents),
778 static struct clk_std clk_uart2 = {
781 .init = &clk_uart2_init,
785 static const struct clk_init_data clk_usp0_init = {
788 .parent_names = std_clk_io_parents,
789 .num_parents = ARRAY_SIZE(std_clk_io_parents),
792 static struct clk_std clk_usp0 = {
795 .init = &clk_usp0_init,
799 static const struct clk_init_data clk_usp1_init = {
802 .parent_names = std_clk_io_parents,
803 .num_parents = ARRAY_SIZE(std_clk_io_parents),
806 static struct clk_std clk_usp1 = {
809 .init = &clk_usp1_init,
813 static const struct clk_init_data clk_usp2_init = {
816 .parent_names = std_clk_io_parents,
817 .num_parents = ARRAY_SIZE(std_clk_io_parents),
820 static struct clk_std clk_usp2 = {
823 .init = &clk_usp2_init,
827 static const struct clk_init_data clk_vip_init = {
830 .parent_names = std_clk_io_parents,
831 .num_parents = ARRAY_SIZE(std_clk_io_parents),
834 static struct clk_std clk_vip = {
837 .init = &clk_vip_init,
841 static const struct clk_init_data clk_spi0_init = {
844 .parent_names = std_clk_io_parents,
845 .num_parents = ARRAY_SIZE(std_clk_io_parents),
848 static struct clk_std clk_spi0 = {
851 .init = &clk_spi0_init,
855 static const struct clk_init_data clk_spi1_init = {
858 .parent_names = std_clk_io_parents,
859 .num_parents = ARRAY_SIZE(std_clk_io_parents),
862 static struct clk_std clk_spi1 = {
865 .init = &clk_spi1_init,
869 static const struct clk_init_data clk_tsc_init = {
872 .parent_names = std_clk_io_parents,
873 .num_parents = ARRAY_SIZE(std_clk_io_parents),
876 static struct clk_std clk_tsc = {
879 .init = &clk_tsc_init,
883 static const struct clk_init_data clk_i2c0_init = {
886 .parent_names = std_clk_io_parents,
887 .num_parents = ARRAY_SIZE(std_clk_io_parents),
890 static struct clk_std clk_i2c0 = {
893 .init = &clk_i2c0_init,
897 static const struct clk_init_data clk_i2c1_init = {
900 .parent_names = std_clk_io_parents,
901 .num_parents = ARRAY_SIZE(std_clk_io_parents),
904 static struct clk_std clk_i2c1 = {
907 .init = &clk_i2c1_init,
911 static const struct clk_init_data clk_pwmc_init = {
914 .parent_names = std_clk_io_parents,
915 .num_parents = ARRAY_SIZE(std_clk_io_parents),
918 static struct clk_std clk_pwmc = {
921 .init = &clk_pwmc_init,
925 static const struct clk_init_data clk_efuse_init = {
928 .parent_names = std_clk_io_parents,
929 .num_parents = ARRAY_SIZE(std_clk_io_parents),
932 static struct clk_std clk_efuse = {
935 .init = &clk_efuse_init,
939 static const struct clk_init_data clk_pulse_init = {
942 .parent_names = std_clk_io_parents,
943 .num_parents = ARRAY_SIZE(std_clk_io_parents),
946 static struct clk_std clk_pulse = {
949 .init = &clk_pulse_init,
953 static const char * const std_clk_dsp_parents[] = {
957 static const struct clk_init_data clk_gps_init = {
960 .parent_names = std_clk_dsp_parents,
961 .num_parents = ARRAY_SIZE(std_clk_dsp_parents),
964 static struct clk_std clk_gps = {
967 .init = &clk_gps_init,
971 static const struct clk_init_data clk_mf_init = {
974 .parent_names = std_clk_io_parents,
975 .num_parents = ARRAY_SIZE(std_clk_io_parents),
978 static struct clk_std clk_mf = {
981 .init = &clk_mf_init,
985 static const char * const std_clk_sys_parents[] = {
989 static const struct clk_init_data clk_security_init = {
992 .parent_names = std_clk_sys_parents,
993 .num_parents = ARRAY_SIZE(std_clk_sys_parents),
996 static struct clk_std clk_security = {
999 .init = &clk_security_init,
1003 static const char * const std_clk_usb_parents[] = {
1007 static const struct clk_init_data clk_usb0_init = {
1010 .parent_names = std_clk_usb_parents,
1011 .num_parents = ARRAY_SIZE(std_clk_usb_parents),
1014 static struct clk_std clk_usb0 = {
1017 .init = &clk_usb0_init,
1021 static const struct clk_init_data clk_usb1_init = {
1024 .parent_names = std_clk_usb_parents,
1025 .num_parents = ARRAY_SIZE(std_clk_usb_parents),
1028 static struct clk_std clk_usb1 = {
1031 .init = &clk_usb1_init,