1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2018-2019 SiFive, Inc.
9 #ifndef __SIFIVE_CLK_SIFIVE_PRCI_H
10 #define __SIFIVE_CLK_SIFIVE_PRCI_H
12 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
17 * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
20 #define EXPECTED_CLK_PARENT_COUNT 2
23 * Register offsets and bitmasks
27 #define PRCI_COREPLLCFG0_OFFSET 0x4
28 #define PRCI_COREPLLCFG0_DIVR_SHIFT 0
29 #define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
30 #define PRCI_COREPLLCFG0_DIVF_SHIFT 6
31 #define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
32 #define PRCI_COREPLLCFG0_DIVQ_SHIFT 15
33 #define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
34 #define PRCI_COREPLLCFG0_RANGE_SHIFT 18
35 #define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
36 #define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
37 #define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
38 #define PRCI_COREPLLCFG0_FSE_SHIFT 25
39 #define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
40 #define PRCI_COREPLLCFG0_LOCK_SHIFT 31
41 #define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
44 #define PRCI_COREPLLCFG1_OFFSET 0x8
45 #define PRCI_COREPLLCFG1_CKE_SHIFT 31
46 #define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
49 #define PRCI_DDRPLLCFG0_OFFSET 0xc
50 #define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
51 #define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
52 #define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
53 #define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
54 #define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
55 #define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
56 #define PRCI_DDRPLLCFG0_RANGE_SHIFT 18
57 #define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
58 #define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24
59 #define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
60 #define PRCI_DDRPLLCFG0_FSE_SHIFT 25
61 #define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
62 #define PRCI_DDRPLLCFG0_LOCK_SHIFT 31
63 #define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT)
66 #define PRCI_DDRPLLCFG1_OFFSET 0x10
67 #define PRCI_DDRPLLCFG1_CKE_SHIFT 31
68 #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
71 #define PRCI_PCIE_AUX_OFFSET 0x14
72 #define PRCI_PCIE_AUX_EN_SHIFT 0
73 #define PRCI_PCIE_AUX_EN_MASK (0x1 << PRCI_PCIE_AUX_EN_SHIFT)
76 #define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c
77 #define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
78 #define PRCI_GEMGXLPLLCFG0_DIVR_MASK (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT)
79 #define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6
80 #define PRCI_GEMGXLPLLCFG0_DIVF_MASK (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT)
81 #define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15
82 #define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT)
83 #define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18
84 #define PRCI_GEMGXLPLLCFG0_RANGE_MASK (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT)
85 #define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24
86 #define PRCI_GEMGXLPLLCFG0_BYPASS_MASK (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT)
87 #define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25
88 #define PRCI_GEMGXLPLLCFG0_FSE_MASK (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT)
89 #define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31
90 #define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT)
93 #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
94 #define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
95 #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
98 #define PRCI_CORECLKSEL_OFFSET 0x24
99 #define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0
100 #define PRCI_CORECLKSEL_CORECLKSEL_MASK \
101 (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT)
103 /* DEVICESRESETREG */
104 #define PRCI_DEVICESRESETREG_OFFSET 0x28
105 #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0
106 #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \
107 (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT)
108 #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1
109 #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \
110 (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT)
111 #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2
112 #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \
113 (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT)
114 #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3
115 #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \
116 (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT)
117 #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5
118 #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \
119 (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
120 #define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT 6
121 #define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \
122 (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT)
124 /* CLKMUXSTATUSREG */
125 #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
126 #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
127 #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
128 (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
131 #define PRCI_CLTXPLLCFG0_OFFSET 0x30
132 #define PRCI_CLTXPLLCFG0_DIVR_SHIFT 0
133 #define PRCI_CLTXPLLCFG0_DIVR_MASK (0x3f << PRCI_CLTXPLLCFG0_DIVR_SHIFT)
134 #define PRCI_CLTXPLLCFG0_DIVF_SHIFT 6
135 #define PRCI_CLTXPLLCFG0_DIVF_MASK (0x1ff << PRCI_CLTXPLLCFG0_DIVF_SHIFT)
136 #define PRCI_CLTXPLLCFG0_DIVQ_SHIFT 15
137 #define PRCI_CLTXPLLCFG0_DIVQ_MASK (0x7 << PRCI_CLTXPLLCFG0_DIVQ_SHIFT)
138 #define PRCI_CLTXPLLCFG0_RANGE_SHIFT 18
139 #define PRCI_CLTXPLLCFG0_RANGE_MASK (0x7 << PRCI_CLTXPLLCFG0_RANGE_SHIFT)
140 #define PRCI_CLTXPLLCFG0_BYPASS_SHIFT 24
141 #define PRCI_CLTXPLLCFG0_BYPASS_MASK (0x1 << PRCI_CLTXPLLCFG0_BYPASS_SHIFT)
142 #define PRCI_CLTXPLLCFG0_FSE_SHIFT 25
143 #define PRCI_CLTXPLLCFG0_FSE_MASK (0x1 << PRCI_CLTXPLLCFG0_FSE_SHIFT)
144 #define PRCI_CLTXPLLCFG0_LOCK_SHIFT 31
145 #define PRCI_CLTXPLLCFG0_LOCK_MASK (0x1 << PRCI_CLTXPLLCFG0_LOCK_SHIFT)
148 #define PRCI_CLTXPLLCFG1_OFFSET 0x34
149 #define PRCI_CLTXPLLCFG1_CKE_SHIFT 31
150 #define PRCI_CLTXPLLCFG1_CKE_MASK (0x1 << PRCI_CLTXPLLCFG1_CKE_SHIFT)
152 /* DVFSCOREPLLCFG0 */
153 #define PRCI_DVFSCOREPLLCFG0_OFFSET 0x38
155 /* DVFSCOREPLLCFG1 */
156 #define PRCI_DVFSCOREPLLCFG1_OFFSET 0x3c
157 #define PRCI_DVFSCOREPLLCFG1_CKE_SHIFT 31
158 #define PRCI_DVFSCOREPLLCFG1_CKE_MASK (0x1 << PRCI_DVFSCOREPLLCFG1_CKE_SHIFT)
161 #define PRCI_COREPLLSEL_OFFSET 0x40
162 #define PRCI_COREPLLSEL_COREPLLSEL_SHIFT 0
163 #define PRCI_COREPLLSEL_COREPLLSEL_MASK \
164 (0x1 << PRCI_COREPLLSEL_COREPLLSEL_SHIFT)
167 #define PRCI_HFPCLKPLLCFG0_OFFSET 0x50
168 #define PRCI_HFPCLKPLL_CFG0_DIVR_SHIFT 0
169 #define PRCI_HFPCLKPLL_CFG0_DIVR_MASK \
170 (0x3f << PRCI_HFPCLKPLLCFG0_DIVR_SHIFT)
171 #define PRCI_HFPCLKPLL_CFG0_DIVF_SHIFT 6
172 #define PRCI_HFPCLKPLL_CFG0_DIVF_MASK \
173 (0x1ff << PRCI_HFPCLKPLLCFG0_DIVF_SHIFT)
174 #define PRCI_HFPCLKPLL_CFG0_DIVQ_SHIFT 15
175 #define PRCI_HFPCLKPLL_CFG0_DIVQ_MASK \
176 (0x7 << PRCI_HFPCLKPLLCFG0_DIVQ_SHIFT)
177 #define PRCI_HFPCLKPLL_CFG0_RANGE_SHIFT 18
178 #define PRCI_HFPCLKPLL_CFG0_RANGE_MASK \
179 (0x7 << PRCI_HFPCLKPLLCFG0_RANGE_SHIFT)
180 #define PRCI_HFPCLKPLL_CFG0_BYPASS_SHIFT 24
181 #define PRCI_HFPCLKPLL_CFG0_BYPASS_MASK \
182 (0x1 << PRCI_HFPCLKPLLCFG0_BYPASS_SHIFT)
183 #define PRCI_HFPCLKPLL_CFG0_FSE_SHIFT 25
184 #define PRCI_HFPCLKPLL_CFG0_FSE_MASK \
185 (0x1 << PRCI_HFPCLKPLLCFG0_FSE_SHIFT)
186 #define PRCI_HFPCLKPLL_CFG0_LOCK_SHIFT 31
187 #define PRCI_HFPCLKPLL_CFG0_LOCK_MASK \
188 (0x1 << PRCI_HFPCLKPLLCFG0_LOCK_SHIFT)
191 #define PRCI_HFPCLKPLLCFG1_OFFSET 0x54
192 #define PRCI_HFPCLKPLLCFG1_CKE_SHIFT 31
193 #define PRCI_HFPCLKPLLCFG1_CKE_MASK \
194 (0x1 << PRCI_HFPCLKPLLCFG1_CKE_SHIFT)
197 #define PRCI_HFPCLKPLLSEL_OFFSET 0x58
198 #define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT 0
199 #define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK \
200 (0x1 << PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT)
203 #define PRCI_HFPCLKPLLDIV_OFFSET 0x5c
206 #define PRCI_PRCIPLL_OFFSET 0xe0
209 #define PRCI_PROCMONCFG_OFFSET 0xf0
216 * struct __prci_data - per-device-instance data
217 * @va: base virtual address of the PRCI IP block
218 * @hw_clks: encapsulates struct clk_hw records
220 * PRCI per-device instance data
224 struct clk_hw_onecell_data hw_clks;
228 * struct __prci_wrpll_data - WRPLL configuration and integration data
229 * @c: WRPLL current configuration record
230 * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
231 * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
232 * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
233 * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address
235 * @enable_bypass and @disable_bypass are used for WRPLL instances
236 * that contain a separate external glitchless clock mux downstream
237 * from the PLL. The WRPLL internal bypass mux is not glitchless.
239 struct __prci_wrpll_data {
241 void (*enable_bypass)(struct __prci_data *pd);
242 void (*disable_bypass)(struct __prci_data *pd);
248 * struct __prci_clock - describes a clock device managed by PRCI
249 * @name: user-readable clock name string - should match the manual
250 * @parent_name: parent name for this clock
251 * @ops: struct clk_ops for the Linux clock framework to use for control
252 * @hw: Linux-private clock data
253 * @pwd: WRPLL-specific data, associated with this clock (if not NULL)
254 * @pd: PRCI-specific data associated with this clock (if not NULL)
256 * PRCI clock data. Used by the PRCI driver to register PRCI-provided
257 * clocks to the Linux clock infrastructure.
259 struct __prci_clock {
261 const char *parent_name;
262 const struct clk_ops *ops;
264 struct __prci_wrpll_data *pwd;
265 struct __prci_data *pd;
268 #define clk_hw_to_prci_clock(pwd) container_of(pwd, struct __prci_clock, hw)
271 * struct prci_clk_desc - describes the information of clocks of each SoCs
272 * @clks: point to a array of __prci_clock
273 * @num_clks: the number of element of clks
275 struct prci_clk_desc {
276 struct __prci_clock *clks;
280 /* Core clock mux control */
281 void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd);
282 void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd);
283 void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd);
284 void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd);
285 void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd);
286 void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd);
287 void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd);
289 /* Linux clock framework integration */
290 long sifive_prci_wrpll_round_rate(struct clk_hw *hw, unsigned long rate,
291 unsigned long *parent_rate);
292 int sifive_prci_wrpll_set_rate(struct clk_hw *hw, unsigned long rate,
293 unsigned long parent_rate);
294 int sifive_clk_is_enabled(struct clk_hw *hw);
295 int sifive_prci_clock_enable(struct clk_hw *hw);
296 void sifive_prci_clock_disable(struct clk_hw *hw);
297 unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw,
298 unsigned long parent_rate);
299 unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw,
300 unsigned long parent_rate);
301 unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw,
302 unsigned long parent_rate);
304 int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw);
305 int sifive_prci_pcie_aux_clock_enable(struct clk_hw *hw);
306 void sifive_prci_pcie_aux_clock_disable(struct clk_hw *hw);
308 #endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */