1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * The FU540 PRCI implements clock and reset control for the SiFive
17 * FU540-C000 chip. This driver assumes that it has sole control
18 * over all PRCI resources.
20 * This driver is based on the PRCI driver written by Wesley Terpstra:
21 * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
24 * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
27 #include <dt-bindings/clock/sifive-fu540-prci.h>
28 #include <linux/clkdev.h>
29 #include <linux/clk-provider.h>
30 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
31 #include <linux/delay.h>
32 #include <linux/err.h>
33 #include <linux/module.h>
35 #include <linux/of_clk.h>
36 #include <linux/platform_device.h>
37 #include <linux/slab.h>
40 * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
43 #define EXPECTED_CLK_PARENT_COUNT 2
46 * Register offsets and bitmasks
50 #define PRCI_COREPLLCFG0_OFFSET 0x4
51 # define PRCI_COREPLLCFG0_DIVR_SHIFT 0
52 # define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
53 # define PRCI_COREPLLCFG0_DIVF_SHIFT 6
54 # define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
55 # define PRCI_COREPLLCFG0_DIVQ_SHIFT 15
56 # define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
57 # define PRCI_COREPLLCFG0_RANGE_SHIFT 18
58 # define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
59 # define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
60 # define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
61 # define PRCI_COREPLLCFG0_FSE_SHIFT 25
62 # define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
63 # define PRCI_COREPLLCFG0_LOCK_SHIFT 31
64 # define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
67 #define PRCI_DDRPLLCFG0_OFFSET 0xc
68 # define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
69 # define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
70 # define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
71 # define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
72 # define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
73 # define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
74 # define PRCI_DDRPLLCFG0_RANGE_SHIFT 18
75 # define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
76 # define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24
77 # define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
78 # define PRCI_DDRPLLCFG0_FSE_SHIFT 25
79 # define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
80 # define PRCI_DDRPLLCFG0_LOCK_SHIFT 31
81 # define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT)
84 #define PRCI_DDRPLLCFG1_OFFSET 0x10
85 # define PRCI_DDRPLLCFG1_CKE_SHIFT 24
86 # define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
89 #define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c
90 # define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
91 # define PRCI_GEMGXLPLLCFG0_DIVR_MASK (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT)
92 # define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6
93 # define PRCI_GEMGXLPLLCFG0_DIVF_MASK (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT)
94 # define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15
95 # define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT)
96 # define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18
97 # define PRCI_GEMGXLPLLCFG0_RANGE_MASK (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT)
98 # define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24
99 # define PRCI_GEMGXLPLLCFG0_BYPASS_MASK (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT)
100 # define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25
101 # define PRCI_GEMGXLPLLCFG0_FSE_MASK (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT)
102 # define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31
103 # define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT)
106 #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
107 # define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24
108 # define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
111 #define PRCI_CORECLKSEL_OFFSET 0x24
112 # define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0
113 # define PRCI_CORECLKSEL_CORECLKSEL_MASK (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT)
115 /* DEVICESRESETREG */
116 #define PRCI_DEVICESRESETREG_OFFSET 0x28
117 # define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0
118 # define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT)
119 # define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1
120 # define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT)
121 # define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2
122 # define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT)
123 # define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3
124 # define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT)
125 # define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5
126 # define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
128 /* CLKMUXSTATUSREG */
129 #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
130 # define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
131 # define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
138 * struct __prci_data - per-device-instance data
139 * @va: base virtual address of the PRCI IP block
140 * @hw_clks: encapsulates struct clk_hw records
142 * PRCI per-device instance data
146 struct clk_hw_onecell_data hw_clks;
150 * struct __prci_wrpll_data - WRPLL configuration and integration data
151 * @c: WRPLL current configuration record
152 * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
153 * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
154 * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
156 * @enable_bypass and @disable_bypass are used for WRPLL instances
157 * that contain a separate external glitchless clock mux downstream
158 * from the PLL. The WRPLL internal bypass mux is not glitchless.
160 struct __prci_wrpll_data {
162 void (*enable_bypass)(struct __prci_data *pd);
163 void (*disable_bypass)(struct __prci_data *pd);
168 * struct __prci_clock - describes a clock device managed by PRCI
169 * @name: user-readable clock name string - should match the manual
170 * @parent_name: parent name for this clock
171 * @ops: struct clk_ops for the Linux clock framework to use for control
172 * @hw: Linux-private clock data
173 * @pwd: WRPLL-specific data, associated with this clock (if not NULL)
174 * @pd: PRCI-specific data associated with this clock (if not NULL)
176 * PRCI clock data. Used by the PRCI driver to register PRCI-provided
177 * clocks to the Linux clock infrastructure.
179 struct __prci_clock {
181 const char *parent_name;
182 const struct clk_ops *ops;
184 struct __prci_wrpll_data *pwd;
185 struct __prci_data *pd;
188 #define clk_hw_to_prci_clock(pwd) container_of(pwd, struct __prci_clock, hw)
195 * __prci_readl() - read from a PRCI register
197 * @offs: register offset to read from (in bytes, from PRCI base address)
199 * Read the register located at offset @offs from the base virtual
200 * address of the PRCI register target described by @pd, and return
201 * the value to the caller.
203 * Context: Any context.
205 * Return: the contents of the register described by @pd and @offs.
207 static u32 __prci_readl(struct __prci_data *pd, u32 offs)
209 return readl_relaxed(pd->va + offs);
212 static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
214 writel_relaxed(v, pd->va + offs);
217 /* WRPLL-related private functions */
220 * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
221 * @c: ptr to a struct wrpll_cfg record to write config into
222 * @r: value read from the PRCI PLL configuration register
224 * Given a value @r read from an FU540 PRCI PLL configuration register,
225 * split it into fields and populate it into the WRPLL configuration record
228 * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros
229 * have the same register layout.
231 * Context: Any context.
233 static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
237 v = r & PRCI_COREPLLCFG0_DIVR_MASK;
238 v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
241 v = r & PRCI_COREPLLCFG0_DIVF_MASK;
242 v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
245 v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
246 v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
249 v = r & PRCI_COREPLLCFG0_RANGE_MASK;
250 v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
253 c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |
254 WRPLL_FLAGS_EXT_FEEDBACK_MASK);
256 /* external feedback mode not supported */
257 c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
261 * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
262 * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
264 * Using a set of WRPLL configuration values pointed to by @c,
265 * assemble a PRCI PLL configuration register value, and return it to
268 * Context: Any context. Caller must ensure that the contents of the
269 * record pointed to by @c do not change during the execution
272 * Returns: a value suitable for writing into a PRCI PLL configuration
275 static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
279 r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;
280 r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
281 r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
282 r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
284 /* external feedback mode not supported */
285 r |= PRCI_COREPLLCFG0_FSE_MASK;
291 * __prci_wrpll_read_cfg() - read the WRPLL configuration from the PRCI
293 * @pwd: PRCI WRPLL metadata
295 * Read the current configuration of the PLL identified by @pwd from
296 * the PRCI identified by @pd, and store it into the local configuration
299 * Context: Any context. Caller must prevent the records pointed to by
300 * @pd and @pwd from changing during execution.
302 static void __prci_wrpll_read_cfg(struct __prci_data *pd,
303 struct __prci_wrpll_data *pwd)
305 __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
309 * __prci_wrpll_write_cfg() - write WRPLL configuration into the PRCI
311 * @pwd: PRCI WRPLL metadata
312 * @c: WRPLL configuration record to write
314 * Write the WRPLL configuration described by @c into the WRPLL
315 * configuration register identified by @pwd in the PRCI instance
316 * described by @c. Make a cached copy of the WRPLL's current
317 * configuration so it can be used by other code.
319 * Context: Any context. Caller must prevent the records pointed to by
320 * @pd and @pwd from changing during execution.
322 static void __prci_wrpll_write_cfg(struct __prci_data *pd,
323 struct __prci_wrpll_data *pwd,
326 __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
328 memcpy(&pwd->c, c, sizeof(*c));
331 /* Core clock mux control */
334 * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
335 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
337 * Switch the CORECLK mux to the HFCLK input source; return once complete.
339 * Context: Any context. Caller must prevent concurrent changes to the
340 * PRCI_CORECLKSEL_OFFSET register.
342 static void __prci_coreclksel_use_hfclk(struct __prci_data *pd)
346 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
347 r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;
348 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
350 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
354 * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
355 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
357 * Switch the CORECLK mux to the PLL output clock; return once complete.
359 * Context: Any context. Caller must prevent concurrent changes to the
360 * PRCI_CORECLKSEL_OFFSET register.
362 static void __prci_coreclksel_use_corepll(struct __prci_data *pd)
366 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
367 r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
368 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
370 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
374 * Linux clock framework integration
376 * See the Linux clock framework documentation for more information on
380 static unsigned long sifive_fu540_prci_wrpll_recalc_rate(struct clk_hw *hw,
381 unsigned long parent_rate)
383 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
384 struct __prci_wrpll_data *pwd = pc->pwd;
386 return wrpll_calc_output_rate(&pwd->c, parent_rate);
389 static long sifive_fu540_prci_wrpll_round_rate(struct clk_hw *hw,
391 unsigned long *parent_rate)
393 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
394 struct __prci_wrpll_data *pwd = pc->pwd;
397 memcpy(&c, &pwd->c, sizeof(c));
399 wrpll_configure_for_rate(&c, rate, *parent_rate);
401 return wrpll_calc_output_rate(&c, *parent_rate);
404 static int sifive_fu540_prci_wrpll_set_rate(struct clk_hw *hw,
406 unsigned long parent_rate)
408 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
409 struct __prci_wrpll_data *pwd = pc->pwd;
410 struct __prci_data *pd = pc->pd;
413 r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
417 if (pwd->enable_bypass)
418 pwd->enable_bypass(pd);
420 __prci_wrpll_write_cfg(pd, pwd, &pwd->c);
422 udelay(wrpll_calc_max_lock_us(&pwd->c));
424 if (pwd->disable_bypass)
425 pwd->disable_bypass(pd);
430 static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = {
431 .set_rate = sifive_fu540_prci_wrpll_set_rate,
432 .round_rate = sifive_fu540_prci_wrpll_round_rate,
433 .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
436 static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
437 .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
440 /* TLCLKSEL clock integration */
442 static unsigned long sifive_fu540_prci_tlclksel_recalc_rate(struct clk_hw *hw,
443 unsigned long parent_rate)
445 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
446 struct __prci_data *pd = pc->pd;
450 v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
451 v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
454 return div_u64(parent_rate, div);
457 static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = {
458 .recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate,
462 * PRCI integration data for each WRPLL instance
465 static struct __prci_wrpll_data __prci_corepll_data = {
466 .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
467 .enable_bypass = __prci_coreclksel_use_hfclk,
468 .disable_bypass = __prci_coreclksel_use_corepll,
471 static struct __prci_wrpll_data __prci_ddrpll_data = {
472 .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
475 static struct __prci_wrpll_data __prci_gemgxlpll_data = {
476 .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
480 * List of clock controls provided by the PRCI
483 static struct __prci_clock __prci_init_clocks[] = {
484 [PRCI_CLK_COREPLL] = {
486 .parent_name = "hfclk",
487 .ops = &sifive_fu540_prci_wrpll_clk_ops,
488 .pwd = &__prci_corepll_data,
490 [PRCI_CLK_DDRPLL] = {
492 .parent_name = "hfclk",
493 .ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
494 .pwd = &__prci_ddrpll_data,
496 [PRCI_CLK_GEMGXLPLL] = {
498 .parent_name = "hfclk",
499 .ops = &sifive_fu540_prci_wrpll_clk_ops,
500 .pwd = &__prci_gemgxlpll_data,
504 .parent_name = "corepll",
505 .ops = &sifive_fu540_prci_tlclksel_clk_ops,
510 * __prci_register_clocks() - register clock controls in the PRCI with Linux
511 * @dev: Linux struct device *
513 * Register the list of clock controls described in __prci_init_plls[] with
514 * the Linux clock framework.
516 * Return: 0 upon success or a negative error code upon failure.
518 static int __prci_register_clocks(struct device *dev, struct __prci_data *pd)
520 struct clk_init_data init = { };
521 struct __prci_clock *pic;
522 int parent_count, i, r;
524 parent_count = of_clk_get_parent_count(dev->of_node);
525 if (parent_count != EXPECTED_CLK_PARENT_COUNT) {
526 dev_err(dev, "expected only two parent clocks, found %d\n",
532 for (i = 0; i < ARRAY_SIZE(__prci_init_clocks); ++i) {
533 pic = &__prci_init_clocks[i];
535 init.name = pic->name;
536 init.parent_names = &pic->parent_name;
537 init.num_parents = 1;
539 pic->hw.init = &init;
544 __prci_wrpll_read_cfg(pd, pic->pwd);
546 r = devm_clk_hw_register(dev, &pic->hw);
548 dev_warn(dev, "Failed to register clock %s: %d\n",
553 r = clk_hw_register_clkdev(&pic->hw, pic->name, dev_name(dev));
555 dev_warn(dev, "Failed to register clkdev for %s: %d\n",
560 pd->hw_clks.hws[i] = &pic->hw;
565 r = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
568 dev_err(dev, "could not add hw_provider: %d\n", r);
576 * Linux device model integration
578 * See the Linux device model documentation for more information about
581 static int sifive_fu540_prci_probe(struct platform_device *pdev)
583 struct device *dev = &pdev->dev;
584 struct resource *res;
585 struct __prci_data *pd;
588 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
592 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
593 pd->va = devm_ioremap_resource(dev, res);
595 return PTR_ERR(pd->va);
597 r = __prci_register_clocks(dev, pd);
599 dev_err(dev, "could not register clocks: %d\n", r);
603 dev_dbg(dev, "SiFive FU540 PRCI probed\n");
608 static const struct of_device_id sifive_fu540_prci_of_match[] = {
609 { .compatible = "sifive,fu540-c000-prci", },
612 MODULE_DEVICE_TABLE(of, sifive_fu540_prci_of_match);
614 static struct platform_driver sifive_fu540_prci_driver = {
616 .name = "sifive-fu540-prci",
617 .of_match_table = sifive_fu540_prci_of_match,
619 .probe = sifive_fu540_prci_probe,
622 static int __init sifive_fu540_prci_init(void)
624 return platform_driver_register(&sifive_fu540_prci_driver);
626 core_initcall(sifive_fu540_prci_init);