1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
10 #include <linux/of_device.h>
11 #include <linux/of_address.h>
12 #include <linux/syscore_ops.h>
13 #include <dt-bindings/clock/rk3568-cru.h>
16 #define RK3568_GRF_SOC_STATUS0 0x580
18 enum rk3568_pmu_plls {
23 apll, dpll, gpll, cpll, npll, vpll,
26 static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
27 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
28 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
29 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
30 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
31 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
32 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
33 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
34 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
43 RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
44 RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
45 RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
46 RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
47 RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
48 RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
49 RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
50 RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
51 RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
52 RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
53 RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
54 RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
55 RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
56 RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
57 RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
58 RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
59 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
60 RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
61 RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
62 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
63 RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
64 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
65 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
66 RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
67 RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
68 RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
69 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
70 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
71 RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
72 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
73 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
74 RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0),
75 RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0),
76 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
77 RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
78 RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
79 RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
80 RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
81 RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
82 RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
83 RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
84 RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
85 RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
89 #define RK3568_DIV_ATCLK_CORE_MASK 0x1f
90 #define RK3568_DIV_ATCLK_CORE_SHIFT 0
91 #define RK3568_DIV_GICCLK_CORE_MASK 0x1f
92 #define RK3568_DIV_GICCLK_CORE_SHIFT 8
93 #define RK3568_DIV_PCLK_CORE_MASK 0x1f
94 #define RK3568_DIV_PCLK_CORE_SHIFT 0
95 #define RK3568_DIV_PERIPHCLK_CORE_MASK 0x1f
96 #define RK3568_DIV_PERIPHCLK_CORE_SHIFT 8
97 #define RK3568_DIV_ACLK_CORE_MASK 0x1f
98 #define RK3568_DIV_ACLK_CORE_SHIFT 8
100 #define RK3568_DIV_SCLK_CORE_MASK 0xf
101 #define RK3568_DIV_SCLK_CORE_SHIFT 0
102 #define RK3568_MUX_SCLK_CORE_MASK 0x3
103 #define RK3568_MUX_SCLK_CORE_SHIFT 8
104 #define RK3568_MUX_SCLK_CORE_NPLL_MASK 0x1
105 #define RK3568_MUX_SCLK_CORE_NPLL_SHIFT 15
106 #define RK3568_MUX_CLK_CORE_APLL_MASK 0x1
107 #define RK3568_MUX_CLK_CORE_APLL_SHIFT 7
108 #define RK3568_MUX_CLK_PVTPLL_MASK 0x1
109 #define RK3568_MUX_CLK_PVTPLL_SHIFT 15
111 #define RK3568_CLKSEL1(_sclk_core) \
113 .reg = RK3568_CLKSEL_CON(2), \
114 .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \
115 RK3568_MUX_SCLK_CORE_NPLL_SHIFT) | \
116 HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \
117 RK3568_MUX_SCLK_CORE_SHIFT) | \
118 HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \
119 RK3568_DIV_SCLK_CORE_SHIFT), \
122 #define RK3568_CLKSEL2(_aclk_core) \
124 .reg = RK3568_CLKSEL_CON(5), \
125 .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \
126 RK3568_DIV_ACLK_CORE_SHIFT), \
129 #define RK3568_CLKSEL3(_atclk_core, _gic_core) \
131 .reg = RK3568_CLKSEL_CON(3), \
132 .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \
133 RK3568_DIV_ATCLK_CORE_SHIFT) | \
134 HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \
135 RK3568_DIV_GICCLK_CORE_SHIFT), \
138 #define RK3568_CLKSEL4(_pclk_core, _periph_core) \
140 .reg = RK3568_CLKSEL_CON(4), \
141 .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \
142 RK3568_DIV_PCLK_CORE_SHIFT) | \
143 HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \
144 RK3568_DIV_PERIPHCLK_CORE_SHIFT), \
147 #define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \
149 .prate = _prate##U, \
151 RK3568_CLKSEL1(_sclk), \
152 RK3568_CLKSEL2(_acore), \
153 RK3568_CLKSEL3(_atcore, _gicclk), \
154 RK3568_CLKSEL4(_pclk, _periph), \
158 static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {
159 RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7),
160 RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7),
161 RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),
162 RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5),
163 RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5),
164 RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5),
165 RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5),
166 RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5),
167 RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5),
168 RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5),
169 RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5),
170 RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5),
171 RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5),
172 RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5),
173 RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5),
174 RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5),
175 RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5),
176 RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5),
177 RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5),
178 RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3),
179 RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3),
180 RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3),
181 RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3),
182 RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3),
183 RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3),
184 RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3),
185 RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3),
186 RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3),
187 RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3),
188 RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3),
191 static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
192 .core_reg[0] = RK3568_CLKSEL_CON(0),
193 .div_core_shift[0] = 0,
194 .div_core_mask[0] = 0x1f,
195 .core_reg[1] = RK3568_CLKSEL_CON(0),
196 .div_core_shift[1] = 8,
197 .div_core_mask[1] = 0x1f,
198 .core_reg[2] = RK3568_CLKSEL_CON(1),
199 .div_core_shift[2] = 0,
200 .div_core_mask[2] = 0x1f,
201 .core_reg[3] = RK3568_CLKSEL_CON(1),
202 .div_core_shift[3] = 8,
203 .div_core_mask[3] = 0x1f,
208 .mux_core_mask = 0x1,
211 PNAME(mux_pll_p) = { "xin24m" };
212 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
213 PNAME(mux_armclk_p) = { "apll", "gpll" };
214 PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
215 PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
216 PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" };
217 PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half" };
218 PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half "};
219 PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half" };
220 PNAME(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half" };
221 PNAME(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" };
222 PNAME(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" };
223 PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
224 PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
225 PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
226 PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
227 PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
228 PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
229 PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
230 PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
231 PNAME(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
232 PNAME(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
233 PNAME(clk_rtc32k_pmu_p) = { "clk_32k_pvtm", "xin32k", "clk_rtc32k_frac" };
234 PNAME(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" };
235 PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" };
236 PNAME(npll_gpll_p) = { "npll", "gpll" };
237 PNAME(cpll_gpll_p) = { "cpll", "gpll" };
238 PNAME(gpll_cpll_p) = { "gpll", "cpll" };
239 PNAME(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" };
240 PNAME(apll_gpll_npll_p) = { "apll", "gpll", "npll" };
241 PNAME(sclk_core_pre_p) = { "sclk_core_src", "npll" };
242 PNAME(gpll150_gpll100_gpll75_xin24m_p) = { "gpll_150m", "gpll_100m", "gpll_75m", "xin24m" };
243 PNAME(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" };
244 PNAME(clk_npu_pre_ndft_p) = { "clk_npu_src", "dummy"};
245 PNAME(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" };
246 PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" };
247 PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" };
248 PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" };
249 PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" };
250 PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" };
251 PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" };
252 PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" };
253 PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" };
254 PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" };
255 PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" };
256 PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" };
257 PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" };
258 PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" };
259 PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" };
260 PNAME(gpll300_gpll200_gpll100_p) = { "gpll_300m", "gpll_200m", "gpll_100m" };
261 PNAME(clk_nandc_p) = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" };
262 PNAME(sclk_sfc_p) = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", "gpll_150m" };
263 PNAME(gpll200_gpll150_cpll125_p) = { "gpll_200m", "gpll_150m", "cpll_125m" };
264 PNAME(cclk_emmc_p) = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", "cpll_50m", "clk_osc0_div_375k" };
265 PNAME(aclk_pipe_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" };
266 PNAME(gpll200_cpll125_p) = { "gpll_200m", "cpll_125m" };
267 PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", "gpll_100m", "xin24m" };
268 PNAME(clk_sdmmc_p) = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", "cpll_50m", "clk_osc0_div_750k" };
269 PNAME(cpll125_cpll50_cpll25_xin24m_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "xin24m" };
270 PNAME(clk_gmac_ptp_p) = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" };
271 PNAME(cpll333_gpll300_gpll200_p) = { "cpll_333m", "gpll_300m", "gpll_200m" };
272 PNAME(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
273 PNAME(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" };
274 PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", "gpll_100m", "xin24m" };
275 PNAME(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" };
276 PNAME(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" };
277 PNAME(gpll400_cpll333_gpll200_p) = { "gpll_400m", "cpll_333m", "gpll_200m" };
278 PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", "xin24m" };
279 PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" };
280 PNAME(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" };
281 PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" };
282 PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" };
283 PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };
284 PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", "gpll_300m", "xin24m" };
285 PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" };
286 PNAME(xin24m_cpll100_p) = { "xin24m", "cpll_100m" };
287 PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"};
288 PNAME(clk_usbphy0_ref_p) = { "clk_ref24m", "xin_osc0_usbphy0_g" };
289 PNAME(clk_usbphy1_ref_p) = { "clk_ref24m", "xin_osc0_usbphy1_g" };
290 PNAME(clk_mipidsiphy0_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" };
291 PNAME(clk_mipidsiphy1_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" };
292 PNAME(clk_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
293 PNAME(clk_pciephy0_ref_p) = { "clk_pciephy0_osc0", "clk_pciephy0_div" };
294 PNAME(clk_pciephy1_ref_p) = { "clk_pciephy1_osc0", "clk_pciephy1_div" };
295 PNAME(clk_pciephy2_ref_p) = { "clk_pciephy2_osc0", "clk_pciephy2_div" };
296 PNAME(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" };
297 PNAME(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" };
298 PNAME(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" };
299 PNAME(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", "clk_gmac0_xpcs_mii" };
300 PNAME(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" };
301 PNAME(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" };
302 PNAME(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" };
303 PNAME(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii" };
304 PNAME(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" };
305 PNAME(clk_pdpmu_p) = { "ppll", "gpll" };
306 PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" };
307 PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" };
308 PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" };
309 PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "dummy_npll", "dummy_vpll" };
311 static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = {
312 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
313 0, RK3568_PMU_PLL_CON(0),
314 RK3568_PMU_MODE_CON0, 0, 4, 0, rk3568_pll_rates),
315 [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
316 0, RK3568_PMU_PLL_CON(16),
317 RK3568_PMU_MODE_CON0, 2, 7, 0, rk3568_pll_rates),
320 static struct rockchip_pll_clock rk3568_pll_clks[] __initdata = {
321 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
322 0, RK3568_PLL_CON(0),
323 RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates),
324 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
325 0, RK3568_PLL_CON(8),
326 RK3568_MODE_CON0, 2, 1, 0, NULL),
327 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
328 0, RK3568_PLL_CON(24),
329 RK3568_MODE_CON0, 4, 2, 0, rk3568_pll_rates),
330 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
331 0, RK3568_PLL_CON(16),
332 RK3568_MODE_CON0, 6, 3, 0, rk3568_pll_rates),
333 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
334 0, RK3568_PLL_CON(32),
335 RK3568_MODE_CON0, 10, 5, 0, rk3568_pll_rates),
336 [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,
337 0, RK3568_PLL_CON(40),
338 RK3568_MODE_CON0, 12, 6, 0, rk3568_pll_rates),
341 #define MFLAGS CLK_MUX_HIWORD_MASK
342 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
343 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
345 static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata =
346 MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
347 RK3568_CLKSEL_CON(11), 10, 2, MFLAGS);
349 static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata =
350 MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
351 RK3568_CLKSEL_CON(13), 10, 2, MFLAGS);
353 static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata =
354 MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
355 RK3568_CLKSEL_CON(15), 10, 2, MFLAGS);
357 static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata =
358 MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
359 RK3568_CLKSEL_CON(17), 10, 2, MFLAGS);
361 static struct rockchip_clk_branch rk3568_i2s2_2ch_fracmux __initdata =
362 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT,
363 RK3568_CLKSEL_CON(19), 10, 2, MFLAGS);
365 static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata =
366 MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT,
367 RK3568_CLKSEL_CON(21), 10, 2, MFLAGS);
369 static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata =
370 MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT,
371 RK3568_CLKSEL_CON(83), 10, 2, MFLAGS);
373 static struct rockchip_clk_branch rk3568_spdif_8ch_fracmux __initdata =
374 MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT,
375 RK3568_CLKSEL_CON(23), 15, 1, MFLAGS);
377 static struct rockchip_clk_branch rk3568_audpwm_fracmux __initdata =
378 MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT,
379 RK3568_CLKSEL_CON(25), 15, 1, MFLAGS);
381 static struct rockchip_clk_branch rk3568_uart1_fracmux __initdata =
382 MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT,
383 RK3568_CLKSEL_CON(52), 12, 2, MFLAGS);
385 static struct rockchip_clk_branch rk3568_uart2_fracmux __initdata =
386 MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT,
387 RK3568_CLKSEL_CON(54), 12, 2, MFLAGS);
389 static struct rockchip_clk_branch rk3568_uart3_fracmux __initdata =
390 MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT,
391 RK3568_CLKSEL_CON(56), 12, 2, MFLAGS);
393 static struct rockchip_clk_branch rk3568_uart4_fracmux __initdata =
394 MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT,
395 RK3568_CLKSEL_CON(58), 12, 2, MFLAGS);
397 static struct rockchip_clk_branch rk3568_uart5_fracmux __initdata =
398 MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT,
399 RK3568_CLKSEL_CON(60), 12, 2, MFLAGS);
401 static struct rockchip_clk_branch rk3568_uart6_fracmux __initdata =
402 MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT,
403 RK3568_CLKSEL_CON(62), 12, 2, MFLAGS);
405 static struct rockchip_clk_branch rk3568_uart7_fracmux __initdata =
406 MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT,
407 RK3568_CLKSEL_CON(64), 12, 2, MFLAGS);
409 static struct rockchip_clk_branch rk3568_uart8_fracmux __initdata =
410 MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT,
411 RK3568_CLKSEL_CON(66), 12, 2, MFLAGS);
413 static struct rockchip_clk_branch rk3568_uart9_fracmux __initdata =
414 MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT,
415 RK3568_CLKSEL_CON(68), 12, 2, MFLAGS);
417 static struct rockchip_clk_branch rk3568_uart0_fracmux __initdata =
418 MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT,
419 RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
421 static struct rockchip_clk_branch rk3568_rtc32k_pmu_fracmux __initdata =
422 MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
423 RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS);
425 static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
427 * Clock-Architecture Diagram 1
430 COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED,
431 RK3568_CLKSEL_CON(75), 0, 5, DFLAGS,
432 RK3568_CLKGATE_CON(35), 0, GFLAGS),
433 COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED,
434 RK3568_CLKSEL_CON(75), 8, 5, DFLAGS,
435 RK3568_CLKGATE_CON(35), 1, GFLAGS),
436 COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED,
437 RK3568_CLKSEL_CON(76), 0, 5, DFLAGS,
438 RK3568_CLKGATE_CON(35), 2, GFLAGS),
439 COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED,
440 RK3568_CLKSEL_CON(76), 8, 5, DFLAGS,
441 RK3568_CLKGATE_CON(35), 3, GFLAGS),
442 COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED,
443 RK3568_CLKSEL_CON(77), 0, 5, DFLAGS,
444 RK3568_CLKGATE_CON(35), 4, GFLAGS),
445 COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED,
446 RK3568_CLKSEL_CON(77), 8, 5, DFLAGS,
447 RK3568_CLKGATE_CON(35), 5, GFLAGS),
448 COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED,
449 RK3568_CLKSEL_CON(78), 0, 6, DFLAGS,
450 RK3568_CLKGATE_CON(35), 6, GFLAGS),
451 COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED,
452 RK3568_CLKSEL_CON(78), 8, 5, DFLAGS,
453 RK3568_CLKGATE_CON(35), 7, GFLAGS),
454 COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED,
455 RK3568_CLKSEL_CON(79), 0, 5, DFLAGS,
456 RK3568_CLKGATE_CON(35), 8, GFLAGS),
457 COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED,
458 RK3568_CLKSEL_CON(79), 8, 5, DFLAGS,
459 RK3568_CLKGATE_CON(35), 9, GFLAGS),
460 COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED,
461 RK3568_CLKSEL_CON(80), 0, 5, DFLAGS,
462 RK3568_CLKGATE_CON(35), 10, GFLAGS),
463 COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
464 RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
465 RK3568_CLKGATE_CON(35), 11, GFLAGS),
466 COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED,
467 RK3568_CLKSEL_CON(80), 8, 5, DFLAGS,
468 RK3568_CLKGATE_CON(35), 12, GFLAGS),
469 COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED,
470 RK3568_CLKSEL_CON(81), 0, 5, DFLAGS,
471 RK3568_CLKGATE_CON(35), 13, GFLAGS),
472 COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED,
473 RK3568_CLKSEL_CON(81), 8, 6, DFLAGS,
474 RK3568_CLKGATE_CON(35), 14, GFLAGS),
475 COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED,
476 RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,
477 RK3568_CLKGATE_CON(35), 15, GFLAGS),
478 FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 0, 1, 2),
479 FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
480 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
481 RK3568_MODE_CON0, 14, 2, MFLAGS),
484 COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED,
485 RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
486 RK3568_CLKGATE_CON(0), 5, GFLAGS),
487 COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IGNORE_UNUSED,
488 RK3568_CLKSEL_CON(2), 15, 1, MFLAGS,
489 RK3568_CLKGATE_CON(0), 7, GFLAGS),
491 COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IGNORE_UNUSED,
492 RK3568_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
493 RK3568_CLKGATE_CON(0), 8, GFLAGS),
494 COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IGNORE_UNUSED,
495 RK3568_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
496 RK3568_CLKGATE_CON(0), 9, GFLAGS),
497 COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
498 RK3568_CLKSEL_CON(4), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
499 RK3568_CLKGATE_CON(0), 10, GFLAGS),
500 COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
501 RK3568_CLKSEL_CON(4), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
502 RK3568_CLKGATE_CON(0), 11, GFLAGS),
503 COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED,
504 RK3568_CLKSEL_CON(5), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
505 RK3568_CLKGATE_CON(0), 14, GFLAGS),
506 COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED,
507 RK3568_CLKSEL_CON(5), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
508 RK3568_CLKGATE_CON(0), 15, GFLAGS),
509 COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IGNORE_UNUSED,
510 RK3568_CLKSEL_CON(5), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
511 RK3568_CLKGATE_CON(1), 0, GFLAGS),
513 COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
514 RK3568_CLKSEL_CON(5), 14, 2, MFLAGS,
515 RK3568_CLKGATE_CON(1), 2, GFLAGS),
517 GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0,
518 RK3568_CLKGATE_CON(1), 10, GFLAGS),
519 GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0,
520 RK3568_CLKGATE_CON(1), 11, GFLAGS),
521 GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED,
522 RK3568_CLKGATE_CON(1), 12, GFLAGS),
523 GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0,
524 RK3568_CLKGATE_CON(1), 9, GFLAGS),
527 COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0,
528 RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
529 RK3568_CLKGATE_CON(2), 0, GFLAGS),
530 MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT,
531 RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY),
532 DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0,
533 RK3568_CLKSEL_CON(6), 8, 2, DFLAGS),
534 DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0,
535 RK3568_CLKSEL_CON(6), 12, 4, DFLAGS),
536 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0,
537 RK3568_CLKGATE_CON(2), 3, GFLAGS),
539 GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0,
540 RK3568_CLKGATE_CON(2), 6, GFLAGS),
541 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
542 RK3568_CLKGATE_CON(2), 7, GFLAGS),
543 GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0,
544 RK3568_CLKGATE_CON(2), 8, GFLAGS),
545 GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED,
546 RK3568_CLKGATE_CON(2), 9, GFLAGS),
549 COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0,
550 RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS,
551 RK3568_CLKGATE_CON(3), 0, GFLAGS),
552 MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
553 RK3568_CLKSEL_CON(7), 8, 1, MFLAGS),
554 MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT,
555 RK3568_CLKSEL_CON(7), 15, 1, MFLAGS),
556 COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 0,
557 RK3568_CLKSEL_CON(8), 0, 4, DFLAGS,
558 RK3568_CLKGATE_CON(3), 2, GFLAGS),
559 COMPOSITE_NOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 0,
560 RK3568_CLKSEL_CON(8), 4, 4, DFLAGS,
561 RK3568_CLKGATE_CON(3), 3, GFLAGS),
562 GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0,
563 RK3568_CLKGATE_CON(3), 4, GFLAGS),
564 GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0,
565 RK3568_CLKGATE_CON(3), 7, GFLAGS),
566 GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0,
567 RK3568_CLKGATE_CON(3), 8, GFLAGS),
569 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0,
570 RK3568_CLKGATE_CON(3), 9, GFLAGS),
571 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
572 RK3568_CLKGATE_CON(3), 10, GFLAGS),
573 GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0,
574 RK3568_CLKGATE_CON(3), 11, GFLAGS),
575 GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED,
576 RK3568_CLKGATE_CON(3), 12, GFLAGS),
579 COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED,
580 RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
581 RK3568_CLKGATE_CON(4), 0, GFLAGS),
582 MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT,
583 RK3568_CLKSEL_CON(9), 15, 1, MFLAGS),
585 COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED,
586 RK3568_CLKSEL_CON(10), 0, 2, DFLAGS,
587 RK3568_CLKGATE_CON(4), 2, GFLAGS),
588 GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
589 RK3568_CLKGATE_CON(4), 15, GFLAGS),
592 COMPOSITE_NODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", gpll200_gpll150_gpll100_xin24m_p, CLK_IGNORE_UNUSED,
593 RK3568_CLKSEL_CON(10), 8, 2, MFLAGS,
594 RK3568_CLKGATE_CON(5), 0, GFLAGS),
595 COMPOSITE_NODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
596 RK3568_CLKSEL_CON(10), 10, 2, MFLAGS,
597 RK3568_CLKGATE_CON(5), 1, GFLAGS),
598 GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0,
599 RK3568_CLKGATE_CON(5), 8, GFLAGS),
600 COMPOSITE_NODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", gpll100_gpll75_gpll50_p, 0,
601 RK3568_CLKSEL_CON(10), 12, 2, MFLAGS,
602 RK3568_CLKGATE_CON(5), 9, GFLAGS),
603 GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED,
604 RK3568_CLKGATE_CON(5), 4, GFLAGS),
605 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED,
606 RK3568_CLKGATE_CON(5), 7, GFLAGS),
607 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0,
608 RK3568_CLKGATE_CON(5), 10, GFLAGS),
609 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0,
610 RK3568_CLKGATE_CON(5), 11, GFLAGS),
611 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0,
612 RK3568_CLKGATE_CON(5), 12, GFLAGS),
613 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0,
614 RK3568_CLKGATE_CON(5), 13, GFLAGS),
616 COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0,
617 RK3568_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 7, DFLAGS,
618 RK3568_CLKGATE_CON(6), 0, GFLAGS),
619 COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
620 RK3568_CLKSEL_CON(12), 0,
621 RK3568_CLKGATE_CON(6), 1, GFLAGS,
622 &rk3568_i2s0_8ch_tx_fracmux),
623 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
624 RK3568_CLKGATE_CON(6), 2, GFLAGS),
625 COMPOSITE_NODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT,
626 RK3568_CLKSEL_CON(11), 15, 1, MFLAGS,
627 RK3568_CLKGATE_CON(6), 3, GFLAGS),
629 COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0,
630 RK3568_CLKSEL_CON(13), 8, 2, MFLAGS, 0, 7, DFLAGS,
631 RK3568_CLKGATE_CON(6), 4, GFLAGS),
632 COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
633 RK3568_CLKSEL_CON(14), 0,
634 RK3568_CLKGATE_CON(6), 5, GFLAGS,
635 &rk3568_i2s0_8ch_rx_fracmux),
636 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
637 RK3568_CLKGATE_CON(6), 6, GFLAGS),
638 COMPOSITE_NODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT,
639 RK3568_CLKSEL_CON(13), 15, 1, MFLAGS,
640 RK3568_CLKGATE_CON(6), 7, GFLAGS),
642 COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0,
643 RK3568_CLKSEL_CON(15), 8, 2, MFLAGS, 0, 7, DFLAGS,
644 RK3568_CLKGATE_CON(6), 8, GFLAGS),
645 COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
646 RK3568_CLKSEL_CON(16), 0,
647 RK3568_CLKGATE_CON(6), 9, GFLAGS,
648 &rk3568_i2s1_8ch_tx_fracmux),
649 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0,
650 RK3568_CLKGATE_CON(6), 10, GFLAGS),
651 COMPOSITE_NODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT,
652 RK3568_CLKSEL_CON(15), 15, 1, MFLAGS,
653 RK3568_CLKGATE_CON(6), 11, GFLAGS),
655 COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0,
656 RK3568_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 7, DFLAGS,
657 RK3568_CLKGATE_CON(6), 12, GFLAGS),
658 COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
659 RK3568_CLKSEL_CON(18), 0,
660 RK3568_CLKGATE_CON(6), 13, GFLAGS,
661 &rk3568_i2s1_8ch_rx_fracmux),
662 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0,
663 RK3568_CLKGATE_CON(6), 14, GFLAGS),
664 COMPOSITE_NODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT,
665 RK3568_CLKSEL_CON(17), 15, 1, MFLAGS,
666 RK3568_CLKGATE_CON(6), 15, GFLAGS),
668 COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0,
669 RK3568_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 7, DFLAGS,
670 RK3568_CLKGATE_CON(7), 0, GFLAGS),
671 COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
672 RK3568_CLKSEL_CON(20), 0,
673 RK3568_CLKGATE_CON(7), 1, GFLAGS,
674 &rk3568_i2s2_2ch_fracmux),
675 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0,
676 RK3568_CLKGATE_CON(7), 2, GFLAGS),
677 COMPOSITE_NODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, CLK_SET_RATE_PARENT,
678 RK3568_CLKSEL_CON(19), 15, 1, MFLAGS,
679 RK3568_CLKGATE_CON(7), 3, GFLAGS),
681 COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0,
682 RK3568_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 7, DFLAGS,
683 RK3568_CLKGATE_CON(7), 4, GFLAGS),
684 COMPOSITE_FRACMUX(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_src", CLK_SET_RATE_PARENT,
685 RK3568_CLKSEL_CON(22), 0,
686 RK3568_CLKGATE_CON(7), 5, GFLAGS,
687 &rk3568_i2s3_2ch_tx_fracmux),
688 GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0,
689 RK3568_CLKGATE_CON(7), 6, GFLAGS),
690 COMPOSITE_NODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT,
691 RK3568_CLKSEL_CON(21), 15, 1, MFLAGS,
692 RK3568_CLKGATE_CON(7), 7, GFLAGS),
694 COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", gpll_cpll_npll_p, 0,
695 RK3568_CLKSEL_CON(83), 8, 2, MFLAGS, 0, 7, DFLAGS,
696 RK3568_CLKGATE_CON(7), 8, GFLAGS),
697 COMPOSITE_FRACMUX(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_src", CLK_SET_RATE_PARENT,
698 RK3568_CLKSEL_CON(84), 0,
699 RK3568_CLKGATE_CON(7), 9, GFLAGS,
700 &rk3568_i2s3_2ch_rx_fracmux),
701 GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0,
702 RK3568_CLKGATE_CON(7), 10, GFLAGS),
703 COMPOSITE_NODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT,
704 RK3568_CLKSEL_CON(83), 15, 1, MFLAGS,
705 RK3568_CLKGATE_CON(7), 11, GFLAGS),
707 GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0,
708 RK3568_CLKGATE_CON(5), 14, GFLAGS),
709 COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0,
710 RK3568_CLKSEL_CON(23), 8, 2, MFLAGS,
711 RK3568_CLKGATE_CON(5), 15, GFLAGS),
712 GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0,
713 RK3568_CLKGATE_CON(7), 12, GFLAGS),
714 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0,
715 RK3568_CLKGATE_CON(7), 13, GFLAGS),
717 COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 0,
718 RK3568_CLKSEL_CON(23), 14, 1, MFLAGS, 0, 7, DFLAGS,
719 RK3568_CLKGATE_CON(7), 14, GFLAGS),
720 COMPOSITE_FRACMUX(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_src", CLK_SET_RATE_PARENT,
721 RK3568_CLKSEL_CON(24), 0,
722 RK3568_CLKGATE_CON(7), 15, GFLAGS,
723 &rk3568_spdif_8ch_fracmux),
725 GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0,
726 RK3568_CLKGATE_CON(8), 0, GFLAGS),
727 COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0,
728 RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS,
729 RK3568_CLKGATE_CON(8), 1, GFLAGS),
730 COMPOSITE_FRACMUX(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", CLK_SET_RATE_PARENT,
731 RK3568_CLKSEL_CON(26), 0,
732 RK3568_CLKGATE_CON(8), 2, GFLAGS,
733 &rk3568_audpwm_fracmux),
735 GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0,
736 RK3568_CLKGATE_CON(8), 3, GFLAGS),
737 COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0,
738 RK3568_CLKSEL_CON(23), 10, 2, MFLAGS,
739 RK3568_CLKGATE_CON(8), 4, GFLAGS),
740 GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0,
741 RK3568_CLKGATE_CON(8), 5, GFLAGS),
742 GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0,
743 RK3568_CLKGATE_CON(8), 6, GFLAGS),
745 /* PD_SECURE_FLASH */
746 COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, 0,
747 RK3568_CLKSEL_CON(27), 0, 2, MFLAGS,
748 RK3568_CLKGATE_CON(8), 7, GFLAGS),
749 COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, 0,
750 RK3568_CLKSEL_CON(27), 2, 2, MFLAGS,
751 RK3568_CLKGATE_CON(8), 8, GFLAGS),
752 GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0,
753 RK3568_CLKGATE_CON(8), 11, GFLAGS),
754 GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0,
755 RK3568_CLKGATE_CON(8), 12, GFLAGS),
756 COMPOSITE_NODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", gpll200_gpll150_gpll100_p, 0,
757 RK3568_CLKSEL_CON(27), 4, 2, MFLAGS,
758 RK3568_CLKGATE_CON(8), 13, GFLAGS),
759 COMPOSITE_NODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", gpll300_gpll200_gpll100_p, 0,
760 RK3568_CLKSEL_CON(27), 6, 2, MFLAGS,
761 RK3568_CLKGATE_CON(8), 14, GFLAGS),
762 GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0,
763 RK3568_CLKGATE_CON(8), 15, GFLAGS),
764 GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED,
765 RK3568_CLKGATE_CON(9), 10, GFLAGS),
766 GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED,
767 RK3568_CLKGATE_CON(9), 11, GFLAGS),
768 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0,
769 RK3568_CLKGATE_CON(26), 9, GFLAGS),
770 GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0,
771 RK3568_CLKGATE_CON(26), 10, GFLAGS),
772 GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0,
773 RK3568_CLKGATE_CON(26), 11, GFLAGS),
774 GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0,
775 RK3568_CLKGATE_CON(9), 0, GFLAGS),
776 COMPOSITE_NODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 0,
777 RK3568_CLKSEL_CON(28), 0, 2, MFLAGS,
778 RK3568_CLKGATE_CON(9), 1, GFLAGS),
779 GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0,
780 RK3568_CLKGATE_CON(9), 2, GFLAGS),
781 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0,
782 RK3568_CLKGATE_CON(9), 3, GFLAGS),
783 COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0,
784 RK3568_CLKSEL_CON(28), 4, 3, MFLAGS,
785 RK3568_CLKGATE_CON(9), 4, GFLAGS),
786 GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0,
787 RK3568_CLKGATE_CON(9), 5, GFLAGS),
788 GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0,
789 RK3568_CLKGATE_CON(9), 6, GFLAGS),
790 COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 0,
791 RK3568_CLKSEL_CON(28), 8, 2, MFLAGS,
792 RK3568_CLKGATE_CON(9), 7, GFLAGS),
793 COMPOSITE_NODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 0,
794 RK3568_CLKSEL_CON(28), 12, 3, MFLAGS,
795 RK3568_CLKGATE_CON(9), 8, GFLAGS),
796 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
797 RK3568_CLKGATE_CON(9), 9, GFLAGS),
798 MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_emmc", RK3568_EMMC_CON0, 1),
799 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_emmc", RK3568_EMMC_CON1, 1),
802 COMPOSITE_NODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 0,
803 RK3568_CLKSEL_CON(29), 0, 2, MFLAGS,
804 RK3568_CLKGATE_CON(10), 0, GFLAGS),
805 COMPOSITE_NOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 0,
806 RK3568_CLKSEL_CON(29), 4, 4, DFLAGS,
807 RK3568_CLKGATE_CON(10), 1, GFLAGS),
808 GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0,
809 RK3568_CLKGATE_CON(12), 0, GFLAGS),
810 GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0,
811 RK3568_CLKGATE_CON(12), 1, GFLAGS),
812 GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0,
813 RK3568_CLKGATE_CON(12), 2, GFLAGS),
814 GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0,
815 RK3568_CLKGATE_CON(12), 3, GFLAGS),
816 GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
817 RK3568_CLKGATE_CON(12), 4, GFLAGS),
818 GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,
819 RK3568_CLKGATE_CON(12), 8, GFLAGS),
820 GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
821 RK3568_CLKGATE_CON(12), 9, GFLAGS),
822 GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0,
823 RK3568_CLKGATE_CON(12), 10, GFLAGS),
824 GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0,
825 RK3568_CLKGATE_CON(12), 11, GFLAGS),
826 GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
827 RK3568_CLKGATE_CON(12), 12, GFLAGS),
828 GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,
829 RK3568_CLKGATE_CON(13), 0, GFLAGS),
830 GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
831 RK3568_CLKGATE_CON(13), 1, GFLAGS),
832 GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0,
833 RK3568_CLKGATE_CON(13), 2, GFLAGS),
834 GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0,
835 RK3568_CLKGATE_CON(13), 3, GFLAGS),
836 GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
837 RK3568_CLKGATE_CON(13), 4, GFLAGS),
838 GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,
839 RK3568_CLKGATE_CON(11), 0, GFLAGS),
840 GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,
841 RK3568_CLKGATE_CON(11), 1, GFLAGS),
842 GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0,
843 RK3568_CLKGATE_CON(11), 2, GFLAGS),
844 GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0,
845 RK3568_CLKGATE_CON(11), 4, GFLAGS),
846 GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0,
847 RK3568_CLKGATE_CON(11), 5, GFLAGS),
848 GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0,
849 RK3568_CLKGATE_CON(11), 6, GFLAGS),
850 GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0,
851 RK3568_CLKGATE_CON(11), 8, GFLAGS),
852 GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0,
853 RK3568_CLKGATE_CON(11), 9, GFLAGS),
854 GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0,
855 RK3568_CLKGATE_CON(11), 10, GFLAGS),
856 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0,
857 RK3568_CLKGATE_CON(10), 8, GFLAGS),
858 GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
859 RK3568_CLKGATE_CON(10), 9, GFLAGS),
860 COMPOSITE_NODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 0,
861 RK3568_CLKSEL_CON(29), 8, 1, MFLAGS,
862 RK3568_CLKGATE_CON(10), 10, GFLAGS),
863 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0,
864 RK3568_CLKGATE_CON(10), 12, GFLAGS),
865 GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
866 RK3568_CLKGATE_CON(10), 13, GFLAGS),
867 COMPOSITE_NODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 0,
868 RK3568_CLKSEL_CON(29), 9, 1, MFLAGS,
869 RK3568_CLKGATE_CON(10), 14, GFLAGS),
870 COMPOSITE_NODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 0,
871 RK3568_CLKSEL_CON(29), 13, 1, MFLAGS,
872 RK3568_CLKGATE_CON(10), 4, GFLAGS),
873 GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0,
874 RK3568_CLKGATE_CON(13), 6, GFLAGS),
877 COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0,
878 RK3568_CLKSEL_CON(30), 0, 2, MFLAGS,
879 RK3568_CLKGATE_CON(14), 8, GFLAGS),
880 COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 0,
881 RK3568_CLKSEL_CON(30), 2, 2, MFLAGS,
882 RK3568_CLKGATE_CON(14), 9, GFLAGS),
883 COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0,
884 RK3568_CLKSEL_CON(30), 4, 4, DFLAGS,
885 RK3568_CLKGATE_CON(14), 10, GFLAGS),
886 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0,
887 RK3568_CLKGATE_CON(15), 0, GFLAGS),
888 COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0,
889 RK3568_CLKSEL_CON(30), 8, 3, MFLAGS,
890 RK3568_CLKGATE_CON(15), 1, GFLAGS),
891 MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "clk_sdmmc0", RK3568_SDMMC0_CON0, 1),
892 MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "clk_sdmmc0", RK3568_SDMMC0_CON1, 1),
894 GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0,
895 RK3568_CLKGATE_CON(15), 2, GFLAGS),
896 COMPOSITE_NODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 0,
897 RK3568_CLKSEL_CON(30), 12, 3, MFLAGS,
898 RK3568_CLKGATE_CON(15), 3, GFLAGS),
899 MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "clk_sdmmc1", RK3568_SDMMC1_CON0, 1),
900 MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "clk_sdmmc1", RK3568_SDMMC1_CON1, 1),
902 GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 0,
903 RK3568_CLKGATE_CON(15), 5, GFLAGS),
904 GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 0,
905 RK3568_CLKGATE_CON(15), 6, GFLAGS),
906 COMPOSITE_NODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 0,
907 RK3568_CLKSEL_CON(31), 8, 2, MFLAGS,
908 RK3568_CLKGATE_CON(15), 7, GFLAGS),
909 COMPOSITE_NODIV(CLK_MAC0_OUT, "clk_mac0_out", cpll125_cpll50_cpll25_xin24m_p, 0,
910 RK3568_CLKSEL_CON(31), 14, 2, MFLAGS,
911 RK3568_CLKGATE_CON(15), 8, GFLAGS),
912 GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0,
913 RK3568_CLKGATE_CON(15), 12, GFLAGS),
914 COMPOSITE_NODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 0,
915 RK3568_CLKSEL_CON(31), 12, 2, MFLAGS,
916 RK3568_CLKGATE_CON(15), 4, GFLAGS),
917 MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
918 RK3568_CLKSEL_CON(31), 2, 1, MFLAGS),
919 FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 0, 1, 5),
920 FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 0, 1, 50),
921 FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 0, 1, 2),
922 FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 0, 1, 20),
923 MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", mux_gmac0_rgmii_speed_p, 0,
924 RK3568_CLKSEL_CON(31), 4, 2, MFLAGS),
925 MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", mux_gmac0_rmii_speed_p, 0,
926 RK3568_CLKSEL_CON(31), 3, 1, MFLAGS),
927 MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, CLK_SET_RATE_PARENT,
928 RK3568_CLKSEL_CON(31), 0, 2, MFLAGS),
931 COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0,
932 RK3568_CLKSEL_CON(32), 0, 2, MFLAGS,
933 RK3568_CLKGATE_CON(16), 0, GFLAGS),
934 COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 0,
935 RK3568_CLKSEL_CON(32), 2, 2, MFLAGS,
936 RK3568_CLKGATE_CON(16), 1, GFLAGS),
937 COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 0,
938 RK3568_CLKSEL_CON(32), 4, 4, DFLAGS,
939 RK3568_CLKGATE_CON(16), 2, GFLAGS),
940 GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0,
941 RK3568_CLKGATE_CON(16), 12, GFLAGS),
942 GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0,
943 RK3568_CLKGATE_CON(16), 13, GFLAGS),
944 GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0,
945 RK3568_CLKGATE_CON(16), 14, GFLAGS),
946 GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0,
947 RK3568_CLKGATE_CON(16), 15, GFLAGS),
948 GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0,
949 RK3568_CLKGATE_CON(17), 0, GFLAGS),
950 COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0,
951 RK3568_CLKSEL_CON(32), 8, 3, MFLAGS,
952 RK3568_CLKGATE_CON(17), 1, GFLAGS),
953 MMC(SCLK_SDMMC2_DRV, "sdmmc2_drv", "clk_sdmmc2", RK3568_SDMMC2_CON0, 1),
954 MMC(SCLK_SDMMC2_SAMPLE, "sdmmc2_sample", "clk_sdmmc2", RK3568_SDMMC2_CON1, 1),
956 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0,
957 RK3568_CLKGATE_CON(17), 3, GFLAGS),
958 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0,
959 RK3568_CLKGATE_CON(17), 4, GFLAGS),
960 COMPOSITE_NODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 0,
961 RK3568_CLKSEL_CON(33), 8, 2, MFLAGS,
962 RK3568_CLKGATE_CON(17), 5, GFLAGS),
963 COMPOSITE_NODIV(CLK_MAC1_OUT, "clk_mac1_out", cpll125_cpll50_cpll25_xin24m_p, 0,
964 RK3568_CLKSEL_CON(33), 14, 2, MFLAGS,
965 RK3568_CLKGATE_CON(17), 6, GFLAGS),
966 GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0,
967 RK3568_CLKGATE_CON(17), 10, GFLAGS),
968 COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 0,
969 RK3568_CLKSEL_CON(33), 12, 2, MFLAGS,
970 RK3568_CLKGATE_CON(17), 2, GFLAGS),
971 MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
972 RK3568_CLKSEL_CON(33), 2, 1, MFLAGS),
973 FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 0, 1, 5),
974 FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 0, 1, 50),
975 FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 0, 1, 2),
976 FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 0, 1, 20),
977 MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", mux_gmac1_rgmii_speed_p, 0,
978 RK3568_CLKSEL_CON(33), 4, 2, MFLAGS),
979 MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0,
980 RK3568_CLKSEL_CON(33), 3, 1, MFLAGS),
981 MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, CLK_SET_RATE_PARENT,
982 RK3568_CLKSEL_CON(33), 0, 2, MFLAGS),
985 COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IGNORE_UNUSED,
986 RK3568_CLKSEL_CON(10), 4, 2, MFLAGS,
987 RK3568_CLKGATE_CON(14), 0, GFLAGS),
988 COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
989 RK3568_CLKSEL_CON(10), 6, 2, MFLAGS,
990 RK3568_CLKGATE_CON(14), 1, GFLAGS),
993 COMPOSITE_NODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 0,
994 RK3568_CLKSEL_CON(34), 0, 2, MFLAGS,
995 RK3568_CLKGATE_CON(18), 0, GFLAGS),
996 COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 0,
997 RK3568_CLKSEL_CON(34), 4, 4, DFLAGS,
998 RK3568_CLKGATE_CON(18), 1, GFLAGS),
999 COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 0,
1000 RK3568_CLKSEL_CON(34), 8, 4, DFLAGS,
1001 RK3568_CLKGATE_CON(18), 2, GFLAGS),
1002 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0,
1003 RK3568_CLKGATE_CON(18), 9, GFLAGS),
1004 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0,
1005 RK3568_CLKGATE_CON(18), 10, GFLAGS),
1006 COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 0,
1007 RK3568_CLKSEL_CON(34), 14, 2, MFLAGS,
1008 RK3568_CLKGATE_CON(18), 11, GFLAGS),
1009 GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0,
1010 RK3568_CLKGATE_CON(18), 13, GFLAGS),
1011 GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0,
1012 RK3568_CLKGATE_CON(19), 0, GFLAGS),
1013 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0,
1014 RK3568_CLKGATE_CON(19), 1, GFLAGS),
1015 COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0,
1016 RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
1017 RK3568_CLKGATE_CON(19), 2, GFLAGS),
1018 GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0,
1019 RK3568_CLKGATE_CON(19), 4, GFLAGS),
1020 COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0,
1021 RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS,
1022 RK3568_CLKGATE_CON(19), 8, GFLAGS),
1023 COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0,
1024 RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS,
1025 RK3568_CLKGATE_CON(19), 9, GFLAGS),
1026 COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 0,
1027 RK3568_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 6, DFLAGS,
1028 RK3568_CLKGATE_CON(19), 10, GFLAGS),
1031 COMPOSITE_NODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 0,
1032 RK3568_CLKSEL_CON(37), 0, 2, MFLAGS,
1033 RK3568_CLKGATE_CON(20), 0, GFLAGS),
1034 COMPOSITE_NOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 0,
1035 RK3568_CLKSEL_CON(37), 8, 4, DFLAGS,
1036 RK3568_CLKGATE_CON(20), 1, GFLAGS),
1037 COMPOSITE_NOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 0,
1038 RK3568_CLKSEL_CON(37), 12, 4, DFLAGS,
1039 RK3568_CLKGATE_CON(20), 2, GFLAGS),
1040 COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0,
1041 RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
1042 RK3568_CLKGATE_CON(20), 6, GFLAGS),
1043 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0,
1044 RK3568_CLKGATE_CON(20), 8, GFLAGS),
1045 GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0,
1046 RK3568_CLKGATE_CON(20), 9, GFLAGS),
1047 COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
1048 RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS,
1049 RK3568_CLKGATE_CON(20), 10, GFLAGS),
1050 COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
1051 RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS,
1052 RK3568_CLKGATE_CON(20), 11, GFLAGS),
1053 COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
1054 RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
1055 RK3568_CLKGATE_CON(20), 12, GFLAGS),
1056 GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0,
1057 RK3568_CLKGATE_CON(20), 13, GFLAGS),
1058 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0,
1059 RK3568_CLKGATE_CON(21), 0, GFLAGS),
1060 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0,
1061 RK3568_CLKGATE_CON(21), 1, GFLAGS),
1062 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0,
1063 RK3568_CLKGATE_CON(21), 2, GFLAGS),
1064 GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0,
1065 RK3568_CLKGATE_CON(21), 3, GFLAGS),
1066 GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1067 RK3568_CLKGATE_CON(21), 4, GFLAGS),
1068 GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0,
1069 RK3568_CLKGATE_CON(21), 5, GFLAGS),
1070 GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0,
1071 RK3568_CLKGATE_CON(21), 6, GFLAGS),
1072 GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0,
1073 RK3568_CLKGATE_CON(21), 7, GFLAGS),
1074 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0,
1075 RK3568_CLKGATE_CON(21), 8, GFLAGS),
1076 COMPOSITE_NODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 0,
1077 RK3568_CLKSEL_CON(38), 8, 2, MFLAGS,
1078 RK3568_CLKGATE_CON(21), 9, GFLAGS),
1081 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0,
1082 RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS,
1083 RK3568_CLKGATE_CON(22), 0, GFLAGS),
1084 COMPOSITE_NOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0,
1085 RK3568_CLKSEL_CON(42), 8, 4, DFLAGS,
1086 RK3568_CLKGATE_CON(22), 1, GFLAGS),
1087 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
1088 RK3568_CLKGATE_CON(22), 4, GFLAGS),
1089 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0,
1090 RK3568_CLKGATE_CON(22), 5, GFLAGS),
1093 COMPOSITE_NODIV(ACLK_RGA_PRE, "aclk_rga_pre", gpll300_cpll250_gpll100_xin24m_p, 0,
1094 RK3568_CLKSEL_CON(43), 0, 2, MFLAGS,
1095 RK3568_CLKGATE_CON(23), 0, GFLAGS),
1096 COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 0,
1097 RK3568_CLKSEL_CON(43), 8, 4, DFLAGS,
1098 RK3568_CLKGATE_CON(23), 1, GFLAGS),
1099 COMPOSITE_NOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 0,
1100 RK3568_CLKSEL_CON(43), 12, 4, DFLAGS,
1101 RK3568_CLKGATE_CON(22), 12, GFLAGS),
1102 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
1103 RK3568_CLKGATE_CON(23), 4, GFLAGS),
1104 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
1105 RK3568_CLKGATE_CON(23), 5, GFLAGS),
1106 COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0,
1107 RK3568_CLKSEL_CON(43), 2, 2, MFLAGS,
1108 RK3568_CLKGATE_CON(23), 6, GFLAGS),
1109 GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0,
1110 RK3568_CLKGATE_CON(23), 7, GFLAGS),
1111 GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0,
1112 RK3568_CLKGATE_CON(23), 8, GFLAGS),
1113 COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0,
1114 RK3568_CLKSEL_CON(43), 4, 2, MFLAGS,
1115 RK3568_CLKGATE_CON(23), 9, GFLAGS),
1116 GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS),
1117 COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0,
1118 RK3568_CLKSEL_CON(43), 6, 2, MFLAGS,
1119 RK3568_CLKGATE_CON(23), 11, GFLAGS),
1120 GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0,
1121 RK3568_CLKGATE_CON(23), 12, GFLAGS),
1122 GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0,
1123 RK3568_CLKGATE_CON(23), 13, GFLAGS),
1124 GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0,
1125 RK3568_CLKGATE_CON(23), 14, GFLAGS),
1126 GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0,
1127 RK3568_CLKGATE_CON(23), 15, GFLAGS),
1128 GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0,
1129 RK3568_CLKGATE_CON(22), 14, GFLAGS),
1130 GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0,
1131 RK3568_CLKGATE_CON(22), 15, GFLAGS),
1134 COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0,
1135 RK3568_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
1136 RK3568_CLKGATE_CON(24), 0, GFLAGS),
1137 COMPOSITE_NOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0,
1138 RK3568_CLKSEL_CON(44), 8, 4, DFLAGS,
1139 RK3568_CLKGATE_CON(24), 1, GFLAGS),
1140 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
1141 RK3568_CLKGATE_CON(24), 6, GFLAGS),
1142 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
1143 RK3568_CLKGATE_CON(24), 7, GFLAGS),
1144 COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0,
1145 RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5, DFLAGS,
1146 RK3568_CLKGATE_CON(24), 8, GFLAGS),
1147 COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT,
1148 RK3568_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS,
1149 RK3568_CLKGATE_CON(25), 0, GFLAGS),
1150 COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0,
1151 RK3568_CLKSEL_CON(47), 8, 4, DFLAGS,
1152 RK3568_CLKGATE_CON(25), 1, GFLAGS),
1153 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
1154 RK3568_CLKGATE_CON(25), 4, GFLAGS),
1155 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0,
1156 RK3568_CLKGATE_CON(25), 5, GFLAGS),
1157 COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0,
1158 RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1159 RK3568_CLKGATE_CON(25), 6, GFLAGS),
1160 COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT,
1161 RK3568_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS,
1162 RK3568_CLKGATE_CON(25), 7, GFLAGS),
1163 COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0,
1164 RK3568_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
1165 RK3568_CLKGATE_CON(25), 8, GFLAGS),
1168 COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 0,
1169 RK3568_CLKSEL_CON(50), 0, 2, MFLAGS,
1170 RK3568_CLKGATE_CON(26), 0, GFLAGS),
1171 COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 0,
1172 RK3568_CLKSEL_CON(50), 4, 2, MFLAGS,
1173 RK3568_CLKGATE_CON(26), 1, GFLAGS),
1174 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0,
1175 RK3568_CLKGATE_CON(26), 4, GFLAGS),
1176 COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 0,
1177 RK3568_CLKSEL_CON(51), 4, 2, MFLAGS, 0, 3, DFLAGS,
1178 RK3568_CLKGATE_CON(26), 5, GFLAGS),
1179 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0,
1180 RK3568_CLKSEL_CON(51), 8, 7, DFLAGS,
1181 RK3568_CLKGATE_CON(26), 6, GFLAGS),
1182 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0,
1183 RK3568_CLKGATE_CON(26), 7, GFLAGS),
1184 GATE(CLK_SARADC, "clk_saradc", "xin24m", 0,
1185 RK3568_CLKGATE_CON(26), 8, GFLAGS),
1186 GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED,
1187 RK3568_CLKGATE_CON(26), 12, GFLAGS),
1188 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0,
1189 RK3568_CLKGATE_CON(26), 13, GFLAGS),
1190 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
1191 RK3568_CLKGATE_CON(26), 14, GFLAGS),
1192 GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED,
1193 RK3568_CLKGATE_CON(32), 13, GFLAGS),
1194 GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED,
1195 RK3568_CLKGATE_CON(32), 14, GFLAGS),
1196 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0,
1197 RK3568_CLKGATE_CON(32), 15, GFLAGS),
1199 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0,
1200 RK3568_CLKGATE_CON(27), 12, GFLAGS),
1201 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0,
1202 RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS,
1203 RK3568_CLKGATE_CON(27), 13, GFLAGS),
1204 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
1205 RK3568_CLKSEL_CON(53), 0,
1206 RK3568_CLKGATE_CON(27), 14, GFLAGS,
1207 &rk3568_uart1_fracmux),
1208 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
1209 RK3568_CLKGATE_CON(27), 15, GFLAGS),
1211 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0,
1212 RK3568_CLKGATE_CON(28), 0, GFLAGS),
1213 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0,
1214 RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS,
1215 RK3568_CLKGATE_CON(28), 1, GFLAGS),
1216 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
1217 RK3568_CLKSEL_CON(55), 0,
1218 RK3568_CLKGATE_CON(28), 2, GFLAGS,
1219 &rk3568_uart2_fracmux),
1220 GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
1221 RK3568_CLKGATE_CON(28), 3, GFLAGS),
1223 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0,
1224 RK3568_CLKGATE_CON(28), 4, GFLAGS),
1225 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0,
1226 RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS,
1227 RK3568_CLKGATE_CON(28), 5, GFLAGS),
1228 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
1229 RK3568_CLKSEL_CON(57), 0,
1230 RK3568_CLKGATE_CON(28), 6, GFLAGS,
1231 &rk3568_uart3_fracmux),
1232 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
1233 RK3568_CLKGATE_CON(28), 7, GFLAGS),
1235 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0,
1236 RK3568_CLKGATE_CON(28), 8, GFLAGS),
1237 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0,
1238 RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS,
1239 RK3568_CLKGATE_CON(28), 9, GFLAGS),
1240 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
1241 RK3568_CLKSEL_CON(59), 0,
1242 RK3568_CLKGATE_CON(28), 10, GFLAGS,
1243 &rk3568_uart4_fracmux),
1244 GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
1245 RK3568_CLKGATE_CON(28), 11, GFLAGS),
1247 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0,
1248 RK3568_CLKGATE_CON(28), 12, GFLAGS),
1249 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0,
1250 RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS,
1251 RK3568_CLKGATE_CON(28), 13, GFLAGS),
1252 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
1253 RK3568_CLKSEL_CON(61), 0,
1254 RK3568_CLKGATE_CON(28), 14, GFLAGS,
1255 &rk3568_uart5_fracmux),
1256 GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
1257 RK3568_CLKGATE_CON(28), 15, GFLAGS),
1259 GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0,
1260 RK3568_CLKGATE_CON(29), 0, GFLAGS),
1261 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0,
1262 RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS,
1263 RK3568_CLKGATE_CON(29), 1, GFLAGS),
1264 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
1265 RK3568_CLKSEL_CON(63), 0,
1266 RK3568_CLKGATE_CON(29), 2, GFLAGS,
1267 &rk3568_uart6_fracmux),
1268 GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0,
1269 RK3568_CLKGATE_CON(29), 3, GFLAGS),
1271 GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0,
1272 RK3568_CLKGATE_CON(29), 4, GFLAGS),
1273 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0,
1274 RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS,
1275 RK3568_CLKGATE_CON(29), 5, GFLAGS),
1276 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
1277 RK3568_CLKSEL_CON(65), 0,
1278 RK3568_CLKGATE_CON(29), 6, GFLAGS,
1279 &rk3568_uart7_fracmux),
1280 GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0,
1281 RK3568_CLKGATE_CON(29), 7, GFLAGS),
1283 GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0,
1284 RK3568_CLKGATE_CON(29), 8, GFLAGS),
1285 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0,
1286 RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS,
1287 RK3568_CLKGATE_CON(29), 9, GFLAGS),
1288 COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT,
1289 RK3568_CLKSEL_CON(67), 0,
1290 RK3568_CLKGATE_CON(29), 10, GFLAGS,
1291 &rk3568_uart8_fracmux),
1292 GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0,
1293 RK3568_CLKGATE_CON(29), 11, GFLAGS),
1295 GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0,
1296 RK3568_CLKGATE_CON(29), 12, GFLAGS),
1297 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0,
1298 RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS,
1299 RK3568_CLKGATE_CON(29), 13, GFLAGS),
1300 COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT,
1301 RK3568_CLKSEL_CON(69), 0,
1302 RK3568_CLKGATE_CON(29), 14, GFLAGS,
1303 &rk3568_uart9_fracmux),
1304 GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0,
1305 RK3568_CLKGATE_CON(29), 15, GFLAGS),
1307 GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0,
1308 RK3568_CLKGATE_CON(27), 5, GFLAGS),
1309 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
1310 RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS,
1311 RK3568_CLKGATE_CON(27), 6, GFLAGS),
1312 GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0,
1313 RK3568_CLKGATE_CON(27), 7, GFLAGS),
1314 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
1315 RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS,
1316 RK3568_CLKGATE_CON(27), 8, GFLAGS),
1317 GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0,
1318 RK3568_CLKGATE_CON(27), 9, GFLAGS),
1319 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0,
1320 RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS,
1321 RK3568_CLKGATE_CON(27), 10, GFLAGS),
1322 COMPOSITE_NODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 0,
1323 RK3568_CLKSEL_CON(71), 8, 2, MFLAGS,
1324 RK3568_CLKGATE_CON(32), 10, GFLAGS),
1325 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0,
1326 RK3568_CLKGATE_CON(30), 0, GFLAGS),
1327 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0,
1328 RK3568_CLKGATE_CON(30), 1, GFLAGS),
1329 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0,
1330 RK3568_CLKGATE_CON(30), 2, GFLAGS),
1331 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0,
1332 RK3568_CLKGATE_CON(30), 3, GFLAGS),
1333 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0,
1334 RK3568_CLKGATE_CON(30), 4, GFLAGS),
1335 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0,
1336 RK3568_CLKGATE_CON(30), 5, GFLAGS),
1337 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0,
1338 RK3568_CLKGATE_CON(30), 6, GFLAGS),
1339 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0,
1340 RK3568_CLKGATE_CON(30), 7, GFLAGS),
1341 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0,
1342 RK3568_CLKGATE_CON(30), 8, GFLAGS),
1343 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0,
1344 RK3568_CLKGATE_CON(30), 9, GFLAGS),
1345 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0,
1346 RK3568_CLKGATE_CON(30), 10, GFLAGS),
1347 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0,
1348 RK3568_CLKSEL_CON(72), 0, 1, MFLAGS,
1349 RK3568_CLKGATE_CON(30), 11, GFLAGS),
1350 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0,
1351 RK3568_CLKGATE_CON(30), 12, GFLAGS),
1352 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0,
1353 RK3568_CLKSEL_CON(72), 2, 1, MFLAGS,
1354 RK3568_CLKGATE_CON(30), 13, GFLAGS),
1355 GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0,
1356 RK3568_CLKGATE_CON(30), 14, GFLAGS),
1357 COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0,
1358 RK3568_CLKSEL_CON(72), 4, 1, MFLAGS,
1359 RK3568_CLKGATE_CON(30), 15, GFLAGS),
1360 GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0,
1361 RK3568_CLKGATE_CON(31), 0, GFLAGS),
1362 COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0,
1363 RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS),
1364 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS),
1365 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0,
1366 RK3568_CLKSEL_CON(72), 8, 1, MFLAGS,
1367 RK3568_CLKGATE_CON(31), 11, GFLAGS),
1368 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
1369 RK3568_CLKGATE_CON(31), 12, GFLAGS),
1370 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0,
1371 RK3568_CLKGATE_CON(31), 13, GFLAGS),
1372 COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0,
1373 RK3568_CLKSEL_CON(72), 10, 1, MFLAGS,
1374 RK3568_CLKGATE_CON(31), 14, GFLAGS),
1375 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
1376 RK3568_CLKGATE_CON(31), 15, GFLAGS),
1377 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0,
1378 RK3568_CLKGATE_CON(32), 0, GFLAGS),
1379 COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0,
1380 RK3568_CLKSEL_CON(72), 12, 1, MFLAGS,
1381 RK3568_CLKGATE_CON(32), 1, GFLAGS),
1382 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
1383 RK3568_CLKGATE_CON(32), 2, GFLAGS),
1384 COMPOSITE_NODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 0,
1385 RK3568_CLKSEL_CON(72), 14, 1, MFLAGS,
1386 RK3568_CLKGATE_CON(32), 11, GFLAGS),
1387 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0,
1388 RK3568_CLKGATE_CON(31), 2, GFLAGS),
1389 GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0,
1390 RK3568_CLKGATE_CON(31), 3, GFLAGS),
1391 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0,
1392 RK3568_CLKGATE_CON(31), 4, GFLAGS),
1393 GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0,
1394 RK3568_CLKGATE_CON(31), 5, GFLAGS),
1395 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0,
1396 RK3568_CLKGATE_CON(31), 6, GFLAGS),
1397 GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0,
1398 RK3568_CLKGATE_CON(31), 7, GFLAGS),
1399 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0,
1400 RK3568_CLKGATE_CON(31), 8, GFLAGS),
1401 GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0,
1402 RK3568_CLKGATE_CON(31), 9, GFLAGS),
1403 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0,
1404 RK3568_CLKGATE_CON(32), 3, GFLAGS),
1405 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
1406 RK3568_CLKGATE_CON(32), 4, GFLAGS),
1407 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
1408 RK3568_CLKGATE_CON(32), 5, GFLAGS),
1409 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
1410 RK3568_CLKGATE_CON(32), 6, GFLAGS),
1411 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
1412 RK3568_CLKGATE_CON(32), 7, GFLAGS),
1413 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
1414 RK3568_CLKGATE_CON(32), 8, GFLAGS),
1415 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
1416 RK3568_CLKGATE_CON(32), 9, GFLAGS),
1419 COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, 0,
1420 RK3568_CLKSEL_CON(73), 0, 2, MFLAGS,
1421 RK3568_CLKGATE_CON(33), 0, GFLAGS),
1422 COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, 0,
1423 RK3568_CLKSEL_CON(73), 4, 2, MFLAGS,
1424 RK3568_CLKGATE_CON(33), 1, GFLAGS),
1425 COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 0,
1426 RK3568_CLKSEL_CON(73), 8, 2, MFLAGS,
1427 RK3568_CLKGATE_CON(33), 2, GFLAGS),
1428 COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 0,
1429 RK3568_CLKSEL_CON(73), 12, 2, MFLAGS,
1430 RK3568_CLKGATE_CON(33), 3, GFLAGS),
1431 GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0,
1432 RK3568_CLKGATE_CON(33), 8, GFLAGS),
1433 COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 0,
1434 RK3568_CLKSEL_CON(73), 15, 1, MFLAGS,
1435 RK3568_CLKGATE_CON(33), 9, GFLAGS),
1436 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0,
1437 RK3568_CLKGATE_CON(33), 13, GFLAGS),
1438 GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0,
1439 RK3568_CLKGATE_CON(33), 14, GFLAGS),
1440 GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0,
1441 RK3568_CLKGATE_CON(33), 15, GFLAGS),
1442 GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0,
1443 RK3568_CLKGATE_CON(34), 4, GFLAGS),
1444 GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0,
1445 RK3568_CLKGATE_CON(34), 5, GFLAGS),
1446 GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0,
1447 RK3568_CLKGATE_CON(34), 6, GFLAGS),
1448 GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0,
1449 RK3568_CLKGATE_CON(34), 11, GFLAGS),
1450 GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0,
1451 RK3568_CLKGATE_CON(34), 12, GFLAGS),
1452 GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0,
1453 RK3568_CLKGATE_CON(34), 13, GFLAGS),
1454 GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0,
1455 RK3568_CLKGATE_CON(34), 14, GFLAGS),
1458 static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = {
1460 FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2),
1461 FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2),
1462 FACTOR(0, "hpll_ph0", "hpll", 0, 1, 2),
1464 MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0,
1465 RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS),
1466 COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", 0,
1467 RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS,
1468 RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS),
1469 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0,
1470 RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS),
1471 GATE(CLK_PMU, "clk_pmu", "xin24m", 0,
1472 RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS),
1473 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
1474 RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS),
1475 COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0,
1476 RK3568_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1477 RK3568_PMU_CLKGATE_CON(1), 1, GFLAGS),
1478 GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0,
1479 RK3568_PMU_CLKGATE_CON(1), 2, GFLAGS),
1481 COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
1482 RK3568_PMU_CLKSEL_CON(1), 0,
1483 RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS,
1484 &rk3568_rtc32k_pmu_fracmux),
1486 COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED,
1487 RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
1488 RK3568_PMU_CLKGATE_CON(0), 0, GFLAGS),
1490 COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0,
1491 RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
1492 RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS),
1493 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
1494 RK3568_PMU_CLKSEL_CON(5), 0,
1495 RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS,
1496 &rk3568_uart0_fracmux),
1497 GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
1498 RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS),
1500 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
1501 RK3568_PMU_CLKGATE_CON(1), 9, GFLAGS),
1502 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", xin24m_32k_p, 0,
1503 RK3568_PMU_CLKSEL_CON(6), 15, 1, MFLAGS,
1504 RK3568_PMU_CLKGATE_CON(1), 10, GFLAGS),
1505 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
1506 RK3568_PMU_CLKGATE_CON(1), 6, GFLAGS),
1507 COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0,
1508 RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
1509 RK3568_PMU_CLKGATE_CON(1), 7, GFLAGS),
1510 GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0,
1511 RK3568_PMU_CLKGATE_CON(1), 8, GFLAGS),
1512 GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
1513 RK3568_PMU_CLKGATE_CON(1), 11, GFLAGS),
1514 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
1515 RK3568_PMU_CLKGATE_CON(1), 12, GFLAGS),
1516 GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
1517 RK3568_PMU_CLKGATE_CON(1), 13, GFLAGS),
1518 COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 0,
1519 RK3568_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
1520 RK3568_PMU_CLKGATE_CON(2), 0, GFLAGS),
1521 GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0,
1522 RK3568_PMU_CLKGATE_CON(2), 1, GFLAGS),
1523 MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0,
1524 RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS),
1525 GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0,
1526 RK3568_PMU_CLKGATE_CON(2), 2, GFLAGS),
1527 MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0,
1528 RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS),
1529 GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0,
1530 RK3568_PMU_CLKGATE_CON(2), 3, GFLAGS),
1531 MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0,
1532 RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS),
1533 GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0,
1534 RK3568_PMU_CLKGATE_CON(2), 4, GFLAGS),
1535 MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0,
1536 RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS),
1537 COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "clk_pdpmu", 0,
1538 RK3568_PMU_CLKSEL_CON(8), 8, 6, DFLAGS,
1539 RK3568_PMU_CLKGATE_CON(2), 5, GFLAGS),
1540 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
1541 RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS),
1542 MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT,
1543 RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS),
1544 COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0,
1545 RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS,
1546 RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS),
1547 GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0,
1548 RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS),
1549 MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT,
1550 RK3568_PMU_CLKSEL_CON(9), 3, 1, MFLAGS),
1551 COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0,
1552 RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS,
1553 RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS),
1554 GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0,
1555 RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS),
1556 MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT,
1557 RK3568_PMU_CLKSEL_CON(9), 7, 1, MFLAGS),
1558 COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0,
1559 RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS,
1560 RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS),
1561 GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0,
1562 RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS),
1563 MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT,
1564 RK3568_PMU_CLKSEL_CON(9), 11, 1, MFLAGS),
1565 GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0,
1566 RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS),
1567 GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0,
1568 RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS),
1569 GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0,
1570 RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS),
1571 MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT,
1572 RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS),
1575 static const char *const rk3568_cru_critical_clocks[] __initconst = {
1586 "aclk_secure_flash",
1587 "hclk_secure_flash",
1588 "aclk_core_niu2bus",
1597 static const char *const rk3568_pmucru_critical_clocks[] __initconst = {
1603 static void __init rk3568_pmu_clk_init(struct device_node *np)
1605 struct rockchip_clk_provider *ctx;
1606 void __iomem *reg_base;
1608 reg_base = of_iomap(np, 0);
1610 pr_err("%s: could not map cru pmu region\n", __func__);
1614 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1616 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1620 rockchip_clk_register_plls(ctx, rk3568_pmu_pll_clks,
1621 ARRAY_SIZE(rk3568_pmu_pll_clks),
1622 RK3568_GRF_SOC_STATUS0);
1624 rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches,
1625 ARRAY_SIZE(rk3568_clk_pmu_branches));
1627 rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0),
1628 ROCKCHIP_SOFTRST_HIWORD_MASK);
1630 rockchip_clk_protect_critical(rk3568_pmucru_critical_clocks,
1631 ARRAY_SIZE(rk3568_pmucru_critical_clocks));
1633 rockchip_clk_of_add_provider(np, ctx);
1636 CLK_OF_DECLARE(rk3568_cru_pmu, "rockchip,rk3568-pmucru", rk3568_pmu_clk_init);
1638 static void __init rk3568_clk_init(struct device_node *np)
1640 struct rockchip_clk_provider *ctx;
1641 void __iomem *reg_base;
1643 reg_base = of_iomap(np, 0);
1645 pr_err("%s: could not map cru region\n", __func__);
1649 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1651 pr_err("%s: rockchip clk init failed\n", __func__);
1656 rockchip_clk_register_plls(ctx, rk3568_pll_clks,
1657 ARRAY_SIZE(rk3568_pll_clks),
1658 RK3568_GRF_SOC_STATUS0);
1660 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1661 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
1662 &rk3568_cpuclk_data, rk3568_cpuclk_rates,
1663 ARRAY_SIZE(rk3568_cpuclk_rates));
1665 rockchip_clk_register_branches(ctx, rk3568_clk_branches,
1666 ARRAY_SIZE(rk3568_clk_branches));
1668 rockchip_register_softrst(np, 30, reg_base + RK3568_SOFTRST_CON(0),
1669 ROCKCHIP_SOFTRST_HIWORD_MASK);
1671 rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST, NULL);
1673 rockchip_clk_protect_critical(rk3568_cru_critical_clocks,
1674 ARRAY_SIZE(rk3568_cru_critical_clocks));
1676 rockchip_clk_of_add_provider(np, ctx);
1679 CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init);
1681 struct clk_rk3568_inits {
1682 void (*inits)(struct device_node *np);
1685 static const struct clk_rk3568_inits clk_rk3568_pmucru_init = {
1686 .inits = rk3568_pmu_clk_init,
1689 static const struct clk_rk3568_inits clk_3568_cru_init = {
1690 .inits = rk3568_clk_init,
1693 static const struct of_device_id clk_rk3568_match_table[] = {
1695 .compatible = "rockchip,rk3568-cru",
1696 .data = &clk_3568_cru_init,
1698 .compatible = "rockchip,rk3568-pmucru",
1699 .data = &clk_rk3568_pmucru_init,
1704 static int __init clk_rk3568_probe(struct platform_device *pdev)
1706 struct device_node *np = pdev->dev.of_node;
1707 const struct clk_rk3568_inits *init_data;
1709 init_data = (struct clk_rk3568_inits *)of_device_get_match_data(&pdev->dev);
1713 if (init_data->inits)
1714 init_data->inits(np);
1719 static struct platform_driver clk_rk3568_driver = {
1721 .name = "clk-rk3568",
1722 .of_match_table = clk_rk3568_match_table,
1723 .suppress_bind_attrs = true,
1726 builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe);
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