drivers/clk/rockchip/clk-rk3308.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
   4  * Author: Finley Xiao <finley.xiao@rock-chips.com>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/io.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/syscore_ops.h>
  12 #include <dt-bindings/clock/rk3308-cru.h>
  13 #include "clk.h"
  14
  15 #define RK3308_GRF_SOC_STATUS0          0x380
  16
  17 enum rk3308_plls {
  18         apll, dpll, vpll0, vpll1,
  19 };
  20
  21 static struct rockchip_pll_rate_table rk3308_pll_rates[] = {
  22         /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  23         RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
  24         RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
  25         RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
  26         RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
  27         RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
  28         RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
  29         RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
  30         RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
  31         RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
  32         RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
  33         RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
  34         RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
  35         RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
  36         RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
  37         RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
  38         RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
  39         RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
  40         RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
  41         RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
  42         RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
  43         RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
  44         RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
  45         RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
  46         RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
  47         RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
  48         RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
  49         RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
  50         RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
  51         RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
  52         RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
  53         RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
  54         RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
  55         RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
  56         RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
  57         RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0),
  58         RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
  59         RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
  60         RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
  61         RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
  62         RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
  63         RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
  64         RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
  65         RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
  66         { /* sentinel */ },
  67 };
  68
  69 #define RK3308_DIV_ACLKM_MASK           0x7
  70 #define RK3308_DIV_ACLKM_SHIFT          12
  71 #define RK3308_DIV_PCLK_DBG_MASK        0xf
  72 #define RK3308_DIV_PCLK_DBG_SHIFT       8
  73
  74 #define RK3308_CLKSEL0(_aclk_core, _pclk_dbg)                           \
  75 {                                                                       \
  76         .reg = RK3308_CLKSEL_CON(0),                                    \
  77         .val = HIWORD_UPDATE(_aclk_core, RK3308_DIV_ACLKM_MASK,         \
  78                              RK3308_DIV_ACLKM_SHIFT) |                  \
  79                HIWORD_UPDATE(_pclk_dbg, RK3308_DIV_PCLK_DBG_MASK,       \
  80                              RK3308_DIV_PCLK_DBG_SHIFT),                \
  81 }
  82
  83 #define RK3308_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg)               \
  84 {                                                                       \
  85         .prate = _prate,                                                \
  86         .divs = {                                                       \
  87                 RK3308_CLKSEL0(_aclk_core, _pclk_dbg),                  \
  88         },                                                              \
  89 }
  90
  91 static struct rockchip_cpuclk_rate_table rk3308_cpuclk_rates[] __initdata = {
  92         RK3308_CPUCLK_RATE(1608000000, 1, 7),
  93         RK3308_CPUCLK_RATE(1512000000, 1, 7),
  94         RK3308_CPUCLK_RATE(1488000000, 1, 5),
  95         RK3308_CPUCLK_RATE(1416000000, 1, 5),
  96         RK3308_CPUCLK_RATE(1392000000, 1, 5),
  97         RK3308_CPUCLK_RATE(1296000000, 1, 5),
  98         RK3308_CPUCLK_RATE(1200000000, 1, 5),
  99         RK3308_CPUCLK_RATE(1104000000, 1, 5),
 100         RK3308_CPUCLK_RATE(1008000000, 1, 5),
 101         RK3308_CPUCLK_RATE(912000000, 1, 5),
 102         RK3308_CPUCLK_RATE(816000000, 1, 3),
 103         RK3308_CPUCLK_RATE(696000000, 1, 3),
 104         RK3308_CPUCLK_RATE(600000000, 1, 3),
 105         RK3308_CPUCLK_RATE(408000000, 1, 1),
 106         RK3308_CPUCLK_RATE(312000000, 1, 1),
 107         RK3308_CPUCLK_RATE(216000000,  1, 1),
 108         RK3308_CPUCLK_RATE(96000000, 1, 1),
 109 };
 110
 111 static const struct rockchip_cpuclk_reg_data rk3308_cpuclk_data = {
 112         .core_reg[0] = RK3308_CLKSEL_CON(0),
 113         .div_core_shift[0] = 0,
 114         .div_core_mask[0] = 0xf,
 115         .num_cores = 1,
 116         .mux_core_alt = 1,
 117         .mux_core_main = 0,
 118         .mux_core_shift = 6,
 119         .mux_core_mask = 0x3,
 120 };
 121
 122 PNAME(mux_pll_p)                = { "xin24m" };
 123 PNAME(mux_usb480m_p)            = { "xin24m", "usb480m_phy", "clk_rtc32k" };
 124 PNAME(mux_armclk_p)             = { "apll_core", "vpll0_core", "vpll1_core" };
 125 PNAME(mux_dpll_vpll0_p)         = { "dpll", "vpll0" };
 126 PNAME(mux_dpll_vpll0_xin24m_p)  = { "dpll", "vpll0", "xin24m" };
 127 PNAME(mux_dpll_vpll0_vpll1_p)   = { "dpll", "vpll0", "vpll1" };
 128 PNAME(mux_dpll_vpll0_vpll1_xin24m_p)    = { "dpll", "vpll0", "vpll1", "xin24m" };
 129 PNAME(mux_dpll_vpll0_vpll1_usb480m_xin24m_p)    = { "dpll", "vpll0", "vpll1", "usb480m", "xin24m" };
 130 PNAME(mux_vpll0_vpll1_p)        = { "vpll0", "vpll1" };
 131 PNAME(mux_vpll0_vpll1_xin24m_p) = { "vpll0", "vpll1", "xin24m" };
 132 PNAME(mux_uart0_p)              = { "clk_uart0_src", "dummy", "clk_uart0_frac" };
 133 PNAME(mux_uart1_p)              = { "clk_uart1_src", "dummy", "clk_uart1_frac" };
 134 PNAME(mux_uart2_p)              = { "clk_uart2_src", "dummy", "clk_uart2_frac" };
 135 PNAME(mux_uart3_p)              = { "clk_uart3_src", "dummy", "clk_uart3_frac" };
 136 PNAME(mux_uart4_p)              = { "clk_uart4_src", "dummy", "clk_uart4_frac" };
 137 PNAME(mux_dclk_vop_p)           = { "dclk_vop_src", "dclk_vop_frac", "xin24m" };
 138 PNAME(mux_nandc_p)              = { "clk_nandc_div", "clk_nandc_div50" };
 139 PNAME(mux_sdmmc_p)              = { "clk_sdmmc_div", "clk_sdmmc_div50" };
 140 PNAME(mux_sdio_p)               = { "clk_sdio_div", "clk_sdio_div50" };
 141 PNAME(mux_emmc_p)               = { "clk_emmc_div", "clk_emmc_div50" };
 142 PNAME(mux_mac_p)                = { "clk_mac_src", "mac_clkin" };
 143 PNAME(mux_mac_rmii_sel_p)       = { "clk_mac_rx_tx_div20", "clk_mac_rx_tx_div2" };
 144 PNAME(mux_ddrstdby_p)           = { "clk_ddrphy1x_out", "clk_ddr_stdby_div4" };
 145 PNAME(mux_rtc32k_p)             = { "xin32k", "clk_pvtm_32k", "clk_rtc32k_frac", "clk_rtc32k_div" };
 146 PNAME(mux_usbphy_ref_p)         = { "xin24m", "clk_usbphy_ref_src" };
 147 PNAME(mux_wifi_src_p)           = { "clk_wifi_dpll", "clk_wifi_vpll0" };
 148 PNAME(mux_wifi_p)               = { "clk_wifi_osc", "clk_wifi_src" };
 149 PNAME(mux_pdm_p)                = { "clk_pdm_src", "clk_pdm_frac" };
 150 PNAME(mux_i2s0_8ch_tx_p)        = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "mclk_i2s0_8ch_in" };
 151 PNAME(mux_i2s0_8ch_tx_rx_p)     = { "clk_i2s0_8ch_tx_mux", "clk_i2s0_8ch_rx_mux"};
 152 PNAME(mux_i2s0_8ch_tx_out_p)    = { "clk_i2s0_8ch_tx", "xin12m" };
 153 PNAME(mux_i2s0_8ch_rx_p)        = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "mclk_i2s0_8ch_in" };
 154 PNAME(mux_i2s0_8ch_rx_tx_p)     = { "clk_i2s0_8ch_rx_mux", "clk_i2s0_8ch_tx_mux"};
 155 PNAME(mux_i2s1_8ch_tx_p)        = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "mclk_i2s1_8ch_in" };
 156 PNAME(mux_i2s1_8ch_tx_rx_p)     = { "clk_i2s1_8ch_tx_mux", "clk_i2s1_8ch_rx_mux"};
 157 PNAME(mux_i2s1_8ch_tx_out_p)    = { "clk_i2s1_8ch_tx", "xin12m" };
 158 PNAME(mux_i2s1_8ch_rx_p)        = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "mclk_i2s1_8ch_in" };
 159 PNAME(mux_i2s1_8ch_rx_tx_p)     = { "clk_i2s1_8ch_rx_mux", "clk_i2s1_8ch_tx_mux"};
 160 PNAME(mux_i2s2_8ch_tx_p)        = { "clk_i2s2_8ch_tx_src", "clk_i2s2_8ch_tx_frac", "mclk_i2s2_8ch_in" };
 161 PNAME(mux_i2s2_8ch_tx_rx_p)     = { "clk_i2s2_8ch_tx_mux", "clk_i2s2_8ch_rx_mux"};
 162 PNAME(mux_i2s2_8ch_tx_out_p)    = { "clk_i2s2_8ch_tx", "xin12m" };
 163 PNAME(mux_i2s2_8ch_rx_p)        = { "clk_i2s2_8ch_rx_src", "clk_i2s2_8ch_rx_frac", "mclk_i2s2_8ch_in" };
 164 PNAME(mux_i2s2_8ch_rx_tx_p)     = { "clk_i2s2_8ch_rx_mux", "clk_i2s2_8ch_tx_mux"};
 165 PNAME(mux_i2s3_8ch_tx_p)        = { "clk_i2s3_8ch_tx_src", "clk_i2s3_8ch_tx_frac", "mclk_i2s3_8ch_in" };
 166 PNAME(mux_i2s3_8ch_tx_rx_p)     = { "clk_i2s3_8ch_tx_mux", "clk_i2s3_8ch_rx_mux"};
 167 PNAME(mux_i2s3_8ch_tx_out_p)    = { "clk_i2s3_8ch_tx", "xin12m" };
 168 PNAME(mux_i2s3_8ch_rx_p)        = { "clk_i2s3_8ch_rx_src", "clk_i2s3_8ch_rx_frac", "mclk_i2s3_8ch_in" };
 169 PNAME(mux_i2s3_8ch_rx_tx_p)     = { "clk_i2s3_8ch_rx_mux", "clk_i2s3_8ch_tx_mux"};
 170 PNAME(mux_i2s0_2ch_p)           = { "clk_i2s0_2ch_src", "clk_i2s0_2ch_frac", "mclk_i2s0_2ch_in" };
 171 PNAME(mux_i2s0_2ch_out_p)       = { "clk_i2s0_2ch", "xin12m" };
 172 PNAME(mux_i2s1_2ch_p)           = { "clk_i2s1_2ch_src", "clk_i2s1_2ch_frac", "mclk_i2s1_2ch_in"};
 173 PNAME(mux_i2s1_2ch_out_p)       = { "clk_i2s1_2ch", "xin12m" };
 174 PNAME(mux_spdif_tx_src_p)       = { "clk_spdif_tx_div", "clk_spdif_tx_div50" };
 175 PNAME(mux_spdif_tx_p)           = { "clk_spdif_tx_src", "clk_spdif_tx_frac", "mclk_i2s0_2ch_in" };
 176 PNAME(mux_spdif_rx_src_p)       = { "clk_spdif_rx_div", "clk_spdif_rx_div50" };
 177 PNAME(mux_spdif_rx_p)           = { "clk_spdif_rx_src", "clk_spdif_rx_frac" };
 178
 179 static struct rockchip_pll_clock rk3308_pll_clks[] __initdata = {
 180         [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
 181                      0, RK3308_PLL_CON(0),
 182                      RK3308_MODE_CON, 0, 0, 0, rk3308_pll_rates),
 183         [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
 184                      0, RK3308_PLL_CON(8),
 185                      RK3308_MODE_CON, 2, 1, 0, rk3308_pll_rates),
 186         [vpll0] = PLL(pll_rk3328, PLL_VPLL0, "vpll0", mux_pll_p,
 187                      0, RK3308_PLL_CON(16),
 188                      RK3308_MODE_CON, 4, 2, 0, rk3308_pll_rates),
 189         [vpll1] = PLL(pll_rk3328, PLL_VPLL1, "vpll1", mux_pll_p,
 190                      0, RK3308_PLL_CON(24),
 191                      RK3308_MODE_CON, 6, 3, 0, rk3308_pll_rates),
 192 };
 193
 194 #define MFLAGS CLK_MUX_HIWORD_MASK
 195 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
 196 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
 197
 198 static struct rockchip_clk_branch rk3308_uart0_fracmux __initdata =
 199         MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
 200                         RK3308_CLKSEL_CON(11), 14, 2, MFLAGS);
 201
 202 static struct rockchip_clk_branch rk3308_uart1_fracmux __initdata =
 203         MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
 204                         RK3308_CLKSEL_CON(14), 14, 2, MFLAGS);
 205
 206 static struct rockchip_clk_branch rk3308_uart2_fracmux __initdata =
 207         MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
 208                         RK3308_CLKSEL_CON(17), 14, 2, MFLAGS);
 209
 210 static struct rockchip_clk_branch rk3308_uart3_fracmux __initdata =
 211         MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
 212                         RK3308_CLKSEL_CON(20), 14, 2, MFLAGS);
 213
 214 static struct rockchip_clk_branch rk3308_uart4_fracmux __initdata =
 215         MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
 216                         RK3308_CLKSEL_CON(23), 14, 2, MFLAGS);
 217
 218 static struct rockchip_clk_branch rk3308_dclk_vop_fracmux __initdata =
 219         MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
 220                         RK3308_CLKSEL_CON(8), 14, 2, MFLAGS);
 221
 222 static struct rockchip_clk_branch rk3308_rtc32k_fracmux __initdata =
 223         MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
 224                         RK3308_CLKSEL_CON(2), 8, 2, MFLAGS);
 225
 226 static struct rockchip_clk_branch rk3308_pdm_fracmux __initdata =
 227         MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
 228                         RK3308_CLKSEL_CON(46), 15, 1, MFLAGS);
 229
 230 static struct rockchip_clk_branch rk3308_i2s0_8ch_tx_fracmux __initdata =
 231         MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
 232                         RK3308_CLKSEL_CON(52), 10, 2, MFLAGS);
 233
 234 static struct rockchip_clk_branch rk3308_i2s0_8ch_rx_fracmux __initdata =
 235         MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
 236                         RK3308_CLKSEL_CON(54), 10, 2, MFLAGS);
 237
 238 static struct rockchip_clk_branch rk3308_i2s1_8ch_tx_fracmux __initdata =
 239         MUX(SCLK_I2S1_8CH_TX_MUX, "clk_i2s1_8ch_tx_mux", mux_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
 240                         RK3308_CLKSEL_CON(56), 10, 2, MFLAGS);
 241
 242 static struct rockchip_clk_branch rk3308_i2s1_8ch_rx_fracmux __initdata =
 243         MUX(SCLK_I2S1_8CH_RX_MUX, "clk_i2s1_8ch_rx_mux", mux_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
 244                         RK3308_CLKSEL_CON(58), 10, 2, MFLAGS);
 245
 246 static struct rockchip_clk_branch rk3308_i2s2_8ch_tx_fracmux __initdata =
 247         MUX(SCLK_I2S2_8CH_TX_MUX, "clk_i2s2_8ch_tx_mux", mux_i2s2_8ch_tx_p, CLK_SET_RATE_PARENT,
 248                         RK3308_CLKSEL_CON(60), 10, 2, MFLAGS);
 249
 250 static struct rockchip_clk_branch rk3308_i2s2_8ch_rx_fracmux __initdata =
 251         MUX(SCLK_I2S2_8CH_RX_MUX, "clk_i2s2_8ch_rx_mux", mux_i2s2_8ch_rx_p, CLK_SET_RATE_PARENT,
 252                         RK3308_CLKSEL_CON(62), 10, 2, MFLAGS);
 253
 254 static struct rockchip_clk_branch rk3308_i2s3_8ch_tx_fracmux __initdata =
 255         MUX(SCLK_I2S3_8CH_TX_MUX, "clk_i2s3_8ch_tx_mux", mux_i2s3_8ch_tx_p, CLK_SET_RATE_PARENT,
 256                         RK3308_CLKSEL_CON(64), 10, 2, MFLAGS);
 257
 258 static struct rockchip_clk_branch rk3308_i2s3_8ch_rx_fracmux __initdata =
 259         MUX(SCLK_I2S3_8CH_RX_MUX, "clk_i2s3_8ch_rx_mux", mux_i2s3_8ch_rx_p, CLK_SET_RATE_PARENT,
 260                         RK3308_CLKSEL_CON(66), 10, 2, MFLAGS);
 261
 262 static struct rockchip_clk_branch rk3308_i2s0_2ch_fracmux __initdata =
 263         MUX(0, "clk_i2s0_2ch_mux", mux_i2s0_2ch_p, CLK_SET_RATE_PARENT,
 264                         RK3308_CLKSEL_CON(68), 10, 2, MFLAGS);
 265
 266 static struct rockchip_clk_branch rk3308_i2s1_2ch_fracmux __initdata =
 267         MUX(0, "clk_i2s1_2ch_mux", mux_i2s1_2ch_p, CLK_SET_RATE_PARENT,
 268                         RK3308_CLKSEL_CON(70), 10, 2, MFLAGS);
 269
 270 static struct rockchip_clk_branch rk3308_spdif_tx_fracmux __initdata =
 271         MUX(0, "clk_spdif_tx_mux", mux_spdif_tx_p, CLK_SET_RATE_PARENT,
 272                         RK3308_CLKSEL_CON(48), 14, 2, MFLAGS);
 273
 274 static struct rockchip_clk_branch rk3308_spdif_rx_fracmux __initdata =
 275         MUX(0, "clk_spdif_rx_mux", mux_spdif_rx_p, CLK_SET_RATE_PARENT,
 276                         RK3308_CLKSEL_CON(50), 15, 1, MFLAGS);
 277
 278
 279 static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
 280         /*
 281          * Clock-Architecture Diagram 1
 282          */
 283
 284         MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
 285                         RK3308_MODE_CON, 8, 2, MFLAGS),
 286         FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
 287
 288         /*
 289          * Clock-Architecture Diagram 2
 290          */
 291
 292         GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
 293                         RK3308_CLKGATE_CON(0), 0, GFLAGS),
 294         GATE(0, "vpll0_core", "vpll0", CLK_IGNORE_UNUSED,
 295                         RK3308_CLKGATE_CON(0), 0, GFLAGS),
 296         GATE(0, "vpll1_core", "vpll1", CLK_IGNORE_UNUSED,
 297                         RK3308_CLKGATE_CON(0), 0, GFLAGS),
 298         COMPOSITE_NOMUX(0, "pclk_core_dbg", "armclk", CLK_IGNORE_UNUSED,
 299                         RK3308_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
 300                         RK3308_CLKGATE_CON(0), 2, GFLAGS),
 301         COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
 302                         RK3308_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 303                         RK3308_CLKGATE_CON(0), 1, GFLAGS),
 304
 305         GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
 306                         RK3308_CLKGATE_CON(0), 3, GFLAGS),
 307
 308         GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
 309                         RK3308_CLKGATE_CON(0), 4, GFLAGS),
 310
 311         /*
 312          * Clock-Architecture Diagram 3
 313          */
 314
 315         COMPOSITE_NODIV(ACLK_BUS_SRC, "clk_bus_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
 316                         RK3308_CLKSEL_CON(5), 6, 2, MFLAGS,
 317                         RK3308_CLKGATE_CON(1), 0, GFLAGS),
 318         COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
 319                         RK3308_CLKSEL_CON(6), 8, 5, DFLAGS,
 320                         RK3308_CLKGATE_CON(1), 3, GFLAGS),
 321         GATE(PCLK_DDR, "pclk_ddr", "pclk_bus", CLK_IGNORE_UNUSED,
 322                         RK3308_CLKGATE_CON(4), 15, GFLAGS),
 323         COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
 324                         RK3308_CLKSEL_CON(6), 0, 5, DFLAGS,
 325                         RK3308_CLKGATE_CON(1), 2, GFLAGS),
 326         COMPOSITE_NOMUX(ACLK_BUS, "aclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
 327                         RK3308_CLKSEL_CON(5), 0, 5, DFLAGS,
 328                         RK3308_CLKGATE_CON(1), 1, GFLAGS),
 329
 330         COMPOSITE(0, "clk_uart0_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
 331                         RK3308_CLKSEL_CON(10), 13, 3, MFLAGS, 0, 5, DFLAGS,
 332                         RK3308_CLKGATE_CON(1), 9, GFLAGS),
 333         COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
 334                         RK3308_CLKSEL_CON(12), 0,
 335                         RK3308_CLKGATE_CON(1), 11, GFLAGS,
 336                         &rk3308_uart0_fracmux),
 337         GATE(SCLK_UART0, "clk_uart0", "clk_uart0_mux", 0,
 338                         RK3308_CLKGATE_CON(1), 12, GFLAGS),
 339
 340         COMPOSITE(0, "clk_uart1_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
 341                         RK3308_CLKSEL_CON(13), 13, 3, MFLAGS, 0, 5, DFLAGS,
 342                         RK3308_CLKGATE_CON(1), 13, GFLAGS),
 343         COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
 344                         RK3308_CLKSEL_CON(15), 0,
 345                         RK3308_CLKGATE_CON(1), 15, GFLAGS,
 346                         &rk3308_uart1_fracmux),
 347         GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
 348                         RK3308_CLKGATE_CON(2), 0, GFLAGS),
 349
 350         COMPOSITE(0, "clk_uart2_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
 351                         RK3308_CLKSEL_CON(16), 13, 3, MFLAGS, 0, 5, DFLAGS,
 352                         RK3308_CLKGATE_CON(2), 1, GFLAGS),
 353         COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
 354                         RK3308_CLKSEL_CON(18), 0,
 355                         RK3308_CLKGATE_CON(2), 3, GFLAGS,
 356                         &rk3308_uart2_fracmux),
 357         GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
 358                         RK3308_CLKGATE_CON(2), 4, GFLAGS),
 359
 360         COMPOSITE(0, "clk_uart3_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
 361                         RK3308_CLKSEL_CON(19), 13, 3, MFLAGS, 0, 5, DFLAGS,
 362                         RK3308_CLKGATE_CON(2), 5, GFLAGS),
 363         COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
 364                         RK3308_CLKSEL_CON(21), 0,
 365                         RK3308_CLKGATE_CON(2), 7, GFLAGS,
 366                         &rk3308_uart3_fracmux),
 367         GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
 368                         RK3308_CLKGATE_CON(2), 8, GFLAGS),
 369
 370         COMPOSITE(0, "clk_uart4_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
 371                         RK3308_CLKSEL_CON(22), 13, 3, MFLAGS, 0, 5, DFLAGS,
 372                         RK3308_CLKGATE_CON(2), 9, GFLAGS),
 373         COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
 374                         RK3308_CLKSEL_CON(24), 0,
 375                         RK3308_CLKGATE_CON(2), 11, GFLAGS,
 376                         &rk3308_uart4_fracmux),
 377         GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
 378                         RK3308_CLKGATE_CON(2), 12, GFLAGS),
 379
 380         COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_dpll_vpll0_xin24m_p, 0,
 381                         RK3308_CLKSEL_CON(25), 14, 2, MFLAGS, 0, 7, DFLAGS,
 382                         RK3308_CLKGATE_CON(2), 13, GFLAGS),
 383         COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_dpll_vpll0_xin24m_p, 0,
 384                         RK3308_CLKSEL_CON(26), 14, 2, MFLAGS, 0, 7, DFLAGS,
 385                         RK3308_CLKGATE_CON(2), 14, GFLAGS),
 386         COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_dpll_vpll0_xin24m_p, 0,
 387                         RK3308_CLKSEL_CON(27), 14, 2, MFLAGS, 0, 7, DFLAGS,
 388                         RK3308_CLKGATE_CON(2), 15, GFLAGS),
 389         COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_dpll_vpll0_xin24m_p, 0,
 390                         RK3308_CLKSEL_CON(28), 14, 2, MFLAGS, 0, 7, DFLAGS,
 391                         RK3308_CLKGATE_CON(3), 0, GFLAGS),
 392
 393         COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 0,
 394                         RK3308_CLKSEL_CON(29), 14, 2, MFLAGS, 0, 7, DFLAGS,
 395                         RK3308_CLKGATE_CON(3), 1, GFLAGS),
 396         COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_dpll_vpll0_xin24m_p, 0,
 397                         RK3308_CLKSEL_CON(74), 14, 2, MFLAGS, 0, 7, DFLAGS,
 398                         RK3308_CLKGATE_CON(15), 0, GFLAGS),
 399         COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_dpll_vpll0_xin24m_p, 0,
 400                         RK3308_CLKSEL_CON(75), 14, 2, MFLAGS, 0, 7, DFLAGS,
 401                         RK3308_CLKGATE_CON(15), 1, GFLAGS),
 402
 403         COMPOSITE(SCLK_SPI0, "clk_spi0", mux_dpll_vpll0_xin24m_p, 0,
 404                         RK3308_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 7, DFLAGS,
 405                         RK3308_CLKGATE_CON(3), 2, GFLAGS),
 406         COMPOSITE(SCLK_SPI1, "clk_spi1", mux_dpll_vpll0_xin24m_p, 0,
 407                         RK3308_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 7, DFLAGS,
 408                         RK3308_CLKGATE_CON(3), 3, GFLAGS),
 409         COMPOSITE(SCLK_SPI2, "clk_spi2", mux_dpll_vpll0_xin24m_p, 0,
 410                         RK3308_CLKSEL_CON(32), 14, 2, MFLAGS, 0, 7, DFLAGS,
 411                         RK3308_CLKGATE_CON(3), 4, GFLAGS),
 412
 413         GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
 414                         RK3308_CLKGATE_CON(3), 10, GFLAGS),
 415         GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
 416                         RK3308_CLKGATE_CON(3), 11, GFLAGS),
 417         GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
 418                         RK3308_CLKGATE_CON(3), 12, GFLAGS),
 419         GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
 420                         RK3308_CLKGATE_CON(3), 13, GFLAGS),
 421         GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
 422                         RK3308_CLKGATE_CON(3), 14, GFLAGS),
 423         GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
 424                         RK3308_CLKGATE_CON(3), 15, GFLAGS),
 425
 426         COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
 427                         RK3308_CLKSEL_CON(33), 0, 11, DFLAGS,
 428                         RK3308_CLKGATE_CON(3), 5, GFLAGS),
 429         COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
 430                         RK3308_CLKSEL_CON(34), 0, 11, DFLAGS,
 431                         RK3308_CLKGATE_CON(3), 6, GFLAGS),
 432
 433         COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
 434                         RK3308_CLKSEL_CON(35), 0, 4, DFLAGS,
 435                         RK3308_CLKGATE_CON(3), 7, GFLAGS),
 436         COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
 437                         RK3308_CLKSEL_CON(35), 4, 2, DFLAGS,
 438                         RK3308_CLKGATE_CON(3), 8, GFLAGS),
 439
 440         GATE(SCLK_CPU_BOOST, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
 441                         RK3308_CLKGATE_CON(3), 9, GFLAGS),
 442
 443         COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_dpll_vpll0_vpll1_p, 0,
 444                         RK3308_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
 445                         RK3308_CLKGATE_CON(1), 4, GFLAGS),
 446         COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_dpll_vpll0_vpll1_p, 0,
 447                         RK3308_CLKSEL_CON(7), 14, 2, MFLAGS, 8, 5, DFLAGS,
 448                         RK3308_CLKGATE_CON(1), 5, GFLAGS),
 449
 450         COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 0,
 451                         RK3308_CLKSEL_CON(8), 10, 2, MFLAGS, 0, 8, DFLAGS,
 452                         RK3308_CLKGATE_CON(1), 6, GFLAGS),
 453         COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
 454                         RK3308_CLKSEL_CON(9), 0,
 455                         RK3308_CLKGATE_CON(1), 7, GFLAGS,
 456                         &rk3308_dclk_vop_fracmux),
 457         GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
 458                         RK3308_CLKGATE_CON(1), 8, GFLAGS),
 459
 460         /*
 461          * Clock-Architecture Diagram 4
 462          */
 463
 464         COMPOSITE_NODIV(ACLK_PERI_SRC, "clk_peri_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
 465                         RK3308_CLKSEL_CON(36), 6, 2, MFLAGS,
 466                         RK3308_CLKGATE_CON(8), 0, GFLAGS),
 467         COMPOSITE_NOMUX(ACLK_PERI, "aclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
 468                         RK3308_CLKSEL_CON(36), 0, 5, DFLAGS,
 469                         RK3308_CLKGATE_CON(8), 1, GFLAGS),
 470         COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
 471                         RK3308_CLKSEL_CON(37), 0, 5, DFLAGS,
 472                         RK3308_CLKGATE_CON(8), 2, GFLAGS),
 473         COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
 474                         RK3308_CLKSEL_CON(37), 8, 5, DFLAGS,
 475                         RK3308_CLKGATE_CON(8), 3, GFLAGS),
 476
 477         COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
 478                         RK3308_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
 479                         RK3308_CLKGATE_CON(8), 4, GFLAGS),
 480         COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
 481                         RK3308_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
 482                         RK3308_CLKGATE_CON(8), 4, GFLAGS),
 483         COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 484                         RK3308_CLKSEL_CON(38), 15, 1, MFLAGS,
 485                         RK3308_CLKGATE_CON(8), 5, GFLAGS),
 486
 487         COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
 488                         RK3308_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS,
 489                         RK3308_CLKGATE_CON(8), 6, GFLAGS),
 490         COMPOSITE(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
 491                         RK3308_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS,
 492                         RK3308_CLKGATE_CON(8), 6, GFLAGS),
 493         COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 494                         RK3308_CLKSEL_CON(39), 15, 1, MFLAGS,
 495                         RK3308_CLKGATE_CON(8), 7, GFLAGS),
 496         MMC(SCLK_SDMMC_DRV,     "sdmmc_drv",    "clk_sdmmc", RK3308_SDMMC_CON0, 1),
 497         MMC(SCLK_SDMMC_SAMPLE,  "sdmmc_sample", "clk_sdmmc", RK3308_SDMMC_CON1, 1),
 498
 499         COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
 500                         RK3308_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS,
 501                         RK3308_CLKGATE_CON(8), 8, GFLAGS),
 502         COMPOSITE(SCLK_SDIO_DIV50, "clk_sdio_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
 503                         RK3308_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS,
 504                         RK3308_CLKGATE_CON(8), 8, GFLAGS),
 505         COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 506                         RK3308_CLKSEL_CON(40), 15, 1, MFLAGS,
 507                         RK3308_CLKGATE_CON(8), 9, GFLAGS),
 508         MMC(SCLK_SDIO_DRV,              "sdio_drv",    "clk_sdio",      RK3308_SDIO_CON0,  1),
 509         MMC(SCLK_SDIO_SAMPLE,   "sdio_sample", "clk_sdio",      RK3308_SDIO_CON1,  1),
 510
 511         COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
 512                         RK3308_CLKSEL_CON(41), 8, 2, MFLAGS, 0, 8, DFLAGS,
 513                         RK3308_CLKGATE_CON(8), 10, GFLAGS),
 514         COMPOSITE(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
 515                         RK3308_CLKSEL_CON(41), 8, 2, MFLAGS, 0, 8, DFLAGS,
 516                         RK3308_CLKGATE_CON(8), 10, GFLAGS),
 517         COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 518                         RK3308_CLKSEL_CON(41), 15, 1, MFLAGS,
 519                         RK3308_CLKGATE_CON(8), 11, GFLAGS),
 520         MMC(SCLK_EMMC_DRV,     "emmc_drv",     "clk_emmc",  RK3308_EMMC_CON0,  1),
 521         MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "clk_emmc",  RK3308_EMMC_CON1,  1),
 522
 523         COMPOSITE(SCLK_SFC, "clk_sfc", mux_dpll_vpll0_vpll1_p, 0,
 524                         RK3308_CLKSEL_CON(42), 14, 2, MFLAGS, 0, 7, DFLAGS,
 525                         RK3308_CLKGATE_CON(8), 12, GFLAGS),
 526
 527         GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k", 0,
 528                         RK3308_CLKGATE_CON(8), 13, GFLAGS),
 529
 530         COMPOSITE(SCLK_MAC_SRC, "clk_mac_src", mux_dpll_vpll0_vpll1_p, 0,
 531                         RK3308_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
 532                         RK3308_CLKGATE_CON(8), 14, GFLAGS),
 533         MUX(SCLK_MAC, "clk_mac", mux_mac_p,  CLK_SET_RATE_PARENT,
 534                         RK3308_CLKSEL_CON(43), 14, 1, MFLAGS),
 535         GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_mac", 0,
 536                         RK3308_CLKGATE_CON(9), 1, GFLAGS),
 537         GATE(SCLK_MAC_RX_TX, "clk_mac_rx_tx", "clk_mac", 0,
 538                         RK3308_CLKGATE_CON(9), 0, GFLAGS),
 539         FACTOR(0, "clk_mac_rx_tx_div2", "clk_mac_rx_tx", 0, 1, 2),
 540         FACTOR(0, "clk_mac_rx_tx_div20", "clk_mac_rx_tx", 0, 1, 20),
 541         MUX(SCLK_MAC_RMII, "clk_mac_rmii_sel", mux_mac_rmii_sel_p,  CLK_SET_RATE_PARENT,
 542                         RK3308_CLKSEL_CON(43), 15, 1, MFLAGS),
 543
 544         COMPOSITE(SCLK_OWIRE, "clk_owire", mux_dpll_vpll0_xin24m_p, 0,
 545                         RK3308_CLKSEL_CON(44), 14, 2, MFLAGS, 8, 6, DFLAGS,
 546                         RK3308_CLKGATE_CON(8), 15, GFLAGS),
 547
 548         /*
 549          * Clock-Architecture Diagram 5
 550          */
 551
 552         GATE(0, "clk_ddr_mon_timer", "xin24m", CLK_IGNORE_UNUSED,
 553                         RK3308_CLKGATE_CON(0), 12, GFLAGS),
 554
 555         GATE(0, "clk_ddr_mon", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
 556                         RK3308_CLKGATE_CON(4), 10, GFLAGS),
 557         GATE(0, "clk_ddr_upctrl", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
 558                         RK3308_CLKGATE_CON(4), 11, GFLAGS),
 559         GATE(0, "clk_ddr_msch", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
 560                         RK3308_CLKGATE_CON(4), 12, GFLAGS),
 561         GATE(0, "clk_ddr_msch_peribus", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
 562                         RK3308_CLKGATE_CON(4), 13, GFLAGS),
 563
 564         COMPOSITE(SCLK_DDRCLK, "clk_ddrphy4x_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
 565                         RK3308_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 3, DFLAGS,
 566                         RK3308_CLKGATE_CON(0), 10, GFLAGS),
 567         GATE(0, "clk_ddrphy4x", "clk_ddrphy4x_src", CLK_IGNORE_UNUSED,
 568                         RK3308_CLKGATE_CON(0), 11, GFLAGS),
 569         FACTOR_GATE(0, "clk_ddr_stdby_div4", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
 570                         RK3308_CLKGATE_CON(0), 13, GFLAGS),
 571         COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED,
 572                         RK3308_CLKSEL_CON(1), 8, 1, MFLAGS,
 573                         RK3308_CLKGATE_CON(4), 14, GFLAGS),
 574
 575         /*
 576          * Clock-Architecture Diagram 6
 577          */
 578
 579         GATE(PCLK_PMU, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED,
 580                         RK3308_CLKGATE_CON(4), 5, GFLAGS),
 581         GATE(SCLK_PMU, "clk_pmu", "pclk_bus", CLK_IGNORE_UNUSED,
 582                         RK3308_CLKGATE_CON(4), 6, GFLAGS),
 583
 584         COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
 585                         RK3308_CLKSEL_CON(3), 0,
 586                         RK3308_CLKGATE_CON(4), 3, GFLAGS,
 587                         &rk3308_rtc32k_fracmux),
 588         MUX(0, "clk_rtc32k_div_src", mux_vpll0_vpll1_p, 0,
 589                         RK3308_CLKSEL_CON(2), 10, 1, MFLAGS),
 590         COMPOSITE_NOMUX(0, "clk_rtc32k_div", "clk_rtc32k_div_src", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
 591                         RK3308_CLKSEL_CON(4), 0, 16, DFLAGS,
 592                         RK3308_CLKGATE_CON(4), 2, GFLAGS),
 593
 594         COMPOSITE(0, "clk_usbphy_ref_src", mux_dpll_vpll0_p, 0,
 595                         RK3308_CLKSEL_CON(72), 6, 1, MFLAGS, 0, 6, DFLAGS,
 596                         RK3308_CLKGATE_CON(4), 7, GFLAGS),
 597         COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT,
 598                         RK3308_CLKSEL_CON(72), 7, 1, MFLAGS,
 599                         RK3308_CLKGATE_CON(4), 8, GFLAGS),
 600
 601         GATE(0, "clk_wifi_dpll", "dpll", 0,
 602                         RK3308_CLKGATE_CON(15), 2, GFLAGS),
 603         GATE(0, "clk_wifi_vpll0", "vpll0", 0,
 604                         RK3308_CLKGATE_CON(15), 3, GFLAGS),
 605         GATE(0, "clk_wifi_osc", "xin24m", 0,
 606                         RK3308_CLKGATE_CON(15), 4, GFLAGS),
 607         COMPOSITE(0, "clk_wifi_src", mux_wifi_src_p, 0,
 608                         RK3308_CLKSEL_CON(44), 6, 1, MFLAGS, 0, 6, DFLAGS,
 609                         RK3308_CLKGATE_CON(4), 0, GFLAGS),
 610         COMPOSITE_NODIV(SCLK_WIFI, "clk_wifi", mux_wifi_p, CLK_SET_RATE_PARENT,
 611                         RK3308_CLKSEL_CON(44), 7, 1, MFLAGS,
 612                         RK3308_CLKGATE_CON(4), 1, GFLAGS),
 613
 614         GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
 615                         RK3308_CLKGATE_CON(4), 4, GFLAGS),
 616
 617         /*
 618          * Clock-Architecture Diagram 7
 619          */
 620
 621         COMPOSITE_NODIV(0, "clk_audio_src", mux_vpll0_vpll1_xin24m_p, 0,
 622                         RK3308_CLKSEL_CON(45), 6, 2, MFLAGS,
 623                         RK3308_CLKGATE_CON(10), 0, GFLAGS),
 624         COMPOSITE_NOMUX(HCLK_AUDIO, "hclk_audio", "clk_audio_src", 0,
 625                         RK3308_CLKSEL_CON(45), 0, 5, DFLAGS,
 626                         RK3308_CLKGATE_CON(10), 1, GFLAGS),
 627         COMPOSITE_NOMUX(PCLK_AUDIO, "pclk_audio", "clk_audio_src", 0,
 628                         RK3308_CLKSEL_CON(45), 8, 5, DFLAGS,
 629                         RK3308_CLKGATE_CON(10), 2, GFLAGS),
 630
 631         COMPOSITE(0, "clk_pdm_src", mux_vpll0_vpll1_xin24m_p, 0,
 632                         RK3308_CLKSEL_CON(46), 8, 2, MFLAGS, 0, 7, DFLAGS,
 633                         RK3308_CLKGATE_CON(10), 3, GFLAGS),
 634         COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
 635                         RK3308_CLKSEL_CON(47), 0,
 636                         RK3308_CLKGATE_CON(10), 4, GFLAGS,
 637                         &rk3308_pdm_fracmux),
 638         GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 0,
 639                         RK3308_CLKGATE_CON(10), 5, GFLAGS),
 640
 641         COMPOSITE(SCLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
 642                         RK3308_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS,
 643                         RK3308_CLKGATE_CON(10), 12, GFLAGS),
 644         COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
 645                         RK3308_CLKSEL_CON(53), 0,
 646                         RK3308_CLKGATE_CON(10), 13, GFLAGS,
 647                         &rk3308_i2s0_8ch_tx_fracmux),
 648         COMPOSITE_NODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
 649                         RK3308_CLKSEL_CON(52), 12, 1, MFLAGS,
 650                         RK3308_CLKGATE_CON(10), 14, GFLAGS),
 651         COMPOSITE_NODIV(SCLK_I2S0_8CH_TX_OUT, "clk_i2s0_8ch_tx_out", mux_i2s0_8ch_tx_out_p, CLK_SET_RATE_PARENT,
 652                         RK3308_CLKSEL_CON(52), 15, 1, MFLAGS,
 653                         RK3308_CLKGATE_CON(10), 15, GFLAGS),
 654
 655         COMPOSITE(SCLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
 656                         RK3308_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS,
 657                         RK3308_CLKGATE_CON(11), 0, GFLAGS),
 658         COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
 659                         RK3308_CLKSEL_CON(55), 0,
 660                         RK3308_CLKGATE_CON(11), 1, GFLAGS,
 661                         &rk3308_i2s0_8ch_rx_fracmux),
 662         COMPOSITE_NODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
 663                         RK3308_CLKSEL_CON(54), 12, 1, MFLAGS,
 664                         RK3308_CLKGATE_CON(11), 2, GFLAGS),
 665         GATE(SCLK_I2S0_8CH_RX_OUT, "clk_i2s0_8ch_rx_out", "clk_i2s0_8ch_rx", 0,
 666                         RK3308_CLKGATE_CON(11), 3, GFLAGS),
 667
 668         COMPOSITE(SCLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
 669                         RK3308_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS,
 670                         RK3308_CLKGATE_CON(11), 4, GFLAGS),
 671         COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
 672                         RK3308_CLKSEL_CON(57), 0,
 673                         RK3308_CLKGATE_CON(11), 5, GFLAGS,
 674                         &rk3308_i2s1_8ch_tx_fracmux),
 675         COMPOSITE_NODIV(SCLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", mux_i2s1_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
 676                         RK3308_CLKSEL_CON(56), 12, 1, MFLAGS,
 677                         RK3308_CLKGATE_CON(11), 6, GFLAGS),
 678         COMPOSITE_NODIV(SCLK_I2S1_8CH_TX_OUT, "clk_i2s1_8ch_tx_out", mux_i2s1_8ch_tx_out_p, CLK_SET_RATE_PARENT,
 679                         RK3308_CLKSEL_CON(56), 15, 1, MFLAGS,
 680                         RK3308_CLKGATE_CON(11), 7, GFLAGS),
 681
 682         COMPOSITE(SCLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
 683                         RK3308_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS,
 684                         RK3308_CLKGATE_CON(11), 8, GFLAGS),
 685         COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
 686                         RK3308_CLKSEL_CON(59), 0,
 687                         RK3308_CLKGATE_CON(11), 9, GFLAGS,
 688                         &rk3308_i2s1_8ch_rx_fracmux),
 689         COMPOSITE_NODIV(SCLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", mux_i2s1_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
 690                         RK3308_CLKSEL_CON(58), 12, 1, MFLAGS,
 691                         RK3308_CLKGATE_CON(11), 10, GFLAGS),
 692         GATE(SCLK_I2S1_8CH_RX_OUT, "clk_i2s1_8ch_rx_out", "clk_i2s1_8ch_rx", 0,
 693                         RK3308_CLKGATE_CON(11), 11, GFLAGS),
 694
 695         COMPOSITE(SCLK_I2S2_8CH_TX_SRC, "clk_i2s2_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
 696                         RK3308_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS,
 697                         RK3308_CLKGATE_CON(11), 12, GFLAGS),
 698         COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_tx_frac", "clk_i2s2_8ch_tx_src", CLK_SET_RATE_PARENT,
 699                         RK3308_CLKSEL_CON(61), 0,
 700                         RK3308_CLKGATE_CON(11), 13, GFLAGS,
 701                         &rk3308_i2s2_8ch_tx_fracmux),
 702         COMPOSITE_NODIV(SCLK_I2S2_8CH_TX, "clk_i2s2_8ch_tx", mux_i2s2_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
 703                         RK3308_CLKSEL_CON(60), 12, 1, MFLAGS,
 704                         RK3308_CLKGATE_CON(11), 14, GFLAGS),
 705         COMPOSITE_NODIV(SCLK_I2S2_8CH_TX_OUT, "clk_i2s2_8ch_tx_out", mux_i2s2_8ch_tx_out_p, CLK_SET_RATE_PARENT,
 706                         RK3308_CLKSEL_CON(60), 15, 1, MFLAGS,
 707                         RK3308_CLKGATE_CON(11), 15, GFLAGS),
 708
 709         COMPOSITE(SCLK_I2S2_8CH_RX_SRC, "clk_i2s2_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
 710                         RK3308_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS,
 711                         RK3308_CLKGATE_CON(12), 0, GFLAGS),
 712         COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_rx_frac", "clk_i2s2_8ch_rx_src", CLK_SET_RATE_PARENT,
 713                         RK3308_CLKSEL_CON(63), 0,
 714                         RK3308_CLKGATE_CON(12), 1, GFLAGS,
 715                         &rk3308_i2s2_8ch_rx_fracmux),
 716         COMPOSITE_NODIV(SCLK_I2S2_8CH_RX, "clk_i2s2_8ch_rx", mux_i2s2_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
 717                         RK3308_CLKSEL_CON(62), 12, 1, MFLAGS,
 718                         RK3308_CLKGATE_CON(12), 2, GFLAGS),
 719         GATE(SCLK_I2S2_8CH_RX_OUT, "clk_i2s2_8ch_rx_out", "clk_i2s2_8ch_rx", 0,
 720                         RK3308_CLKGATE_CON(12), 3, GFLAGS),
 721
 722         COMPOSITE(SCLK_I2S3_8CH_TX_SRC, "clk_i2s3_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
 723                         RK3308_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS,
 724                         RK3308_CLKGATE_CON(12), 4, GFLAGS),
 725         COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_tx_frac", "clk_i2s3_8ch_tx_src", CLK_SET_RATE_PARENT,
 726                         RK3308_CLKSEL_CON(65), 0,
 727                         RK3308_CLKGATE_CON(12), 5, GFLAGS,
 728                         &rk3308_i2s3_8ch_tx_fracmux),
 729         COMPOSITE_NODIV(SCLK_I2S3_8CH_TX, "clk_i2s3_8ch_tx", mux_i2s3_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
 730                         RK3308_CLKSEL_CON(64), 12, 1, MFLAGS,
 731                         RK3308_CLKGATE_CON(12), 6, GFLAGS),
 732         COMPOSITE_NODIV(SCLK_I2S3_8CH_TX_OUT, "clk_i2s3_8ch_tx_out", mux_i2s3_8ch_tx_out_p, CLK_SET_RATE_PARENT,
 733                         RK3308_CLKSEL_CON(64), 15, 1, MFLAGS,
 734                         RK3308_CLKGATE_CON(12), 7, GFLAGS),
 735
 736         COMPOSITE(SCLK_I2S3_8CH_RX_SRC, "clk_i2s3_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
 737                         RK3308_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS,
 738                         RK3308_CLKGATE_CON(12), 8, GFLAGS),
 739         COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_rx_frac", "clk_i2s3_8ch_rx_src", CLK_SET_RATE_PARENT,
 740                         RK3308_CLKSEL_CON(67), 0,
 741                         RK3308_CLKGATE_CON(12), 9, GFLAGS,
 742                         &rk3308_i2s3_8ch_rx_fracmux),
 743         COMPOSITE_NODIV(SCLK_I2S3_8CH_RX, "clk_i2s3_8ch_rx", mux_i2s3_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
 744                         RK3308_CLKSEL_CON(66), 12, 1, MFLAGS,
 745                         RK3308_CLKGATE_CON(12), 10, GFLAGS),
 746         GATE(SCLK_I2S3_8CH_RX_OUT, "clk_i2s3_8ch_rx_out", "clk_i2s3_8ch_rx", 0,
 747                         RK3308_CLKGATE_CON(12), 11, GFLAGS),
 748
 749         COMPOSITE(SCLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", mux_vpll0_vpll1_xin24m_p, 0,
 750                         RK3308_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS,
 751                         RK3308_CLKGATE_CON(12), 12, GFLAGS),
 752         COMPOSITE_FRACMUX(0, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT,
 753                         RK3308_CLKSEL_CON(69), 0,
 754                         RK3308_CLKGATE_CON(12), 13, GFLAGS,
 755                         &rk3308_i2s0_2ch_fracmux),
 756         GATE(SCLK_I2S0_2CH, "clk_i2s0_2ch", "clk_i2s0_2ch_mux", 0,
 757                         RK3308_CLKGATE_CON(12), 14, GFLAGS),
 758         COMPOSITE_NODIV(SCLK_I2S0_2CH_OUT, "clk_i2s0_2ch_out", mux_i2s0_2ch_out_p, CLK_SET_RATE_PARENT,
 759                         RK3308_CLKSEL_CON(68), 15, 1, MFLAGS,
 760                         RK3308_CLKGATE_CON(12), 15, GFLAGS),
 761
 762         COMPOSITE(SCLK_I2S1_2CH_SRC, "clk_i2s1_2ch_src", mux_vpll0_vpll1_xin24m_p, 0,
 763                         RK3308_CLKSEL_CON(70), 8, 2, MFLAGS, 0, 7, DFLAGS,
 764                         RK3308_CLKGATE_CON(13), 0, GFLAGS),
 765         COMPOSITE_FRACMUX(0, "clk_i2s1_2ch_frac", "clk_i2s1_2ch_src", CLK_SET_RATE_PARENT,
 766                         RK3308_CLKSEL_CON(71), 0,
 767                         RK3308_CLKGATE_CON(13), 1, GFLAGS,
 768                         &rk3308_i2s1_2ch_fracmux),
 769         GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 0,
 770                         RK3308_CLKGATE_CON(13), 2, GFLAGS),
 771         COMPOSITE_NODIV(SCLK_I2S1_2CH_OUT, "clk_i2s1_2ch_out", mux_i2s1_2ch_out_p, CLK_SET_RATE_PARENT,
 772                         RK3308_CLKSEL_CON(70), 15, 1, MFLAGS,
 773                         RK3308_CLKGATE_CON(13), 3, GFLAGS),
 774
 775         COMPOSITE(SCLK_SPDIF_TX_DIV, "clk_spdif_tx_div", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
 776                         RK3308_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
 777                         RK3308_CLKGATE_CON(10), 6, GFLAGS),
 778         COMPOSITE(SCLK_SPDIF_TX_DIV50, "clk_spdif_tx_div50", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
 779                         RK3308_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
 780                         RK3308_CLKGATE_CON(10), 6, GFLAGS),
 781         MUX(0, "clk_spdif_tx_src", mux_spdif_tx_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 782                         RK3308_CLKSEL_CON(48), 12, 1, MFLAGS),
 783         COMPOSITE_FRACMUX(0, "clk_spdif_tx_frac", "clk_spdif_tx_src", CLK_SET_RATE_PARENT,
 784                         RK3308_CLKSEL_CON(49), 0,
 785                         RK3308_CLKGATE_CON(10), 7, GFLAGS,
 786                         &rk3308_spdif_tx_fracmux),
 787         GATE(SCLK_SPDIF_TX, "clk_spdif_tx", "clk_spdif_tx_mux", 0,
 788                         RK3308_CLKGATE_CON(10), 8, GFLAGS),
 789
 790         COMPOSITE(SCLK_SPDIF_RX_DIV, "clk_spdif_rx_div", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
 791                         RK3308_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
 792                         RK3308_CLKGATE_CON(10), 9, GFLAGS),
 793         COMPOSITE(SCLK_SPDIF_RX_DIV50, "clk_spdif_rx_div50", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
 794                         RK3308_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
 795                         RK3308_CLKGATE_CON(10), 9, GFLAGS),
 796         MUX(0, "clk_spdif_rx_src", mux_spdif_rx_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 797                         RK3308_CLKSEL_CON(50), 14, 1, MFLAGS),
 798         COMPOSITE_FRACMUX(0, "clk_spdif_rx_frac", "clk_spdif_rx_src", CLK_SET_RATE_PARENT,
 799                         RK3308_CLKSEL_CON(51), 0,
 800                         RK3308_CLKGATE_CON(10), 10, GFLAGS,
 801                         &rk3308_spdif_rx_fracmux),
 802         GATE(SCLK_SPDIF_RX, "clk_spdif_rx", "clk_spdif_rx_mux", 0,
 803                         RK3308_CLKGATE_CON(10), 11, GFLAGS),
 804
 805         /*
 806          * Clock-Architecture Diagram 8
 807          */
 808
 809         GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 5, GFLAGS),
 810         GATE(0, "pclk_core_dbg_niu", "aclk_core", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 6, GFLAGS),
 811         GATE(0, "pclk_core_dbg_daplite", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 7, GFLAGS),
 812         GATE(0, "aclk_core_perf", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 8, GFLAGS),
 813         GATE(0, "pclk_core_grf", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 9, GFLAGS),
 814
 815         GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 2, GFLAGS),
 816         GATE(0, "aclk_peribus_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 3, GFLAGS),
 817         GATE(ACLK_MAC, "aclk_mac", "aclk_peri", 0, RK3308_CLKGATE_CON(9), 4, GFLAGS),
 818
 819         GATE(0, "hclk_peri_niu", "hclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 5, GFLAGS),
 820         GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 6, GFLAGS),
 821         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 7, GFLAGS),
 822         GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 8, GFLAGS),
 823         GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 9, GFLAGS),
 824         GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 10, GFLAGS),
 825         GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 11, GFLAGS),
 826         GATE(HCLK_HOST, "hclk_host", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 12, GFLAGS),
 827         GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 13, GFLAGS),
 828
 829         GATE(0, "pclk_peri_niu", "pclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 14, GFLAGS),
 830         GATE(PCLK_MAC, "pclk_mac", "pclk_peri", 0, RK3308_CLKGATE_CON(9), 15, GFLAGS),
 831
 832         GATE(0, "hclk_audio_niu", "hclk_audio", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(14), 0, GFLAGS),
 833         GATE(HCLK_PDM, "hclk_pdm", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 1, GFLAGS),
 834         GATE(HCLK_SPDIFTX, "hclk_spdiftx", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 2, GFLAGS),
 835         GATE(HCLK_SPDIFRX, "hclk_spdifrx", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 3, GFLAGS),
 836         GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 4, GFLAGS),
 837         GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 5, GFLAGS),
 838         GATE(HCLK_I2S2_8CH, "hclk_i2s2_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 6, GFLAGS),
 839         GATE(HCLK_I2S3_8CH, "hclk_i2s3_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 7, GFLAGS),
 840         GATE(HCLK_I2S0_2CH, "hclk_i2s0_2ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 8, GFLAGS),
 841         GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 9, GFLAGS),
 842         GATE(HCLK_VAD, "hclk_vad", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 10, GFLAGS),
 843
 844         GATE(0, "pclk_audio_niu", "pclk_audio", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(14), 11, GFLAGS),
 845         GATE(PCLK_ACODEC, "pclk_acodec", "pclk_audio", 0, RK3308_CLKGATE_CON(14), 12, GFLAGS),
 846
 847         GATE(0, "aclk_bus_niu", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 0, GFLAGS),
 848         GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 1, GFLAGS),
 849         GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 2, GFLAGS),
 850         GATE(ACLK_VOP, "aclk_vop", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 3, GFLAGS),
 851         GATE(0, "aclk_gic", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 4, GFLAGS),
 852         /* aclk_dmaci0 is controlled by sgrf_clkgat_con. */
 853         SGRF_GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus"),
 854         /* aclk_dmac1 is controlled by sgrf_clkgat_con. */
 855         SGRF_GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus"),
 856         /* watchdog pclk is controlled by sgrf_clkgat_con. */
 857         SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),
 858
 859         GATE(0, "hclk_bus_niu", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 5, GFLAGS),
 860         GATE(0, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 6, GFLAGS),
 861         GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3308_CLKGATE_CON(5), 7, GFLAGS),
 862         GATE(HCLK_VOP, "hclk_vop", "hclk_bus", 0, RK3308_CLKGATE_CON(5), 8, GFLAGS),
 863
 864         GATE(0, "pclk_bus_niu", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 9, GFLAGS),
 865         GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 10, GFLAGS),
 866         GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 11, GFLAGS),
 867         GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 12, GFLAGS),
 868         GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 13, GFLAGS),
 869         GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 14, GFLAGS),
 870         GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 15, GFLAGS),
 871         GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 0, GFLAGS),
 872         GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 1, GFLAGS),
 873         GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 2, GFLAGS),
 874         GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 3, GFLAGS),
 875         GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 4, GFLAGS),
 876         GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 5, GFLAGS),
 877         GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 6, GFLAGS),
 878         GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 7, GFLAGS),
 879         GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 8, GFLAGS),
 880         GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 9, GFLAGS),
 881         GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 10, GFLAGS),
 882         GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 12, GFLAGS),
 883         GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 13, GFLAGS),
 884         GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 14, GFLAGS),
 885         GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 15, GFLAGS),
 886         GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 0, GFLAGS),
 887         GATE(PCLK_SGRF, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 1, GFLAGS),
 888         GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 2, GFLAGS),
 889         GATE(PCLK_USBSD_DET, "pclk_usbsd_det", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 3, GFLAGS),
 890         GATE(PCLK_DDR_UPCTL, "pclk_ddr_upctl", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 4, GFLAGS),
 891         GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 5, GFLAGS),
 892         GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 6, GFLAGS),
 893         GATE(PCLK_DDR_STDBY, "pclk_ddr_stdby", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 7, GFLAGS),
 894         GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 8, GFLAGS),
 895         GATE(PCLK_CRU, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 9, GFLAGS),
 896         GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 10, GFLAGS),
 897         GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 11, GFLAGS),
 898         GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 12, GFLAGS),
 899         GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 13, GFLAGS),
 900         GATE(PCLK_CAN, "pclk_can", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 14, GFLAGS),
 901         GATE(PCLK_OWIRE, "pclk_owire", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 15, GFLAGS),
 902 };
 903
 904 static const char *const rk3308_critical_clocks[] __initconst = {
 905         "aclk_bus",
 906         "hclk_bus",
 907         "pclk_bus",
 908         "aclk_peri",
 909         "hclk_peri",
 910         "pclk_peri",
 911         "hclk_audio",
 912         "pclk_audio",
 913         "sclk_ddrc",
 914         "clk_ddrphy4x",
 915 };
 916
 917 static void __init rk3308_clk_init(struct device_node *np)
 918 {
 919         struct rockchip_clk_provider *ctx;
 920         void __iomem *reg_base;
 921
 922         reg_base = of_iomap(np, 0);
 923         if (!reg_base) {
 924                 pr_err("%s: could not map cru region\n", __func__);
 925                 return;
 926         }
 927
 928         ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
 929         if (IS_ERR(ctx)) {
 930                 pr_err("%s: rockchip clk init failed\n", __func__);
 931                 iounmap(reg_base);
 932                 return;
 933         }
 934
 935         rockchip_clk_register_plls(ctx, rk3308_pll_clks,
 936                                    ARRAY_SIZE(rk3308_pll_clks),
 937                                    RK3308_GRF_SOC_STATUS0);
 938         rockchip_clk_register_branches(ctx, rk3308_clk_branches,
 939                                        ARRAY_SIZE(rk3308_clk_branches));
 940         rockchip_clk_protect_critical(rk3308_critical_clocks,
 941                                       ARRAY_SIZE(rk3308_critical_clocks));
 942
 943         rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
 944                                      mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
 945                                      &rk3308_cpuclk_data, rk3308_cpuclk_rates,
 946                                      ARRAY_SIZE(rk3308_cpuclk_rates));
 947
 948         rockchip_register_softrst(np, 10, reg_base + RK3308_SOFTRST_CON(0),
 949                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
 950
 951         rockchip_register_restart_notifier(ctx, RK3308_GLB_SRST_FST, NULL);
 952
 953         rockchip_clk_of_add_provider(np, ctx);
 954 }
 955
 956 CLK_OF_DECLARE(rk3308_cru, "rockchip,rk3308-cru", rk3308_clk_init);