1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 Ideas On Board SPRL
6 * Copyright (C) 2015 Glider bvba
8 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk/renesas.h>
15 #include <linux/device.h>
18 #include <linux/of_address.h>
19 #include <linux/pm_clock.h>
20 #include <linux/pm_domain.h>
21 #include <linux/spinlock.h>
24 * MSTP clocks. We can't use standard gate clocks as we need to poll on the
25 * status register when enabling the clock.
28 #define MSTP_MAX_CLOCKS 32
31 * struct mstp_clock_group - MSTP gating clocks group
33 * @data: clock specifier translation for clocks in this group
34 * @smstpcr: module stop control register
35 * @mstpsr: module stop status register (optional)
36 * @lock: protects writes to SMSTPCR
37 * @width_8bit: registers are 8-bit, not 32-bit
38 * @clks: clocks in this group
40 struct mstp_clock_group {
41 struct clk_onecell_data data;
42 void __iomem *smstpcr;
50 * struct mstp_clock - MSTP gating clock
51 * @hw: handle between common and hardware-specific interfaces
52 * @bit_index: control bit index
53 * @group: MSTP clocks group
58 struct mstp_clock_group *group;
61 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
63 static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
66 return group->width_8bit ? readb(reg) : readl(reg);
69 static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
72 group->width_8bit ? writeb(val, reg) : writel(val, reg);
75 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
77 struct mstp_clock *clock = to_mstp_clock(hw);
78 struct mstp_clock_group *group = clock->group;
79 u32 bitmask = BIT(clock->bit_index);
84 spin_lock_irqsave(&group->lock, flags);
86 value = cpg_mstp_read(group, group->smstpcr);
91 cpg_mstp_write(group, value, group->smstpcr);
94 /* dummy read to ensure write has completed */
95 cpg_mstp_read(group, group->smstpcr);
96 barrier_data(group->smstpcr);
99 spin_unlock_irqrestore(&group->lock, flags);
101 if (!enable || !group->mstpsr)
104 for (i = 1000; i > 0; --i) {
105 if (!(cpg_mstp_read(group, group->mstpsr) & bitmask))
111 pr_err("%s: failed to enable %p[%d]\n", __func__,
112 group->smstpcr, clock->bit_index);
119 static int cpg_mstp_clock_enable(struct clk_hw *hw)
121 return cpg_mstp_clock_endisable(hw, true);
124 static void cpg_mstp_clock_disable(struct clk_hw *hw)
126 cpg_mstp_clock_endisable(hw, false);
129 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
131 struct mstp_clock *clock = to_mstp_clock(hw);
132 struct mstp_clock_group *group = clock->group;
136 value = cpg_mstp_read(group, group->mstpsr);
138 value = cpg_mstp_read(group, group->smstpcr);
140 return !(value & BIT(clock->bit_index));
143 static const struct clk_ops cpg_mstp_clock_ops = {
144 .enable = cpg_mstp_clock_enable,
145 .disable = cpg_mstp_clock_disable,
146 .is_enabled = cpg_mstp_clock_is_enabled,
149 static struct clk * __init cpg_mstp_clock_register(const char *name,
150 const char *parent_name, unsigned int index,
151 struct mstp_clock_group *group)
153 struct clk_init_data init = {};
154 struct mstp_clock *clock;
157 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
159 return ERR_PTR(-ENOMEM);
162 init.ops = &cpg_mstp_clock_ops;
163 init.flags = CLK_SET_RATE_PARENT;
164 /* INTC-SYS is the module clock of the GIC, and must not be disabled */
165 if (!strcmp(name, "intc-sys")) {
166 pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);
167 init.flags |= CLK_IS_CRITICAL;
169 init.parent_names = &parent_name;
170 init.num_parents = 1;
172 clock->bit_index = index;
173 clock->group = group;
174 clock->hw.init = &init;
176 clk = clk_register(NULL, &clock->hw);
184 static void __init cpg_mstp_clocks_init(struct device_node *np)
186 struct mstp_clock_group *group;
191 group = kzalloc(struct_size(group, clks, MSTP_MAX_CLOCKS), GFP_KERNEL);
196 spin_lock_init(&group->lock);
197 group->data.clks = clks;
199 group->smstpcr = of_iomap(np, 0);
200 group->mstpsr = of_iomap(np, 1);
202 if (group->smstpcr == NULL) {
203 pr_err("%s: failed to remap SMSTPCR\n", __func__);
208 if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
209 group->width_8bit = true;
211 for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
212 clks[i] = ERR_PTR(-ENOENT);
214 if (of_find_property(np, "clock-indices", &i))
215 idxname = "clock-indices";
217 idxname = "renesas,clock-indices";
219 for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
220 const char *parent_name;
225 /* Skip clocks with no name. */
226 ret = of_property_read_string_index(np, "clock-output-names",
228 if (ret < 0 || strlen(name) == 0)
231 parent_name = of_clk_get_parent_name(np, i);
232 ret = of_property_read_u32_index(np, idxname, i, &clkidx);
233 if (parent_name == NULL || ret < 0)
236 if (clkidx >= MSTP_MAX_CLOCKS) {
237 pr_err("%s: invalid clock %pOFn %s index %u\n",
238 __func__, np, name, clkidx);
242 clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
244 if (!IS_ERR(clks[clkidx])) {
245 group->data.clk_num = max(group->data.clk_num,
248 * Register a clkdev to let board code retrieve the
249 * clock by name and register aliases for non-DT
252 * FIXME: Remove this when all devices that require a
253 * clock will be instantiated from DT.
255 clk_register_clkdev(clks[clkidx], name, NULL);
257 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
258 __func__, np, name, PTR_ERR(clks[clkidx]));
262 of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
264 CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
266 int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)
268 struct device_node *np = dev->of_node;
269 struct of_phandle_args clkspec;
274 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
276 if (of_device_is_compatible(clkspec.np,
277 "renesas,cpg-mstp-clocks"))
280 /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */
281 if (of_node_name_eq(clkspec.np, "zb_clk"))
284 of_node_put(clkspec.np);
291 clk = of_clk_get_from_provider(&clkspec);
292 of_node_put(clkspec.np);
297 error = pm_clk_create(dev);
301 error = pm_clk_add_clk(dev, clk);
314 void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
316 if (!pm_clk_no_clocks(dev))
320 void __init cpg_mstp_add_clk_domain(struct device_node *np)
322 struct generic_pm_domain *pd;
325 if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
326 pr_warn("%pOF lacks #power-domain-cells\n", np);
330 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
335 pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
336 GENPD_FLAG_ACTIVE_WAKEUP;
337 pd->attach_dev = cpg_mstp_attach_dev;
338 pd->detach_dev = cpg_mstp_detach_dev;
339 pm_genpd_init(pd, &pm_domain_always_on_gov, false);
341 of_genpd_add_provider_simple(np, pd);