1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
20 #include "clk-regmap.h"
21 #include "clk-regmap-divider.h"
22 #include "clk-alpha-pll.h"
24 #include "clk-branch.h"
49 static const struct clk_div_table post_div_table_fabia_even[] = {
57 static struct clk_alpha_pll mmpll0 = {
59 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
62 .enable_mask = BIT(0),
63 .hw.init = &(struct clk_init_data){
65 .parent_data = &(const struct clk_parent_data){
69 .ops = &clk_alpha_pll_fixed_fabia_ops,
74 static struct clk_alpha_pll_postdiv mmpll0_out_even = {
77 .post_div_table = post_div_table_fabia_even,
78 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
80 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
81 .clkr.hw.init = &(struct clk_init_data){
82 .name = "mmpll0_out_even",
83 .parent_hws = (const struct clk_hw *[]){ &mmpll0.clkr.hw },
85 .ops = &clk_alpha_pll_postdiv_fabia_ops,
89 static struct clk_alpha_pll mmpll1 = {
91 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
94 .enable_mask = BIT(1),
95 .hw.init = &(struct clk_init_data){
97 .parent_data = &(const struct clk_parent_data){
101 .ops = &clk_alpha_pll_fixed_fabia_ops,
106 static struct clk_alpha_pll_postdiv mmpll1_out_even = {
109 .post_div_table = post_div_table_fabia_even,
110 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
112 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
113 .clkr.hw.init = &(struct clk_init_data){
114 .name = "mmpll1_out_even",
115 .parent_hws = (const struct clk_hw *[]){ &mmpll1.clkr.hw },
117 .ops = &clk_alpha_pll_postdiv_fabia_ops,
121 static struct clk_alpha_pll mmpll3 = {
123 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
124 .clkr.hw.init = &(struct clk_init_data){
126 .parent_data = &(const struct clk_parent_data){
130 .ops = &clk_alpha_pll_fixed_fabia_ops,
134 static struct clk_alpha_pll_postdiv mmpll3_out_even = {
137 .post_div_table = post_div_table_fabia_even,
138 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
140 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
141 .clkr.hw.init = &(struct clk_init_data){
142 .name = "mmpll3_out_even",
143 .parent_hws = (const struct clk_hw *[]){ &mmpll3.clkr.hw },
145 .ops = &clk_alpha_pll_postdiv_fabia_ops,
149 static struct clk_alpha_pll mmpll4 = {
151 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
152 .clkr.hw.init = &(struct clk_init_data){
154 .parent_data = &(const struct clk_parent_data){
158 .ops = &clk_alpha_pll_fixed_fabia_ops,
162 static struct clk_alpha_pll_postdiv mmpll4_out_even = {
165 .post_div_table = post_div_table_fabia_even,
166 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
168 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
169 .clkr.hw.init = &(struct clk_init_data){
170 .name = "mmpll4_out_even",
171 .parent_hws = (const struct clk_hw *[]){ &mmpll4.clkr.hw },
173 .ops = &clk_alpha_pll_postdiv_fabia_ops,
177 static struct clk_alpha_pll mmpll5 = {
179 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
180 .clkr.hw.init = &(struct clk_init_data){
182 .parent_data = &(const struct clk_parent_data){
186 .ops = &clk_alpha_pll_fixed_fabia_ops,
190 static struct clk_alpha_pll_postdiv mmpll5_out_even = {
193 .post_div_table = post_div_table_fabia_even,
194 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
196 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
197 .clkr.hw.init = &(struct clk_init_data){
198 .name = "mmpll5_out_even",
199 .parent_hws = (const struct clk_hw *[]){ &mmpll5.clkr.hw },
201 .ops = &clk_alpha_pll_postdiv_fabia_ops,
205 static struct clk_alpha_pll mmpll6 = {
207 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
208 .clkr.hw.init = &(struct clk_init_data){
210 .parent_data = &(const struct clk_parent_data){
214 .ops = &clk_alpha_pll_fixed_fabia_ops,
218 static struct clk_alpha_pll_postdiv mmpll6_out_even = {
221 .post_div_table = post_div_table_fabia_even,
222 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
224 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
225 .clkr.hw.init = &(struct clk_init_data){
226 .name = "mmpll6_out_even",
227 .parent_hws = (const struct clk_hw *[]){ &mmpll6.clkr.hw },
229 .ops = &clk_alpha_pll_postdiv_fabia_ops,
233 static struct clk_alpha_pll mmpll7 = {
235 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
236 .clkr.hw.init = &(struct clk_init_data){
238 .parent_data = &(const struct clk_parent_data){
242 .ops = &clk_alpha_pll_fixed_fabia_ops,
246 static struct clk_alpha_pll_postdiv mmpll7_out_even = {
249 .post_div_table = post_div_table_fabia_even,
250 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
252 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
253 .clkr.hw.init = &(struct clk_init_data){
254 .name = "mmpll7_out_even",
255 .parent_hws = (const struct clk_hw *[]){ &mmpll7.clkr.hw },
257 .ops = &clk_alpha_pll_postdiv_fabia_ops,
261 static struct clk_alpha_pll mmpll10 = {
263 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
264 .clkr.hw.init = &(struct clk_init_data){
266 .parent_data = &(const struct clk_parent_data){
270 .ops = &clk_alpha_pll_fixed_fabia_ops,
274 static struct clk_alpha_pll_postdiv mmpll10_out_even = {
277 .post_div_table = post_div_table_fabia_even,
278 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
280 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
281 .clkr.hw.init = &(struct clk_init_data){
282 .name = "mmpll10_out_even",
283 .parent_hws = (const struct clk_hw *[]){ &mmpll10.clkr.hw },
285 .ops = &clk_alpha_pll_postdiv_fabia_ops,
289 static const struct parent_map mmss_xo_hdmi_map[] = {
294 static const struct clk_parent_data mmss_xo_hdmi[] = {
296 { .fw_name = "hdmipll" },
299 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
305 static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
307 { .fw_name = "dsi0dsi" },
308 { .fw_name = "dsi1dsi" },
311 static const struct parent_map mmss_xo_dsibyte_map[] = {
313 { P_DSI0PLL_BYTE, 1 },
314 { P_DSI1PLL_BYTE, 2 },
317 static const struct clk_parent_data mmss_xo_dsibyte[] = {
319 { .fw_name = "dsi0byte" },
320 { .fw_name = "dsi1byte" },
323 static const struct parent_map mmss_xo_dp_map[] = {
329 static const struct clk_parent_data mmss_xo_dp[] = {
331 { .fw_name = "dplink" },
332 { .fw_name = "dpvco" },
335 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
341 static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
343 { .fw_name = "gpll0" },
344 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
347 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
349 { P_MMPLL0_OUT_EVEN, 1 },
354 static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
356 { .hw = &mmpll0_out_even.clkr.hw },
357 { .fw_name = "gpll0" },
358 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
361 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
363 { P_MMPLL0_OUT_EVEN, 1 },
364 { P_MMPLL1_OUT_EVEN, 2 },
369 static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
371 { .hw = &mmpll0_out_even.clkr.hw },
372 { .hw = &mmpll1_out_even.clkr.hw },
373 { .fw_name = "gpll0" },
374 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
377 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
379 { P_MMPLL0_OUT_EVEN, 1 },
380 { P_MMPLL5_OUT_EVEN, 2 },
385 static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
387 { .hw = &mmpll0_out_even.clkr.hw },
388 { .hw = &mmpll5_out_even.clkr.hw },
389 { .fw_name = "gpll0" },
390 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
393 static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = {
395 { P_MMPLL0_OUT_EVEN, 1 },
396 { P_MMPLL3_OUT_EVEN, 3 },
397 { P_MMPLL6_OUT_EVEN, 4 },
402 static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div[] = {
404 { .hw = &mmpll0_out_even.clkr.hw },
405 { .hw = &mmpll3_out_even.clkr.hw },
406 { .hw = &mmpll6_out_even.clkr.hw },
407 { .fw_name = "gpll0" },
408 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
411 static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
413 { P_MMPLL4_OUT_EVEN, 1 },
414 { P_MMPLL7_OUT_EVEN, 2 },
415 { P_MMPLL10_OUT_EVEN, 3 },
420 static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
422 { .hw = &mmpll4_out_even.clkr.hw },
423 { .hw = &mmpll7_out_even.clkr.hw },
424 { .hw = &mmpll10_out_even.clkr.hw },
425 { .fw_name = "gpll0" },
426 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
429 static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
431 { P_MMPLL0_OUT_EVEN, 1 },
432 { P_MMPLL7_OUT_EVEN, 2 },
433 { P_MMPLL10_OUT_EVEN, 3 },
438 static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div[] = {
440 { .hw = &mmpll0_out_even.clkr.hw },
441 { .hw = &mmpll7_out_even.clkr.hw },
442 { .hw = &mmpll10_out_even.clkr.hw },
443 { .fw_name = "gpll0" },
444 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
447 static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
449 { P_MMPLL0_OUT_EVEN, 1 },
450 { P_MMPLL4_OUT_EVEN, 2 },
451 { P_MMPLL7_OUT_EVEN, 3 },
452 { P_MMPLL10_OUT_EVEN, 4 },
457 static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
459 { .hw = &mmpll0_out_even.clkr.hw },
460 { .hw = &mmpll4_out_even.clkr.hw },
461 { .hw = &mmpll7_out_even.clkr.hw },
462 { .hw = &mmpll10_out_even.clkr.hw },
463 { .fw_name = "gpll0" },
464 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
467 static struct clk_rcg2 byte0_clk_src = {
470 .parent_map = mmss_xo_dsibyte_map,
471 .clkr.hw.init = &(struct clk_init_data){
472 .name = "byte0_clk_src",
473 .parent_data = mmss_xo_dsibyte,
474 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
475 .ops = &clk_byte2_ops,
476 .flags = CLK_SET_RATE_PARENT,
480 static struct clk_rcg2 byte1_clk_src = {
483 .parent_map = mmss_xo_dsibyte_map,
484 .clkr.hw.init = &(struct clk_init_data){
485 .name = "byte1_clk_src",
486 .parent_data = mmss_xo_dsibyte,
487 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
488 .ops = &clk_byte2_ops,
489 .flags = CLK_SET_RATE_PARENT,
493 static const struct freq_tbl ftbl_cci_clk_src[] = {
494 F(37500000, P_GPLL0, 16, 0, 0),
495 F(50000000, P_GPLL0, 12, 0, 0),
496 F(100000000, P_GPLL0, 6, 0, 0),
500 static struct clk_rcg2 cci_clk_src = {
503 .parent_map = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map,
504 .freq_tbl = ftbl_cci_clk_src,
505 .clkr.hw.init = &(struct clk_init_data){
506 .name = "cci_clk_src",
507 .parent_data = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div,
508 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div),
509 .ops = &clk_rcg2_ops,
513 static const struct freq_tbl ftbl_cpp_clk_src[] = {
514 F(100000000, P_GPLL0, 6, 0, 0),
515 F(200000000, P_GPLL0, 3, 0, 0),
516 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
517 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
518 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
519 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
520 F(600000000, P_GPLL0, 1, 0, 0),
524 static struct clk_rcg2 cpp_clk_src = {
527 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
528 .freq_tbl = ftbl_cpp_clk_src,
529 .clkr.hw.init = &(struct clk_init_data){
530 .name = "cpp_clk_src",
531 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
532 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
533 .ops = &clk_rcg2_ops,
537 static const struct freq_tbl ftbl_csi_clk_src[] = {
538 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
539 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
540 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
541 F(300000000, P_GPLL0, 2, 0, 0),
542 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
543 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
547 static struct clk_rcg2 csi0_clk_src = {
550 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
551 .freq_tbl = ftbl_csi_clk_src,
552 .clkr.hw.init = &(struct clk_init_data){
553 .name = "csi0_clk_src",
554 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
555 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
556 .ops = &clk_rcg2_ops,
560 static struct clk_rcg2 csi1_clk_src = {
563 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
564 .freq_tbl = ftbl_csi_clk_src,
565 .clkr.hw.init = &(struct clk_init_data){
566 .name = "csi1_clk_src",
567 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
568 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
569 .ops = &clk_rcg2_ops,
573 static struct clk_rcg2 csi2_clk_src = {
576 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
577 .freq_tbl = ftbl_csi_clk_src,
578 .clkr.hw.init = &(struct clk_init_data){
579 .name = "csi2_clk_src",
580 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
581 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
582 .ops = &clk_rcg2_ops,
586 static struct clk_rcg2 csi3_clk_src = {
589 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
590 .freq_tbl = ftbl_csi_clk_src,
591 .clkr.hw.init = &(struct clk_init_data){
592 .name = "csi3_clk_src",
593 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
594 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
595 .ops = &clk_rcg2_ops,
599 static const struct freq_tbl ftbl_csiphy_clk_src[] = {
600 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
601 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
602 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
603 F(300000000, P_GPLL0, 2, 0, 0),
604 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
608 static struct clk_rcg2 csiphy_clk_src = {
611 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
612 .freq_tbl = ftbl_csiphy_clk_src,
613 .clkr.hw.init = &(struct clk_init_data){
614 .name = "csiphy_clk_src",
615 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
616 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
617 .ops = &clk_rcg2_ops,
621 static const struct freq_tbl ftbl_csiphytimer_clk_src[] = {
622 F(200000000, P_GPLL0, 3, 0, 0),
623 F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
627 static struct clk_rcg2 csi0phytimer_clk_src = {
630 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
631 .freq_tbl = ftbl_csiphytimer_clk_src,
632 .clkr.hw.init = &(struct clk_init_data){
633 .name = "csi0phytimer_clk_src",
634 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
635 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
636 .ops = &clk_rcg2_ops,
640 static struct clk_rcg2 csi1phytimer_clk_src = {
643 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
644 .freq_tbl = ftbl_csiphytimer_clk_src,
645 .clkr.hw.init = &(struct clk_init_data){
646 .name = "csi1phytimer_clk_src",
647 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
648 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
649 .ops = &clk_rcg2_ops,
653 static struct clk_rcg2 csi2phytimer_clk_src = {
656 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
657 .freq_tbl = ftbl_csiphytimer_clk_src,
658 .clkr.hw.init = &(struct clk_init_data){
659 .name = "csi2phytimer_clk_src",
660 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
661 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
662 .ops = &clk_rcg2_ops,
666 static const struct freq_tbl ftbl_dp_aux_clk_src[] = {
667 F(19200000, P_XO, 1, 0, 0),
671 static struct clk_rcg2 dp_aux_clk_src = {
674 .parent_map = mmss_xo_gpll0_gpll0_div_map,
675 .freq_tbl = ftbl_dp_aux_clk_src,
676 .clkr.hw.init = &(struct clk_init_data){
677 .name = "dp_aux_clk_src",
678 .parent_data = mmss_xo_gpll0_gpll0_div,
679 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
680 .ops = &clk_rcg2_ops,
684 static const struct freq_tbl ftbl_dp_crypto_clk_src[] = {
685 F(101250, P_DPLINK, 1, 5, 16),
686 F(168750, P_DPLINK, 1, 5, 16),
687 F(337500, P_DPLINK, 1, 5, 16),
691 static struct clk_rcg2 dp_crypto_clk_src = {
694 .parent_map = mmss_xo_dp_map,
695 .freq_tbl = ftbl_dp_crypto_clk_src,
696 .clkr.hw.init = &(struct clk_init_data){
697 .name = "dp_crypto_clk_src",
698 .parent_data = mmss_xo_dp,
699 .num_parents = ARRAY_SIZE(mmss_xo_dp),
700 .ops = &clk_rcg2_ops,
704 static const struct freq_tbl ftbl_dp_link_clk_src[] = {
705 F(162000, P_DPLINK, 2, 0, 0),
706 F(270000, P_DPLINK, 2, 0, 0),
707 F(540000, P_DPLINK, 2, 0, 0),
711 static struct clk_rcg2 dp_link_clk_src = {
714 .parent_map = mmss_xo_dp_map,
715 .freq_tbl = ftbl_dp_link_clk_src,
716 .clkr.hw.init = &(struct clk_init_data){
717 .name = "dp_link_clk_src",
718 .parent_data = mmss_xo_dp,
719 .num_parents = ARRAY_SIZE(mmss_xo_dp),
720 .ops = &clk_rcg2_ops,
724 static const struct freq_tbl ftbl_dp_pixel_clk_src[] = {
725 F(154000000, P_DPVCO, 1, 0, 0),
726 F(337500000, P_DPVCO, 2, 0, 0),
727 F(675000000, P_DPVCO, 2, 0, 0),
731 static struct clk_rcg2 dp_pixel_clk_src = {
734 .parent_map = mmss_xo_dp_map,
735 .freq_tbl = ftbl_dp_pixel_clk_src,
736 .clkr.hw.init = &(struct clk_init_data){
737 .name = "dp_pixel_clk_src",
738 .parent_data = mmss_xo_dp,
739 .num_parents = ARRAY_SIZE(mmss_xo_dp),
740 .ops = &clk_rcg2_ops,
744 static const struct freq_tbl ftbl_esc_clk_src[] = {
745 F(19200000, P_XO, 1, 0, 0),
749 static struct clk_rcg2 esc0_clk_src = {
752 .parent_map = mmss_xo_dsibyte_map,
753 .freq_tbl = ftbl_esc_clk_src,
754 .clkr.hw.init = &(struct clk_init_data){
755 .name = "esc0_clk_src",
756 .parent_data = mmss_xo_dsibyte,
757 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
758 .ops = &clk_rcg2_ops,
762 static struct clk_rcg2 esc1_clk_src = {
765 .parent_map = mmss_xo_dsibyte_map,
766 .freq_tbl = ftbl_esc_clk_src,
767 .clkr.hw.init = &(struct clk_init_data){
768 .name = "esc1_clk_src",
769 .parent_data = mmss_xo_dsibyte,
770 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
771 .ops = &clk_rcg2_ops,
775 static const struct freq_tbl ftbl_extpclk_clk_src[] = {
776 { .src = P_HDMIPLL },
780 static struct clk_rcg2 extpclk_clk_src = {
783 .parent_map = mmss_xo_hdmi_map,
784 .freq_tbl = ftbl_extpclk_clk_src,
785 .clkr.hw.init = &(struct clk_init_data){
786 .name = "extpclk_clk_src",
787 .parent_data = mmss_xo_hdmi,
788 .num_parents = ARRAY_SIZE(mmss_xo_hdmi),
789 .ops = &clk_byte_ops,
790 .flags = CLK_SET_RATE_PARENT,
794 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
795 F(100000000, P_GPLL0, 6, 0, 0),
796 F(200000000, P_GPLL0, 3, 0, 0),
797 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
798 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
799 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
803 static struct clk_rcg2 fd_core_clk_src = {
806 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
807 .freq_tbl = ftbl_fd_core_clk_src,
808 .clkr.hw.init = &(struct clk_init_data){
809 .name = "fd_core_clk_src",
810 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
811 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
812 .ops = &clk_rcg2_ops,
816 static const struct freq_tbl ftbl_hdmi_clk_src[] = {
817 F(19200000, P_XO, 1, 0, 0),
821 static struct clk_rcg2 hdmi_clk_src = {
824 .parent_map = mmss_xo_gpll0_gpll0_div_map,
825 .freq_tbl = ftbl_hdmi_clk_src,
826 .clkr.hw.init = &(struct clk_init_data){
827 .name = "hdmi_clk_src",
828 .parent_data = mmss_xo_gpll0_gpll0_div,
829 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
830 .ops = &clk_rcg2_ops,
834 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
835 F(75000000, P_GPLL0, 8, 0, 0),
836 F(150000000, P_GPLL0, 4, 0, 0),
837 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
838 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
842 static struct clk_rcg2 jpeg0_clk_src = {
845 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
846 .freq_tbl = ftbl_jpeg0_clk_src,
847 .clkr.hw.init = &(struct clk_init_data){
848 .name = "jpeg0_clk_src",
849 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
850 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
851 .ops = &clk_rcg2_ops,
855 static const struct freq_tbl ftbl_maxi_clk_src[] = {
856 F(19200000, P_XO, 1, 0, 0),
857 F(75000000, P_GPLL0_DIV, 4, 0, 0),
858 F(171428571, P_GPLL0, 3.5, 0, 0),
859 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
860 F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
864 static struct clk_rcg2 maxi_clk_src = {
867 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
868 .freq_tbl = ftbl_maxi_clk_src,
869 .clkr.hw.init = &(struct clk_init_data){
870 .name = "maxi_clk_src",
871 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
872 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
873 .ops = &clk_rcg2_ops,
877 static const struct freq_tbl ftbl_mclk_clk_src[] = {
878 F(4800000, P_XO, 4, 0, 0),
879 F(6000000, P_GPLL0_DIV, 10, 1, 5),
880 F(8000000, P_GPLL0_DIV, 1, 2, 75),
881 F(9600000, P_XO, 2, 0, 0),
882 F(16666667, P_GPLL0_DIV, 2, 1, 9),
883 F(19200000, P_XO, 1, 0, 0),
884 F(24000000, P_GPLL0_DIV, 1, 2, 25),
885 F(33333333, P_GPLL0_DIV, 1, 2, 9),
886 F(48000000, P_GPLL0, 1, 2, 25),
887 F(66666667, P_GPLL0, 1, 2, 9),
891 static struct clk_rcg2 mclk0_clk_src = {
894 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
895 .freq_tbl = ftbl_mclk_clk_src,
896 .clkr.hw.init = &(struct clk_init_data){
897 .name = "mclk0_clk_src",
898 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
899 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
900 .ops = &clk_rcg2_ops,
904 static struct clk_rcg2 mclk1_clk_src = {
907 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
908 .freq_tbl = ftbl_mclk_clk_src,
909 .clkr.hw.init = &(struct clk_init_data){
910 .name = "mclk1_clk_src",
911 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
912 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
913 .ops = &clk_rcg2_ops,
917 static struct clk_rcg2 mclk2_clk_src = {
920 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
921 .freq_tbl = ftbl_mclk_clk_src,
922 .clkr.hw.init = &(struct clk_init_data){
923 .name = "mclk2_clk_src",
924 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
925 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
926 .ops = &clk_rcg2_ops,
930 static struct clk_rcg2 mclk3_clk_src = {
933 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
934 .freq_tbl = ftbl_mclk_clk_src,
935 .clkr.hw.init = &(struct clk_init_data){
936 .name = "mclk3_clk_src",
937 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
938 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
939 .ops = &clk_rcg2_ops,
943 static const struct freq_tbl ftbl_mdp_clk_src[] = {
944 F(85714286, P_GPLL0, 7, 0, 0),
945 F(100000000, P_GPLL0, 6, 0, 0),
946 F(150000000, P_GPLL0, 4, 0, 0),
947 F(171428571, P_GPLL0, 3.5, 0, 0),
948 F(200000000, P_GPLL0, 3, 0, 0),
949 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
950 F(300000000, P_GPLL0, 2, 0, 0),
951 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
952 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
956 static struct clk_rcg2 mdp_clk_src = {
959 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
960 .freq_tbl = ftbl_mdp_clk_src,
961 .clkr.hw.init = &(struct clk_init_data){
962 .name = "mdp_clk_src",
963 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
964 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
965 .ops = &clk_rcg2_ops,
969 static const struct freq_tbl ftbl_vsync_clk_src[] = {
970 F(19200000, P_XO, 1, 0, 0),
974 static struct clk_rcg2 vsync_clk_src = {
977 .parent_map = mmss_xo_gpll0_gpll0_div_map,
978 .freq_tbl = ftbl_vsync_clk_src,
979 .clkr.hw.init = &(struct clk_init_data){
980 .name = "vsync_clk_src",
981 .parent_data = mmss_xo_gpll0_gpll0_div,
982 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
983 .ops = &clk_rcg2_ops,
987 static const struct freq_tbl ftbl_ahb_clk_src[] = {
988 F(19200000, P_XO, 1, 0, 0),
989 F(40000000, P_GPLL0, 15, 0, 0),
990 F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
994 static struct clk_rcg2 ahb_clk_src = {
997 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
998 .freq_tbl = ftbl_ahb_clk_src,
999 .clkr.hw.init = &(struct clk_init_data){
1000 .name = "ahb_clk_src",
1001 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
1002 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
1003 .ops = &clk_rcg2_ops,
1007 static const struct freq_tbl ftbl_axi_clk_src[] = {
1008 F(75000000, P_GPLL0, 8, 0, 0),
1009 F(171428571, P_GPLL0, 3.5, 0, 0),
1010 F(240000000, P_GPLL0, 2.5, 0, 0),
1011 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
1012 F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1017 static struct clk_rcg2 axi_clk_src = {
1020 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
1021 .freq_tbl = ftbl_axi_clk_src,
1022 .clkr.hw.init = &(struct clk_init_data){
1023 .name = "axi_clk_src",
1024 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
1025 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
1026 .ops = &clk_rcg2_ops,
1030 static struct clk_rcg2 pclk0_clk_src = {
1034 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1035 .clkr.hw.init = &(struct clk_init_data){
1036 .name = "pclk0_clk_src",
1037 .parent_data = mmss_xo_dsi0pll_dsi1pll,
1038 .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
1039 .ops = &clk_pixel_ops,
1040 .flags = CLK_SET_RATE_PARENT,
1044 static struct clk_rcg2 pclk1_clk_src = {
1048 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1049 .clkr.hw.init = &(struct clk_init_data){
1050 .name = "pclk1_clk_src",
1051 .parent_data = mmss_xo_dsi0pll_dsi1pll,
1052 .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
1053 .ops = &clk_pixel_ops,
1054 .flags = CLK_SET_RATE_PARENT,
1058 static const struct freq_tbl ftbl_rot_clk_src[] = {
1059 F(171428571, P_GPLL0, 3.5, 0, 0),
1060 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
1061 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
1062 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1066 static struct clk_rcg2 rot_clk_src = {
1069 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
1070 .freq_tbl = ftbl_rot_clk_src,
1071 .clkr.hw.init = &(struct clk_init_data){
1072 .name = "rot_clk_src",
1073 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
1074 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
1075 .ops = &clk_rcg2_ops,
1079 static const struct freq_tbl ftbl_video_core_clk_src[] = {
1080 F(200000000, P_GPLL0, 3, 0, 0),
1081 F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
1082 F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
1083 F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
1084 F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
1088 static struct clk_rcg2 video_core_clk_src = {
1091 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1092 .freq_tbl = ftbl_video_core_clk_src,
1093 .clkr.hw.init = &(struct clk_init_data){
1094 .name = "video_core_clk_src",
1095 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1096 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1097 .ops = &clk_rcg2_ops,
1101 static struct clk_rcg2 video_subcore0_clk_src = {
1104 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1105 .freq_tbl = ftbl_video_core_clk_src,
1106 .clkr.hw.init = &(struct clk_init_data){
1107 .name = "video_subcore0_clk_src",
1108 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1109 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1110 .ops = &clk_rcg2_ops,
1114 static struct clk_rcg2 video_subcore1_clk_src = {
1117 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1118 .freq_tbl = ftbl_video_core_clk_src,
1119 .clkr.hw.init = &(struct clk_init_data){
1120 .name = "video_subcore1_clk_src",
1121 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1122 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1123 .ops = &clk_rcg2_ops,
1127 static const struct freq_tbl ftbl_vfe_clk_src[] = {
1128 F(200000000, P_GPLL0, 3, 0, 0),
1129 F(300000000, P_GPLL0, 2, 0, 0),
1130 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
1131 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
1132 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1133 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
1134 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
1135 F(600000000, P_GPLL0, 1, 0, 0),
1139 static struct clk_rcg2 vfe0_clk_src = {
1142 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1143 .freq_tbl = ftbl_vfe_clk_src,
1144 .clkr.hw.init = &(struct clk_init_data){
1145 .name = "vfe0_clk_src",
1146 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1147 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
1148 .ops = &clk_rcg2_ops,
1152 static struct clk_rcg2 vfe1_clk_src = {
1155 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1156 .freq_tbl = ftbl_vfe_clk_src,
1157 .clkr.hw.init = &(struct clk_init_data){
1158 .name = "vfe1_clk_src",
1159 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1160 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
1161 .ops = &clk_rcg2_ops,
1165 static struct clk_branch misc_ahb_clk = {
1170 .enable_reg = 0x328,
1171 .enable_mask = BIT(0),
1172 .hw.init = &(struct clk_init_data){
1173 .name = "misc_ahb_clk",
1174 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1176 .ops = &clk_branch2_ops,
1177 .flags = CLK_SET_RATE_PARENT,
1182 static struct clk_branch video_core_clk = {
1185 .enable_reg = 0x1028,
1186 .enable_mask = BIT(0),
1187 .hw.init = &(struct clk_init_data){
1188 .name = "video_core_clk",
1189 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
1191 .ops = &clk_branch2_ops,
1192 .flags = CLK_SET_RATE_PARENT,
1197 static struct clk_branch video_ahb_clk = {
1202 .enable_reg = 0x1030,
1203 .enable_mask = BIT(0),
1204 .hw.init = &(struct clk_init_data){
1205 .name = "video_ahb_clk",
1206 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1208 .ops = &clk_branch2_ops,
1209 .flags = CLK_SET_RATE_PARENT,
1214 static struct clk_branch video_axi_clk = {
1217 .enable_reg = 0x1034,
1218 .enable_mask = BIT(0),
1219 .hw.init = &(struct clk_init_data){
1220 .name = "video_axi_clk",
1221 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1223 .ops = &clk_branch2_ops,
1228 static struct clk_branch video_maxi_clk = {
1231 .enable_reg = 0x1038,
1232 .enable_mask = BIT(0),
1233 .hw.init = &(struct clk_init_data){
1234 .name = "video_maxi_clk",
1235 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
1237 .ops = &clk_branch2_ops,
1238 .flags = CLK_SET_RATE_PARENT,
1243 static struct clk_branch video_subcore0_clk = {
1246 .enable_reg = 0x1048,
1247 .enable_mask = BIT(0),
1248 .hw.init = &(struct clk_init_data){
1249 .name = "video_subcore0_clk",
1250 .parent_hws = (const struct clk_hw *[]){ &video_subcore0_clk_src.clkr.hw },
1252 .ops = &clk_branch2_ops,
1253 .flags = CLK_SET_RATE_PARENT,
1258 static struct clk_branch video_subcore1_clk = {
1261 .enable_reg = 0x104c,
1262 .enable_mask = BIT(0),
1263 .hw.init = &(struct clk_init_data){
1264 .name = "video_subcore1_clk",
1265 .parent_hws = (const struct clk_hw *[]){ &video_subcore1_clk_src.clkr.hw },
1267 .ops = &clk_branch2_ops,
1268 .flags = CLK_SET_RATE_PARENT,
1273 static struct clk_branch mdss_ahb_clk = {
1278 .enable_reg = 0x2308,
1279 .enable_mask = BIT(0),
1280 .hw.init = &(struct clk_init_data){
1281 .name = "mdss_ahb_clk",
1282 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1284 .ops = &clk_branch2_ops,
1285 .flags = CLK_SET_RATE_PARENT,
1290 static struct clk_branch mdss_hdmi_dp_ahb_clk = {
1293 .enable_reg = 0x230c,
1294 .enable_mask = BIT(0),
1295 .hw.init = &(struct clk_init_data){
1296 .name = "mdss_hdmi_dp_ahb_clk",
1297 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1299 .ops = &clk_branch2_ops,
1300 .flags = CLK_SET_RATE_PARENT,
1305 static struct clk_branch mdss_axi_clk = {
1308 .enable_reg = 0x2310,
1309 .enable_mask = BIT(0),
1310 .hw.init = &(struct clk_init_data){
1311 .name = "mdss_axi_clk",
1312 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1314 .ops = &clk_branch2_ops,
1319 static struct clk_branch mdss_pclk0_clk = {
1322 .enable_reg = 0x2314,
1323 .enable_mask = BIT(0),
1324 .hw.init = &(struct clk_init_data){
1325 .name = "mdss_pclk0_clk",
1326 .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
1328 .ops = &clk_branch2_ops,
1329 .flags = CLK_SET_RATE_PARENT,
1334 static struct clk_branch mdss_pclk1_clk = {
1337 .enable_reg = 0x2318,
1338 .enable_mask = BIT(0),
1339 .hw.init = &(struct clk_init_data){
1340 .name = "mdss_pclk1_clk",
1341 .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
1343 .ops = &clk_branch2_ops,
1344 .flags = CLK_SET_RATE_PARENT,
1349 static struct clk_branch mdss_mdp_clk = {
1352 .enable_reg = 0x231c,
1353 .enable_mask = BIT(0),
1354 .hw.init = &(struct clk_init_data){
1355 .name = "mdss_mdp_clk",
1356 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1358 .ops = &clk_branch2_ops,
1359 .flags = CLK_SET_RATE_PARENT,
1364 static struct clk_branch mdss_mdp_lut_clk = {
1367 .enable_reg = 0x2320,
1368 .enable_mask = BIT(0),
1369 .hw.init = &(struct clk_init_data){
1370 .name = "mdss_mdp_lut_clk",
1371 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1373 .ops = &clk_branch2_ops,
1374 .flags = CLK_SET_RATE_PARENT,
1379 static struct clk_branch mdss_extpclk_clk = {
1382 .enable_reg = 0x2324,
1383 .enable_mask = BIT(0),
1384 .hw.init = &(struct clk_init_data){
1385 .name = "mdss_extpclk_clk",
1386 .parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
1388 .ops = &clk_branch2_ops,
1389 .flags = CLK_SET_RATE_PARENT,
1394 static struct clk_branch mdss_vsync_clk = {
1397 .enable_reg = 0x2328,
1398 .enable_mask = BIT(0),
1399 .hw.init = &(struct clk_init_data){
1400 .name = "mdss_vsync_clk",
1401 .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
1403 .ops = &clk_branch2_ops,
1404 .flags = CLK_SET_RATE_PARENT,
1409 static struct clk_branch mdss_hdmi_clk = {
1412 .enable_reg = 0x2338,
1413 .enable_mask = BIT(0),
1414 .hw.init = &(struct clk_init_data){
1415 .name = "mdss_hdmi_clk",
1416 .parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
1418 .ops = &clk_branch2_ops,
1419 .flags = CLK_SET_RATE_PARENT,
1424 static struct clk_branch mdss_byte0_clk = {
1427 .enable_reg = 0x233c,
1428 .enable_mask = BIT(0),
1429 .hw.init = &(struct clk_init_data){
1430 .name = "mdss_byte0_clk",
1431 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1433 .ops = &clk_branch2_ops,
1434 .flags = CLK_SET_RATE_PARENT,
1439 static struct clk_branch mdss_byte1_clk = {
1442 .enable_reg = 0x2340,
1443 .enable_mask = BIT(0),
1444 .hw.init = &(struct clk_init_data){
1445 .name = "mdss_byte1_clk",
1446 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1448 .ops = &clk_branch2_ops,
1449 .flags = CLK_SET_RATE_PARENT,
1454 static struct clk_branch mdss_esc0_clk = {
1457 .enable_reg = 0x2344,
1458 .enable_mask = BIT(0),
1459 .hw.init = &(struct clk_init_data){
1460 .name = "mdss_esc0_clk",
1461 .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
1463 .ops = &clk_branch2_ops,
1464 .flags = CLK_SET_RATE_PARENT,
1469 static struct clk_branch mdss_esc1_clk = {
1472 .enable_reg = 0x2348,
1473 .enable_mask = BIT(0),
1474 .hw.init = &(struct clk_init_data){
1475 .name = "mdss_esc1_clk",
1476 .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
1478 .ops = &clk_branch2_ops,
1479 .flags = CLK_SET_RATE_PARENT,
1484 static struct clk_branch mdss_rot_clk = {
1487 .enable_reg = 0x2350,
1488 .enable_mask = BIT(0),
1489 .hw.init = &(struct clk_init_data){
1490 .name = "mdss_rot_clk",
1491 .parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw },
1493 .ops = &clk_branch2_ops,
1494 .flags = CLK_SET_RATE_PARENT,
1499 static struct clk_branch mdss_dp_link_clk = {
1502 .enable_reg = 0x2354,
1503 .enable_mask = BIT(0),
1504 .hw.init = &(struct clk_init_data){
1505 .name = "mdss_dp_link_clk",
1506 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1508 .ops = &clk_branch2_ops,
1509 .flags = CLK_SET_RATE_PARENT,
1514 static struct clk_branch mdss_dp_link_intf_clk = {
1517 .enable_reg = 0x2358,
1518 .enable_mask = BIT(0),
1519 .hw.init = &(struct clk_init_data){
1520 .name = "mdss_dp_link_intf_clk",
1521 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1523 .ops = &clk_branch2_ops,
1524 .flags = CLK_SET_RATE_PARENT,
1529 static struct clk_branch mdss_dp_crypto_clk = {
1532 .enable_reg = 0x235c,
1533 .enable_mask = BIT(0),
1534 .hw.init = &(struct clk_init_data){
1535 .name = "mdss_dp_crypto_clk",
1536 .parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw },
1538 .ops = &clk_branch2_ops,
1539 .flags = CLK_SET_RATE_PARENT,
1544 static struct clk_branch mdss_dp_pixel_clk = {
1547 .enable_reg = 0x2360,
1548 .enable_mask = BIT(0),
1549 .hw.init = &(struct clk_init_data){
1550 .name = "mdss_dp_pixel_clk",
1551 .parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw },
1553 .ops = &clk_branch2_ops,
1554 .flags = CLK_SET_RATE_PARENT,
1559 static struct clk_branch mdss_dp_aux_clk = {
1562 .enable_reg = 0x2364,
1563 .enable_mask = BIT(0),
1564 .hw.init = &(struct clk_init_data){
1565 .name = "mdss_dp_aux_clk",
1566 .parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw },
1568 .ops = &clk_branch2_ops,
1569 .flags = CLK_SET_RATE_PARENT,
1574 static struct clk_branch mdss_byte0_intf_clk = {
1577 .enable_reg = 0x2374,
1578 .enable_mask = BIT(0),
1579 .hw.init = &(struct clk_init_data){
1580 .name = "mdss_byte0_intf_clk",
1581 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1583 .ops = &clk_branch2_ops,
1584 .flags = CLK_SET_RATE_PARENT,
1589 static struct clk_branch mdss_byte1_intf_clk = {
1592 .enable_reg = 0x2378,
1593 .enable_mask = BIT(0),
1594 .hw.init = &(struct clk_init_data){
1595 .name = "mdss_byte1_intf_clk",
1596 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1598 .ops = &clk_branch2_ops,
1599 .flags = CLK_SET_RATE_PARENT,
1604 static struct clk_branch camss_csi0phytimer_clk = {
1607 .enable_reg = 0x3024,
1608 .enable_mask = BIT(0),
1609 .hw.init = &(struct clk_init_data){
1610 .name = "camss_csi0phytimer_clk",
1611 .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1613 .ops = &clk_branch2_ops,
1614 .flags = CLK_SET_RATE_PARENT,
1619 static struct clk_branch camss_csi1phytimer_clk = {
1622 .enable_reg = 0x3054,
1623 .enable_mask = BIT(0),
1624 .hw.init = &(struct clk_init_data){
1625 .name = "camss_csi1phytimer_clk",
1626 .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1628 .ops = &clk_branch2_ops,
1629 .flags = CLK_SET_RATE_PARENT,
1634 static struct clk_branch camss_csi2phytimer_clk = {
1637 .enable_reg = 0x3084,
1638 .enable_mask = BIT(0),
1639 .hw.init = &(struct clk_init_data){
1640 .name = "camss_csi2phytimer_clk",
1641 .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1643 .ops = &clk_branch2_ops,
1644 .flags = CLK_SET_RATE_PARENT,
1649 static struct clk_branch camss_csi0_clk = {
1652 .enable_reg = 0x30b4,
1653 .enable_mask = BIT(0),
1654 .hw.init = &(struct clk_init_data){
1655 .name = "camss_csi0_clk",
1656 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1658 .ops = &clk_branch2_ops,
1659 .flags = CLK_SET_RATE_PARENT,
1664 static struct clk_branch camss_csi0_ahb_clk = {
1667 .enable_reg = 0x30bc,
1668 .enable_mask = BIT(0),
1669 .hw.init = &(struct clk_init_data){
1670 .name = "camss_csi0_ahb_clk",
1671 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1673 .ops = &clk_branch2_ops,
1674 .flags = CLK_SET_RATE_PARENT,
1679 static struct clk_branch camss_csi0rdi_clk = {
1682 .enable_reg = 0x30d4,
1683 .enable_mask = BIT(0),
1684 .hw.init = &(struct clk_init_data){
1685 .name = "camss_csi0rdi_clk",
1686 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1688 .ops = &clk_branch2_ops,
1689 .flags = CLK_SET_RATE_PARENT,
1694 static struct clk_branch camss_csi0pix_clk = {
1697 .enable_reg = 0x30e4,
1698 .enable_mask = BIT(0),
1699 .hw.init = &(struct clk_init_data){
1700 .name = "camss_csi0pix_clk",
1701 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1703 .ops = &clk_branch2_ops,
1704 .flags = CLK_SET_RATE_PARENT,
1709 static struct clk_branch camss_csi1_clk = {
1712 .enable_reg = 0x3124,
1713 .enable_mask = BIT(0),
1714 .hw.init = &(struct clk_init_data){
1715 .name = "camss_csi1_clk",
1716 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1718 .ops = &clk_branch2_ops,
1719 .flags = CLK_SET_RATE_PARENT,
1724 static struct clk_branch camss_csi1_ahb_clk = {
1727 .enable_reg = 0x3128,
1728 .enable_mask = BIT(0),
1729 .hw.init = &(struct clk_init_data){
1730 .name = "camss_csi1_ahb_clk",
1731 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1733 .ops = &clk_branch2_ops,
1734 .flags = CLK_SET_RATE_PARENT,
1739 static struct clk_branch camss_csi1rdi_clk = {
1742 .enable_reg = 0x3144,
1743 .enable_mask = BIT(0),
1744 .hw.init = &(struct clk_init_data){
1745 .name = "camss_csi1rdi_clk",
1746 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1748 .ops = &clk_branch2_ops,
1749 .flags = CLK_SET_RATE_PARENT,
1754 static struct clk_branch camss_csi1pix_clk = {
1757 .enable_reg = 0x3154,
1758 .enable_mask = BIT(0),
1759 .hw.init = &(struct clk_init_data){
1760 .name = "camss_csi1pix_clk",
1761 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1763 .ops = &clk_branch2_ops,
1764 .flags = CLK_SET_RATE_PARENT,
1769 static struct clk_branch camss_csi2_clk = {
1772 .enable_reg = 0x3184,
1773 .enable_mask = BIT(0),
1774 .hw.init = &(struct clk_init_data){
1775 .name = "camss_csi2_clk",
1776 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1778 .ops = &clk_branch2_ops,
1779 .flags = CLK_SET_RATE_PARENT,
1784 static struct clk_branch camss_csi2_ahb_clk = {
1787 .enable_reg = 0x3188,
1788 .enable_mask = BIT(0),
1789 .hw.init = &(struct clk_init_data){
1790 .name = "camss_csi2_ahb_clk",
1791 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1793 .ops = &clk_branch2_ops,
1794 .flags = CLK_SET_RATE_PARENT,
1799 static struct clk_branch camss_csi2rdi_clk = {
1802 .enable_reg = 0x31a4,
1803 .enable_mask = BIT(0),
1804 .hw.init = &(struct clk_init_data){
1805 .name = "camss_csi2rdi_clk",
1806 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1808 .ops = &clk_branch2_ops,
1809 .flags = CLK_SET_RATE_PARENT,
1814 static struct clk_branch camss_csi2pix_clk = {
1817 .enable_reg = 0x31b4,
1818 .enable_mask = BIT(0),
1819 .hw.init = &(struct clk_init_data){
1820 .name = "camss_csi2pix_clk",
1821 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1823 .ops = &clk_branch2_ops,
1824 .flags = CLK_SET_RATE_PARENT,
1829 static struct clk_branch camss_csi3_clk = {
1832 .enable_reg = 0x31e4,
1833 .enable_mask = BIT(0),
1834 .hw.init = &(struct clk_init_data){
1835 .name = "camss_csi3_clk",
1836 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1838 .ops = &clk_branch2_ops,
1839 .flags = CLK_SET_RATE_PARENT,
1844 static struct clk_branch camss_csi3_ahb_clk = {
1847 .enable_reg = 0x31e8,
1848 .enable_mask = BIT(0),
1849 .hw.init = &(struct clk_init_data){
1850 .name = "camss_csi3_ahb_clk",
1851 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1853 .ops = &clk_branch2_ops,
1854 .flags = CLK_SET_RATE_PARENT,
1859 static struct clk_branch camss_csi3rdi_clk = {
1862 .enable_reg = 0x3204,
1863 .enable_mask = BIT(0),
1864 .hw.init = &(struct clk_init_data){
1865 .name = "camss_csi3rdi_clk",
1866 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1868 .ops = &clk_branch2_ops,
1869 .flags = CLK_SET_RATE_PARENT,
1874 static struct clk_branch camss_csi3pix_clk = {
1877 .enable_reg = 0x3214,
1878 .enable_mask = BIT(0),
1879 .hw.init = &(struct clk_init_data){
1880 .name = "camss_csi3pix_clk",
1881 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1883 .ops = &clk_branch2_ops,
1884 .flags = CLK_SET_RATE_PARENT,
1889 static struct clk_branch camss_ispif_ahb_clk = {
1892 .enable_reg = 0x3224,
1893 .enable_mask = BIT(0),
1894 .hw.init = &(struct clk_init_data){
1895 .name = "camss_ispif_ahb_clk",
1896 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1898 .ops = &clk_branch2_ops,
1899 .flags = CLK_SET_RATE_PARENT,
1904 static struct clk_branch camss_cci_clk = {
1907 .enable_reg = 0x3344,
1908 .enable_mask = BIT(0),
1909 .hw.init = &(struct clk_init_data){
1910 .name = "camss_cci_clk",
1911 .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1913 .ops = &clk_branch2_ops,
1914 .flags = CLK_SET_RATE_PARENT,
1919 static struct clk_branch camss_cci_ahb_clk = {
1922 .enable_reg = 0x3348,
1923 .enable_mask = BIT(0),
1924 .hw.init = &(struct clk_init_data){
1925 .name = "camss_cci_ahb_clk",
1926 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1928 .ops = &clk_branch2_ops,
1929 .flags = CLK_SET_RATE_PARENT,
1934 static struct clk_branch camss_mclk0_clk = {
1937 .enable_reg = 0x3384,
1938 .enable_mask = BIT(0),
1939 .hw.init = &(struct clk_init_data){
1940 .name = "camss_mclk0_clk",
1941 .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1943 .ops = &clk_branch2_ops,
1944 .flags = CLK_SET_RATE_PARENT,
1949 static struct clk_branch camss_mclk1_clk = {
1952 .enable_reg = 0x33b4,
1953 .enable_mask = BIT(0),
1954 .hw.init = &(struct clk_init_data){
1955 .name = "camss_mclk1_clk",
1956 .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1958 .ops = &clk_branch2_ops,
1959 .flags = CLK_SET_RATE_PARENT,
1964 static struct clk_branch camss_mclk2_clk = {
1967 .enable_reg = 0x33e4,
1968 .enable_mask = BIT(0),
1969 .hw.init = &(struct clk_init_data){
1970 .name = "camss_mclk2_clk",
1971 .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
1973 .ops = &clk_branch2_ops,
1974 .flags = CLK_SET_RATE_PARENT,
1979 static struct clk_branch camss_mclk3_clk = {
1982 .enable_reg = 0x3414,
1983 .enable_mask = BIT(0),
1984 .hw.init = &(struct clk_init_data){
1985 .name = "camss_mclk3_clk",
1986 .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
1988 .ops = &clk_branch2_ops,
1989 .flags = CLK_SET_RATE_PARENT,
1994 static struct clk_branch camss_top_ahb_clk = {
1997 .enable_reg = 0x3484,
1998 .enable_mask = BIT(0),
1999 .hw.init = &(struct clk_init_data){
2000 .name = "camss_top_ahb_clk",
2001 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2003 .ops = &clk_branch2_ops,
2004 .flags = CLK_SET_RATE_PARENT,
2009 static struct clk_branch camss_ahb_clk = {
2012 .enable_reg = 0x348c,
2013 .enable_mask = BIT(0),
2014 .hw.init = &(struct clk_init_data){
2015 .name = "camss_ahb_clk",
2016 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2018 .ops = &clk_branch2_ops,
2019 .flags = CLK_SET_RATE_PARENT,
2024 static struct clk_branch camss_micro_ahb_clk = {
2027 .enable_reg = 0x3494,
2028 .enable_mask = BIT(0),
2029 .hw.init = &(struct clk_init_data){
2030 .name = "camss_micro_ahb_clk",
2031 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2033 .ops = &clk_branch2_ops,
2034 .flags = CLK_SET_RATE_PARENT,
2039 static struct clk_branch camss_jpeg0_clk = {
2042 .enable_reg = 0x35a8,
2043 .enable_mask = BIT(0),
2044 .hw.init = &(struct clk_init_data){
2045 .name = "camss_jpeg0_clk",
2046 .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
2048 .ops = &clk_branch2_ops,
2049 .flags = CLK_SET_RATE_PARENT,
2054 static struct clk_branch camss_jpeg_ahb_clk = {
2057 .enable_reg = 0x35b4,
2058 .enable_mask = BIT(0),
2059 .hw.init = &(struct clk_init_data){
2060 .name = "camss_jpeg_ahb_clk",
2061 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2063 .ops = &clk_branch2_ops,
2064 .flags = CLK_SET_RATE_PARENT,
2069 static struct clk_branch camss_jpeg_axi_clk = {
2072 .enable_reg = 0x35b8,
2073 .enable_mask = BIT(0),
2074 .hw.init = &(struct clk_init_data){
2075 .name = "camss_jpeg_axi_clk",
2076 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2078 .ops = &clk_branch2_ops,
2083 static struct clk_branch camss_vfe0_ahb_clk = {
2086 .enable_reg = 0x3668,
2087 .enable_mask = BIT(0),
2088 .hw.init = &(struct clk_init_data){
2089 .name = "camss_vfe0_ahb_clk",
2090 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2092 .ops = &clk_branch2_ops,
2093 .flags = CLK_SET_RATE_PARENT,
2098 static struct clk_branch camss_vfe1_ahb_clk = {
2101 .enable_reg = 0x3678,
2102 .enable_mask = BIT(0),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "camss_vfe1_ahb_clk",
2105 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2107 .ops = &clk_branch2_ops,
2108 .flags = CLK_SET_RATE_PARENT,
2113 static struct clk_branch camss_vfe0_clk = {
2116 .enable_reg = 0x36a8,
2117 .enable_mask = BIT(0),
2118 .hw.init = &(struct clk_init_data){
2119 .name = "camss_vfe0_clk",
2120 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2122 .ops = &clk_branch2_ops,
2123 .flags = CLK_SET_RATE_PARENT,
2128 static struct clk_branch camss_vfe1_clk = {
2131 .enable_reg = 0x36ac,
2132 .enable_mask = BIT(0),
2133 .hw.init = &(struct clk_init_data){
2134 .name = "camss_vfe1_clk",
2135 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2137 .ops = &clk_branch2_ops,
2138 .flags = CLK_SET_RATE_PARENT,
2143 static struct clk_branch camss_cpp_clk = {
2146 .enable_reg = 0x36b0,
2147 .enable_mask = BIT(0),
2148 .hw.init = &(struct clk_init_data){
2149 .name = "camss_cpp_clk",
2150 .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
2152 .ops = &clk_branch2_ops,
2153 .flags = CLK_SET_RATE_PARENT,
2158 static struct clk_branch camss_cpp_ahb_clk = {
2161 .enable_reg = 0x36b4,
2162 .enable_mask = BIT(0),
2163 .hw.init = &(struct clk_init_data){
2164 .name = "camss_cpp_ahb_clk",
2165 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2167 .ops = &clk_branch2_ops,
2168 .flags = CLK_SET_RATE_PARENT,
2173 static struct clk_branch camss_vfe_vbif_ahb_clk = {
2176 .enable_reg = 0x36b8,
2177 .enable_mask = BIT(0),
2178 .hw.init = &(struct clk_init_data){
2179 .name = "camss_vfe_vbif_ahb_clk",
2180 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2182 .ops = &clk_branch2_ops,
2183 .flags = CLK_SET_RATE_PARENT,
2188 static struct clk_branch camss_vfe_vbif_axi_clk = {
2191 .enable_reg = 0x36bc,
2192 .enable_mask = BIT(0),
2193 .hw.init = &(struct clk_init_data){
2194 .name = "camss_vfe_vbif_axi_clk",
2195 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2197 .ops = &clk_branch2_ops,
2202 static struct clk_branch camss_cpp_axi_clk = {
2205 .enable_reg = 0x36c4,
2206 .enable_mask = BIT(0),
2207 .hw.init = &(struct clk_init_data){
2208 .name = "camss_cpp_axi_clk",
2209 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2211 .ops = &clk_branch2_ops,
2216 static struct clk_branch camss_cpp_vbif_ahb_clk = {
2219 .enable_reg = 0x36c8,
2220 .enable_mask = BIT(0),
2221 .hw.init = &(struct clk_init_data){
2222 .name = "camss_cpp_vbif_ahb_clk",
2223 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2225 .ops = &clk_branch2_ops,
2226 .flags = CLK_SET_RATE_PARENT,
2231 static struct clk_branch camss_csi_vfe0_clk = {
2234 .enable_reg = 0x3704,
2235 .enable_mask = BIT(0),
2236 .hw.init = &(struct clk_init_data){
2237 .name = "camss_csi_vfe0_clk",
2238 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2240 .ops = &clk_branch2_ops,
2241 .flags = CLK_SET_RATE_PARENT,
2246 static struct clk_branch camss_csi_vfe1_clk = {
2249 .enable_reg = 0x3714,
2250 .enable_mask = BIT(0),
2251 .hw.init = &(struct clk_init_data){
2252 .name = "camss_csi_vfe1_clk",
2253 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2255 .ops = &clk_branch2_ops,
2256 .flags = CLK_SET_RATE_PARENT,
2261 static struct clk_branch camss_vfe0_stream_clk = {
2264 .enable_reg = 0x3720,
2265 .enable_mask = BIT(0),
2266 .hw.init = &(struct clk_init_data){
2267 .name = "camss_vfe0_stream_clk",
2268 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2270 .ops = &clk_branch2_ops,
2271 .flags = CLK_SET_RATE_PARENT,
2276 static struct clk_branch camss_vfe1_stream_clk = {
2279 .enable_reg = 0x3724,
2280 .enable_mask = BIT(0),
2281 .hw.init = &(struct clk_init_data){
2282 .name = "camss_vfe1_stream_clk",
2283 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2285 .ops = &clk_branch2_ops,
2286 .flags = CLK_SET_RATE_PARENT,
2291 static struct clk_branch camss_cphy_csid0_clk = {
2294 .enable_reg = 0x3730,
2295 .enable_mask = BIT(0),
2296 .hw.init = &(struct clk_init_data){
2297 .name = "camss_cphy_csid0_clk",
2298 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2300 .ops = &clk_branch2_ops,
2301 .flags = CLK_SET_RATE_PARENT,
2306 static struct clk_branch camss_cphy_csid1_clk = {
2309 .enable_reg = 0x3734,
2310 .enable_mask = BIT(0),
2311 .hw.init = &(struct clk_init_data){
2312 .name = "camss_cphy_csid1_clk",
2313 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2315 .ops = &clk_branch2_ops,
2316 .flags = CLK_SET_RATE_PARENT,
2321 static struct clk_branch camss_cphy_csid2_clk = {
2324 .enable_reg = 0x3738,
2325 .enable_mask = BIT(0),
2326 .hw.init = &(struct clk_init_data){
2327 .name = "camss_cphy_csid2_clk",
2328 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2330 .ops = &clk_branch2_ops,
2331 .flags = CLK_SET_RATE_PARENT,
2336 static struct clk_branch camss_cphy_csid3_clk = {
2339 .enable_reg = 0x373c,
2340 .enable_mask = BIT(0),
2341 .hw.init = &(struct clk_init_data){
2342 .name = "camss_cphy_csid3_clk",
2343 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2345 .ops = &clk_branch2_ops,
2346 .flags = CLK_SET_RATE_PARENT,
2351 static struct clk_branch camss_csiphy0_clk = {
2354 .enable_reg = 0x3740,
2355 .enable_mask = BIT(0),
2356 .hw.init = &(struct clk_init_data){
2357 .name = "camss_csiphy0_clk",
2358 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2360 .ops = &clk_branch2_ops,
2361 .flags = CLK_SET_RATE_PARENT,
2366 static struct clk_branch camss_csiphy1_clk = {
2369 .enable_reg = 0x3744,
2370 .enable_mask = BIT(0),
2371 .hw.init = &(struct clk_init_data){
2372 .name = "camss_csiphy1_clk",
2373 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2375 .ops = &clk_branch2_ops,
2376 .flags = CLK_SET_RATE_PARENT,
2381 static struct clk_branch camss_csiphy2_clk = {
2384 .enable_reg = 0x3748,
2385 .enable_mask = BIT(0),
2386 .hw.init = &(struct clk_init_data){
2387 .name = "camss_csiphy2_clk",
2388 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2390 .ops = &clk_branch2_ops,
2391 .flags = CLK_SET_RATE_PARENT,
2396 static struct clk_branch fd_core_clk = {
2399 .enable_reg = 0x3b68,
2400 .enable_mask = BIT(0),
2401 .hw.init = &(struct clk_init_data){
2402 .name = "fd_core_clk",
2403 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2405 .ops = &clk_branch2_ops,
2406 .flags = CLK_SET_RATE_PARENT,
2411 static struct clk_branch fd_core_uar_clk = {
2414 .enable_reg = 0x3b6c,
2415 .enable_mask = BIT(0),
2416 .hw.init = &(struct clk_init_data){
2417 .name = "fd_core_uar_clk",
2418 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2420 .ops = &clk_branch2_ops,
2421 .flags = CLK_SET_RATE_PARENT,
2426 static struct clk_branch fd_ahb_clk = {
2429 .enable_reg = 0x3b74,
2430 .enable_mask = BIT(0),
2431 .hw.init = &(struct clk_init_data){
2432 .name = "fd_ahb_clk",
2433 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2435 .ops = &clk_branch2_ops,
2436 .flags = CLK_SET_RATE_PARENT,
2441 static struct clk_branch mnoc_ahb_clk = {
2444 .enable_reg = 0x5024,
2445 .enable_mask = BIT(0),
2446 .hw.init = &(struct clk_init_data){
2447 .name = "mnoc_ahb_clk",
2448 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2450 .ops = &clk_branch2_ops,
2451 .flags = CLK_SET_RATE_PARENT,
2456 static struct clk_branch bimc_smmu_ahb_clk = {
2461 .enable_reg = 0xe004,
2462 .enable_mask = BIT(0),
2463 .hw.init = &(struct clk_init_data){
2464 .name = "bimc_smmu_ahb_clk",
2465 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2467 .ops = &clk_branch2_ops,
2468 .flags = CLK_SET_RATE_PARENT,
2473 static struct clk_branch bimc_smmu_axi_clk = {
2478 .enable_reg = 0xe008,
2479 .enable_mask = BIT(0),
2480 .hw.init = &(struct clk_init_data){
2481 .name = "bimc_smmu_axi_clk",
2482 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2484 .ops = &clk_branch2_ops,
2489 static struct clk_branch mnoc_maxi_clk = {
2492 .enable_reg = 0xf004,
2493 .enable_mask = BIT(0),
2494 .hw.init = &(struct clk_init_data){
2495 .name = "mnoc_maxi_clk",
2496 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2498 .ops = &clk_branch2_ops,
2499 .flags = CLK_SET_RATE_PARENT,
2504 static struct clk_branch vmem_maxi_clk = {
2507 .enable_reg = 0xf064,
2508 .enable_mask = BIT(0),
2509 .hw.init = &(struct clk_init_data){
2510 .name = "vmem_maxi_clk",
2511 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2513 .ops = &clk_branch2_ops,
2514 .flags = CLK_SET_RATE_PARENT,
2519 static struct clk_branch vmem_ahb_clk = {
2522 .enable_reg = 0xf068,
2523 .enable_mask = BIT(0),
2524 .hw.init = &(struct clk_init_data){
2525 .name = "vmem_ahb_clk",
2526 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2528 .ops = &clk_branch2_ops,
2529 .flags = CLK_SET_RATE_PARENT,
2534 static struct gdsc video_top_gdsc = {
2537 .name = "video_top",
2539 .pwrsts = PWRSTS_OFF_ON,
2542 static struct gdsc video_subcore0_gdsc = {
2545 .name = "video_subcore0",
2547 .parent = &video_top_gdsc.pd,
2548 .pwrsts = PWRSTS_OFF_ON,
2551 static struct gdsc video_subcore1_gdsc = {
2554 .name = "video_subcore1",
2556 .parent = &video_top_gdsc.pd,
2557 .pwrsts = PWRSTS_OFF_ON,
2560 static struct gdsc mdss_gdsc = {
2562 .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
2567 .pwrsts = PWRSTS_OFF_ON,
2570 static struct gdsc camss_top_gdsc = {
2572 .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
2576 .name = "camss_top",
2578 .pwrsts = PWRSTS_OFF_ON,
2581 static struct gdsc camss_vfe0_gdsc = {
2584 .name = "camss_vfe0",
2586 .parent = &camss_top_gdsc.pd,
2587 .pwrsts = PWRSTS_OFF_ON,
2590 static struct gdsc camss_vfe1_gdsc = {
2593 .name = "camss_vfe1_gdsc",
2595 .parent = &camss_top_gdsc.pd,
2596 .pwrsts = PWRSTS_OFF_ON,
2599 static struct gdsc camss_cpp_gdsc = {
2602 .name = "camss_cpp",
2604 .parent = &camss_top_gdsc.pd,
2605 .pwrsts = PWRSTS_OFF_ON,
2608 static struct gdsc bimc_smmu_gdsc = {
2610 .gds_hw_ctrl = 0xe024,
2612 .name = "bimc_smmu",
2614 .pwrsts = PWRSTS_OFF_ON,
2615 .flags = HW_CTRL | ALWAYS_ON,
2618 static struct clk_regmap *mmcc_msm8998_clocks[] = {
2619 [MMPLL0] = &mmpll0.clkr,
2620 [MMPLL0_OUT_EVEN] = &mmpll0_out_even.clkr,
2621 [MMPLL1] = &mmpll1.clkr,
2622 [MMPLL1_OUT_EVEN] = &mmpll1_out_even.clkr,
2623 [MMPLL3] = &mmpll3.clkr,
2624 [MMPLL3_OUT_EVEN] = &mmpll3_out_even.clkr,
2625 [MMPLL4] = &mmpll4.clkr,
2626 [MMPLL4_OUT_EVEN] = &mmpll4_out_even.clkr,
2627 [MMPLL5] = &mmpll5.clkr,
2628 [MMPLL5_OUT_EVEN] = &mmpll5_out_even.clkr,
2629 [MMPLL6] = &mmpll6.clkr,
2630 [MMPLL6_OUT_EVEN] = &mmpll6_out_even.clkr,
2631 [MMPLL7] = &mmpll7.clkr,
2632 [MMPLL7_OUT_EVEN] = &mmpll7_out_even.clkr,
2633 [MMPLL10] = &mmpll10.clkr,
2634 [MMPLL10_OUT_EVEN] = &mmpll10_out_even.clkr,
2635 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2636 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2637 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2638 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2639 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2640 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2641 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2642 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2643 [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr,
2644 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2645 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2646 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2647 [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr,
2648 [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr,
2649 [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr,
2650 [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr,
2651 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2652 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2653 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2654 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2655 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2656 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2657 [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
2658 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2659 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2660 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2661 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2662 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2663 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2664 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2665 [AXI_CLK_SRC] = &axi_clk_src.clkr,
2666 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2667 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2668 [ROT_CLK_SRC] = &rot_clk_src.clkr,
2669 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
2670 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
2671 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
2672 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2673 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2674 [MISC_AHB_CLK] = &misc_ahb_clk.clkr,
2675 [VIDEO_CORE_CLK] = &video_core_clk.clkr,
2676 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
2677 [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
2678 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
2679 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
2680 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
2681 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2682 [MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr,
2683 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2684 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2685 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2686 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2687 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2688 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2689 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2690 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2691 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2692 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2693 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2694 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2695 [MDSS_ROT_CLK] = &mdss_rot_clk.clkr,
2696 [MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr,
2697 [MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr,
2698 [MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr,
2699 [MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr,
2700 [MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr,
2701 [MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr,
2702 [MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr,
2703 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
2704 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
2705 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
2706 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2707 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2708 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2709 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2710 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2711 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2712 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2713 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2714 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2715 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2716 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2717 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2718 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2719 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2720 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2721 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2722 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2723 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
2724 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
2725 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2726 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2727 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2728 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2729 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2730 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2731 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2732 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
2733 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
2734 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
2735 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
2736 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
2737 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
2738 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
2739 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
2740 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
2741 [CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr,
2742 [CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr,
2743 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
2744 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
2745 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2746 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2747 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
2748 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
2749 [CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr,
2750 [CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr,
2751 [CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr,
2752 [CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr,
2753 [CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr,
2754 [CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr,
2755 [CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr,
2756 [FD_CORE_CLK] = &fd_core_clk.clkr,
2757 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
2758 [FD_AHB_CLK] = &fd_ahb_clk.clkr,
2759 [MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr,
2760 [BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr,
2761 [BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr,
2762 [MNOC_MAXI_CLK] = &mnoc_maxi_clk.clkr,
2763 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
2764 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
2767 static struct gdsc *mmcc_msm8998_gdscs[] = {
2768 [VIDEO_TOP_GDSC] = &video_top_gdsc,
2769 [VIDEO_SUBCORE0_GDSC] = &video_subcore0_gdsc,
2770 [VIDEO_SUBCORE1_GDSC] = &video_subcore1_gdsc,
2771 [MDSS_GDSC] = &mdss_gdsc,
2772 [CAMSS_TOP_GDSC] = &camss_top_gdsc,
2773 [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
2774 [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
2775 [CAMSS_CPP_GDSC] = &camss_cpp_gdsc,
2776 [BIMC_SMMU_GDSC] = &bimc_smmu_gdsc,
2779 static const struct qcom_reset_map mmcc_msm8998_resets[] = {
2780 [SPDM_BCR] = { 0x200 },
2781 [SPDM_RM_BCR] = { 0x300 },
2782 [MISC_BCR] = { 0x320 },
2783 [VIDEO_TOP_BCR] = { 0x1020 },
2784 [THROTTLE_VIDEO_BCR] = { 0x1180 },
2785 [MDSS_BCR] = { 0x2300 },
2786 [THROTTLE_MDSS_BCR] = { 0x2460 },
2787 [CAMSS_PHY0_BCR] = { 0x3020 },
2788 [CAMSS_PHY1_BCR] = { 0x3050 },
2789 [CAMSS_PHY2_BCR] = { 0x3080 },
2790 [CAMSS_CSI0_BCR] = { 0x30b0 },
2791 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
2792 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
2793 [CAMSS_CSI1_BCR] = { 0x3120 },
2794 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
2795 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
2796 [CAMSS_CSI2_BCR] = { 0x3180 },
2797 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
2798 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
2799 [CAMSS_CSI3_BCR] = { 0x31e0 },
2800 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
2801 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
2802 [CAMSS_ISPIF_BCR] = { 0x3220 },
2803 [CAMSS_CCI_BCR] = { 0x3340 },
2804 [CAMSS_TOP_BCR] = { 0x3480 },
2805 [CAMSS_AHB_BCR] = { 0x3488 },
2806 [CAMSS_MICRO_BCR] = { 0x3490 },
2807 [CAMSS_JPEG_BCR] = { 0x35a0 },
2808 [CAMSS_VFE0_BCR] = { 0x3660 },
2809 [CAMSS_VFE1_BCR] = { 0x3670 },
2810 [CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
2811 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
2812 [CAMSS_CPP_BCR] = { 0x36d0 },
2813 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
2814 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
2815 [CAMSS_FD_BCR] = { 0x3b60 },
2816 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
2817 [MNOCAHB_BCR] = { 0x5020 },
2818 [MNOCAXI_BCR] = { 0xd020 },
2819 [BMIC_SMMU_BCR] = { 0xe000 },
2820 [MNOC_MAXI_BCR] = { 0xf000 },
2821 [VMEM_BCR] = { 0xf060 },
2822 [BTO_BCR] = { 0x10004 },
2825 static const struct regmap_config mmcc_msm8998_regmap_config = {
2829 .max_register = 0x10004,
2833 static const struct qcom_cc_desc mmcc_msm8998_desc = {
2834 .config = &mmcc_msm8998_regmap_config,
2835 .clks = mmcc_msm8998_clocks,
2836 .num_clks = ARRAY_SIZE(mmcc_msm8998_clocks),
2837 .resets = mmcc_msm8998_resets,
2838 .num_resets = ARRAY_SIZE(mmcc_msm8998_resets),
2839 .gdscs = mmcc_msm8998_gdscs,
2840 .num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs),
2843 static const struct of_device_id mmcc_msm8998_match_table[] = {
2844 { .compatible = "qcom,mmcc-msm8998" },
2847 MODULE_DEVICE_TABLE(of, mmcc_msm8998_match_table);
2849 static int mmcc_msm8998_probe(struct platform_device *pdev)
2851 struct regmap *regmap;
2853 regmap = qcom_cc_map(pdev, &mmcc_msm8998_desc);
2855 return PTR_ERR(regmap);
2857 return qcom_cc_really_probe(pdev, &mmcc_msm8998_desc, regmap);
2860 static struct platform_driver mmcc_msm8998_driver = {
2861 .probe = mmcc_msm8998_probe,
2863 .name = "mmcc-msm8998",
2864 .of_match_table = mmcc_msm8998_match_table,
2867 module_platform_driver(mmcc_msm8998_driver);
2869 MODULE_DESCRIPTION("QCOM MMCC MSM8998 Driver");
2870 MODULE_LICENSE("GPL v2");