2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
24 #include <linux/clk.h>
26 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
29 #include "clk-regmap.h"
30 #include "clk-regmap-divider.h"
31 #include "clk-alpha-pll.h"
33 #include "clk-branch.h"
36 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
57 static const struct parent_map mmss_xo_hdmi_map[] = {
62 static const char * const mmss_xo_hdmi[] = {
67 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
73 static const char * const mmss_xo_dsi0pll_dsi1pll[] = {
79 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
85 static const char * const mmss_xo_gpll0_gpll0_div[] = {
91 static const struct parent_map mmss_xo_dsibyte_map[] = {
93 { P_DSI0PLL_BYTE, 1 },
97 static const char * const mmss_xo_dsibyte[] = {
103 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
110 static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = {
117 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
125 static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
133 static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = {
141 static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = {
149 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
157 static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
165 static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = {
173 static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = {
181 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = {
190 static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = {
199 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = {
209 static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = {
219 static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = {
229 static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = {
239 static struct clk_fixed_factor gpll0_div = {
242 .hw.init = &(struct clk_init_data){
244 .parent_names = (const char *[]){ "gpll0" },
246 .ops = &clk_fixed_factor_ops,
250 static struct pll_vco mmpll_p_vco[] = {
251 { 250000000, 500000000, 3 },
252 { 500000000, 1000000000, 2 },
253 { 1000000000, 1500000000, 1 },
254 { 1500000000, 2000000000, 0 },
257 static struct pll_vco mmpll_gfx_vco[] = {
258 { 400000000, 1000000000, 2 },
259 { 1000000000, 1500000000, 1 },
260 { 1500000000, 2000000000, 0 },
263 static struct pll_vco mmpll_t_vco[] = {
264 { 500000000, 1500000000, 0 },
267 static struct clk_alpha_pll mmpll0_early = {
269 .vco_table = mmpll_p_vco,
270 .num_vco = ARRAY_SIZE(mmpll_p_vco),
273 .enable_mask = BIT(0),
274 .hw.init = &(struct clk_init_data){
275 .name = "mmpll0_early",
276 .parent_names = (const char *[]){ "xo" },
278 .ops = &clk_alpha_pll_ops,
283 static struct clk_alpha_pll_postdiv mmpll0 = {
286 .clkr.hw.init = &(struct clk_init_data){
288 .parent_names = (const char *[]){ "mmpll0_early" },
290 .ops = &clk_alpha_pll_postdiv_ops,
291 .flags = CLK_SET_RATE_PARENT,
295 static struct clk_alpha_pll mmpll1_early = {
297 .vco_table = mmpll_p_vco,
298 .num_vco = ARRAY_SIZE(mmpll_p_vco),
301 .enable_mask = BIT(1),
302 .hw.init = &(struct clk_init_data){
303 .name = "mmpll1_early",
304 .parent_names = (const char *[]){ "xo" },
306 .ops = &clk_alpha_pll_ops,
311 static struct clk_alpha_pll_postdiv mmpll1 = {
314 .clkr.hw.init = &(struct clk_init_data){
316 .parent_names = (const char *[]){ "mmpll1_early" },
318 .ops = &clk_alpha_pll_postdiv_ops,
319 .flags = CLK_SET_RATE_PARENT,
323 static struct clk_alpha_pll mmpll2_early = {
325 .vco_table = mmpll_gfx_vco,
326 .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
327 .clkr.hw.init = &(struct clk_init_data){
328 .name = "mmpll2_early",
329 .parent_names = (const char *[]){ "xo" },
331 .ops = &clk_alpha_pll_ops,
335 static struct clk_alpha_pll_postdiv mmpll2 = {
338 .clkr.hw.init = &(struct clk_init_data){
340 .parent_names = (const char *[]){ "mmpll2_early" },
342 .ops = &clk_alpha_pll_postdiv_ops,
343 .flags = CLK_SET_RATE_PARENT,
347 static struct clk_alpha_pll mmpll3_early = {
349 .vco_table = mmpll_p_vco,
350 .num_vco = ARRAY_SIZE(mmpll_p_vco),
351 .clkr.hw.init = &(struct clk_init_data){
352 .name = "mmpll3_early",
353 .parent_names = (const char *[]){ "xo" },
355 .ops = &clk_alpha_pll_ops,
359 static struct clk_alpha_pll_postdiv mmpll3 = {
362 .clkr.hw.init = &(struct clk_init_data){
364 .parent_names = (const char *[]){ "mmpll3_early" },
366 .ops = &clk_alpha_pll_postdiv_ops,
367 .flags = CLK_SET_RATE_PARENT,
371 static struct clk_alpha_pll mmpll4_early = {
373 .vco_table = mmpll_t_vco,
374 .num_vco = ARRAY_SIZE(mmpll_t_vco),
375 .clkr.hw.init = &(struct clk_init_data){
376 .name = "mmpll4_early",
377 .parent_names = (const char *[]){ "xo" },
379 .ops = &clk_alpha_pll_ops,
383 static struct clk_alpha_pll_postdiv mmpll4 = {
386 .clkr.hw.init = &(struct clk_init_data){
388 .parent_names = (const char *[]){ "mmpll4_early" },
390 .ops = &clk_alpha_pll_postdiv_ops,
391 .flags = CLK_SET_RATE_PARENT,
395 static struct clk_alpha_pll mmpll5_early = {
397 .vco_table = mmpll_p_vco,
398 .num_vco = ARRAY_SIZE(mmpll_p_vco),
399 .clkr.hw.init = &(struct clk_init_data){
400 .name = "mmpll5_early",
401 .parent_names = (const char *[]){ "xo" },
403 .ops = &clk_alpha_pll_ops,
407 static struct clk_alpha_pll_postdiv mmpll5 = {
410 .clkr.hw.init = &(struct clk_init_data){
412 .parent_names = (const char *[]){ "mmpll5_early" },
414 .ops = &clk_alpha_pll_postdiv_ops,
415 .flags = CLK_SET_RATE_PARENT,
419 static struct clk_alpha_pll mmpll8_early = {
421 .vco_table = mmpll_gfx_vco,
422 .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
423 .clkr.hw.init = &(struct clk_init_data){
424 .name = "mmpll8_early",
425 .parent_names = (const char *[]){ "xo" },
427 .ops = &clk_alpha_pll_ops,
431 static struct clk_alpha_pll_postdiv mmpll8 = {
434 .clkr.hw.init = &(struct clk_init_data){
436 .parent_names = (const char *[]){ "mmpll8_early" },
438 .ops = &clk_alpha_pll_postdiv_ops,
439 .flags = CLK_SET_RATE_PARENT,
443 static struct clk_alpha_pll mmpll9_early = {
445 .vco_table = mmpll_t_vco,
446 .num_vco = ARRAY_SIZE(mmpll_t_vco),
447 .clkr.hw.init = &(struct clk_init_data){
448 .name = "mmpll9_early",
449 .parent_names = (const char *[]){ "xo" },
451 .ops = &clk_alpha_pll_ops,
455 static struct clk_alpha_pll_postdiv mmpll9 = {
458 .clkr.hw.init = &(struct clk_init_data){
460 .parent_names = (const char *[]){ "mmpll9_early" },
462 .ops = &clk_alpha_pll_postdiv_ops,
463 .flags = CLK_SET_RATE_PARENT,
467 static const struct freq_tbl ftbl_ahb_clk_src[] = {
468 F(19200000, P_XO, 1, 0, 0),
469 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
470 F(80000000, P_MMPLL0, 10, 0, 0),
474 static struct clk_rcg2 ahb_clk_src = {
477 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
478 .freq_tbl = ftbl_ahb_clk_src,
479 .clkr.hw.init = &(struct clk_init_data){
480 .name = "ahb_clk_src",
481 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
483 .ops = &clk_rcg2_ops,
487 static const struct freq_tbl ftbl_axi_clk_src[] = {
488 F(19200000, P_XO, 1, 0, 0),
489 F(75000000, P_GPLL0_DIV, 4, 0, 0),
490 F(100000000, P_GPLL0, 6, 0, 0),
491 F(171430000, P_GPLL0, 3.5, 0, 0),
492 F(200000000, P_GPLL0, 3, 0, 0),
493 F(320000000, P_MMPLL0, 2.5, 0, 0),
494 F(400000000, P_MMPLL0, 2, 0, 0),
498 static struct clk_rcg2 axi_clk_src = {
501 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
502 .freq_tbl = ftbl_axi_clk_src,
503 .clkr.hw.init = &(struct clk_init_data){
504 .name = "axi_clk_src",
505 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
507 .ops = &clk_rcg2_ops,
511 static struct clk_rcg2 maxi_clk_src = {
514 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
515 .freq_tbl = ftbl_axi_clk_src,
516 .clkr.hw.init = &(struct clk_init_data){
517 .name = "maxi_clk_src",
518 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
520 .ops = &clk_rcg2_ops,
524 static struct clk_rcg2 gfx3d_clk_src = {
527 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
528 .clkr.hw.init = &(struct clk_init_data){
529 .name = "gfx3d_clk_src",
530 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
532 .ops = &clk_gfx3d_ops,
533 .flags = CLK_SET_RATE_PARENT,
537 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
538 F(19200000, P_XO, 1, 0, 0),
542 static struct clk_rcg2 rbbmtimer_clk_src = {
545 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
546 .freq_tbl = ftbl_rbbmtimer_clk_src,
547 .clkr.hw.init = &(struct clk_init_data){
548 .name = "rbbmtimer_clk_src",
549 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
551 .ops = &clk_rcg2_ops,
555 static struct clk_rcg2 isense_clk_src = {
558 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map,
559 .clkr.hw.init = &(struct clk_init_data){
560 .name = "isense_clk_src",
561 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div,
563 .ops = &clk_rcg2_ops,
567 static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
568 F(19200000, P_XO, 1, 0, 0),
569 F(50000000, P_GPLL0, 12, 0, 0),
573 static struct clk_rcg2 rbcpr_clk_src = {
576 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
577 .freq_tbl = ftbl_rbcpr_clk_src,
578 .clkr.hw.init = &(struct clk_init_data){
579 .name = "rbcpr_clk_src",
580 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
582 .ops = &clk_rcg2_ops,
586 static const struct freq_tbl ftbl_video_core_clk_src[] = {
587 F(75000000, P_GPLL0_DIV, 4, 0, 0),
588 F(150000000, P_GPLL0, 4, 0, 0),
589 F(346666667, P_MMPLL3, 3, 0, 0),
590 F(520000000, P_MMPLL3, 2, 0, 0),
594 static struct clk_rcg2 video_core_clk_src = {
598 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
599 .freq_tbl = ftbl_video_core_clk_src,
600 .clkr.hw.init = &(struct clk_init_data){
601 .name = "video_core_clk_src",
602 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
604 .ops = &clk_rcg2_ops,
608 static struct clk_rcg2 video_subcore0_clk_src = {
612 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
613 .freq_tbl = ftbl_video_core_clk_src,
614 .clkr.hw.init = &(struct clk_init_data){
615 .name = "video_subcore0_clk_src",
616 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
618 .ops = &clk_rcg2_ops,
622 static struct clk_rcg2 video_subcore1_clk_src = {
626 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
627 .freq_tbl = ftbl_video_core_clk_src,
628 .clkr.hw.init = &(struct clk_init_data){
629 .name = "video_subcore1_clk_src",
630 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
632 .ops = &clk_rcg2_ops,
636 static struct clk_rcg2 pclk0_clk_src = {
640 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
641 .clkr.hw.init = &(struct clk_init_data){
642 .name = "pclk0_clk_src",
643 .parent_names = mmss_xo_dsi0pll_dsi1pll,
645 .ops = &clk_pixel_ops,
646 .flags = CLK_SET_RATE_PARENT,
650 static struct clk_rcg2 pclk1_clk_src = {
654 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
655 .clkr.hw.init = &(struct clk_init_data){
656 .name = "pclk1_clk_src",
657 .parent_names = mmss_xo_dsi0pll_dsi1pll,
659 .ops = &clk_pixel_ops,
660 .flags = CLK_SET_RATE_PARENT,
664 static const struct freq_tbl ftbl_mdp_clk_src[] = {
665 F(85714286, P_GPLL0, 7, 0, 0),
666 F(100000000, P_GPLL0, 6, 0, 0),
667 F(150000000, P_GPLL0, 4, 0, 0),
668 F(171428571, P_GPLL0, 3.5, 0, 0),
669 F(200000000, P_GPLL0, 3, 0, 0),
670 F(275000000, P_MMPLL5, 3, 0, 0),
671 F(300000000, P_GPLL0, 2, 0, 0),
672 F(330000000, P_MMPLL5, 2.5, 0, 0),
673 F(412500000, P_MMPLL5, 2, 0, 0),
677 static struct clk_rcg2 mdp_clk_src = {
680 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
681 .freq_tbl = ftbl_mdp_clk_src,
682 .clkr.hw.init = &(struct clk_init_data){
683 .name = "mdp_clk_src",
684 .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
686 .ops = &clk_rcg2_ops,
690 static struct freq_tbl extpclk_freq_tbl[] = {
691 { .src = P_HDMIPLL },
695 static struct clk_rcg2 extpclk_clk_src = {
698 .parent_map = mmss_xo_hdmi_map,
699 .freq_tbl = extpclk_freq_tbl,
700 .clkr.hw.init = &(struct clk_init_data){
701 .name = "extpclk_clk_src",
702 .parent_names = mmss_xo_hdmi,
704 .ops = &clk_byte_ops,
705 .flags = CLK_SET_RATE_PARENT,
709 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
710 F(19200000, P_XO, 1, 0, 0),
714 static struct clk_rcg2 vsync_clk_src = {
717 .parent_map = mmss_xo_gpll0_gpll0_div_map,
718 .freq_tbl = ftbl_mdss_vsync_clk,
719 .clkr.hw.init = &(struct clk_init_data){
720 .name = "vsync_clk_src",
721 .parent_names = mmss_xo_gpll0_gpll0_div,
723 .ops = &clk_rcg2_ops,
727 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
728 F(19200000, P_XO, 1, 0, 0),
732 static struct clk_rcg2 hdmi_clk_src = {
735 .parent_map = mmss_xo_gpll0_gpll0_div_map,
736 .freq_tbl = ftbl_mdss_hdmi_clk,
737 .clkr.hw.init = &(struct clk_init_data){
738 .name = "hdmi_clk_src",
739 .parent_names = mmss_xo_gpll0_gpll0_div,
741 .ops = &clk_rcg2_ops,
745 static struct clk_rcg2 byte0_clk_src = {
748 .parent_map = mmss_xo_dsibyte_map,
749 .clkr.hw.init = &(struct clk_init_data){
750 .name = "byte0_clk_src",
751 .parent_names = mmss_xo_dsibyte,
753 .ops = &clk_byte2_ops,
754 .flags = CLK_SET_RATE_PARENT,
758 static struct clk_rcg2 byte1_clk_src = {
761 .parent_map = mmss_xo_dsibyte_map,
762 .clkr.hw.init = &(struct clk_init_data){
763 .name = "byte1_clk_src",
764 .parent_names = mmss_xo_dsibyte,
766 .ops = &clk_byte2_ops,
767 .flags = CLK_SET_RATE_PARENT,
771 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
772 F(19200000, P_XO, 1, 0, 0),
776 static struct clk_rcg2 esc0_clk_src = {
779 .parent_map = mmss_xo_dsibyte_map,
780 .freq_tbl = ftbl_mdss_esc0_1_clk,
781 .clkr.hw.init = &(struct clk_init_data){
782 .name = "esc0_clk_src",
783 .parent_names = mmss_xo_dsibyte,
785 .ops = &clk_rcg2_ops,
789 static struct clk_rcg2 esc1_clk_src = {
792 .parent_map = mmss_xo_dsibyte_map,
793 .freq_tbl = ftbl_mdss_esc0_1_clk,
794 .clkr.hw.init = &(struct clk_init_data){
795 .name = "esc1_clk_src",
796 .parent_names = mmss_xo_dsibyte,
798 .ops = &clk_rcg2_ops,
802 static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
803 F(10000, P_XO, 16, 1, 120),
804 F(24000, P_XO, 16, 1, 50),
805 F(6000000, P_GPLL0_DIV, 10, 1, 5),
806 F(12000000, P_GPLL0_DIV, 1, 1, 25),
807 F(13000000, P_GPLL0_DIV, 2, 13, 150),
808 F(24000000, P_GPLL0_DIV, 1, 2, 25),
812 static struct clk_rcg2 camss_gp0_clk_src = {
816 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
817 .freq_tbl = ftbl_camss_gp0_clk_src,
818 .clkr.hw.init = &(struct clk_init_data){
819 .name = "camss_gp0_clk_src",
820 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
822 .ops = &clk_rcg2_ops,
826 static struct clk_rcg2 camss_gp1_clk_src = {
830 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
831 .freq_tbl = ftbl_camss_gp0_clk_src,
832 .clkr.hw.init = &(struct clk_init_data){
833 .name = "camss_gp1_clk_src",
834 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
836 .ops = &clk_rcg2_ops,
840 static const struct freq_tbl ftbl_mclk0_clk_src[] = {
841 F(4800000, P_XO, 4, 0, 0),
842 F(6000000, P_GPLL0_DIV, 10, 1, 5),
843 F(8000000, P_GPLL0_DIV, 1, 2, 75),
844 F(9600000, P_XO, 2, 0, 0),
845 F(16666667, P_GPLL0_DIV, 2, 1, 9),
846 F(19200000, P_XO, 1, 0, 0),
847 F(24000000, P_GPLL0_DIV, 1, 2, 25),
848 F(33333333, P_GPLL0_DIV, 1, 1, 9),
849 F(48000000, P_GPLL0, 1, 2, 25),
850 F(66666667, P_GPLL0, 1, 1, 9),
854 static struct clk_rcg2 mclk0_clk_src = {
858 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
859 .freq_tbl = ftbl_mclk0_clk_src,
860 .clkr.hw.init = &(struct clk_init_data){
861 .name = "mclk0_clk_src",
862 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
864 .ops = &clk_rcg2_ops,
868 static struct clk_rcg2 mclk1_clk_src = {
872 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
873 .freq_tbl = ftbl_mclk0_clk_src,
874 .clkr.hw.init = &(struct clk_init_data){
875 .name = "mclk1_clk_src",
876 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
878 .ops = &clk_rcg2_ops,
882 static struct clk_rcg2 mclk2_clk_src = {
886 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
887 .freq_tbl = ftbl_mclk0_clk_src,
888 .clkr.hw.init = &(struct clk_init_data){
889 .name = "mclk2_clk_src",
890 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
892 .ops = &clk_rcg2_ops,
896 static struct clk_rcg2 mclk3_clk_src = {
900 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
901 .freq_tbl = ftbl_mclk0_clk_src,
902 .clkr.hw.init = &(struct clk_init_data){
903 .name = "mclk3_clk_src",
904 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
906 .ops = &clk_rcg2_ops,
910 static const struct freq_tbl ftbl_cci_clk_src[] = {
911 F(19200000, P_XO, 1, 0, 0),
912 F(37500000, P_GPLL0, 16, 0, 0),
913 F(50000000, P_GPLL0, 12, 0, 0),
914 F(100000000, P_GPLL0, 6, 0, 0),
918 static struct clk_rcg2 cci_clk_src = {
922 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
923 .freq_tbl = ftbl_cci_clk_src,
924 .clkr.hw.init = &(struct clk_init_data){
925 .name = "cci_clk_src",
926 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
928 .ops = &clk_rcg2_ops,
932 static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
933 F(100000000, P_GPLL0_DIV, 3, 0, 0),
934 F(200000000, P_GPLL0, 3, 0, 0),
935 F(266666667, P_MMPLL0, 3, 0, 0),
939 static struct clk_rcg2 csi0phytimer_clk_src = {
942 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
943 .freq_tbl = ftbl_csi0phytimer_clk_src,
944 .clkr.hw.init = &(struct clk_init_data){
945 .name = "csi0phytimer_clk_src",
946 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
948 .ops = &clk_rcg2_ops,
952 static struct clk_rcg2 csi1phytimer_clk_src = {
955 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
956 .freq_tbl = ftbl_csi0phytimer_clk_src,
957 .clkr.hw.init = &(struct clk_init_data){
958 .name = "csi1phytimer_clk_src",
959 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
961 .ops = &clk_rcg2_ops,
965 static struct clk_rcg2 csi2phytimer_clk_src = {
968 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
969 .freq_tbl = ftbl_csi0phytimer_clk_src,
970 .clkr.hw.init = &(struct clk_init_data){
971 .name = "csi2phytimer_clk_src",
972 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
974 .ops = &clk_rcg2_ops,
978 static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = {
979 F(100000000, P_GPLL0_DIV, 3, 0, 0),
980 F(200000000, P_GPLL0, 3, 0, 0),
981 F(320000000, P_MMPLL4, 3, 0, 0),
982 F(384000000, P_MMPLL4, 2.5, 0, 0),
986 static struct clk_rcg2 csiphy0_3p_clk_src = {
989 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
990 .freq_tbl = ftbl_csiphy0_3p_clk_src,
991 .clkr.hw.init = &(struct clk_init_data){
992 .name = "csiphy0_3p_clk_src",
993 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
995 .ops = &clk_rcg2_ops,
999 static struct clk_rcg2 csiphy1_3p_clk_src = {
1002 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1003 .freq_tbl = ftbl_csiphy0_3p_clk_src,
1004 .clkr.hw.init = &(struct clk_init_data){
1005 .name = "csiphy1_3p_clk_src",
1006 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1008 .ops = &clk_rcg2_ops,
1012 static struct clk_rcg2 csiphy2_3p_clk_src = {
1015 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1016 .freq_tbl = ftbl_csiphy0_3p_clk_src,
1017 .clkr.hw.init = &(struct clk_init_data){
1018 .name = "csiphy2_3p_clk_src",
1019 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1021 .ops = &clk_rcg2_ops,
1025 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
1026 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1027 F(150000000, P_GPLL0, 4, 0, 0),
1028 F(228571429, P_MMPLL0, 3.5, 0, 0),
1029 F(266666667, P_MMPLL0, 3, 0, 0),
1030 F(320000000, P_MMPLL0, 2.5, 0, 0),
1031 F(480000000, P_MMPLL4, 2, 0, 0),
1035 static struct clk_rcg2 jpeg0_clk_src = {
1038 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1039 .freq_tbl = ftbl_jpeg0_clk_src,
1040 .clkr.hw.init = &(struct clk_init_data){
1041 .name = "jpeg0_clk_src",
1042 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1044 .ops = &clk_rcg2_ops,
1048 static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
1049 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1050 F(150000000, P_GPLL0, 4, 0, 0),
1051 F(228571429, P_MMPLL0, 3.5, 0, 0),
1052 F(266666667, P_MMPLL0, 3, 0, 0),
1053 F(320000000, P_MMPLL0, 2.5, 0, 0),
1057 static struct clk_rcg2 jpeg2_clk_src = {
1060 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1061 .freq_tbl = ftbl_jpeg2_clk_src,
1062 .clkr.hw.init = &(struct clk_init_data){
1063 .name = "jpeg2_clk_src",
1064 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1066 .ops = &clk_rcg2_ops,
1070 static struct clk_rcg2 jpeg_dma_clk_src = {
1073 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1074 .freq_tbl = ftbl_jpeg0_clk_src,
1075 .clkr.hw.init = &(struct clk_init_data){
1076 .name = "jpeg_dma_clk_src",
1077 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1079 .ops = &clk_rcg2_ops,
1083 static const struct freq_tbl ftbl_vfe0_clk_src[] = {
1084 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1085 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1086 F(300000000, P_GPLL0, 2, 0, 0),
1087 F(320000000, P_MMPLL0, 2.5, 0, 0),
1088 F(480000000, P_MMPLL4, 2, 0, 0),
1089 F(600000000, P_GPLL0, 1, 0, 0),
1093 static struct clk_rcg2 vfe0_clk_src = {
1096 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1097 .freq_tbl = ftbl_vfe0_clk_src,
1098 .clkr.hw.init = &(struct clk_init_data){
1099 .name = "vfe0_clk_src",
1100 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1102 .ops = &clk_rcg2_ops,
1106 static struct clk_rcg2 vfe1_clk_src = {
1109 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1110 .freq_tbl = ftbl_vfe0_clk_src,
1111 .clkr.hw.init = &(struct clk_init_data){
1112 .name = "vfe1_clk_src",
1113 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1115 .ops = &clk_rcg2_ops,
1119 static const struct freq_tbl ftbl_cpp_clk_src[] = {
1120 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1121 F(200000000, P_GPLL0, 3, 0, 0),
1122 F(320000000, P_MMPLL0, 2.5, 0, 0),
1123 F(480000000, P_MMPLL4, 2, 0, 0),
1124 F(640000000, P_MMPLL4, 1.5, 0, 0),
1128 static struct clk_rcg2 cpp_clk_src = {
1131 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1132 .freq_tbl = ftbl_cpp_clk_src,
1133 .clkr.hw.init = &(struct clk_init_data){
1134 .name = "cpp_clk_src",
1135 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1137 .ops = &clk_rcg2_ops,
1141 static const struct freq_tbl ftbl_csi0_clk_src[] = {
1142 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1143 F(200000000, P_GPLL0, 3, 0, 0),
1144 F(266666667, P_MMPLL0, 3, 0, 0),
1145 F(480000000, P_MMPLL4, 2, 0, 0),
1146 F(600000000, P_GPLL0, 1, 0, 0),
1150 static struct clk_rcg2 csi0_clk_src = {
1153 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1154 .freq_tbl = ftbl_csi0_clk_src,
1155 .clkr.hw.init = &(struct clk_init_data){
1156 .name = "csi0_clk_src",
1157 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1159 .ops = &clk_rcg2_ops,
1163 static struct clk_rcg2 csi1_clk_src = {
1166 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1167 .freq_tbl = ftbl_csi0_clk_src,
1168 .clkr.hw.init = &(struct clk_init_data){
1169 .name = "csi1_clk_src",
1170 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1172 .ops = &clk_rcg2_ops,
1176 static struct clk_rcg2 csi2_clk_src = {
1179 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1180 .freq_tbl = ftbl_csi0_clk_src,
1181 .clkr.hw.init = &(struct clk_init_data){
1182 .name = "csi2_clk_src",
1183 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1185 .ops = &clk_rcg2_ops,
1189 static struct clk_rcg2 csi3_clk_src = {
1192 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1193 .freq_tbl = ftbl_csi0_clk_src,
1194 .clkr.hw.init = &(struct clk_init_data){
1195 .name = "csi3_clk_src",
1196 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1198 .ops = &clk_rcg2_ops,
1202 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
1203 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1204 F(200000000, P_GPLL0, 3, 0, 0),
1205 F(400000000, P_MMPLL0, 2, 0, 0),
1209 static struct clk_rcg2 fd_core_clk_src = {
1212 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
1213 .freq_tbl = ftbl_fd_core_clk_src,
1214 .clkr.hw.init = &(struct clk_init_data){
1215 .name = "fd_core_clk_src",
1216 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
1218 .ops = &clk_rcg2_ops,
1222 static struct clk_branch mmss_mmagic_ahb_clk = {
1225 .enable_reg = 0x5024,
1226 .enable_mask = BIT(0),
1227 .hw.init = &(struct clk_init_data){
1228 .name = "mmss_mmagic_ahb_clk",
1229 .parent_names = (const char *[]){ "ahb_clk_src" },
1231 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1232 .ops = &clk_branch2_ops,
1237 static struct clk_branch mmss_mmagic_cfg_ahb_clk = {
1240 .enable_reg = 0x5054,
1241 .enable_mask = BIT(0),
1242 .hw.init = &(struct clk_init_data){
1243 .name = "mmss_mmagic_cfg_ahb_clk",
1244 .parent_names = (const char *[]){ "ahb_clk_src" },
1246 .flags = CLK_SET_RATE_PARENT,
1247 .ops = &clk_branch2_ops,
1252 static struct clk_branch mmss_misc_ahb_clk = {
1255 .enable_reg = 0x5018,
1256 .enable_mask = BIT(0),
1257 .hw.init = &(struct clk_init_data){
1258 .name = "mmss_misc_ahb_clk",
1259 .parent_names = (const char *[]){ "ahb_clk_src" },
1261 .flags = CLK_SET_RATE_PARENT,
1262 .ops = &clk_branch2_ops,
1267 static struct clk_branch mmss_misc_cxo_clk = {
1270 .enable_reg = 0x5014,
1271 .enable_mask = BIT(0),
1272 .hw.init = &(struct clk_init_data){
1273 .name = "mmss_misc_cxo_clk",
1274 .parent_names = (const char *[]){ "xo" },
1276 .ops = &clk_branch2_ops,
1281 static struct clk_branch mmss_mmagic_axi_clk = {
1284 .enable_reg = 0x506c,
1285 .enable_mask = BIT(0),
1286 .hw.init = &(struct clk_init_data){
1287 .name = "mmss_mmagic_axi_clk",
1288 .parent_names = (const char *[]){ "axi_clk_src" },
1290 .flags = CLK_SET_RATE_PARENT,
1291 .ops = &clk_branch2_ops,
1296 static struct clk_branch mmss_mmagic_maxi_clk = {
1299 .enable_reg = 0x5074,
1300 .enable_mask = BIT(0),
1301 .hw.init = &(struct clk_init_data){
1302 .name = "mmss_mmagic_maxi_clk",
1303 .parent_names = (const char *[]){ "maxi_clk_src" },
1305 .flags = CLK_SET_RATE_PARENT,
1306 .ops = &clk_branch2_ops,
1311 static struct clk_branch mmagic_camss_axi_clk = {
1314 .enable_reg = 0x3c44,
1315 .enable_mask = BIT(0),
1316 .hw.init = &(struct clk_init_data){
1317 .name = "mmagic_camss_axi_clk",
1318 .parent_names = (const char *[]){ "axi_clk_src" },
1320 .flags = CLK_SET_RATE_PARENT,
1321 .ops = &clk_branch2_ops,
1326 static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = {
1329 .enable_reg = 0x3c48,
1330 .enable_mask = BIT(0),
1331 .hw.init = &(struct clk_init_data){
1332 .name = "mmagic_camss_noc_cfg_ahb_clk",
1333 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1335 .flags = CLK_SET_RATE_PARENT,
1336 .ops = &clk_branch2_ops,
1341 static struct clk_branch smmu_vfe_ahb_clk = {
1344 .enable_reg = 0x3c04,
1345 .enable_mask = BIT(0),
1346 .hw.init = &(struct clk_init_data){
1347 .name = "smmu_vfe_ahb_clk",
1348 .parent_names = (const char *[]){ "ahb_clk_src" },
1350 .flags = CLK_SET_RATE_PARENT,
1351 .ops = &clk_branch2_ops,
1356 static struct clk_branch smmu_vfe_axi_clk = {
1359 .enable_reg = 0x3c08,
1360 .enable_mask = BIT(0),
1361 .hw.init = &(struct clk_init_data){
1362 .name = "smmu_vfe_axi_clk",
1363 .parent_names = (const char *[]){ "axi_clk_src" },
1365 .flags = CLK_SET_RATE_PARENT,
1366 .ops = &clk_branch2_ops,
1371 static struct clk_branch smmu_cpp_ahb_clk = {
1374 .enable_reg = 0x3c14,
1375 .enable_mask = BIT(0),
1376 .hw.init = &(struct clk_init_data){
1377 .name = "smmu_cpp_ahb_clk",
1378 .parent_names = (const char *[]){ "ahb_clk_src" },
1380 .flags = CLK_SET_RATE_PARENT,
1381 .ops = &clk_branch2_ops,
1386 static struct clk_branch smmu_cpp_axi_clk = {
1389 .enable_reg = 0x3c18,
1390 .enable_mask = BIT(0),
1391 .hw.init = &(struct clk_init_data){
1392 .name = "smmu_cpp_axi_clk",
1393 .parent_names = (const char *[]){ "axi_clk_src" },
1395 .flags = CLK_SET_RATE_PARENT,
1396 .ops = &clk_branch2_ops,
1401 static struct clk_branch smmu_jpeg_ahb_clk = {
1404 .enable_reg = 0x3c24,
1405 .enable_mask = BIT(0),
1406 .hw.init = &(struct clk_init_data){
1407 .name = "smmu_jpeg_ahb_clk",
1408 .parent_names = (const char *[]){ "ahb_clk_src" },
1410 .flags = CLK_SET_RATE_PARENT,
1411 .ops = &clk_branch2_ops,
1416 static struct clk_branch smmu_jpeg_axi_clk = {
1419 .enable_reg = 0x3c28,
1420 .enable_mask = BIT(0),
1421 .hw.init = &(struct clk_init_data){
1422 .name = "smmu_jpeg_axi_clk",
1423 .parent_names = (const char *[]){ "axi_clk_src" },
1425 .flags = CLK_SET_RATE_PARENT,
1426 .ops = &clk_branch2_ops,
1431 static struct clk_branch mmagic_mdss_axi_clk = {
1434 .enable_reg = 0x2474,
1435 .enable_mask = BIT(0),
1436 .hw.init = &(struct clk_init_data){
1437 .name = "mmagic_mdss_axi_clk",
1438 .parent_names = (const char *[]){ "axi_clk_src" },
1440 .flags = CLK_SET_RATE_PARENT,
1441 .ops = &clk_branch2_ops,
1446 static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = {
1449 .enable_reg = 0x2478,
1450 .enable_mask = BIT(0),
1451 .hw.init = &(struct clk_init_data){
1452 .name = "mmagic_mdss_noc_cfg_ahb_clk",
1453 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1455 .flags = CLK_SET_RATE_PARENT,
1456 .ops = &clk_branch2_ops,
1461 static struct clk_branch smmu_rot_ahb_clk = {
1464 .enable_reg = 0x2444,
1465 .enable_mask = BIT(0),
1466 .hw.init = &(struct clk_init_data){
1467 .name = "smmu_rot_ahb_clk",
1468 .parent_names = (const char *[]){ "ahb_clk_src" },
1470 .flags = CLK_SET_RATE_PARENT,
1471 .ops = &clk_branch2_ops,
1476 static struct clk_branch smmu_rot_axi_clk = {
1479 .enable_reg = 0x2448,
1480 .enable_mask = BIT(0),
1481 .hw.init = &(struct clk_init_data){
1482 .name = "smmu_rot_axi_clk",
1483 .parent_names = (const char *[]){ "axi_clk_src" },
1485 .flags = CLK_SET_RATE_PARENT,
1486 .ops = &clk_branch2_ops,
1491 static struct clk_branch smmu_mdp_ahb_clk = {
1494 .enable_reg = 0x2454,
1495 .enable_mask = BIT(0),
1496 .hw.init = &(struct clk_init_data){
1497 .name = "smmu_mdp_ahb_clk",
1498 .parent_names = (const char *[]){ "ahb_clk_src" },
1500 .flags = CLK_SET_RATE_PARENT,
1501 .ops = &clk_branch2_ops,
1506 static struct clk_branch smmu_mdp_axi_clk = {
1509 .enable_reg = 0x2458,
1510 .enable_mask = BIT(0),
1511 .hw.init = &(struct clk_init_data){
1512 .name = "smmu_mdp_axi_clk",
1513 .parent_names = (const char *[]){ "axi_clk_src" },
1515 .flags = CLK_SET_RATE_PARENT,
1516 .ops = &clk_branch2_ops,
1521 static struct clk_branch mmagic_video_axi_clk = {
1524 .enable_reg = 0x1194,
1525 .enable_mask = BIT(0),
1526 .hw.init = &(struct clk_init_data){
1527 .name = "mmagic_video_axi_clk",
1528 .parent_names = (const char *[]){ "axi_clk_src" },
1530 .flags = CLK_SET_RATE_PARENT,
1531 .ops = &clk_branch2_ops,
1536 static struct clk_branch mmagic_video_noc_cfg_ahb_clk = {
1539 .enable_reg = 0x1198,
1540 .enable_mask = BIT(0),
1541 .hw.init = &(struct clk_init_data){
1542 .name = "mmagic_video_noc_cfg_ahb_clk",
1543 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1545 .flags = CLK_SET_RATE_PARENT,
1546 .ops = &clk_branch2_ops,
1551 static struct clk_branch smmu_video_ahb_clk = {
1554 .enable_reg = 0x1174,
1555 .enable_mask = BIT(0),
1556 .hw.init = &(struct clk_init_data){
1557 .name = "smmu_video_ahb_clk",
1558 .parent_names = (const char *[]){ "ahb_clk_src" },
1560 .flags = CLK_SET_RATE_PARENT,
1561 .ops = &clk_branch2_ops,
1566 static struct clk_branch smmu_video_axi_clk = {
1569 .enable_reg = 0x1178,
1570 .enable_mask = BIT(0),
1571 .hw.init = &(struct clk_init_data){
1572 .name = "smmu_video_axi_clk",
1573 .parent_names = (const char *[]){ "axi_clk_src" },
1575 .flags = CLK_SET_RATE_PARENT,
1576 .ops = &clk_branch2_ops,
1581 static struct clk_branch mmagic_bimc_axi_clk = {
1584 .enable_reg = 0x5294,
1585 .enable_mask = BIT(0),
1586 .hw.init = &(struct clk_init_data){
1587 .name = "mmagic_bimc_axi_clk",
1588 .parent_names = (const char *[]){ "axi_clk_src" },
1590 .flags = CLK_SET_RATE_PARENT,
1591 .ops = &clk_branch2_ops,
1596 static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = {
1599 .enable_reg = 0x5298,
1600 .enable_mask = BIT(0),
1601 .hw.init = &(struct clk_init_data){
1602 .name = "mmagic_bimc_noc_cfg_ahb_clk",
1603 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1605 .flags = CLK_SET_RATE_PARENT,
1606 .ops = &clk_branch2_ops,
1611 static struct clk_branch gpu_gx_gfx3d_clk = {
1614 .enable_reg = 0x4028,
1615 .enable_mask = BIT(0),
1616 .hw.init = &(struct clk_init_data){
1617 .name = "gpu_gx_gfx3d_clk",
1618 .parent_names = (const char *[]){ "gfx3d_clk_src" },
1620 .flags = CLK_SET_RATE_PARENT,
1621 .ops = &clk_branch2_ops,
1626 static struct clk_branch gpu_gx_rbbmtimer_clk = {
1629 .enable_reg = 0x40b0,
1630 .enable_mask = BIT(0),
1631 .hw.init = &(struct clk_init_data){
1632 .name = "gpu_gx_rbbmtimer_clk",
1633 .parent_names = (const char *[]){ "rbbmtimer_clk_src" },
1635 .flags = CLK_SET_RATE_PARENT,
1636 .ops = &clk_branch2_ops,
1641 static struct clk_branch gpu_ahb_clk = {
1644 .enable_reg = 0x403c,
1645 .enable_mask = BIT(0),
1646 .hw.init = &(struct clk_init_data){
1647 .name = "gpu_ahb_clk",
1648 .parent_names = (const char *[]){ "ahb_clk_src" },
1650 .flags = CLK_SET_RATE_PARENT,
1651 .ops = &clk_branch2_ops,
1656 static struct clk_branch gpu_aon_isense_clk = {
1659 .enable_reg = 0x4044,
1660 .enable_mask = BIT(0),
1661 .hw.init = &(struct clk_init_data){
1662 .name = "gpu_aon_isense_clk",
1663 .parent_names = (const char *[]){ "isense_clk_src" },
1665 .flags = CLK_SET_RATE_PARENT,
1666 .ops = &clk_branch2_ops,
1671 static struct clk_branch vmem_maxi_clk = {
1674 .enable_reg = 0x1204,
1675 .enable_mask = BIT(0),
1676 .hw.init = &(struct clk_init_data){
1677 .name = "vmem_maxi_clk",
1678 .parent_names = (const char *[]){ "maxi_clk_src" },
1680 .flags = CLK_SET_RATE_PARENT,
1681 .ops = &clk_branch2_ops,
1686 static struct clk_branch vmem_ahb_clk = {
1689 .enable_reg = 0x1208,
1690 .enable_mask = BIT(0),
1691 .hw.init = &(struct clk_init_data){
1692 .name = "vmem_ahb_clk",
1693 .parent_names = (const char *[]){ "ahb_clk_src" },
1695 .flags = CLK_SET_RATE_PARENT,
1696 .ops = &clk_branch2_ops,
1701 static struct clk_branch mmss_rbcpr_clk = {
1704 .enable_reg = 0x4084,
1705 .enable_mask = BIT(0),
1706 .hw.init = &(struct clk_init_data){
1707 .name = "mmss_rbcpr_clk",
1708 .parent_names = (const char *[]){ "rbcpr_clk_src" },
1710 .flags = CLK_SET_RATE_PARENT,
1711 .ops = &clk_branch2_ops,
1716 static struct clk_branch mmss_rbcpr_ahb_clk = {
1719 .enable_reg = 0x4088,
1720 .enable_mask = BIT(0),
1721 .hw.init = &(struct clk_init_data){
1722 .name = "mmss_rbcpr_ahb_clk",
1723 .parent_names = (const char *[]){ "ahb_clk_src" },
1725 .flags = CLK_SET_RATE_PARENT,
1726 .ops = &clk_branch2_ops,
1731 static struct clk_branch video_core_clk = {
1734 .enable_reg = 0x1028,
1735 .enable_mask = BIT(0),
1736 .hw.init = &(struct clk_init_data){
1737 .name = "video_core_clk",
1738 .parent_names = (const char *[]){ "video_core_clk_src" },
1740 .flags = CLK_SET_RATE_PARENT,
1741 .ops = &clk_branch2_ops,
1746 static struct clk_branch video_axi_clk = {
1749 .enable_reg = 0x1034,
1750 .enable_mask = BIT(0),
1751 .hw.init = &(struct clk_init_data){
1752 .name = "video_axi_clk",
1753 .parent_names = (const char *[]){ "axi_clk_src" },
1755 .flags = CLK_SET_RATE_PARENT,
1756 .ops = &clk_branch2_ops,
1761 static struct clk_branch video_maxi_clk = {
1764 .enable_reg = 0x1038,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "video_maxi_clk",
1768 .parent_names = (const char *[]){ "maxi_clk_src" },
1770 .flags = CLK_SET_RATE_PARENT,
1771 .ops = &clk_branch2_ops,
1776 static struct clk_branch video_ahb_clk = {
1779 .enable_reg = 0x1030,
1780 .enable_mask = BIT(0),
1781 .hw.init = &(struct clk_init_data){
1782 .name = "video_ahb_clk",
1783 .parent_names = (const char *[]){ "ahb_clk_src" },
1785 .flags = CLK_SET_RATE_PARENT,
1786 .ops = &clk_branch2_ops,
1791 static struct clk_branch video_subcore0_clk = {
1794 .enable_reg = 0x1048,
1795 .enable_mask = BIT(0),
1796 .hw.init = &(struct clk_init_data){
1797 .name = "video_subcore0_clk",
1798 .parent_names = (const char *[]){ "video_subcore0_clk_src" },
1800 .flags = CLK_SET_RATE_PARENT,
1801 .ops = &clk_branch2_ops,
1806 static struct clk_branch video_subcore1_clk = {
1809 .enable_reg = 0x104c,
1810 .enable_mask = BIT(0),
1811 .hw.init = &(struct clk_init_data){
1812 .name = "video_subcore1_clk",
1813 .parent_names = (const char *[]){ "video_subcore1_clk_src" },
1815 .flags = CLK_SET_RATE_PARENT,
1816 .ops = &clk_branch2_ops,
1821 static struct clk_branch mdss_ahb_clk = {
1824 .enable_reg = 0x2308,
1825 .enable_mask = BIT(0),
1826 .hw.init = &(struct clk_init_data){
1827 .name = "mdss_ahb_clk",
1828 .parent_names = (const char *[]){ "ahb_clk_src" },
1830 .flags = CLK_SET_RATE_PARENT,
1831 .ops = &clk_branch2_ops,
1836 static struct clk_branch mdss_hdmi_ahb_clk = {
1839 .enable_reg = 0x230c,
1840 .enable_mask = BIT(0),
1841 .hw.init = &(struct clk_init_data){
1842 .name = "mdss_hdmi_ahb_clk",
1843 .parent_names = (const char *[]){ "ahb_clk_src" },
1845 .flags = CLK_SET_RATE_PARENT,
1846 .ops = &clk_branch2_ops,
1851 static struct clk_branch mdss_axi_clk = {
1854 .enable_reg = 0x2310,
1855 .enable_mask = BIT(0),
1856 .hw.init = &(struct clk_init_data){
1857 .name = "mdss_axi_clk",
1858 .parent_names = (const char *[]){ "axi_clk_src" },
1860 .flags = CLK_SET_RATE_PARENT,
1861 .ops = &clk_branch2_ops,
1866 static struct clk_branch mdss_pclk0_clk = {
1869 .enable_reg = 0x2314,
1870 .enable_mask = BIT(0),
1871 .hw.init = &(struct clk_init_data){
1872 .name = "mdss_pclk0_clk",
1873 .parent_names = (const char *[]){ "pclk0_clk_src" },
1875 .flags = CLK_SET_RATE_PARENT,
1876 .ops = &clk_branch2_ops,
1881 static struct clk_branch mdss_pclk1_clk = {
1884 .enable_reg = 0x2318,
1885 .enable_mask = BIT(0),
1886 .hw.init = &(struct clk_init_data){
1887 .name = "mdss_pclk1_clk",
1888 .parent_names = (const char *[]){ "pclk1_clk_src" },
1890 .flags = CLK_SET_RATE_PARENT,
1891 .ops = &clk_branch2_ops,
1896 static struct clk_branch mdss_mdp_clk = {
1899 .enable_reg = 0x231c,
1900 .enable_mask = BIT(0),
1901 .hw.init = &(struct clk_init_data){
1902 .name = "mdss_mdp_clk",
1903 .parent_names = (const char *[]){ "mdp_clk_src" },
1905 .flags = CLK_SET_RATE_PARENT,
1906 .ops = &clk_branch2_ops,
1911 static struct clk_branch mdss_extpclk_clk = {
1914 .enable_reg = 0x2324,
1915 .enable_mask = BIT(0),
1916 .hw.init = &(struct clk_init_data){
1917 .name = "mdss_extpclk_clk",
1918 .parent_names = (const char *[]){ "extpclk_clk_src" },
1920 .flags = CLK_SET_RATE_PARENT,
1921 .ops = &clk_branch2_ops,
1926 static struct clk_branch mdss_vsync_clk = {
1929 .enable_reg = 0x2328,
1930 .enable_mask = BIT(0),
1931 .hw.init = &(struct clk_init_data){
1932 .name = "mdss_vsync_clk",
1933 .parent_names = (const char *[]){ "vsync_clk_src" },
1935 .flags = CLK_SET_RATE_PARENT,
1936 .ops = &clk_branch2_ops,
1941 static struct clk_branch mdss_hdmi_clk = {
1944 .enable_reg = 0x2338,
1945 .enable_mask = BIT(0),
1946 .hw.init = &(struct clk_init_data){
1947 .name = "mdss_hdmi_clk",
1948 .parent_names = (const char *[]){ "hdmi_clk_src" },
1950 .flags = CLK_SET_RATE_PARENT,
1951 .ops = &clk_branch2_ops,
1956 static struct clk_branch mdss_byte0_clk = {
1959 .enable_reg = 0x233c,
1960 .enable_mask = BIT(0),
1961 .hw.init = &(struct clk_init_data){
1962 .name = "mdss_byte0_clk",
1963 .parent_names = (const char *[]){ "byte0_clk_src" },
1965 .flags = CLK_SET_RATE_PARENT,
1966 .ops = &clk_branch2_ops,
1971 static struct clk_branch mdss_byte1_clk = {
1974 .enable_reg = 0x2340,
1975 .enable_mask = BIT(0),
1976 .hw.init = &(struct clk_init_data){
1977 .name = "mdss_byte1_clk",
1978 .parent_names = (const char *[]){ "byte1_clk_src" },
1980 .flags = CLK_SET_RATE_PARENT,
1981 .ops = &clk_branch2_ops,
1986 static struct clk_branch mdss_esc0_clk = {
1989 .enable_reg = 0x2344,
1990 .enable_mask = BIT(0),
1991 .hw.init = &(struct clk_init_data){
1992 .name = "mdss_esc0_clk",
1993 .parent_names = (const char *[]){ "esc0_clk_src" },
1995 .flags = CLK_SET_RATE_PARENT,
1996 .ops = &clk_branch2_ops,
2001 static struct clk_branch mdss_esc1_clk = {
2004 .enable_reg = 0x2348,
2005 .enable_mask = BIT(0),
2006 .hw.init = &(struct clk_init_data){
2007 .name = "mdss_esc1_clk",
2008 .parent_names = (const char *[]){ "esc1_clk_src" },
2010 .flags = CLK_SET_RATE_PARENT,
2011 .ops = &clk_branch2_ops,
2016 static struct clk_branch camss_top_ahb_clk = {
2019 .enable_reg = 0x3484,
2020 .enable_mask = BIT(0),
2021 .hw.init = &(struct clk_init_data){
2022 .name = "camss_top_ahb_clk",
2023 .parent_names = (const char *[]){ "ahb_clk_src" },
2025 .flags = CLK_SET_RATE_PARENT,
2026 .ops = &clk_branch2_ops,
2031 static struct clk_branch camss_ahb_clk = {
2034 .enable_reg = 0x348c,
2035 .enable_mask = BIT(0),
2036 .hw.init = &(struct clk_init_data){
2037 .name = "camss_ahb_clk",
2038 .parent_names = (const char *[]){ "ahb_clk_src" },
2040 .flags = CLK_SET_RATE_PARENT,
2041 .ops = &clk_branch2_ops,
2046 static struct clk_branch camss_micro_ahb_clk = {
2049 .enable_reg = 0x3494,
2050 .enable_mask = BIT(0),
2051 .hw.init = &(struct clk_init_data){
2052 .name = "camss_micro_ahb_clk",
2053 .parent_names = (const char *[]){ "ahb_clk_src" },
2055 .flags = CLK_SET_RATE_PARENT,
2056 .ops = &clk_branch2_ops,
2061 static struct clk_branch camss_gp0_clk = {
2064 .enable_reg = 0x3444,
2065 .enable_mask = BIT(0),
2066 .hw.init = &(struct clk_init_data){
2067 .name = "camss_gp0_clk",
2068 .parent_names = (const char *[]){ "camss_gp0_clk_src" },
2070 .flags = CLK_SET_RATE_PARENT,
2071 .ops = &clk_branch2_ops,
2076 static struct clk_branch camss_gp1_clk = {
2079 .enable_reg = 0x3474,
2080 .enable_mask = BIT(0),
2081 .hw.init = &(struct clk_init_data){
2082 .name = "camss_gp1_clk",
2083 .parent_names = (const char *[]){ "camss_gp1_clk_src" },
2085 .flags = CLK_SET_RATE_PARENT,
2086 .ops = &clk_branch2_ops,
2091 static struct clk_branch camss_mclk0_clk = {
2094 .enable_reg = 0x3384,
2095 .enable_mask = BIT(0),
2096 .hw.init = &(struct clk_init_data){
2097 .name = "camss_mclk0_clk",
2098 .parent_names = (const char *[]){ "mclk0_clk_src" },
2100 .flags = CLK_SET_RATE_PARENT,
2101 .ops = &clk_branch2_ops,
2106 static struct clk_branch camss_mclk1_clk = {
2109 .enable_reg = 0x33b4,
2110 .enable_mask = BIT(0),
2111 .hw.init = &(struct clk_init_data){
2112 .name = "camss_mclk1_clk",
2113 .parent_names = (const char *[]){ "mclk1_clk_src" },
2115 .flags = CLK_SET_RATE_PARENT,
2116 .ops = &clk_branch2_ops,
2121 static struct clk_branch camss_mclk2_clk = {
2124 .enable_reg = 0x33e4,
2125 .enable_mask = BIT(0),
2126 .hw.init = &(struct clk_init_data){
2127 .name = "camss_mclk2_clk",
2128 .parent_names = (const char *[]){ "mclk2_clk_src" },
2130 .flags = CLK_SET_RATE_PARENT,
2131 .ops = &clk_branch2_ops,
2136 static struct clk_branch camss_mclk3_clk = {
2139 .enable_reg = 0x3414,
2140 .enable_mask = BIT(0),
2141 .hw.init = &(struct clk_init_data){
2142 .name = "camss_mclk3_clk",
2143 .parent_names = (const char *[]){ "mclk3_clk_src" },
2145 .flags = CLK_SET_RATE_PARENT,
2146 .ops = &clk_branch2_ops,
2151 static struct clk_branch camss_cci_clk = {
2154 .enable_reg = 0x3344,
2155 .enable_mask = BIT(0),
2156 .hw.init = &(struct clk_init_data){
2157 .name = "camss_cci_clk",
2158 .parent_names = (const char *[]){ "cci_clk_src" },
2160 .flags = CLK_SET_RATE_PARENT,
2161 .ops = &clk_branch2_ops,
2166 static struct clk_branch camss_cci_ahb_clk = {
2169 .enable_reg = 0x3348,
2170 .enable_mask = BIT(0),
2171 .hw.init = &(struct clk_init_data){
2172 .name = "camss_cci_ahb_clk",
2173 .parent_names = (const char *[]){ "ahb_clk_src" },
2175 .flags = CLK_SET_RATE_PARENT,
2176 .ops = &clk_branch2_ops,
2181 static struct clk_branch camss_csi0phytimer_clk = {
2184 .enable_reg = 0x3024,
2185 .enable_mask = BIT(0),
2186 .hw.init = &(struct clk_init_data){
2187 .name = "camss_csi0phytimer_clk",
2188 .parent_names = (const char *[]){ "csi0phytimer_clk_src" },
2190 .flags = CLK_SET_RATE_PARENT,
2191 .ops = &clk_branch2_ops,
2196 static struct clk_branch camss_csi1phytimer_clk = {
2199 .enable_reg = 0x3054,
2200 .enable_mask = BIT(0),
2201 .hw.init = &(struct clk_init_data){
2202 .name = "camss_csi1phytimer_clk",
2203 .parent_names = (const char *[]){ "csi1phytimer_clk_src" },
2205 .flags = CLK_SET_RATE_PARENT,
2206 .ops = &clk_branch2_ops,
2211 static struct clk_branch camss_csi2phytimer_clk = {
2214 .enable_reg = 0x3084,
2215 .enable_mask = BIT(0),
2216 .hw.init = &(struct clk_init_data){
2217 .name = "camss_csi2phytimer_clk",
2218 .parent_names = (const char *[]){ "csi2phytimer_clk_src" },
2220 .flags = CLK_SET_RATE_PARENT,
2221 .ops = &clk_branch2_ops,
2226 static struct clk_branch camss_csiphy0_3p_clk = {
2229 .enable_reg = 0x3234,
2230 .enable_mask = BIT(0),
2231 .hw.init = &(struct clk_init_data){
2232 .name = "camss_csiphy0_3p_clk",
2233 .parent_names = (const char *[]){ "csiphy0_3p_clk_src" },
2235 .flags = CLK_SET_RATE_PARENT,
2236 .ops = &clk_branch2_ops,
2241 static struct clk_branch camss_csiphy1_3p_clk = {
2244 .enable_reg = 0x3254,
2245 .enable_mask = BIT(0),
2246 .hw.init = &(struct clk_init_data){
2247 .name = "camss_csiphy1_3p_clk",
2248 .parent_names = (const char *[]){ "csiphy1_3p_clk_src" },
2250 .flags = CLK_SET_RATE_PARENT,
2251 .ops = &clk_branch2_ops,
2256 static struct clk_branch camss_csiphy2_3p_clk = {
2259 .enable_reg = 0x3274,
2260 .enable_mask = BIT(0),
2261 .hw.init = &(struct clk_init_data){
2262 .name = "camss_csiphy2_3p_clk",
2263 .parent_names = (const char *[]){ "csiphy2_3p_clk_src" },
2265 .flags = CLK_SET_RATE_PARENT,
2266 .ops = &clk_branch2_ops,
2271 static struct clk_branch camss_jpeg0_clk = {
2274 .enable_reg = 0x35a8,
2275 .enable_mask = BIT(0),
2276 .hw.init = &(struct clk_init_data){
2277 .name = "camss_jpeg0_clk",
2278 .parent_names = (const char *[]){ "jpeg0_clk_src" },
2280 .flags = CLK_SET_RATE_PARENT,
2281 .ops = &clk_branch2_ops,
2286 static struct clk_branch camss_jpeg2_clk = {
2289 .enable_reg = 0x35b0,
2290 .enable_mask = BIT(0),
2291 .hw.init = &(struct clk_init_data){
2292 .name = "camss_jpeg2_clk",
2293 .parent_names = (const char *[]){ "jpeg2_clk_src" },
2295 .flags = CLK_SET_RATE_PARENT,
2296 .ops = &clk_branch2_ops,
2301 static struct clk_branch camss_jpeg_dma_clk = {
2304 .enable_reg = 0x35c0,
2305 .enable_mask = BIT(0),
2306 .hw.init = &(struct clk_init_data){
2307 .name = "camss_jpeg_dma_clk",
2308 .parent_names = (const char *[]){ "jpeg_dma_clk_src" },
2310 .flags = CLK_SET_RATE_PARENT,
2311 .ops = &clk_branch2_ops,
2316 static struct clk_branch camss_jpeg_ahb_clk = {
2319 .enable_reg = 0x35b4,
2320 .enable_mask = BIT(0),
2321 .hw.init = &(struct clk_init_data){
2322 .name = "camss_jpeg_ahb_clk",
2323 .parent_names = (const char *[]){ "ahb_clk_src" },
2325 .flags = CLK_SET_RATE_PARENT,
2326 .ops = &clk_branch2_ops,
2331 static struct clk_branch camss_jpeg_axi_clk = {
2334 .enable_reg = 0x35b8,
2335 .enable_mask = BIT(0),
2336 .hw.init = &(struct clk_init_data){
2337 .name = "camss_jpeg_axi_clk",
2338 .parent_names = (const char *[]){ "axi_clk_src" },
2340 .flags = CLK_SET_RATE_PARENT,
2341 .ops = &clk_branch2_ops,
2346 static struct clk_branch camss_vfe_ahb_clk = {
2349 .enable_reg = 0x36b8,
2350 .enable_mask = BIT(0),
2351 .hw.init = &(struct clk_init_data){
2352 .name = "camss_vfe_ahb_clk",
2353 .parent_names = (const char *[]){ "ahb_clk_src" },
2355 .flags = CLK_SET_RATE_PARENT,
2356 .ops = &clk_branch2_ops,
2361 static struct clk_branch camss_vfe_axi_clk = {
2364 .enable_reg = 0x36bc,
2365 .enable_mask = BIT(0),
2366 .hw.init = &(struct clk_init_data){
2367 .name = "camss_vfe_axi_clk",
2368 .parent_names = (const char *[]){ "axi_clk_src" },
2370 .flags = CLK_SET_RATE_PARENT,
2371 .ops = &clk_branch2_ops,
2376 static struct clk_branch camss_vfe0_clk = {
2379 .enable_reg = 0x36a8,
2380 .enable_mask = BIT(0),
2381 .hw.init = &(struct clk_init_data){
2382 .name = "camss_vfe0_clk",
2383 .parent_names = (const char *[]){ "vfe0_clk_src" },
2385 .flags = CLK_SET_RATE_PARENT,
2386 .ops = &clk_branch2_ops,
2391 static struct clk_branch camss_vfe0_stream_clk = {
2394 .enable_reg = 0x3720,
2395 .enable_mask = BIT(0),
2396 .hw.init = &(struct clk_init_data){
2397 .name = "camss_vfe0_stream_clk",
2398 .parent_names = (const char *[]){ "vfe0_clk_src" },
2400 .flags = CLK_SET_RATE_PARENT,
2401 .ops = &clk_branch2_ops,
2406 static struct clk_branch camss_vfe0_ahb_clk = {
2409 .enable_reg = 0x3668,
2410 .enable_mask = BIT(0),
2411 .hw.init = &(struct clk_init_data){
2412 .name = "camss_vfe0_ahb_clk",
2413 .parent_names = (const char *[]){ "ahb_clk_src" },
2415 .flags = CLK_SET_RATE_PARENT,
2416 .ops = &clk_branch2_ops,
2421 static struct clk_branch camss_vfe1_clk = {
2424 .enable_reg = 0x36ac,
2425 .enable_mask = BIT(0),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "camss_vfe1_clk",
2428 .parent_names = (const char *[]){ "vfe1_clk_src" },
2430 .flags = CLK_SET_RATE_PARENT,
2431 .ops = &clk_branch2_ops,
2436 static struct clk_branch camss_vfe1_stream_clk = {
2439 .enable_reg = 0x3724,
2440 .enable_mask = BIT(0),
2441 .hw.init = &(struct clk_init_data){
2442 .name = "camss_vfe1_stream_clk",
2443 .parent_names = (const char *[]){ "vfe1_clk_src" },
2445 .flags = CLK_SET_RATE_PARENT,
2446 .ops = &clk_branch2_ops,
2451 static struct clk_branch camss_vfe1_ahb_clk = {
2454 .enable_reg = 0x3678,
2455 .enable_mask = BIT(0),
2456 .hw.init = &(struct clk_init_data){
2457 .name = "camss_vfe1_ahb_clk",
2458 .parent_names = (const char *[]){ "ahb_clk_src" },
2460 .flags = CLK_SET_RATE_PARENT,
2461 .ops = &clk_branch2_ops,
2466 static struct clk_branch camss_csi_vfe0_clk = {
2469 .enable_reg = 0x3704,
2470 .enable_mask = BIT(0),
2471 .hw.init = &(struct clk_init_data){
2472 .name = "camss_csi_vfe0_clk",
2473 .parent_names = (const char *[]){ "vfe0_clk_src" },
2475 .flags = CLK_SET_RATE_PARENT,
2476 .ops = &clk_branch2_ops,
2481 static struct clk_branch camss_csi_vfe1_clk = {
2484 .enable_reg = 0x3714,
2485 .enable_mask = BIT(0),
2486 .hw.init = &(struct clk_init_data){
2487 .name = "camss_csi_vfe1_clk",
2488 .parent_names = (const char *[]){ "vfe1_clk_src" },
2490 .flags = CLK_SET_RATE_PARENT,
2491 .ops = &clk_branch2_ops,
2496 static struct clk_branch camss_cpp_vbif_ahb_clk = {
2499 .enable_reg = 0x36c8,
2500 .enable_mask = BIT(0),
2501 .hw.init = &(struct clk_init_data){
2502 .name = "camss_cpp_vbif_ahb_clk",
2503 .parent_names = (const char *[]){ "ahb_clk_src" },
2505 .flags = CLK_SET_RATE_PARENT,
2506 .ops = &clk_branch2_ops,
2511 static struct clk_branch camss_cpp_axi_clk = {
2514 .enable_reg = 0x36c4,
2515 .enable_mask = BIT(0),
2516 .hw.init = &(struct clk_init_data){
2517 .name = "camss_cpp_axi_clk",
2518 .parent_names = (const char *[]){ "axi_clk_src" },
2520 .flags = CLK_SET_RATE_PARENT,
2521 .ops = &clk_branch2_ops,
2526 static struct clk_branch camss_cpp_clk = {
2529 .enable_reg = 0x36b0,
2530 .enable_mask = BIT(0),
2531 .hw.init = &(struct clk_init_data){
2532 .name = "camss_cpp_clk",
2533 .parent_names = (const char *[]){ "cpp_clk_src" },
2535 .flags = CLK_SET_RATE_PARENT,
2536 .ops = &clk_branch2_ops,
2541 static struct clk_branch camss_cpp_ahb_clk = {
2544 .enable_reg = 0x36b4,
2545 .enable_mask = BIT(0),
2546 .hw.init = &(struct clk_init_data){
2547 .name = "camss_cpp_ahb_clk",
2548 .parent_names = (const char *[]){ "ahb_clk_src" },
2550 .flags = CLK_SET_RATE_PARENT,
2551 .ops = &clk_branch2_ops,
2556 static struct clk_branch camss_csi0_clk = {
2559 .enable_reg = 0x30b4,
2560 .enable_mask = BIT(0),
2561 .hw.init = &(struct clk_init_data){
2562 .name = "camss_csi0_clk",
2563 .parent_names = (const char *[]){ "csi0_clk_src" },
2565 .flags = CLK_SET_RATE_PARENT,
2566 .ops = &clk_branch2_ops,
2571 static struct clk_branch camss_csi0_ahb_clk = {
2574 .enable_reg = 0x30bc,
2575 .enable_mask = BIT(0),
2576 .hw.init = &(struct clk_init_data){
2577 .name = "camss_csi0_ahb_clk",
2578 .parent_names = (const char *[]){ "ahb_clk_src" },
2580 .flags = CLK_SET_RATE_PARENT,
2581 .ops = &clk_branch2_ops,
2586 static struct clk_branch camss_csi0phy_clk = {
2589 .enable_reg = 0x30c4,
2590 .enable_mask = BIT(0),
2591 .hw.init = &(struct clk_init_data){
2592 .name = "camss_csi0phy_clk",
2593 .parent_names = (const char *[]){ "csi0_clk_src" },
2595 .flags = CLK_SET_RATE_PARENT,
2596 .ops = &clk_branch2_ops,
2601 static struct clk_branch camss_csi0rdi_clk = {
2604 .enable_reg = 0x30d4,
2605 .enable_mask = BIT(0),
2606 .hw.init = &(struct clk_init_data){
2607 .name = "camss_csi0rdi_clk",
2608 .parent_names = (const char *[]){ "csi0_clk_src" },
2610 .flags = CLK_SET_RATE_PARENT,
2611 .ops = &clk_branch2_ops,
2616 static struct clk_branch camss_csi0pix_clk = {
2619 .enable_reg = 0x30e4,
2620 .enable_mask = BIT(0),
2621 .hw.init = &(struct clk_init_data){
2622 .name = "camss_csi0pix_clk",
2623 .parent_names = (const char *[]){ "csi0_clk_src" },
2625 .flags = CLK_SET_RATE_PARENT,
2626 .ops = &clk_branch2_ops,
2631 static struct clk_branch camss_csi1_clk = {
2634 .enable_reg = 0x3124,
2635 .enable_mask = BIT(0),
2636 .hw.init = &(struct clk_init_data){
2637 .name = "camss_csi1_clk",
2638 .parent_names = (const char *[]){ "csi1_clk_src" },
2640 .flags = CLK_SET_RATE_PARENT,
2641 .ops = &clk_branch2_ops,
2646 static struct clk_branch camss_csi1_ahb_clk = {
2649 .enable_reg = 0x3128,
2650 .enable_mask = BIT(0),
2651 .hw.init = &(struct clk_init_data){
2652 .name = "camss_csi1_ahb_clk",
2653 .parent_names = (const char *[]){ "ahb_clk_src" },
2655 .flags = CLK_SET_RATE_PARENT,
2656 .ops = &clk_branch2_ops,
2661 static struct clk_branch camss_csi1phy_clk = {
2664 .enable_reg = 0x3134,
2665 .enable_mask = BIT(0),
2666 .hw.init = &(struct clk_init_data){
2667 .name = "camss_csi1phy_clk",
2668 .parent_names = (const char *[]){ "csi1_clk_src" },
2670 .flags = CLK_SET_RATE_PARENT,
2671 .ops = &clk_branch2_ops,
2676 static struct clk_branch camss_csi1rdi_clk = {
2679 .enable_reg = 0x3144,
2680 .enable_mask = BIT(0),
2681 .hw.init = &(struct clk_init_data){
2682 .name = "camss_csi1rdi_clk",
2683 .parent_names = (const char *[]){ "csi1_clk_src" },
2685 .flags = CLK_SET_RATE_PARENT,
2686 .ops = &clk_branch2_ops,
2691 static struct clk_branch camss_csi1pix_clk = {
2694 .enable_reg = 0x3154,
2695 .enable_mask = BIT(0),
2696 .hw.init = &(struct clk_init_data){
2697 .name = "camss_csi1pix_clk",
2698 .parent_names = (const char *[]){ "csi1_clk_src" },
2700 .flags = CLK_SET_RATE_PARENT,
2701 .ops = &clk_branch2_ops,
2706 static struct clk_branch camss_csi2_clk = {
2709 .enable_reg = 0x3184,
2710 .enable_mask = BIT(0),
2711 .hw.init = &(struct clk_init_data){
2712 .name = "camss_csi2_clk",
2713 .parent_names = (const char *[]){ "csi2_clk_src" },
2715 .flags = CLK_SET_RATE_PARENT,
2716 .ops = &clk_branch2_ops,
2721 static struct clk_branch camss_csi2_ahb_clk = {
2724 .enable_reg = 0x3188,
2725 .enable_mask = BIT(0),
2726 .hw.init = &(struct clk_init_data){
2727 .name = "camss_csi2_ahb_clk",
2728 .parent_names = (const char *[]){ "ahb_clk_src" },
2730 .flags = CLK_SET_RATE_PARENT,
2731 .ops = &clk_branch2_ops,
2736 static struct clk_branch camss_csi2phy_clk = {
2739 .enable_reg = 0x3194,
2740 .enable_mask = BIT(0),
2741 .hw.init = &(struct clk_init_data){
2742 .name = "camss_csi2phy_clk",
2743 .parent_names = (const char *[]){ "csi2_clk_src" },
2745 .flags = CLK_SET_RATE_PARENT,
2746 .ops = &clk_branch2_ops,
2751 static struct clk_branch camss_csi2rdi_clk = {
2754 .enable_reg = 0x31a4,
2755 .enable_mask = BIT(0),
2756 .hw.init = &(struct clk_init_data){
2757 .name = "camss_csi2rdi_clk",
2758 .parent_names = (const char *[]){ "csi2_clk_src" },
2760 .flags = CLK_SET_RATE_PARENT,
2761 .ops = &clk_branch2_ops,
2766 static struct clk_branch camss_csi2pix_clk = {
2769 .enable_reg = 0x31b4,
2770 .enable_mask = BIT(0),
2771 .hw.init = &(struct clk_init_data){
2772 .name = "camss_csi2pix_clk",
2773 .parent_names = (const char *[]){ "csi2_clk_src" },
2775 .flags = CLK_SET_RATE_PARENT,
2776 .ops = &clk_branch2_ops,
2781 static struct clk_branch camss_csi3_clk = {
2784 .enable_reg = 0x31e4,
2785 .enable_mask = BIT(0),
2786 .hw.init = &(struct clk_init_data){
2787 .name = "camss_csi3_clk",
2788 .parent_names = (const char *[]){ "csi3_clk_src" },
2790 .flags = CLK_SET_RATE_PARENT,
2791 .ops = &clk_branch2_ops,
2796 static struct clk_branch camss_csi3_ahb_clk = {
2799 .enable_reg = 0x31e8,
2800 .enable_mask = BIT(0),
2801 .hw.init = &(struct clk_init_data){
2802 .name = "camss_csi3_ahb_clk",
2803 .parent_names = (const char *[]){ "ahb_clk_src" },
2805 .flags = CLK_SET_RATE_PARENT,
2806 .ops = &clk_branch2_ops,
2811 static struct clk_branch camss_csi3phy_clk = {
2814 .enable_reg = 0x31f4,
2815 .enable_mask = BIT(0),
2816 .hw.init = &(struct clk_init_data){
2817 .name = "camss_csi3phy_clk",
2818 .parent_names = (const char *[]){ "csi3_clk_src" },
2820 .flags = CLK_SET_RATE_PARENT,
2821 .ops = &clk_branch2_ops,
2826 static struct clk_branch camss_csi3rdi_clk = {
2829 .enable_reg = 0x3204,
2830 .enable_mask = BIT(0),
2831 .hw.init = &(struct clk_init_data){
2832 .name = "camss_csi3rdi_clk",
2833 .parent_names = (const char *[]){ "csi3_clk_src" },
2835 .flags = CLK_SET_RATE_PARENT,
2836 .ops = &clk_branch2_ops,
2841 static struct clk_branch camss_csi3pix_clk = {
2844 .enable_reg = 0x3214,
2845 .enable_mask = BIT(0),
2846 .hw.init = &(struct clk_init_data){
2847 .name = "camss_csi3pix_clk",
2848 .parent_names = (const char *[]){ "csi3_clk_src" },
2850 .flags = CLK_SET_RATE_PARENT,
2851 .ops = &clk_branch2_ops,
2856 static struct clk_branch camss_ispif_ahb_clk = {
2859 .enable_reg = 0x3224,
2860 .enable_mask = BIT(0),
2861 .hw.init = &(struct clk_init_data){
2862 .name = "camss_ispif_ahb_clk",
2863 .parent_names = (const char *[]){ "ahb_clk_src" },
2865 .flags = CLK_SET_RATE_PARENT,
2866 .ops = &clk_branch2_ops,
2871 static struct clk_branch fd_core_clk = {
2874 .enable_reg = 0x3b68,
2875 .enable_mask = BIT(0),
2876 .hw.init = &(struct clk_init_data){
2877 .name = "fd_core_clk",
2878 .parent_names = (const char *[]){ "fd_core_clk_src" },
2880 .flags = CLK_SET_RATE_PARENT,
2881 .ops = &clk_branch2_ops,
2886 static struct clk_branch fd_core_uar_clk = {
2889 .enable_reg = 0x3b6c,
2890 .enable_mask = BIT(0),
2891 .hw.init = &(struct clk_init_data){
2892 .name = "fd_core_uar_clk",
2893 .parent_names = (const char *[]){ "fd_core_clk_src" },
2895 .flags = CLK_SET_RATE_PARENT,
2896 .ops = &clk_branch2_ops,
2901 static struct clk_branch fd_ahb_clk = {
2902 .halt_reg = 0x3ba74,
2904 .enable_reg = 0x3ba74,
2905 .enable_mask = BIT(0),
2906 .hw.init = &(struct clk_init_data){
2907 .name = "fd_ahb_clk",
2908 .parent_names = (const char *[]){ "ahb_clk_src" },
2910 .flags = CLK_SET_RATE_PARENT,
2911 .ops = &clk_branch2_ops,
2916 static struct clk_hw *mmcc_msm8996_hws[] = {
2920 static struct clk_regmap *mmcc_msm8996_clocks[] = {
2921 [MMPLL0_EARLY] = &mmpll0_early.clkr,
2922 [MMPLL0_PLL] = &mmpll0.clkr,
2923 [MMPLL1_EARLY] = &mmpll1_early.clkr,
2924 [MMPLL1_PLL] = &mmpll1.clkr,
2925 [MMPLL2_EARLY] = &mmpll2_early.clkr,
2926 [MMPLL2_PLL] = &mmpll2.clkr,
2927 [MMPLL3_EARLY] = &mmpll3_early.clkr,
2928 [MMPLL3_PLL] = &mmpll3.clkr,
2929 [MMPLL4_EARLY] = &mmpll4_early.clkr,
2930 [MMPLL4_PLL] = &mmpll4.clkr,
2931 [MMPLL5_EARLY] = &mmpll5_early.clkr,
2932 [MMPLL5_PLL] = &mmpll5.clkr,
2933 [MMPLL8_EARLY] = &mmpll8_early.clkr,
2934 [MMPLL8_PLL] = &mmpll8.clkr,
2935 [MMPLL9_EARLY] = &mmpll9_early.clkr,
2936 [MMPLL9_PLL] = &mmpll9.clkr,
2937 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2938 [AXI_CLK_SRC] = &axi_clk_src.clkr,
2939 [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
2940 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2941 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
2942 [ISENSE_CLK_SRC] = &isense_clk_src.clkr,
2943 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
2944 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
2945 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
2946 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
2947 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2948 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2949 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2950 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2951 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2952 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2953 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2954 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2955 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2956 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2957 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2958 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2959 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2960 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2961 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2962 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2963 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2964 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2965 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2966 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2967 [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr,
2968 [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr,
2969 [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr,
2970 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2971 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2972 [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
2973 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2974 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2975 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2976 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2977 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2978 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2979 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2980 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2981 [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr,
2982 [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr,
2983 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2984 [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr,
2985 [MMSS_MMAGIC_AXI_CLK] = &mmss_mmagic_axi_clk.clkr,
2986 [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr,
2987 [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr,
2988 [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr,
2989 [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr,
2990 [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr,
2991 [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr,
2992 [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr,
2993 [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr,
2994 [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr,
2995 [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr,
2996 [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr,
2997 [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr,
2998 [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr,
2999 [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr,
3000 [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr,
3001 [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr,
3002 [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr,
3003 [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr,
3004 [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr,
3005 [MMAGIC_BIMC_AXI_CLK] = &mmagic_bimc_axi_clk.clkr,
3006 [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr,
3007 [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr,
3008 [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr,
3009 [GPU_AHB_CLK] = &gpu_ahb_clk.clkr,
3010 [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr,
3011 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
3012 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
3013 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3014 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3015 [VIDEO_CORE_CLK] = &video_core_clk.clkr,
3016 [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
3017 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
3018 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
3019 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
3020 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
3021 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3022 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3023 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3024 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3025 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3026 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3027 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3028 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3029 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3030 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3031 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3032 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3033 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3034 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3035 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3036 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3037 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3038 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3039 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3040 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3041 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3042 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3043 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
3044 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
3045 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
3046 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
3047 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
3048 [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr,
3049 [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr,
3050 [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr,
3051 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
3052 [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr,
3053 [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
3054 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
3055 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
3056 [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr,
3057 [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr,
3058 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
3059 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
3060 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
3061 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
3062 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
3063 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
3064 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3065 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3066 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
3067 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
3068 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
3069 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
3070 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3071 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3072 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3073 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3074 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3075 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3076 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3077 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3078 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3079 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3080 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3081 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3082 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3083 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3084 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3085 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3086 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3087 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3088 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3089 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3090 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3091 [FD_CORE_CLK] = &fd_core_clk.clkr,
3092 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
3093 [FD_AHB_CLK] = &fd_ahb_clk.clkr,
3096 static const struct qcom_reset_map mmcc_msm8996_resets[] = {
3097 [MMAGICAHB_BCR] = { 0x5020 },
3098 [MMAGIC_CFG_BCR] = { 0x5050 },
3099 [MISC_BCR] = { 0x5010 },
3100 [BTO_BCR] = { 0x5030 },
3101 [MMAGICAXI_BCR] = { 0x5060 },
3102 [MMAGICMAXI_BCR] = { 0x5070 },
3103 [DSA_BCR] = { 0x50a0 },
3104 [MMAGIC_CAMSS_BCR] = { 0x3c40 },
3105 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
3106 [SMMU_VFE_BCR] = { 0x3c00 },
3107 [SMMU_CPP_BCR] = { 0x3c10 },
3108 [SMMU_JPEG_BCR] = { 0x3c20 },
3109 [MMAGIC_MDSS_BCR] = { 0x2470 },
3110 [THROTTLE_MDSS_BCR] = { 0x2460 },
3111 [SMMU_ROT_BCR] = { 0x2440 },
3112 [SMMU_MDP_BCR] = { 0x2450 },
3113 [MMAGIC_VIDEO_BCR] = { 0x1190 },
3114 [THROTTLE_VIDEO_BCR] = { 0x1180 },
3115 [SMMU_VIDEO_BCR] = { 0x1170 },
3116 [MMAGIC_BIMC_BCR] = { 0x5290 },
3117 [GPU_GX_BCR] = { 0x4020 },
3118 [GPU_BCR] = { 0x4030 },
3119 [GPU_AON_BCR] = { 0x4040 },
3120 [VMEM_BCR] = { 0x1200 },
3121 [MMSS_RBCPR_BCR] = { 0x4080 },
3122 [VIDEO_BCR] = { 0x1020 },
3123 [MDSS_BCR] = { 0x2300 },
3124 [CAMSS_TOP_BCR] = { 0x3480 },
3125 [CAMSS_AHB_BCR] = { 0x3488 },
3126 [CAMSS_MICRO_BCR] = { 0x3490 },
3127 [CAMSS_CCI_BCR] = { 0x3340 },
3128 [CAMSS_PHY0_BCR] = { 0x3020 },
3129 [CAMSS_PHY1_BCR] = { 0x3050 },
3130 [CAMSS_PHY2_BCR] = { 0x3080 },
3131 [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
3132 [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
3133 [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
3134 [CAMSS_JPEG_BCR] = { 0x35a0 },
3135 [CAMSS_VFE_BCR] = { 0x36a0 },
3136 [CAMSS_VFE0_BCR] = { 0x3660 },
3137 [CAMSS_VFE1_BCR] = { 0x3670 },
3138 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
3139 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
3140 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
3141 [CAMSS_CPP_BCR] = { 0x36d0 },
3142 [CAMSS_CSI0_BCR] = { 0x30b0 },
3143 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
3144 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
3145 [CAMSS_CSI1_BCR] = { 0x3120 },
3146 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
3147 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
3148 [CAMSS_CSI2_BCR] = { 0x3180 },
3149 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
3150 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
3151 [CAMSS_CSI3_BCR] = { 0x31e0 },
3152 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
3153 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
3154 [CAMSS_ISPIF_BCR] = { 0x3220 },
3155 [FD_BCR] = { 0x3b60 },
3156 [MMSS_SPDM_RM_BCR] = { 0x300 },
3159 static const struct regmap_config mmcc_msm8996_regmap_config = {
3163 .max_register = 0xb008,
3167 static const struct qcom_cc_desc mmcc_msm8996_desc = {
3168 .config = &mmcc_msm8996_regmap_config,
3169 .clks = mmcc_msm8996_clocks,
3170 .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks),
3171 .resets = mmcc_msm8996_resets,
3172 .num_resets = ARRAY_SIZE(mmcc_msm8996_resets),
3175 static const struct of_device_id mmcc_msm8996_match_table[] = {
3176 { .compatible = "qcom,mmcc-msm8996" },
3179 MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table);
3181 static int mmcc_msm8996_probe(struct platform_device *pdev)
3184 struct device *dev = &pdev->dev;
3186 struct regmap *regmap;
3188 regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc);
3190 return PTR_ERR(regmap);
3192 /* Disable the AHB DCD */
3193 regmap_update_bits(regmap, 0x50d8, BIT(31), 0);
3194 /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */
3195 regmap_update_bits(regmap, 0x5054, BIT(15), 0);
3197 for (i = 0; i < ARRAY_SIZE(mmcc_msm8996_hws); i++) {
3198 clk = devm_clk_register(dev, mmcc_msm8996_hws[i]);
3200 return PTR_ERR(clk);
3203 return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap);
3206 static struct platform_driver mmcc_msm8996_driver = {
3207 .probe = mmcc_msm8996_probe,
3209 .name = "mmcc-msm8996",
3210 .of_match_table = mmcc_msm8996_match_table,
3213 module_platform_driver(mmcc_msm8996_driver);
3215 MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver");
3216 MODULE_LICENSE("GPL v2");
3217 MODULE_ALIAS("platform:mmcc-msm8996");