drivers/clk/qcom/mmcc-msm8960.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/delay.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/of_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/regmap.h>
  17 #include <linux/reset-controller.h>
  18
  19 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
  20 #include <dt-bindings/reset/qcom,mmcc-msm8960.h>
  21
  22 #include "common.h"
  23 #include "clk-regmap.h"
  24 #include "clk-pll.h"
  25 #include "clk-rcg.h"
  26 #include "clk-branch.h"
  27 #include "reset.h"
  28
  29 enum {
  30         P_PXO,
  31         P_PLL8,
  32         P_PLL2,
  33         P_PLL3,
  34         P_PLL15,
  35         P_HDMI_PLL,
  36         P_DSI1_PLL_DSICLK,
  37         P_DSI2_PLL_DSICLK,
  38         P_DSI1_PLL_BYTECLK,
  39         P_DSI2_PLL_BYTECLK,
  40 };
  41
  42 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
  43
  44 static struct clk_pll pll2 = {
  45         .l_reg = 0x320,
  46         .m_reg = 0x324,
  47         .n_reg = 0x328,
  48         .config_reg = 0x32c,
  49         .mode_reg = 0x31c,
  50         .status_reg = 0x334,
  51         .status_bit = 16,
  52         .clkr.hw.init = &(struct clk_init_data){
  53                 .name = "pll2",
  54                 .parent_data = (const struct clk_parent_data[]){
  55                         { .fw_name = "pxo", .name = "pxo_board" },
  56                 },
  57                 .num_parents = 1,
  58                 .ops = &clk_pll_ops,
  59         },
  60 };
  61
  62 static struct clk_pll pll15 = {
  63         .l_reg = 0x33c,
  64         .m_reg = 0x340,
  65         .n_reg = 0x344,
  66         .config_reg = 0x348,
  67         .mode_reg = 0x338,
  68         .status_reg = 0x350,
  69         .status_bit = 16,
  70         .clkr.hw.init = &(struct clk_init_data){
  71                 .name = "pll15",
  72                 .parent_data = (const struct clk_parent_data[]){
  73                         { .fw_name = "pxo", .name = "pxo_board" },
  74                 },
  75                 .num_parents = 1,
  76                 .ops = &clk_pll_ops,
  77         },
  78 };
  79
  80 static const struct pll_config pll15_config = {
  81         .l = 33,
  82         .m = 1,
  83         .n = 3,
  84         .vco_val = 0x2 << 16,
  85         .vco_mask = 0x3 << 16,
  86         .pre_div_val = 0x0,
  87         .pre_div_mask = BIT(19),
  88         .post_div_val = 0x0,
  89         .post_div_mask = 0x3 << 20,
  90         .mn_ena_mask = BIT(22),
  91         .main_output_mask = BIT(23),
  92 };
  93
  94 static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
  95         { P_PXO, 0 },
  96         { P_PLL8, 2 },
  97         { P_PLL2, 1 }
  98 };
  99
 100 static const struct clk_parent_data mmcc_pxo_pll8_pll2[] = {
 101         { .fw_name = "pxo", .name = "pxo_board" },
 102         { .fw_name = "pll8_vote", .name = "pll8_vote" },
 103         { .hw = &pll2.clkr.hw },
 104 };
 105
 106 static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
 107         { P_PXO, 0 },
 108         { P_PLL8, 2 },
 109         { P_PLL2, 1 },
 110         { P_PLL3, 3 }
 111 };
 112
 113 static const struct clk_parent_data mmcc_pxo_pll8_pll2_pll15[] = {
 114         { .fw_name = "pxo", .name = "pxo_board" },
 115         { .fw_name = "pll8_vote", .name = "pll8_vote" },
 116         { .hw = &pll2.clkr.hw },
 117         { .hw = &pll15.clkr.hw },
 118 };
 119
 120 static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
 121         { P_PXO, 0 },
 122         { P_PLL8, 2 },
 123         { P_PLL2, 1 },
 124         { P_PLL15, 3 }
 125 };
 126
 127 static const struct clk_parent_data mmcc_pxo_pll8_pll2_pll3[] = {
 128         { .fw_name = "pxo", .name = "pxo_board" },
 129         { .fw_name = "pll8_vote", .name = "pll8_vote" },
 130         { .hw = &pll2.clkr.hw },
 131         { .fw_name = "pll3", .name = "pll3" },
 132 };
 133
 134 static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = {
 135         { P_PXO, 0 },
 136         { P_DSI2_PLL_DSICLK, 1 },
 137         { P_DSI1_PLL_DSICLK, 3 },
 138 };
 139
 140 static const struct clk_parent_data mmcc_pxo_dsi2_dsi1[] = {
 141         { .fw_name = "pxo", .name = "pxo_board" },
 142         { .fw_name = "dsi2pll", .name = "dsi2pll" },
 143         { .fw_name = "dsi1pll", .name = "dsi1pll" },
 144 };
 145
 146 static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = {
 147         { P_PXO, 0 },
 148         { P_DSI1_PLL_BYTECLK, 1 },
 149         { P_DSI2_PLL_BYTECLK, 2 },
 150 };
 151
 152 static const struct clk_parent_data mmcc_pxo_dsi1_dsi2_byte[] = {
 153         { .fw_name = "pxo", .name = "pxo_board" },
 154         { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
 155         { .fw_name = "dsi2pllbyte", .name = "dsi2pllbyte" },
 156 };
 157
 158 static struct freq_tbl clk_tbl_cam[] = {
 159         {   6000000, P_PLL8, 4, 1, 16 },
 160         {   8000000, P_PLL8, 4, 1, 12 },
 161         {  12000000, P_PLL8, 4, 1,  8 },
 162         {  16000000, P_PLL8, 4, 1,  6 },
 163         {  19200000, P_PLL8, 4, 1,  5 },
 164         {  24000000, P_PLL8, 4, 1,  4 },
 165         {  32000000, P_PLL8, 4, 1,  3 },
 166         {  48000000, P_PLL8, 4, 1,  2 },
 167         {  64000000, P_PLL8, 3, 1,  2 },
 168         {  96000000, P_PLL8, 4, 0,  0 },
 169         { 128000000, P_PLL8, 3, 0,  0 },
 170         { }
 171 };
 172
 173 static struct clk_rcg camclk0_src = {
 174         .ns_reg = 0x0148,
 175         .md_reg = 0x0144,
 176         .mn = {
 177                 .mnctr_en_bit = 5,
 178                 .mnctr_reset_bit = 8,
 179                 .reset_in_cc = true,
 180                 .mnctr_mode_shift = 6,
 181                 .n_val_shift = 24,
 182                 .m_val_shift = 8,
 183                 .width = 8,
 184         },
 185         .p = {
 186                 .pre_div_shift = 14,
 187                 .pre_div_width = 2,
 188         },
 189         .s = {
 190                 .src_sel_shift = 0,
 191                 .parent_map = mmcc_pxo_pll8_pll2_map,
 192         },
 193         .freq_tbl = clk_tbl_cam,
 194         .clkr = {
 195                 .enable_reg = 0x0140,
 196                 .enable_mask = BIT(2),
 197                 .hw.init = &(struct clk_init_data){
 198                         .name = "camclk0_src",
 199                         .parent_data = mmcc_pxo_pll8_pll2,
 200                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 201                         .ops = &clk_rcg_ops,
 202                 },
 203         },
 204 };
 205
 206 static struct clk_branch camclk0_clk = {
 207         .halt_reg = 0x01e8,
 208         .halt_bit = 15,
 209         .clkr = {
 210                 .enable_reg = 0x0140,
 211                 .enable_mask = BIT(0),
 212                 .hw.init = &(struct clk_init_data){
 213                         .name = "camclk0_clk",
 214                         .parent_hws = (const struct clk_hw*[]){
 215                                 &camclk0_src.clkr.hw
 216                         },
 217                         .num_parents = 1,
 218                         .ops = &clk_branch_ops,
 219                 },
 220         },
 221
 222 };
 223
 224 static struct clk_rcg camclk1_src = {
 225         .ns_reg = 0x015c,
 226         .md_reg = 0x0158,
 227         .mn = {
 228                 .mnctr_en_bit = 5,
 229                 .mnctr_reset_bit = 8,
 230                 .reset_in_cc = true,
 231                 .mnctr_mode_shift = 6,
 232                 .n_val_shift = 24,
 233                 .m_val_shift = 8,
 234                 .width = 8,
 235         },
 236         .p = {
 237                 .pre_div_shift = 14,
 238                 .pre_div_width = 2,
 239         },
 240         .s = {
 241                 .src_sel_shift = 0,
 242                 .parent_map = mmcc_pxo_pll8_pll2_map,
 243         },
 244         .freq_tbl = clk_tbl_cam,
 245         .clkr = {
 246                 .enable_reg = 0x0154,
 247                 .enable_mask = BIT(2),
 248                 .hw.init = &(struct clk_init_data){
 249                         .name = "camclk1_src",
 250                         .parent_data = mmcc_pxo_pll8_pll2,
 251                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 252                         .ops = &clk_rcg_ops,
 253                 },
 254         },
 255 };
 256
 257 static struct clk_branch camclk1_clk = {
 258         .halt_reg = 0x01e8,
 259         .halt_bit = 16,
 260         .clkr = {
 261                 .enable_reg = 0x0154,
 262                 .enable_mask = BIT(0),
 263                 .hw.init = &(struct clk_init_data){
 264                         .name = "camclk1_clk",
 265                         .parent_hws = (const struct clk_hw*[]){
 266                                 &camclk1_src.clkr.hw
 267                         },
 268                         .num_parents = 1,
 269                         .ops = &clk_branch_ops,
 270                 },
 271         },
 272
 273 };
 274
 275 static struct clk_rcg camclk2_src = {
 276         .ns_reg = 0x0228,
 277         .md_reg = 0x0224,
 278         .mn = {
 279                 .mnctr_en_bit = 5,
 280                 .mnctr_reset_bit = 8,
 281                 .reset_in_cc = true,
 282                 .mnctr_mode_shift = 6,
 283                 .n_val_shift = 24,
 284                 .m_val_shift = 8,
 285                 .width = 8,
 286         },
 287         .p = {
 288                 .pre_div_shift = 14,
 289                 .pre_div_width = 2,
 290         },
 291         .s = {
 292                 .src_sel_shift = 0,
 293                 .parent_map = mmcc_pxo_pll8_pll2_map,
 294         },
 295         .freq_tbl = clk_tbl_cam,
 296         .clkr = {
 297                 .enable_reg = 0x0220,
 298                 .enable_mask = BIT(2),
 299                 .hw.init = &(struct clk_init_data){
 300                         .name = "camclk2_src",
 301                         .parent_data = mmcc_pxo_pll8_pll2,
 302                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 303                         .ops = &clk_rcg_ops,
 304                 },
 305         },
 306 };
 307
 308 static struct clk_branch camclk2_clk = {
 309         .halt_reg = 0x01e8,
 310         .halt_bit = 16,
 311         .clkr = {
 312                 .enable_reg = 0x0220,
 313                 .enable_mask = BIT(0),
 314                 .hw.init = &(struct clk_init_data){
 315                         .name = "camclk2_clk",
 316                         .parent_hws = (const struct clk_hw*[]){
 317                                 &camclk2_src.clkr.hw
 318                         },
 319                         .num_parents = 1,
 320                         .ops = &clk_branch_ops,
 321                 },
 322         },
 323
 324 };
 325
 326 static struct freq_tbl clk_tbl_csi[] = {
 327         {  27000000, P_PXO,  1, 0, 0 },
 328         {  85330000, P_PLL8, 1, 2, 9 },
 329         { 177780000, P_PLL2, 1, 2, 9 },
 330         { }
 331 };
 332
 333 static struct clk_rcg csi0_src = {
 334         .ns_reg = 0x0048,
 335         .md_reg = 0x0044,
 336         .mn = {
 337                 .mnctr_en_bit = 5,
 338                 .mnctr_reset_bit = 7,
 339                 .mnctr_mode_shift = 6,
 340                 .n_val_shift = 24,
 341                 .m_val_shift = 8,
 342                 .width = 8,
 343         },
 344         .p = {
 345                 .pre_div_shift = 14,
 346                 .pre_div_width = 2,
 347         },
 348         .s = {
 349                 .src_sel_shift = 0,
 350                 .parent_map = mmcc_pxo_pll8_pll2_map,
 351         },
 352         .freq_tbl = clk_tbl_csi,
 353         .clkr = {
 354                 .enable_reg = 0x0040,
 355                 .enable_mask = BIT(2),
 356                 .hw.init = &(struct clk_init_data){
 357                         .name = "csi0_src",
 358                         .parent_data = mmcc_pxo_pll8_pll2,
 359                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 360                         .ops = &clk_rcg_ops,
 361                 },
 362         },
 363 };
 364
 365 static struct clk_branch csi0_clk = {
 366         .halt_reg = 0x01cc,
 367         .halt_bit = 13,
 368         .clkr = {
 369                 .enable_reg = 0x0040,
 370                 .enable_mask = BIT(0),
 371                 .hw.init = &(struct clk_init_data){
 372                         .parent_hws = (const struct clk_hw*[]){
 373                                 &csi0_src.clkr.hw
 374                         },
 375                         .num_parents = 1,
 376                         .name = "csi0_clk",
 377                         .ops = &clk_branch_ops,
 378                         .flags = CLK_SET_RATE_PARENT,
 379                 },
 380         },
 381 };
 382
 383 static struct clk_branch csi0_phy_clk = {
 384         .halt_reg = 0x01e8,
 385         .halt_bit = 9,
 386         .clkr = {
 387                 .enable_reg = 0x0040,
 388                 .enable_mask = BIT(8),
 389                 .hw.init = &(struct clk_init_data){
 390                         .parent_hws = (const struct clk_hw*[]){
 391                                 &csi0_src.clkr.hw
 392                         },
 393                         .num_parents = 1,
 394                         .name = "csi0_phy_clk",
 395                         .ops = &clk_branch_ops,
 396                         .flags = CLK_SET_RATE_PARENT,
 397                 },
 398         },
 399 };
 400
 401 static struct clk_rcg csi1_src = {
 402         .ns_reg = 0x0010,
 403         .md_reg = 0x0028,
 404         .mn = {
 405                 .mnctr_en_bit = 5,
 406                 .mnctr_reset_bit = 7,
 407                 .mnctr_mode_shift = 6,
 408                 .n_val_shift = 24,
 409                 .m_val_shift = 8,
 410                 .width = 8,
 411         },
 412         .p = {
 413                 .pre_div_shift = 14,
 414                 .pre_div_width = 2,
 415         },
 416         .s = {
 417                 .src_sel_shift = 0,
 418                 .parent_map = mmcc_pxo_pll8_pll2_map,
 419         },
 420         .freq_tbl = clk_tbl_csi,
 421         .clkr = {
 422                 .enable_reg = 0x0024,
 423                 .enable_mask = BIT(2),
 424                 .hw.init = &(struct clk_init_data){
 425                         .name = "csi1_src",
 426                         .parent_data = mmcc_pxo_pll8_pll2,
 427                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 428                         .ops = &clk_rcg_ops,
 429                 },
 430         },
 431 };
 432
 433 static struct clk_branch csi1_clk = {
 434         .halt_reg = 0x01cc,
 435         .halt_bit = 14,
 436         .clkr = {
 437                 .enable_reg = 0x0024,
 438                 .enable_mask = BIT(0),
 439                 .hw.init = &(struct clk_init_data){
 440                         .parent_hws = (const struct clk_hw*[]){
 441                                 &csi1_src.clkr.hw
 442                         },
 443                         .num_parents = 1,
 444                         .name = "csi1_clk",
 445                         .ops = &clk_branch_ops,
 446                         .flags = CLK_SET_RATE_PARENT,
 447                 },
 448         },
 449 };
 450
 451 static struct clk_branch csi1_phy_clk = {
 452         .halt_reg = 0x01e8,
 453         .halt_bit = 10,
 454         .clkr = {
 455                 .enable_reg = 0x0024,
 456                 .enable_mask = BIT(8),
 457                 .hw.init = &(struct clk_init_data){
 458                         .parent_hws = (const struct clk_hw*[]){
 459                                 &csi1_src.clkr.hw
 460                         },
 461                         .num_parents = 1,
 462                         .name = "csi1_phy_clk",
 463                         .ops = &clk_branch_ops,
 464                         .flags = CLK_SET_RATE_PARENT,
 465                 },
 466         },
 467 };
 468
 469 static struct clk_rcg csi2_src = {
 470         .ns_reg = 0x0234,
 471         .md_reg = 0x022c,
 472         .mn = {
 473                 .mnctr_en_bit = 5,
 474                 .mnctr_reset_bit = 7,
 475                 .mnctr_mode_shift = 6,
 476                 .n_val_shift = 24,
 477                 .m_val_shift = 8,
 478                 .width = 8,
 479         },
 480         .p = {
 481                 .pre_div_shift = 14,
 482                 .pre_div_width = 2,
 483         },
 484         .s = {
 485                 .src_sel_shift = 0,
 486                 .parent_map = mmcc_pxo_pll8_pll2_map,
 487         },
 488         .freq_tbl = clk_tbl_csi,
 489         .clkr = {
 490                 .enable_reg = 0x022c,
 491                 .enable_mask = BIT(2),
 492                 .hw.init = &(struct clk_init_data){
 493                         .name = "csi2_src",
 494                         .parent_data = mmcc_pxo_pll8_pll2,
 495                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 496                         .ops = &clk_rcg_ops,
 497                 },
 498         },
 499 };
 500
 501 static struct clk_branch csi2_clk = {
 502         .halt_reg = 0x01cc,
 503         .halt_bit = 29,
 504         .clkr = {
 505                 .enable_reg = 0x022c,
 506                 .enable_mask = BIT(0),
 507                 .hw.init = &(struct clk_init_data){
 508                         .parent_hws = (const struct clk_hw*[]){
 509                                 &csi2_src.clkr.hw
 510                         },
 511                         .num_parents = 1,
 512                         .name = "csi2_clk",
 513                         .ops = &clk_branch_ops,
 514                         .flags = CLK_SET_RATE_PARENT,
 515                 },
 516         },
 517 };
 518
 519 static struct clk_branch csi2_phy_clk = {
 520         .halt_reg = 0x01e8,
 521         .halt_bit = 29,
 522         .clkr = {
 523                 .enable_reg = 0x022c,
 524                 .enable_mask = BIT(8),
 525                 .hw.init = &(struct clk_init_data){
 526                         .parent_hws = (const struct clk_hw*[]){
 527                                 &csi2_src.clkr.hw
 528                         },
 529                         .num_parents = 1,
 530                         .name = "csi2_phy_clk",
 531                         .ops = &clk_branch_ops,
 532                         .flags = CLK_SET_RATE_PARENT,
 533                 },
 534         },
 535 };
 536
 537 struct clk_pix_rdi {
 538         u32 s_reg;
 539         u32 s_mask;
 540         u32 s2_reg;
 541         u32 s2_mask;
 542         struct clk_regmap clkr;
 543 };
 544
 545 #define to_clk_pix_rdi(_hw) \
 546         container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
 547
 548 static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
 549 {
 550         int i;
 551         int ret = 0;
 552         u32 val;
 553         struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
 554         int num_parents = clk_hw_get_num_parents(hw);
 555
 556         /*
 557          * These clocks select three inputs via two muxes. One mux selects
 558          * between csi0 and csi1 and the second mux selects between that mux's
 559          * output and csi2. The source and destination selections for each
 560          * mux must be clocking for the switch to succeed so just turn on
 561          * all three sources because it's easier than figuring out what source
 562          * needs to be on at what time.
 563          */
 564         for (i = 0; i < num_parents; i++) {
 565                 struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
 566                 ret = clk_prepare_enable(p->clk);
 567                 if (ret)
 568                         goto err;
 569         }
 570
 571         if (index == 2)
 572                 val = rdi->s2_mask;
 573         else
 574                 val = 0;
 575         regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
 576         /*
 577          * Wait at least 6 cycles of slowest clock
 578          * for the glitch-free MUX to fully switch sources.
 579          */
 580         udelay(1);
 581
 582         if (index == 1)
 583                 val = rdi->s_mask;
 584         else
 585                 val = 0;
 586         regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
 587         /*
 588          * Wait at least 6 cycles of slowest clock
 589          * for the glitch-free MUX to fully switch sources.
 590          */
 591         udelay(1);
 592
 593 err:
 594         for (i--; i >= 0; i--) {
 595                 struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
 596                 clk_disable_unprepare(p->clk);
 597         }
 598
 599         return ret;
 600 }
 601
 602 static u8 pix_rdi_get_parent(struct clk_hw *hw)
 603 {
 604         u32 val;
 605         struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
 606
 607
 608         regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
 609         if (val & rdi->s2_mask)
 610                 return 2;
 611
 612         regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
 613         if (val & rdi->s_mask)
 614                 return 1;
 615
 616         return 0;
 617 }
 618
 619 static const struct clk_ops clk_ops_pix_rdi = {
 620         .enable = clk_enable_regmap,
 621         .disable = clk_disable_regmap,
 622         .set_parent = pix_rdi_set_parent,
 623         .get_parent = pix_rdi_get_parent,
 624         .determine_rate = __clk_mux_determine_rate,
 625 };
 626
 627 static const struct clk_hw *pix_rdi_parents[] = {
 628         &csi0_clk.clkr.hw,
 629         &csi1_clk.clkr.hw,
 630         &csi2_clk.clkr.hw,
 631 };
 632
 633 static struct clk_pix_rdi csi_pix_clk = {
 634         .s_reg = 0x0058,
 635         .s_mask = BIT(25),
 636         .s2_reg = 0x0238,
 637         .s2_mask = BIT(13),
 638         .clkr = {
 639                 .enable_reg = 0x0058,
 640                 .enable_mask = BIT(26),
 641                 .hw.init = &(struct clk_init_data){
 642                         .name = "csi_pix_clk",
 643                         .parent_hws = pix_rdi_parents,
 644                         .num_parents = ARRAY_SIZE(pix_rdi_parents),
 645                         .ops = &clk_ops_pix_rdi,
 646                 },
 647         },
 648 };
 649
 650 static struct clk_pix_rdi csi_pix1_clk = {
 651         .s_reg = 0x0238,
 652         .s_mask = BIT(8),
 653         .s2_reg = 0x0238,
 654         .s2_mask = BIT(9),
 655         .clkr = {
 656                 .enable_reg = 0x0238,
 657                 .enable_mask = BIT(10),
 658                 .hw.init = &(struct clk_init_data){
 659                         .name = "csi_pix1_clk",
 660                         .parent_hws = pix_rdi_parents,
 661                         .num_parents = ARRAY_SIZE(pix_rdi_parents),
 662                         .ops = &clk_ops_pix_rdi,
 663                 },
 664         },
 665 };
 666
 667 static struct clk_pix_rdi csi_rdi_clk = {
 668         .s_reg = 0x0058,
 669         .s_mask = BIT(12),
 670         .s2_reg = 0x0238,
 671         .s2_mask = BIT(12),
 672         .clkr = {
 673                 .enable_reg = 0x0058,
 674                 .enable_mask = BIT(13),
 675                 .hw.init = &(struct clk_init_data){
 676                         .name = "csi_rdi_clk",
 677                         .parent_hws = pix_rdi_parents,
 678                         .num_parents = ARRAY_SIZE(pix_rdi_parents),
 679                         .ops = &clk_ops_pix_rdi,
 680                 },
 681         },
 682 };
 683
 684 static struct clk_pix_rdi csi_rdi1_clk = {
 685         .s_reg = 0x0238,
 686         .s_mask = BIT(0),
 687         .s2_reg = 0x0238,
 688         .s2_mask = BIT(1),
 689         .clkr = {
 690                 .enable_reg = 0x0238,
 691                 .enable_mask = BIT(2),
 692                 .hw.init = &(struct clk_init_data){
 693                         .name = "csi_rdi1_clk",
 694                         .parent_hws = pix_rdi_parents,
 695                         .num_parents = ARRAY_SIZE(pix_rdi_parents),
 696                         .ops = &clk_ops_pix_rdi,
 697                 },
 698         },
 699 };
 700
 701 static struct clk_pix_rdi csi_rdi2_clk = {
 702         .s_reg = 0x0238,
 703         .s_mask = BIT(4),
 704         .s2_reg = 0x0238,
 705         .s2_mask = BIT(5),
 706         .clkr = {
 707                 .enable_reg = 0x0238,
 708                 .enable_mask = BIT(6),
 709                 .hw.init = &(struct clk_init_data){
 710                         .name = "csi_rdi2_clk",
 711                         .parent_hws = pix_rdi_parents,
 712                         .num_parents = ARRAY_SIZE(pix_rdi_parents),
 713                         .ops = &clk_ops_pix_rdi,
 714                 },
 715         },
 716 };
 717
 718 static struct freq_tbl clk_tbl_csiphytimer[] = {
 719         {  85330000, P_PLL8, 1, 2, 9 },
 720         { 177780000, P_PLL2, 1, 2, 9 },
 721         { }
 722 };
 723
 724 static struct clk_rcg csiphytimer_src = {
 725         .ns_reg = 0x0168,
 726         .md_reg = 0x0164,
 727         .mn = {
 728                 .mnctr_en_bit = 5,
 729                 .mnctr_reset_bit = 8,
 730                 .reset_in_cc = true,
 731                 .mnctr_mode_shift = 6,
 732                 .n_val_shift = 24,
 733                 .m_val_shift = 8,
 734                 .width = 8,
 735         },
 736         .p = {
 737                 .pre_div_shift = 14,
 738                 .pre_div_width = 2,
 739         },
 740         .s = {
 741                 .src_sel_shift = 0,
 742                 .parent_map = mmcc_pxo_pll8_pll2_map,
 743         },
 744         .freq_tbl = clk_tbl_csiphytimer,
 745         .clkr = {
 746                 .enable_reg = 0x0160,
 747                 .enable_mask = BIT(2),
 748                 .hw.init = &(struct clk_init_data){
 749                         .name = "csiphytimer_src",
 750                         .parent_data = mmcc_pxo_pll8_pll2,
 751                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 752                         .ops = &clk_rcg_ops,
 753                 },
 754         },
 755 };
 756
 757 static struct clk_branch csiphy0_timer_clk = {
 758         .halt_reg = 0x01e8,
 759         .halt_bit = 17,
 760         .clkr = {
 761                 .enable_reg = 0x0160,
 762                 .enable_mask = BIT(0),
 763                 .hw.init = &(struct clk_init_data){
 764                         .parent_hws = (const struct clk_hw*[]){
 765                                 &csiphytimer_src.clkr.hw,
 766                         },
 767                         .num_parents = 1,
 768                         .name = "csiphy0_timer_clk",
 769                         .ops = &clk_branch_ops,
 770                         .flags = CLK_SET_RATE_PARENT,
 771                 },
 772         },
 773 };
 774
 775 static struct clk_branch csiphy1_timer_clk = {
 776         .halt_reg = 0x01e8,
 777         .halt_bit = 18,
 778         .clkr = {
 779                 .enable_reg = 0x0160,
 780                 .enable_mask = BIT(9),
 781                 .hw.init = &(struct clk_init_data){
 782                         .parent_hws = (const struct clk_hw*[]){
 783                                 &csiphytimer_src.clkr.hw,
 784                         },
 785                         .num_parents = 1,
 786                         .name = "csiphy1_timer_clk",
 787                         .ops = &clk_branch_ops,
 788                         .flags = CLK_SET_RATE_PARENT,
 789                 },
 790         },
 791 };
 792
 793 static struct clk_branch csiphy2_timer_clk = {
 794         .halt_reg = 0x01e8,
 795         .halt_bit = 30,
 796         .clkr = {
 797                 .enable_reg = 0x0160,
 798                 .enable_mask = BIT(11),
 799                 .hw.init = &(struct clk_init_data){
 800                         .parent_hws = (const struct clk_hw*[]){
 801                                 &csiphytimer_src.clkr.hw,
 802                         },
 803                         .num_parents = 1,
 804                         .name = "csiphy2_timer_clk",
 805                         .ops = &clk_branch_ops,
 806                         .flags = CLK_SET_RATE_PARENT,
 807                 },
 808         },
 809 };
 810
 811 static struct freq_tbl clk_tbl_gfx2d[] = {
 812         F_MN( 27000000, P_PXO,  1,  0),
 813         F_MN( 48000000, P_PLL8, 1,  8),
 814         F_MN( 54857000, P_PLL8, 1,  7),
 815         F_MN( 64000000, P_PLL8, 1,  6),
 816         F_MN( 76800000, P_PLL8, 1,  5),
 817         F_MN( 96000000, P_PLL8, 1,  4),
 818         F_MN(128000000, P_PLL8, 1,  3),
 819         F_MN(145455000, P_PLL2, 2, 11),
 820         F_MN(160000000, P_PLL2, 1,  5),
 821         F_MN(177778000, P_PLL2, 2,  9),
 822         F_MN(200000000, P_PLL2, 1,  4),
 823         F_MN(228571000, P_PLL2, 2,  7),
 824         { }
 825 };
 826
 827 static struct clk_dyn_rcg gfx2d0_src = {
 828         .ns_reg[0] = 0x0070,
 829         .ns_reg[1] = 0x0070,
 830         .md_reg[0] = 0x0064,
 831         .md_reg[1] = 0x0068,
 832         .bank_reg = 0x0060,
 833         .mn[0] = {
 834                 .mnctr_en_bit = 8,
 835                 .mnctr_reset_bit = 25,
 836                 .mnctr_mode_shift = 9,
 837                 .n_val_shift = 20,
 838                 .m_val_shift = 4,
 839                 .width = 4,
 840         },
 841         .mn[1] = {
 842                 .mnctr_en_bit = 5,
 843                 .mnctr_reset_bit = 24,
 844                 .mnctr_mode_shift = 6,
 845                 .n_val_shift = 16,
 846                 .m_val_shift = 4,
 847                 .width = 4,
 848         },
 849         .s[0] = {
 850                 .src_sel_shift = 3,
 851                 .parent_map = mmcc_pxo_pll8_pll2_map,
 852         },
 853         .s[1] = {
 854                 .src_sel_shift = 0,
 855                 .parent_map = mmcc_pxo_pll8_pll2_map,
 856         },
 857         .mux_sel_bit = 11,
 858         .freq_tbl = clk_tbl_gfx2d,
 859         .clkr = {
 860                 .enable_reg = 0x0060,
 861                 .enable_mask = BIT(2),
 862                 .hw.init = &(struct clk_init_data){
 863                         .name = "gfx2d0_src",
 864                         .parent_data = mmcc_pxo_pll8_pll2,
 865                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 866                         .ops = &clk_dyn_rcg_ops,
 867                 },
 868         },
 869 };
 870
 871 static struct clk_branch gfx2d0_clk = {
 872         .halt_reg = 0x01c8,
 873         .halt_bit = 9,
 874         .clkr = {
 875                 .enable_reg = 0x0060,
 876                 .enable_mask = BIT(0),
 877                 .hw.init = &(struct clk_init_data){
 878                         .name = "gfx2d0_clk",
 879                         .parent_hws = (const struct clk_hw*[]){
 880                                 &gfx2d0_src.clkr.hw
 881                         },
 882                         .num_parents = 1,
 883                         .ops = &clk_branch_ops,
 884                         .flags = CLK_SET_RATE_PARENT,
 885                 },
 886         },
 887 };
 888
 889 static struct clk_dyn_rcg gfx2d1_src = {
 890         .ns_reg[0] = 0x007c,
 891         .ns_reg[1] = 0x007c,
 892         .md_reg[0] = 0x0078,
 893         .md_reg[1] = 0x006c,
 894         .bank_reg = 0x0074,
 895         .mn[0] = {
 896                 .mnctr_en_bit = 8,
 897                 .mnctr_reset_bit = 25,
 898                 .mnctr_mode_shift = 9,
 899                 .n_val_shift = 20,
 900                 .m_val_shift = 4,
 901                 .width = 4,
 902         },
 903         .mn[1] = {
 904                 .mnctr_en_bit = 5,
 905                 .mnctr_reset_bit = 24,
 906                 .mnctr_mode_shift = 6,
 907                 .n_val_shift = 16,
 908                 .m_val_shift = 4,
 909                 .width = 4,
 910         },
 911         .s[0] = {
 912                 .src_sel_shift = 3,
 913                 .parent_map = mmcc_pxo_pll8_pll2_map,
 914         },
 915         .s[1] = {
 916                 .src_sel_shift = 0,
 917                 .parent_map = mmcc_pxo_pll8_pll2_map,
 918         },
 919         .mux_sel_bit = 11,
 920         .freq_tbl = clk_tbl_gfx2d,
 921         .clkr = {
 922                 .enable_reg = 0x0074,
 923                 .enable_mask = BIT(2),
 924                 .hw.init = &(struct clk_init_data){
 925                         .name = "gfx2d1_src",
 926                         .parent_data = mmcc_pxo_pll8_pll2,
 927                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 928                         .ops = &clk_dyn_rcg_ops,
 929                 },
 930         },
 931 };
 932
 933 static struct clk_branch gfx2d1_clk = {
 934         .halt_reg = 0x01c8,
 935         .halt_bit = 14,
 936         .clkr = {
 937                 .enable_reg = 0x0074,
 938                 .enable_mask = BIT(0),
 939                 .hw.init = &(struct clk_init_data){
 940                         .name = "gfx2d1_clk",
 941                         .parent_hws = (const struct clk_hw*[]){
 942                                 &gfx2d1_src.clkr.hw
 943                         },
 944                         .num_parents = 1,
 945                         .ops = &clk_branch_ops,
 946                         .flags = CLK_SET_RATE_PARENT,
 947                 },
 948         },
 949 };
 950
 951 static struct freq_tbl clk_tbl_gfx3d[] = {
 952         F_MN( 27000000, P_PXO,  1,  0),
 953         F_MN( 48000000, P_PLL8, 1,  8),
 954         F_MN( 54857000, P_PLL8, 1,  7),
 955         F_MN( 64000000, P_PLL8, 1,  6),
 956         F_MN( 76800000, P_PLL8, 1,  5),
 957         F_MN( 96000000, P_PLL8, 1,  4),
 958         F_MN(128000000, P_PLL8, 1,  3),
 959         F_MN(145455000, P_PLL2, 2, 11),
 960         F_MN(160000000, P_PLL2, 1,  5),
 961         F_MN(177778000, P_PLL2, 2,  9),
 962         F_MN(200000000, P_PLL2, 1,  4),
 963         F_MN(228571000, P_PLL2, 2,  7),
 964         F_MN(266667000, P_PLL2, 1,  3),
 965         F_MN(300000000, P_PLL3, 1,  4),
 966         F_MN(320000000, P_PLL2, 2,  5),
 967         F_MN(400000000, P_PLL2, 1,  2),
 968         { }
 969 };
 970
 971 static struct freq_tbl clk_tbl_gfx3d_8064[] = {
 972         F_MN( 27000000, P_PXO,   0,  0),
 973         F_MN( 48000000, P_PLL8,  1,  8),
 974         F_MN( 54857000, P_PLL8,  1,  7),
 975         F_MN( 64000000, P_PLL8,  1,  6),
 976         F_MN( 76800000, P_PLL8,  1,  5),
 977         F_MN( 96000000, P_PLL8,  1,  4),
 978         F_MN(128000000, P_PLL8,  1,  3),
 979         F_MN(145455000, P_PLL2,  2, 11),
 980         F_MN(160000000, P_PLL2,  1,  5),
 981         F_MN(177778000, P_PLL2,  2,  9),
 982         F_MN(192000000, P_PLL8,  1,  2),
 983         F_MN(200000000, P_PLL2,  1,  4),
 984         F_MN(228571000, P_PLL2,  2,  7),
 985         F_MN(266667000, P_PLL2,  1,  3),
 986         F_MN(320000000, P_PLL2,  2,  5),
 987         F_MN(400000000, P_PLL2,  1,  2),
 988         F_MN(450000000, P_PLL15, 1,  2),
 989         { }
 990 };
 991
 992 static struct clk_dyn_rcg gfx3d_src = {
 993         .ns_reg[0] = 0x008c,
 994         .ns_reg[1] = 0x008c,
 995         .md_reg[0] = 0x0084,
 996         .md_reg[1] = 0x0088,
 997         .bank_reg = 0x0080,
 998         .mn[0] = {
 999                 .mnctr_en_bit = 8,
1000                 .mnctr_reset_bit = 25,
1001                 .mnctr_mode_shift = 9,
1002                 .n_val_shift = 18,
1003                 .m_val_shift = 4,
1004                 .width = 4,
1005         },
1006         .mn[1] = {
1007                 .mnctr_en_bit = 5,
1008                 .mnctr_reset_bit = 24,
1009                 .mnctr_mode_shift = 6,
1010                 .n_val_shift = 14,
1011                 .m_val_shift = 4,
1012                 .width = 4,
1013         },
1014         .s[0] = {
1015                 .src_sel_shift = 3,
1016                 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
1017         },
1018         .s[1] = {
1019                 .src_sel_shift = 0,
1020                 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
1021         },
1022         .mux_sel_bit = 11,
1023         .freq_tbl = clk_tbl_gfx3d,
1024         .clkr = {
1025                 .enable_reg = 0x0080,
1026                 .enable_mask = BIT(2),
1027                 .hw.init = &(struct clk_init_data){
1028                         .name = "gfx3d_src",
1029                         .parent_data = mmcc_pxo_pll8_pll2_pll3,
1030                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll3),
1031                         .ops = &clk_dyn_rcg_ops,
1032                 },
1033         },
1034 };
1035
1036 static const struct clk_init_data gfx3d_8064_init = {
1037         .name = "gfx3d_src",
1038         .parent_data = mmcc_pxo_pll8_pll2_pll15,
1039         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll15),
1040         .ops = &clk_dyn_rcg_ops,
1041 };
1042
1043 static struct clk_branch gfx3d_clk = {
1044         .halt_reg = 0x01c8,
1045         .halt_bit = 4,
1046         .clkr = {
1047                 .enable_reg = 0x0080,
1048                 .enable_mask = BIT(0),
1049                 .hw.init = &(struct clk_init_data){
1050                         .name = "gfx3d_clk",
1051                         .parent_hws = (const struct clk_hw*[]){
1052                                 &gfx3d_src.clkr.hw
1053                         },
1054                         .num_parents = 1,
1055                         .ops = &clk_branch_ops,
1056                         .flags = CLK_SET_RATE_PARENT,
1057                 },
1058         },
1059 };
1060
1061 static struct freq_tbl clk_tbl_vcap[] = {
1062         F_MN( 27000000, P_PXO,  0,  0),
1063         F_MN( 54860000, P_PLL8, 1,  7),
1064         F_MN( 64000000, P_PLL8, 1,  6),
1065         F_MN( 76800000, P_PLL8, 1,  5),
1066         F_MN(128000000, P_PLL8, 1,  3),
1067         F_MN(160000000, P_PLL2, 1,  5),
1068         F_MN(200000000, P_PLL2, 1,  4),
1069         { }
1070 };
1071
1072 static struct clk_dyn_rcg vcap_src = {
1073         .ns_reg[0] = 0x021c,
1074         .ns_reg[1] = 0x021c,
1075         .md_reg[0] = 0x01ec,
1076         .md_reg[1] = 0x0218,
1077         .bank_reg = 0x0178,
1078         .mn[0] = {
1079                 .mnctr_en_bit = 8,
1080                 .mnctr_reset_bit = 23,
1081                 .mnctr_mode_shift = 9,
1082                 .n_val_shift = 18,
1083                 .m_val_shift = 4,
1084                 .width = 4,
1085         },
1086         .mn[1] = {
1087                 .mnctr_en_bit = 5,
1088                 .mnctr_reset_bit = 22,
1089                 .mnctr_mode_shift = 6,
1090                 .n_val_shift = 14,
1091                 .m_val_shift = 4,
1092                 .width = 4,
1093         },
1094         .s[0] = {
1095                 .src_sel_shift = 3,
1096                 .parent_map = mmcc_pxo_pll8_pll2_map,
1097         },
1098         .s[1] = {
1099                 .src_sel_shift = 0,
1100                 .parent_map = mmcc_pxo_pll8_pll2_map,
1101         },
1102         .mux_sel_bit = 11,
1103         .freq_tbl = clk_tbl_vcap,
1104         .clkr = {
1105                 .enable_reg = 0x0178,
1106                 .enable_mask = BIT(2),
1107                 .hw.init = &(struct clk_init_data){
1108                         .name = "vcap_src",
1109                         .parent_data = mmcc_pxo_pll8_pll2,
1110                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1111                         .ops = &clk_dyn_rcg_ops,
1112                 },
1113         },
1114 };
1115
1116 static struct clk_branch vcap_clk = {
1117         .halt_reg = 0x0240,
1118         .halt_bit = 15,
1119         .clkr = {
1120                 .enable_reg = 0x0178,
1121                 .enable_mask = BIT(0),
1122                 .hw.init = &(struct clk_init_data){
1123                         .name = "vcap_clk",
1124                         .parent_hws = (const struct clk_hw*[]){
1125                                 &vcap_src.clkr.hw
1126                         },
1127                         .num_parents = 1,
1128                         .ops = &clk_branch_ops,
1129                         .flags = CLK_SET_RATE_PARENT,
1130                 },
1131         },
1132 };
1133
1134 static struct clk_branch vcap_npl_clk = {
1135         .halt_reg = 0x0240,
1136         .halt_bit = 25,
1137         .clkr = {
1138                 .enable_reg = 0x0178,
1139                 .enable_mask = BIT(13),
1140                 .hw.init = &(struct clk_init_data){
1141                         .name = "vcap_npl_clk",
1142                         .parent_hws = (const struct clk_hw*[]){
1143                                 &vcap_src.clkr.hw
1144                         },
1145                         .num_parents = 1,
1146                         .ops = &clk_branch_ops,
1147                         .flags = CLK_SET_RATE_PARENT,
1148                 },
1149         },
1150 };
1151
1152 static struct freq_tbl clk_tbl_ijpeg[] = {
1153         {  27000000, P_PXO,  1, 0,  0 },
1154         {  36570000, P_PLL8, 1, 2, 21 },
1155         {  54860000, P_PLL8, 7, 0,  0 },
1156         {  96000000, P_PLL8, 4, 0,  0 },
1157         { 109710000, P_PLL8, 1, 2,  7 },
1158         { 128000000, P_PLL8, 3, 0,  0 },
1159         { 153600000, P_PLL8, 1, 2,  5 },
1160         { 200000000, P_PLL2, 4, 0,  0 },
1161         { 228571000, P_PLL2, 1, 2,  7 },
1162         { 266667000, P_PLL2, 1, 1,  3 },
1163         { 320000000, P_PLL2, 1, 2,  5 },
1164         { }
1165 };
1166
1167 static struct clk_rcg ijpeg_src = {
1168         .ns_reg = 0x00a0,
1169         .md_reg = 0x009c,
1170         .mn = {
1171                 .mnctr_en_bit = 5,
1172                 .mnctr_reset_bit = 7,
1173                 .mnctr_mode_shift = 6,
1174                 .n_val_shift = 16,
1175                 .m_val_shift = 8,
1176                 .width = 8,
1177         },
1178         .p = {
1179                 .pre_div_shift = 12,
1180                 .pre_div_width = 2,
1181         },
1182         .s = {
1183                 .src_sel_shift = 0,
1184                 .parent_map = mmcc_pxo_pll8_pll2_map,
1185         },
1186         .freq_tbl = clk_tbl_ijpeg,
1187         .clkr = {
1188                 .enable_reg = 0x0098,
1189                 .enable_mask = BIT(2),
1190                 .hw.init = &(struct clk_init_data){
1191                         .name = "ijpeg_src",
1192                         .parent_data = mmcc_pxo_pll8_pll2,
1193                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1194                         .ops = &clk_rcg_ops,
1195                 },
1196         },
1197 };
1198
1199 static struct clk_branch ijpeg_clk = {
1200         .halt_reg = 0x01c8,
1201         .halt_bit = 24,
1202         .clkr = {
1203                 .enable_reg = 0x0098,
1204                 .enable_mask = BIT(0),
1205                 .hw.init = &(struct clk_init_data){
1206                         .name = "ijpeg_clk",
1207                         .parent_hws = (const struct clk_hw*[]){
1208                                 &ijpeg_src.clkr.hw
1209                         },
1210                         .num_parents = 1,
1211                         .ops = &clk_branch_ops,
1212                         .flags = CLK_SET_RATE_PARENT,
1213                 },
1214         },
1215 };
1216
1217 static struct freq_tbl clk_tbl_jpegd[] = {
1218         {  64000000, P_PLL8, 6 },
1219         {  76800000, P_PLL8, 5 },
1220         {  96000000, P_PLL8, 4 },
1221         { 160000000, P_PLL2, 5 },
1222         { 200000000, P_PLL2, 4 },
1223         { }
1224 };
1225
1226 static struct clk_rcg jpegd_src = {
1227         .ns_reg = 0x00ac,
1228         .p = {
1229                 .pre_div_shift = 12,
1230                 .pre_div_width = 4,
1231         },
1232         .s = {
1233                 .src_sel_shift = 0,
1234                 .parent_map = mmcc_pxo_pll8_pll2_map,
1235         },
1236         .freq_tbl = clk_tbl_jpegd,
1237         .clkr = {
1238                 .enable_reg = 0x00a4,
1239                 .enable_mask = BIT(2),
1240                 .hw.init = &(struct clk_init_data){
1241                         .name = "jpegd_src",
1242                         .parent_data = mmcc_pxo_pll8_pll2,
1243                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1244                         .ops = &clk_rcg_ops,
1245                 },
1246         },
1247 };
1248
1249 static struct clk_branch jpegd_clk = {
1250         .halt_reg = 0x01c8,
1251         .halt_bit = 19,
1252         .clkr = {
1253                 .enable_reg = 0x00a4,
1254                 .enable_mask = BIT(0),
1255                 .hw.init = &(struct clk_init_data){
1256                         .name = "jpegd_clk",
1257                         .parent_hws = (const struct clk_hw*[]){
1258                                 &jpegd_src.clkr.hw
1259                         },
1260                         .num_parents = 1,
1261                         .ops = &clk_branch_ops,
1262                         .flags = CLK_SET_RATE_PARENT,
1263                 },
1264         },
1265 };
1266
1267 static struct freq_tbl clk_tbl_mdp[] = {
1268         {   9600000, P_PLL8, 1, 1, 40 },
1269         {  13710000, P_PLL8, 1, 1, 28 },
1270         {  27000000, P_PXO,  1, 0,  0 },
1271         {  29540000, P_PLL8, 1, 1, 13 },
1272         {  34910000, P_PLL8, 1, 1, 11 },
1273         {  38400000, P_PLL8, 1, 1, 10 },
1274         {  59080000, P_PLL8, 1, 2, 13 },
1275         {  76800000, P_PLL8, 1, 1,  5 },
1276         {  85330000, P_PLL8, 1, 2,  9 },
1277         {  96000000, P_PLL8, 1, 1,  4 },
1278         { 128000000, P_PLL8, 1, 1,  3 },
1279         { 160000000, P_PLL2, 1, 1,  5 },
1280         { 177780000, P_PLL2, 1, 2,  9 },
1281         { 200000000, P_PLL2, 1, 1,  4 },
1282         { 228571000, P_PLL2, 1, 2,  7 },
1283         { 266667000, P_PLL2, 1, 1,  3 },
1284         { }
1285 };
1286
1287 static struct clk_dyn_rcg mdp_src = {
1288         .ns_reg[0] = 0x00d0,
1289         .ns_reg[1] = 0x00d0,
1290         .md_reg[0] = 0x00c4,
1291         .md_reg[1] = 0x00c8,
1292         .bank_reg = 0x00c0,
1293         .mn[0] = {
1294                 .mnctr_en_bit = 8,
1295                 .mnctr_reset_bit = 31,
1296                 .mnctr_mode_shift = 9,
1297                 .n_val_shift = 22,
1298                 .m_val_shift = 8,
1299                 .width = 8,
1300         },
1301         .mn[1] = {
1302                 .mnctr_en_bit = 5,
1303                 .mnctr_reset_bit = 30,
1304                 .mnctr_mode_shift = 6,
1305                 .n_val_shift = 14,
1306                 .m_val_shift = 8,
1307                 .width = 8,
1308         },
1309         .s[0] = {
1310                 .src_sel_shift = 3,
1311                 .parent_map = mmcc_pxo_pll8_pll2_map,
1312         },
1313         .s[1] = {
1314                 .src_sel_shift = 0,
1315                 .parent_map = mmcc_pxo_pll8_pll2_map,
1316         },
1317         .mux_sel_bit = 11,
1318         .freq_tbl = clk_tbl_mdp,
1319         .clkr = {
1320                 .enable_reg = 0x00c0,
1321                 .enable_mask = BIT(2),
1322                 .hw.init = &(struct clk_init_data){
1323                         .name = "mdp_src",
1324                         .parent_data = mmcc_pxo_pll8_pll2,
1325                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1326                         .ops = &clk_dyn_rcg_ops,
1327                 },
1328         },
1329 };
1330
1331 static struct clk_branch mdp_clk = {
1332         .halt_reg = 0x01d0,
1333         .halt_bit = 10,
1334         .clkr = {
1335                 .enable_reg = 0x00c0,
1336                 .enable_mask = BIT(0),
1337                 .hw.init = &(struct clk_init_data){
1338                         .name = "mdp_clk",
1339                         .parent_hws = (const struct clk_hw*[]){
1340                                 &mdp_src.clkr.hw
1341                         },
1342                         .num_parents = 1,
1343                         .ops = &clk_branch_ops,
1344                         .flags = CLK_SET_RATE_PARENT,
1345                 },
1346         },
1347 };
1348
1349 static struct clk_branch mdp_lut_clk = {
1350         .halt_reg = 0x01e8,
1351         .halt_bit = 13,
1352         .clkr = {
1353                 .enable_reg = 0x016c,
1354                 .enable_mask = BIT(0),
1355                 .hw.init = &(struct clk_init_data){
1356                         .parent_hws = (const struct clk_hw*[]){
1357                                 &mdp_src.clkr.hw
1358                         },
1359                         .num_parents = 1,
1360                         .name = "mdp_lut_clk",
1361                         .ops = &clk_branch_ops,
1362                         .flags = CLK_SET_RATE_PARENT,
1363                 },
1364         },
1365 };
1366
1367 static struct clk_branch mdp_vsync_clk = {
1368         .halt_reg = 0x01cc,
1369         .halt_bit = 22,
1370         .clkr = {
1371                 .enable_reg = 0x0058,
1372                 .enable_mask = BIT(6),
1373                 .hw.init = &(struct clk_init_data){
1374                         .name = "mdp_vsync_clk",
1375                         .parent_data = (const struct clk_parent_data[]){
1376                                 { .fw_name = "pxo", .name = "pxo_board" },
1377                         },
1378                         .num_parents = 1,
1379                         .ops = &clk_branch_ops
1380                 },
1381         },
1382 };
1383
1384 static struct freq_tbl clk_tbl_rot[] = {
1385         {  27000000, P_PXO,   1 },
1386         {  29540000, P_PLL8, 13 },
1387         {  32000000, P_PLL8, 12 },
1388         {  38400000, P_PLL8, 10 },
1389         {  48000000, P_PLL8,  8 },
1390         {  54860000, P_PLL8,  7 },
1391         {  64000000, P_PLL8,  6 },
1392         {  76800000, P_PLL8,  5 },
1393         {  96000000, P_PLL8,  4 },
1394         { 100000000, P_PLL2,  8 },
1395         { 114290000, P_PLL2,  7 },
1396         { 133330000, P_PLL2,  6 },
1397         { 160000000, P_PLL2,  5 },
1398         { 200000000, P_PLL2,  4 },
1399         { }
1400 };
1401
1402 static struct clk_dyn_rcg rot_src = {
1403         .ns_reg[0] = 0x00e8,
1404         .ns_reg[1] = 0x00e8,
1405         .bank_reg = 0x00e8,
1406         .p[0] = {
1407                 .pre_div_shift = 22,
1408                 .pre_div_width = 4,
1409         },
1410         .p[1] = {
1411                 .pre_div_shift = 26,
1412                 .pre_div_width = 4,
1413         },
1414         .s[0] = {
1415                 .src_sel_shift = 16,
1416                 .parent_map = mmcc_pxo_pll8_pll2_map,
1417         },
1418         .s[1] = {
1419                 .src_sel_shift = 19,
1420                 .parent_map = mmcc_pxo_pll8_pll2_map,
1421         },
1422         .mux_sel_bit = 30,
1423         .freq_tbl = clk_tbl_rot,
1424         .clkr = {
1425                 .enable_reg = 0x00e0,
1426                 .enable_mask = BIT(2),
1427                 .hw.init = &(struct clk_init_data){
1428                         .name = "rot_src",
1429                         .parent_data = mmcc_pxo_pll8_pll2,
1430                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1431                         .ops = &clk_dyn_rcg_ops,
1432                 },
1433         },
1434 };
1435
1436 static struct clk_branch rot_clk = {
1437         .halt_reg = 0x01d0,
1438         .halt_bit = 15,
1439         .clkr = {
1440                 .enable_reg = 0x00e0,
1441                 .enable_mask = BIT(0),
1442                 .hw.init = &(struct clk_init_data){
1443                         .name = "rot_clk",
1444                         .parent_hws = (const struct clk_hw*[]){
1445                                 &rot_src.clkr.hw
1446                         },
1447                         .num_parents = 1,
1448                         .ops = &clk_branch_ops,
1449                         .flags = CLK_SET_RATE_PARENT,
1450                 },
1451         },
1452 };
1453
1454 static const struct parent_map mmcc_pxo_hdmi_map[] = {
1455         { P_PXO, 0 },
1456         { P_HDMI_PLL, 3 }
1457 };
1458
1459 static const struct clk_parent_data mmcc_pxo_hdmi[] = {
1460         { .fw_name = "pxo", .name = "pxo_board" },
1461         { .fw_name = "hdmipll", .name = "hdmi_pll" },
1462 };
1463
1464 static struct freq_tbl clk_tbl_tv[] = {
1465         {  .src = P_HDMI_PLL, .pre_div = 1 },
1466         { }
1467 };
1468
1469 static struct clk_rcg tv_src = {
1470         .ns_reg = 0x00f4,
1471         .md_reg = 0x00f0,
1472         .mn = {
1473                 .mnctr_en_bit = 5,
1474                 .mnctr_reset_bit = 7,
1475                 .mnctr_mode_shift = 6,
1476                 .n_val_shift = 16,
1477                 .m_val_shift = 8,
1478                 .width = 8,
1479         },
1480         .p = {
1481                 .pre_div_shift = 14,
1482                 .pre_div_width = 2,
1483         },
1484         .s = {
1485                 .src_sel_shift = 0,
1486                 .parent_map = mmcc_pxo_hdmi_map,
1487         },
1488         .freq_tbl = clk_tbl_tv,
1489         .clkr = {
1490                 .enable_reg = 0x00ec,
1491                 .enable_mask = BIT(2),
1492                 .hw.init = &(struct clk_init_data){
1493                         .name = "tv_src",
1494                         .parent_data = mmcc_pxo_hdmi,
1495                         .num_parents = ARRAY_SIZE(mmcc_pxo_hdmi),
1496                         .ops = &clk_rcg_bypass_ops,
1497                         .flags = CLK_SET_RATE_PARENT,
1498                 },
1499         },
1500 };
1501
1502 static struct clk_branch tv_enc_clk = {
1503         .halt_reg = 0x01d4,
1504         .halt_bit = 9,
1505         .clkr = {
1506                 .enable_reg = 0x00ec,
1507                 .enable_mask = BIT(8),
1508                 .hw.init = &(struct clk_init_data){
1509                         .parent_hws = (const struct clk_hw*[]){
1510                                 &tv_src.clkr.hw,
1511                         },
1512                         .num_parents = 1,
1513                         .name = "tv_enc_clk",
1514                         .ops = &clk_branch_ops,
1515                         .flags = CLK_SET_RATE_PARENT,
1516                 },
1517         },
1518 };
1519
1520 static struct clk_branch tv_dac_clk = {
1521         .halt_reg = 0x01d4,
1522         .halt_bit = 10,
1523         .clkr = {
1524                 .enable_reg = 0x00ec,
1525                 .enable_mask = BIT(10),
1526                 .hw.init = &(struct clk_init_data){
1527                         .parent_hws = (const struct clk_hw*[]){
1528                                 &tv_src.clkr.hw,
1529                         },
1530                         .num_parents = 1,
1531                         .name = "tv_dac_clk",
1532                         .ops = &clk_branch_ops,
1533                         .flags = CLK_SET_RATE_PARENT,
1534                 },
1535         },
1536 };
1537
1538 static struct clk_branch mdp_tv_clk = {
1539         .halt_reg = 0x01d4,
1540         .halt_bit = 12,
1541         .clkr = {
1542                 .enable_reg = 0x00ec,
1543                 .enable_mask = BIT(0),
1544                 .hw.init = &(struct clk_init_data){
1545                         .parent_hws = (const struct clk_hw*[]){
1546                                 &tv_src.clkr.hw,
1547                         },
1548                         .num_parents = 1,
1549                         .name = "mdp_tv_clk",
1550                         .ops = &clk_branch_ops,
1551                         .flags = CLK_SET_RATE_PARENT,
1552                 },
1553         },
1554 };
1555
1556 static struct clk_branch hdmi_tv_clk = {
1557         .halt_reg = 0x01d4,
1558         .halt_bit = 11,
1559         .clkr = {
1560                 .enable_reg = 0x00ec,
1561                 .enable_mask = BIT(12),
1562                 .hw.init = &(struct clk_init_data){
1563                         .parent_hws = (const struct clk_hw*[]){
1564                                 &tv_src.clkr.hw,
1565                         },
1566                         .num_parents = 1,
1567                         .name = "hdmi_tv_clk",
1568                         .ops = &clk_branch_ops,
1569                         .flags = CLK_SET_RATE_PARENT,
1570                 },
1571         },
1572 };
1573
1574 static struct clk_branch rgb_tv_clk = {
1575         .halt_reg = 0x0240,
1576         .halt_bit = 27,
1577         .clkr = {
1578                 .enable_reg = 0x0124,
1579                 .enable_mask = BIT(14),
1580                 .hw.init = &(struct clk_init_data){
1581                         .parent_hws = (const struct clk_hw*[]){
1582                                 &tv_src.clkr.hw,
1583                         },
1584                         .num_parents = 1,
1585                         .name = "rgb_tv_clk",
1586                         .ops = &clk_branch_ops,
1587                         .flags = CLK_SET_RATE_PARENT,
1588                 },
1589         },
1590 };
1591
1592 static struct clk_branch npl_tv_clk = {
1593         .halt_reg = 0x0240,
1594         .halt_bit = 26,
1595         .clkr = {
1596                 .enable_reg = 0x0124,
1597                 .enable_mask = BIT(16),
1598                 .hw.init = &(struct clk_init_data){
1599                         .parent_hws = (const struct clk_hw*[]){
1600                                 &tv_src.clkr.hw,
1601                         },
1602                         .num_parents = 1,
1603                         .name = "npl_tv_clk",
1604                         .ops = &clk_branch_ops,
1605                         .flags = CLK_SET_RATE_PARENT,
1606                 },
1607         },
1608 };
1609
1610 static struct clk_branch hdmi_app_clk = {
1611         .halt_reg = 0x01cc,
1612         .halt_bit = 25,
1613         .clkr = {
1614                 .enable_reg = 0x005c,
1615                 .enable_mask = BIT(11),
1616                 .hw.init = &(struct clk_init_data){
1617                         .parent_data = (const struct clk_parent_data[]){
1618                                 { .fw_name = "pxo", .name = "pxo_board" },
1619                         },
1620                         .num_parents = 1,
1621                         .name = "hdmi_app_clk",
1622                         .ops = &clk_branch_ops,
1623                 },
1624         },
1625 };
1626
1627 static struct freq_tbl clk_tbl_vcodec[] = {
1628         F_MN( 27000000, P_PXO,  1,  0),
1629         F_MN( 32000000, P_PLL8, 1, 12),
1630         F_MN( 48000000, P_PLL8, 1,  8),
1631         F_MN( 54860000, P_PLL8, 1,  7),
1632         F_MN( 96000000, P_PLL8, 1,  4),
1633         F_MN(133330000, P_PLL2, 1,  6),
1634         F_MN(200000000, P_PLL2, 1,  4),
1635         F_MN(228570000, P_PLL2, 2,  7),
1636         F_MN(266670000, P_PLL2, 1,  3),
1637         { }
1638 };
1639
1640 static struct clk_dyn_rcg vcodec_src = {
1641         .ns_reg[0] = 0x0100,
1642         .ns_reg[1] = 0x0100,
1643         .md_reg[0] = 0x00fc,
1644         .md_reg[1] = 0x0128,
1645         .bank_reg = 0x00f8,
1646         .mn[0] = {
1647                 .mnctr_en_bit = 5,
1648                 .mnctr_reset_bit = 31,
1649                 .mnctr_mode_shift = 6,
1650                 .n_val_shift = 11,
1651                 .m_val_shift = 8,
1652                 .width = 8,
1653         },
1654         .mn[1] = {
1655                 .mnctr_en_bit = 10,
1656                 .mnctr_reset_bit = 30,
1657                 .mnctr_mode_shift = 11,
1658                 .n_val_shift = 19,
1659                 .m_val_shift = 8,
1660                 .width = 8,
1661         },
1662         .s[0] = {
1663                 .src_sel_shift = 27,
1664                 .parent_map = mmcc_pxo_pll8_pll2_map,
1665         },
1666         .s[1] = {
1667                 .src_sel_shift = 0,
1668                 .parent_map = mmcc_pxo_pll8_pll2_map,
1669         },
1670         .mux_sel_bit = 13,
1671         .freq_tbl = clk_tbl_vcodec,
1672         .clkr = {
1673                 .enable_reg = 0x00f8,
1674                 .enable_mask = BIT(2),
1675                 .hw.init = &(struct clk_init_data){
1676                         .name = "vcodec_src",
1677                         .parent_data = mmcc_pxo_pll8_pll2,
1678                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1679                         .ops = &clk_dyn_rcg_ops,
1680                 },
1681         },
1682 };
1683
1684 static struct clk_branch vcodec_clk = {
1685         .halt_reg = 0x01d0,
1686         .halt_bit = 29,
1687         .clkr = {
1688                 .enable_reg = 0x00f8,
1689                 .enable_mask = BIT(0),
1690                 .hw.init = &(struct clk_init_data){
1691                         .name = "vcodec_clk",
1692                         .parent_hws = (const struct clk_hw*[]){
1693                                 &vcodec_src.clkr.hw
1694                         },
1695                         .num_parents = 1,
1696                         .ops = &clk_branch_ops,
1697                         .flags = CLK_SET_RATE_PARENT,
1698                 },
1699         },
1700 };
1701
1702 static struct freq_tbl clk_tbl_vpe[] = {
1703         {  27000000, P_PXO,   1 },
1704         {  34909000, P_PLL8, 11 },
1705         {  38400000, P_PLL8, 10 },
1706         {  64000000, P_PLL8,  6 },
1707         {  76800000, P_PLL8,  5 },
1708         {  96000000, P_PLL8,  4 },
1709         { 100000000, P_PLL2,  8 },
1710         { 160000000, P_PLL2,  5 },
1711         { }
1712 };
1713
1714 static struct clk_rcg vpe_src = {
1715         .ns_reg = 0x0118,
1716         .p = {
1717                 .pre_div_shift = 12,
1718                 .pre_div_width = 4,
1719         },
1720         .s = {
1721                 .src_sel_shift = 0,
1722                 .parent_map = mmcc_pxo_pll8_pll2_map,
1723         },
1724         .freq_tbl = clk_tbl_vpe,
1725         .clkr = {
1726                 .enable_reg = 0x0110,
1727                 .enable_mask = BIT(2),
1728                 .hw.init = &(struct clk_init_data){
1729                         .name = "vpe_src",
1730                         .parent_data = mmcc_pxo_pll8_pll2,
1731                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1732                         .ops = &clk_rcg_ops,
1733                 },
1734         },
1735 };
1736
1737 static struct clk_branch vpe_clk = {
1738         .halt_reg = 0x01c8,
1739         .halt_bit = 28,
1740         .clkr = {
1741                 .enable_reg = 0x0110,
1742                 .enable_mask = BIT(0),
1743                 .hw.init = &(struct clk_init_data){
1744                         .name = "vpe_clk",
1745                         .parent_hws = (const struct clk_hw*[]){
1746                                 &vpe_src.clkr.hw
1747                         },
1748                         .num_parents = 1,
1749                         .ops = &clk_branch_ops,
1750                         .flags = CLK_SET_RATE_PARENT,
1751                 },
1752         },
1753 };
1754
1755 static struct freq_tbl clk_tbl_vfe[] = {
1756         {  13960000, P_PLL8,  1, 2, 55 },
1757         {  27000000, P_PXO,   1, 0,  0 },
1758         {  36570000, P_PLL8,  1, 2, 21 },
1759         {  38400000, P_PLL8,  2, 1,  5 },
1760         {  45180000, P_PLL8,  1, 2, 17 },
1761         {  48000000, P_PLL8,  2, 1,  4 },
1762         {  54860000, P_PLL8,  1, 1,  7 },
1763         {  64000000, P_PLL8,  2, 1,  3 },
1764         {  76800000, P_PLL8,  1, 1,  5 },
1765         {  96000000, P_PLL8,  2, 1,  2 },
1766         { 109710000, P_PLL8,  1, 2,  7 },
1767         { 128000000, P_PLL8,  1, 1,  3 },
1768         { 153600000, P_PLL8,  1, 2,  5 },
1769         { 200000000, P_PLL2,  2, 1,  2 },
1770         { 228570000, P_PLL2,  1, 2,  7 },
1771         { 266667000, P_PLL2,  1, 1,  3 },
1772         { 320000000, P_PLL2,  1, 2,  5 },
1773         { }
1774 };
1775
1776 static struct clk_rcg vfe_src = {
1777         .ns_reg = 0x0108,
1778         .mn = {
1779                 .mnctr_en_bit = 5,
1780                 .mnctr_reset_bit = 7,
1781                 .mnctr_mode_shift = 6,
1782                 .n_val_shift = 16,
1783                 .m_val_shift = 8,
1784                 .width = 8,
1785         },
1786         .p = {
1787                 .pre_div_shift = 10,
1788                 .pre_div_width = 1,
1789         },
1790         .s = {
1791                 .src_sel_shift = 0,
1792                 .parent_map = mmcc_pxo_pll8_pll2_map,
1793         },
1794         .freq_tbl = clk_tbl_vfe,
1795         .clkr = {
1796                 .enable_reg = 0x0104,
1797                 .enable_mask = BIT(2),
1798                 .hw.init = &(struct clk_init_data){
1799                         .name = "vfe_src",
1800                         .parent_data = mmcc_pxo_pll8_pll2,
1801                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1802                         .ops = &clk_rcg_ops,
1803                 },
1804         },
1805 };
1806
1807 static struct clk_branch vfe_clk = {
1808         .halt_reg = 0x01cc,
1809         .halt_bit = 6,
1810         .clkr = {
1811                 .enable_reg = 0x0104,
1812                 .enable_mask = BIT(0),
1813                 .hw.init = &(struct clk_init_data){
1814                         .name = "vfe_clk",
1815                         .parent_hws = (const struct clk_hw*[]){
1816                                 &vfe_src.clkr.hw
1817                         },
1818                         .num_parents = 1,
1819                         .ops = &clk_branch_ops,
1820                         .flags = CLK_SET_RATE_PARENT,
1821                 },
1822         },
1823 };
1824
1825 static struct clk_branch vfe_csi_clk = {
1826         .halt_reg = 0x01cc,
1827         .halt_bit = 8,
1828         .clkr = {
1829                 .enable_reg = 0x0104,
1830                 .enable_mask = BIT(12),
1831                 .hw.init = &(struct clk_init_data){
1832                         .parent_hws = (const struct clk_hw*[]){
1833                                 &vfe_src.clkr.hw
1834                         },
1835                         .num_parents = 1,
1836                         .name = "vfe_csi_clk",
1837                         .ops = &clk_branch_ops,
1838                         .flags = CLK_SET_RATE_PARENT,
1839                 },
1840         },
1841 };
1842
1843 static struct clk_branch gmem_axi_clk = {
1844         .halt_reg = 0x01d8,
1845         .halt_bit = 6,
1846         .clkr = {
1847                 .enable_reg = 0x0018,
1848                 .enable_mask = BIT(24),
1849                 .hw.init = &(struct clk_init_data){
1850                         .name = "gmem_axi_clk",
1851                         .ops = &clk_branch_ops,
1852                 },
1853         },
1854 };
1855
1856 static struct clk_branch ijpeg_axi_clk = {
1857         .hwcg_reg = 0x0018,
1858         .hwcg_bit = 11,
1859         .halt_reg = 0x01d8,
1860         .halt_bit = 4,
1861         .clkr = {
1862                 .enable_reg = 0x0018,
1863                 .enable_mask = BIT(21),
1864                 .hw.init = &(struct clk_init_data){
1865                         .name = "ijpeg_axi_clk",
1866                         .ops = &clk_branch_ops,
1867                 },
1868         },
1869 };
1870
1871 static struct clk_branch mmss_imem_axi_clk = {
1872         .hwcg_reg = 0x0018,
1873         .hwcg_bit = 15,
1874         .halt_reg = 0x01d8,
1875         .halt_bit = 7,
1876         .clkr = {
1877                 .enable_reg = 0x0018,
1878                 .enable_mask = BIT(22),
1879                 .hw.init = &(struct clk_init_data){
1880                         .name = "mmss_imem_axi_clk",
1881                         .ops = &clk_branch_ops,
1882                 },
1883         },
1884 };
1885
1886 static struct clk_branch jpegd_axi_clk = {
1887         .halt_reg = 0x01d8,
1888         .halt_bit = 5,
1889         .clkr = {
1890                 .enable_reg = 0x0018,
1891                 .enable_mask = BIT(25),
1892                 .hw.init = &(struct clk_init_data){
1893                         .name = "jpegd_axi_clk",
1894                         .ops = &clk_branch_ops,
1895                 },
1896         },
1897 };
1898
1899 static struct clk_branch vcodec_axi_b_clk = {
1900         .hwcg_reg = 0x0114,
1901         .hwcg_bit = 22,
1902         .halt_reg = 0x01e8,
1903         .halt_bit = 25,
1904         .clkr = {
1905                 .enable_reg = 0x0114,
1906                 .enable_mask = BIT(23),
1907                 .hw.init = &(struct clk_init_data){
1908                         .name = "vcodec_axi_b_clk",
1909                         .ops = &clk_branch_ops,
1910                 },
1911         },
1912 };
1913
1914 static struct clk_branch vcodec_axi_a_clk = {
1915         .hwcg_reg = 0x0114,
1916         .hwcg_bit = 24,
1917         .halt_reg = 0x01e8,
1918         .halt_bit = 26,
1919         .clkr = {
1920                 .enable_reg = 0x0114,
1921                 .enable_mask = BIT(25),
1922                 .hw.init = &(struct clk_init_data){
1923                         .name = "vcodec_axi_a_clk",
1924                         .ops = &clk_branch_ops,
1925                 },
1926         },
1927 };
1928
1929 static struct clk_branch vcodec_axi_clk = {
1930         .hwcg_reg = 0x0018,
1931         .hwcg_bit = 13,
1932         .halt_reg = 0x01d8,
1933         .halt_bit = 3,
1934         .clkr = {
1935                 .enable_reg = 0x0018,
1936                 .enable_mask = BIT(19),
1937                 .hw.init = &(struct clk_init_data){
1938                         .name = "vcodec_axi_clk",
1939                         .ops = &clk_branch_ops,
1940                 },
1941         },
1942 };
1943
1944 static struct clk_branch vfe_axi_clk = {
1945         .halt_reg = 0x01d8,
1946         .halt_bit = 0,
1947         .clkr = {
1948                 .enable_reg = 0x0018,
1949                 .enable_mask = BIT(18),
1950                 .hw.init = &(struct clk_init_data){
1951                         .name = "vfe_axi_clk",
1952                         .ops = &clk_branch_ops,
1953                 },
1954         },
1955 };
1956
1957 static struct clk_branch mdp_axi_clk = {
1958         .hwcg_reg = 0x0018,
1959         .hwcg_bit = 16,
1960         .halt_reg = 0x01d8,
1961         .halt_bit = 8,
1962         .clkr = {
1963                 .enable_reg = 0x0018,
1964                 .enable_mask = BIT(23),
1965                 .hw.init = &(struct clk_init_data){
1966                         .name = "mdp_axi_clk",
1967                         .ops = &clk_branch_ops,
1968                 },
1969         },
1970 };
1971
1972 static struct clk_branch rot_axi_clk = {
1973         .hwcg_reg = 0x0020,
1974         .hwcg_bit = 25,
1975         .halt_reg = 0x01d8,
1976         .halt_bit = 2,
1977         .clkr = {
1978                 .enable_reg = 0x0020,
1979                 .enable_mask = BIT(24),
1980                 .hw.init = &(struct clk_init_data){
1981                         .name = "rot_axi_clk",
1982                         .ops = &clk_branch_ops,
1983                 },
1984         },
1985 };
1986
1987 static struct clk_branch vcap_axi_clk = {
1988         .halt_reg = 0x0240,
1989         .halt_bit = 20,
1990         .hwcg_reg = 0x0244,
1991         .hwcg_bit = 11,
1992         .clkr = {
1993                 .enable_reg = 0x0244,
1994                 .enable_mask = BIT(12),
1995                 .hw.init = &(struct clk_init_data){
1996                         .name = "vcap_axi_clk",
1997                         .ops = &clk_branch_ops,
1998                 },
1999         },
2000 };
2001
2002 static struct clk_branch vpe_axi_clk = {
2003         .hwcg_reg = 0x0020,
2004         .hwcg_bit = 27,
2005         .halt_reg = 0x01d8,
2006         .halt_bit = 1,
2007         .clkr = {
2008                 .enable_reg = 0x0020,
2009                 .enable_mask = BIT(26),
2010                 .hw.init = &(struct clk_init_data){
2011                         .name = "vpe_axi_clk",
2012                         .ops = &clk_branch_ops,
2013                 },
2014         },
2015 };
2016
2017 static struct clk_branch gfx3d_axi_clk = {
2018         .hwcg_reg = 0x0244,
2019         .hwcg_bit = 24,
2020         .halt_reg = 0x0240,
2021         .halt_bit = 30,
2022         .clkr = {
2023                 .enable_reg = 0x0244,
2024                 .enable_mask = BIT(25),
2025                 .hw.init = &(struct clk_init_data){
2026                         .name = "gfx3d_axi_clk",
2027                         .ops = &clk_branch_ops,
2028                 },
2029         },
2030 };
2031
2032 static struct clk_branch amp_ahb_clk = {
2033         .halt_reg = 0x01dc,
2034         .halt_bit = 18,
2035         .clkr = {
2036                 .enable_reg = 0x0008,
2037                 .enable_mask = BIT(24),
2038                 .hw.init = &(struct clk_init_data){
2039                         .name = "amp_ahb_clk",
2040                         .ops = &clk_branch_ops,
2041                 },
2042         },
2043 };
2044
2045 static struct clk_branch csi_ahb_clk = {
2046         .halt_reg = 0x01dc,
2047         .halt_bit = 16,
2048         .clkr = {
2049                 .enable_reg = 0x0008,
2050                 .enable_mask = BIT(7),
2051                 .hw.init = &(struct clk_init_data){
2052                         .name = "csi_ahb_clk",
2053                         .ops = &clk_branch_ops,
2054                 },
2055         },
2056 };
2057
2058 static struct clk_branch dsi_m_ahb_clk = {
2059         .halt_reg = 0x01dc,
2060         .halt_bit = 19,
2061         .clkr = {
2062                 .enable_reg = 0x0008,
2063                 .enable_mask = BIT(9),
2064                 .hw.init = &(struct clk_init_data){
2065                         .name = "dsi_m_ahb_clk",
2066                         .ops = &clk_branch_ops,
2067                 },
2068         },
2069 };
2070
2071 static struct clk_branch dsi_s_ahb_clk = {
2072         .hwcg_reg = 0x0038,
2073         .hwcg_bit = 20,
2074         .halt_reg = 0x01dc,
2075         .halt_bit = 21,
2076         .clkr = {
2077                 .enable_reg = 0x0008,
2078                 .enable_mask = BIT(18),
2079                 .hw.init = &(struct clk_init_data){
2080                         .name = "dsi_s_ahb_clk",
2081                         .ops = &clk_branch_ops,
2082                 },
2083         },
2084 };
2085
2086 static struct clk_branch dsi2_m_ahb_clk = {
2087         .halt_reg = 0x01d8,
2088         .halt_bit = 18,
2089         .clkr = {
2090                 .enable_reg = 0x0008,
2091                 .enable_mask = BIT(17),
2092                 .hw.init = &(struct clk_init_data){
2093                         .name = "dsi2_m_ahb_clk",
2094                         .ops = &clk_branch_ops,
2095                 },
2096         },
2097 };
2098
2099 static struct clk_branch dsi2_s_ahb_clk = {
2100         .hwcg_reg = 0x0038,
2101         .hwcg_bit = 15,
2102         .halt_reg = 0x01dc,
2103         .halt_bit = 20,
2104         .clkr = {
2105                 .enable_reg = 0x0008,
2106                 .enable_mask = BIT(22),
2107                 .hw.init = &(struct clk_init_data){
2108                         .name = "dsi2_s_ahb_clk",
2109                         .ops = &clk_branch_ops,
2110                 },
2111         },
2112 };
2113
2114 static struct clk_rcg dsi1_src = {
2115         .ns_reg = 0x0054,
2116         .md_reg = 0x0050,
2117         .mn = {
2118                 .mnctr_en_bit = 5,
2119                 .mnctr_reset_bit = 7,
2120                 .mnctr_mode_shift = 6,
2121                 .n_val_shift = 24,
2122                 .m_val_shift = 8,
2123                 .width = 8,
2124         },
2125         .p = {
2126                 .pre_div_shift = 14,
2127                 .pre_div_width = 2,
2128         },
2129         .s = {
2130                 .src_sel_shift = 0,
2131                 .parent_map = mmcc_pxo_dsi2_dsi1_map,
2132         },
2133         .clkr = {
2134                 .enable_reg = 0x004c,
2135                 .enable_mask = BIT(2),
2136                 .hw.init = &(struct clk_init_data){
2137                         .name = "dsi1_src",
2138                         .parent_data = mmcc_pxo_dsi2_dsi1,
2139                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
2140                         .ops = &clk_rcg_bypass2_ops,
2141                         .flags = CLK_SET_RATE_PARENT,
2142                 },
2143         },
2144 };
2145
2146 static struct clk_branch dsi1_clk = {
2147         .halt_reg = 0x01d0,
2148         .halt_bit = 2,
2149         .clkr = {
2150                 .enable_reg = 0x004c,
2151                 .enable_mask = BIT(0),
2152                 .hw.init = &(struct clk_init_data){
2153                         .name = "dsi1_clk",
2154                         .parent_hws = (const struct clk_hw*[]){
2155                                 &dsi1_src.clkr.hw
2156                         },
2157                         .num_parents = 1,
2158                         .ops = &clk_branch_ops,
2159                         .flags = CLK_SET_RATE_PARENT,
2160                 },
2161         },
2162 };
2163
2164 static struct clk_rcg dsi2_src = {
2165         .ns_reg = 0x012c,
2166         .md_reg = 0x00a8,
2167         .mn = {
2168                 .mnctr_en_bit = 5,
2169                 .mnctr_reset_bit = 7,
2170                 .mnctr_mode_shift = 6,
2171                 .n_val_shift = 24,
2172                 .m_val_shift = 8,
2173                 .width = 8,
2174         },
2175         .p = {
2176                 .pre_div_shift = 14,
2177                 .pre_div_width = 2,
2178         },
2179         .s = {
2180                 .src_sel_shift = 0,
2181                 .parent_map = mmcc_pxo_dsi2_dsi1_map,
2182         },
2183         .clkr = {
2184                 .enable_reg = 0x003c,
2185                 .enable_mask = BIT(2),
2186                 .hw.init = &(struct clk_init_data){
2187                         .name = "dsi2_src",
2188                         .parent_data = mmcc_pxo_dsi2_dsi1,
2189                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
2190                         .ops = &clk_rcg_bypass2_ops,
2191                         .flags = CLK_SET_RATE_PARENT,
2192                 },
2193         },
2194 };
2195
2196 static struct clk_branch dsi2_clk = {
2197         .halt_reg = 0x01d0,
2198         .halt_bit = 20,
2199         .clkr = {
2200                 .enable_reg = 0x003c,
2201                 .enable_mask = BIT(0),
2202                 .hw.init = &(struct clk_init_data){
2203                         .name = "dsi2_clk",
2204                         .parent_hws = (const struct clk_hw*[]){
2205                                 &dsi2_src.clkr.hw
2206                         },
2207                         .num_parents = 1,
2208                         .ops = &clk_branch_ops,
2209                         .flags = CLK_SET_RATE_PARENT,
2210                 },
2211         },
2212 };
2213
2214 static struct clk_rcg dsi1_byte_src = {
2215         .ns_reg = 0x00b0,
2216         .p = {
2217                 .pre_div_shift = 12,
2218                 .pre_div_width = 4,
2219         },
2220         .s = {
2221                 .src_sel_shift = 0,
2222                 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2223         },
2224         .clkr = {
2225                 .enable_reg = 0x0090,
2226                 .enable_mask = BIT(2),
2227                 .hw.init = &(struct clk_init_data){
2228                         .name = "dsi1_byte_src",
2229                         .parent_data = mmcc_pxo_dsi1_dsi2_byte,
2230                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
2231                         .ops = &clk_rcg_bypass2_ops,
2232                         .flags = CLK_SET_RATE_PARENT,
2233                 },
2234         },
2235 };
2236
2237 static struct clk_branch dsi1_byte_clk = {
2238         .halt_reg = 0x01cc,
2239         .halt_bit = 21,
2240         .clkr = {
2241                 .enable_reg = 0x0090,
2242                 .enable_mask = BIT(0),
2243                 .hw.init = &(struct clk_init_data){
2244                         .name = "dsi1_byte_clk",
2245                         .parent_hws = (const struct clk_hw*[]){
2246                                 &dsi1_byte_src.clkr.hw
2247                         },
2248                         .num_parents = 1,
2249                         .ops = &clk_branch_ops,
2250                         .flags = CLK_SET_RATE_PARENT,
2251                 },
2252         },
2253 };
2254
2255 static struct clk_rcg dsi2_byte_src = {
2256         .ns_reg = 0x012c,
2257         .p = {
2258                 .pre_div_shift = 12,
2259                 .pre_div_width = 4,
2260         },
2261         .s = {
2262                 .src_sel_shift = 0,
2263                 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2264         },
2265         .clkr = {
2266                 .enable_reg = 0x0130,
2267                 .enable_mask = BIT(2),
2268                 .hw.init = &(struct clk_init_data){
2269                         .name = "dsi2_byte_src",
2270                         .parent_data = mmcc_pxo_dsi1_dsi2_byte,
2271                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
2272                         .ops = &clk_rcg_bypass2_ops,
2273                         .flags = CLK_SET_RATE_PARENT,
2274                 },
2275         },
2276 };
2277
2278 static struct clk_branch dsi2_byte_clk = {
2279         .halt_reg = 0x01cc,
2280         .halt_bit = 20,
2281         .clkr = {
2282                 .enable_reg = 0x00b4,
2283                 .enable_mask = BIT(0),
2284                 .hw.init = &(struct clk_init_data){
2285                         .name = "dsi2_byte_clk",
2286                         .parent_hws = (const struct clk_hw*[]){
2287                                 &dsi2_byte_src.clkr.hw
2288                         },
2289                         .num_parents = 1,
2290                         .ops = &clk_branch_ops,
2291                         .flags = CLK_SET_RATE_PARENT,
2292                 },
2293         },
2294 };
2295
2296 static struct clk_rcg dsi1_esc_src = {
2297         .ns_reg = 0x0011c,
2298         .p = {
2299                 .pre_div_shift = 12,
2300                 .pre_div_width = 4,
2301         },
2302         .s = {
2303                 .src_sel_shift = 0,
2304                 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2305         },
2306         .clkr = {
2307                 .enable_reg = 0x00cc,
2308                 .enable_mask = BIT(2),
2309                 .hw.init = &(struct clk_init_data){
2310                         .name = "dsi1_esc_src",
2311                         .parent_data = mmcc_pxo_dsi1_dsi2_byte,
2312                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
2313                         .ops = &clk_rcg_esc_ops,
2314                 },
2315         },
2316 };
2317
2318 static struct clk_branch dsi1_esc_clk = {
2319         .halt_reg = 0x01e8,
2320         .halt_bit = 1,
2321         .clkr = {
2322                 .enable_reg = 0x00cc,
2323                 .enable_mask = BIT(0),
2324                 .hw.init = &(struct clk_init_data){
2325                         .name = "dsi1_esc_clk",
2326                         .parent_hws = (const struct clk_hw*[]){
2327                                 &dsi1_esc_src.clkr.hw
2328                         },
2329                         .num_parents = 1,
2330                         .ops = &clk_branch_ops,
2331                         .flags = CLK_SET_RATE_PARENT,
2332                 },
2333         },
2334 };
2335
2336 static struct clk_rcg dsi2_esc_src = {
2337         .ns_reg = 0x0150,
2338         .p = {
2339                 .pre_div_shift = 12,
2340                 .pre_div_width = 4,
2341         },
2342         .s = {
2343                 .src_sel_shift = 0,
2344                 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2345         },
2346         .clkr = {
2347                 .enable_reg = 0x013c,
2348                 .enable_mask = BIT(2),
2349                 .hw.init = &(struct clk_init_data){
2350                         .name = "dsi2_esc_src",
2351                         .parent_data = mmcc_pxo_dsi1_dsi2_byte,
2352                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
2353                         .ops = &clk_rcg_esc_ops,
2354                 },
2355         },
2356 };
2357
2358 static struct clk_branch dsi2_esc_clk = {
2359         .halt_reg = 0x01e8,
2360         .halt_bit = 3,
2361         .clkr = {
2362                 .enable_reg = 0x013c,
2363                 .enable_mask = BIT(0),
2364                 .hw.init = &(struct clk_init_data){
2365                         .name = "dsi2_esc_clk",
2366                         .parent_hws = (const struct clk_hw*[]){
2367                                 &dsi2_esc_src.clkr.hw
2368                         },
2369                         .num_parents = 1,
2370                         .ops = &clk_branch_ops,
2371                         .flags = CLK_SET_RATE_PARENT,
2372                 },
2373         },
2374 };
2375
2376 static struct clk_rcg dsi1_pixel_src = {
2377         .ns_reg = 0x0138,
2378         .md_reg = 0x0134,
2379         .mn = {
2380                 .mnctr_en_bit = 5,
2381                 .mnctr_reset_bit = 7,
2382                 .mnctr_mode_shift = 6,
2383                 .n_val_shift = 16,
2384                 .m_val_shift = 8,
2385                 .width = 8,
2386         },
2387         .p = {
2388                 .pre_div_shift = 12,
2389                 .pre_div_width = 4,
2390         },
2391         .s = {
2392                 .src_sel_shift = 0,
2393                 .parent_map = mmcc_pxo_dsi2_dsi1_map,
2394         },
2395         .clkr = {
2396                 .enable_reg = 0x0130,
2397                 .enable_mask = BIT(2),
2398                 .hw.init = &(struct clk_init_data){
2399                         .name = "dsi1_pixel_src",
2400                         .parent_data = mmcc_pxo_dsi2_dsi1,
2401                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
2402                         .ops = &clk_rcg_pixel_ops,
2403                 },
2404         },
2405 };
2406
2407 static struct clk_branch dsi1_pixel_clk = {
2408         .halt_reg = 0x01d0,
2409         .halt_bit = 6,
2410         .clkr = {
2411                 .enable_reg = 0x0130,
2412                 .enable_mask = BIT(0),
2413                 .hw.init = &(struct clk_init_data){
2414                         .name = "mdp_pclk1_clk",
2415                         .parent_hws = (const struct clk_hw*[]){
2416                                 &dsi1_pixel_src.clkr.hw
2417                         },
2418                         .num_parents = 1,
2419                         .ops = &clk_branch_ops,
2420                         .flags = CLK_SET_RATE_PARENT,
2421                 },
2422         },
2423 };
2424
2425 static struct clk_rcg dsi2_pixel_src = {
2426         .ns_reg = 0x00e4,
2427         .md_reg = 0x00b8,
2428         .mn = {
2429                 .mnctr_en_bit = 5,
2430                 .mnctr_reset_bit = 7,
2431                 .mnctr_mode_shift = 6,
2432                 .n_val_shift = 16,
2433                 .m_val_shift = 8,
2434                 .width = 8,
2435         },
2436         .p = {
2437                 .pre_div_shift = 12,
2438                 .pre_div_width = 4,
2439         },
2440         .s = {
2441                 .src_sel_shift = 0,
2442                 .parent_map = mmcc_pxo_dsi2_dsi1_map,
2443         },
2444         .clkr = {
2445                 .enable_reg = 0x0094,
2446                 .enable_mask = BIT(2),
2447                 .hw.init = &(struct clk_init_data){
2448                         .name = "dsi2_pixel_src",
2449                         .parent_data = mmcc_pxo_dsi2_dsi1,
2450                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
2451                         .ops = &clk_rcg_pixel_ops,
2452                 },
2453         },
2454 };
2455
2456 static struct clk_branch dsi2_pixel_clk = {
2457         .halt_reg = 0x01d0,
2458         .halt_bit = 19,
2459         .clkr = {
2460                 .enable_reg = 0x0094,
2461                 .enable_mask = BIT(0),
2462                 .hw.init = &(struct clk_init_data){
2463                         .name = "mdp_pclk2_clk",
2464                         .parent_hws = (const struct clk_hw*[]){
2465                                 &dsi2_pixel_src.clkr.hw
2466                         },
2467                         .num_parents = 1,
2468                         .ops = &clk_branch_ops,
2469                         .flags = CLK_SET_RATE_PARENT,
2470                 },
2471         },
2472 };
2473
2474 static struct clk_branch gfx2d0_ahb_clk = {
2475         .hwcg_reg = 0x0038,
2476         .hwcg_bit = 28,
2477         .halt_reg = 0x01dc,
2478         .halt_bit = 2,
2479         .clkr = {
2480                 .enable_reg = 0x0008,
2481                 .enable_mask = BIT(19),
2482                 .hw.init = &(struct clk_init_data){
2483                         .name = "gfx2d0_ahb_clk",
2484                         .ops = &clk_branch_ops,
2485                 },
2486         },
2487 };
2488
2489 static struct clk_branch gfx2d1_ahb_clk = {
2490         .hwcg_reg = 0x0038,
2491         .hwcg_bit = 29,
2492         .halt_reg = 0x01dc,
2493         .halt_bit = 3,
2494         .clkr = {
2495                 .enable_reg = 0x0008,
2496                 .enable_mask = BIT(2),
2497                 .hw.init = &(struct clk_init_data){
2498                         .name = "gfx2d1_ahb_clk",
2499                         .ops = &clk_branch_ops,
2500                 },
2501         },
2502 };
2503
2504 static struct clk_branch gfx3d_ahb_clk = {
2505         .hwcg_reg = 0x0038,
2506         .hwcg_bit = 27,
2507         .halt_reg = 0x01dc,
2508         .halt_bit = 4,
2509         .clkr = {
2510                 .enable_reg = 0x0008,
2511                 .enable_mask = BIT(3),
2512                 .hw.init = &(struct clk_init_data){
2513                         .name = "gfx3d_ahb_clk",
2514                         .ops = &clk_branch_ops,
2515                 },
2516         },
2517 };
2518
2519 static struct clk_branch hdmi_m_ahb_clk = {
2520         .hwcg_reg = 0x0038,
2521         .hwcg_bit = 21,
2522         .halt_reg = 0x01dc,
2523         .halt_bit = 5,
2524         .clkr = {
2525                 .enable_reg = 0x0008,
2526                 .enable_mask = BIT(14),
2527                 .hw.init = &(struct clk_init_data){
2528                         .name = "hdmi_m_ahb_clk",
2529                         .ops = &clk_branch_ops,
2530                 },
2531         },
2532 };
2533
2534 static struct clk_branch hdmi_s_ahb_clk = {
2535         .hwcg_reg = 0x0038,
2536         .hwcg_bit = 22,
2537         .halt_reg = 0x01dc,
2538         .halt_bit = 6,
2539         .clkr = {
2540                 .enable_reg = 0x0008,
2541                 .enable_mask = BIT(4),
2542                 .hw.init = &(struct clk_init_data){
2543                         .name = "hdmi_s_ahb_clk",
2544                         .ops = &clk_branch_ops,
2545                 },
2546         },
2547 };
2548
2549 static struct clk_branch ijpeg_ahb_clk = {
2550         .halt_reg = 0x01dc,
2551         .halt_bit = 9,
2552         .clkr = {
2553                 .enable_reg = 0x0008,
2554                 .enable_mask = BIT(5),
2555                 .hw.init = &(struct clk_init_data){
2556                         .name = "ijpeg_ahb_clk",
2557                         .ops = &clk_branch_ops,
2558                 },
2559         },
2560 };
2561
2562 static struct clk_branch mmss_imem_ahb_clk = {
2563         .hwcg_reg = 0x0038,
2564         .hwcg_bit = 12,
2565         .halt_reg = 0x01dc,
2566         .halt_bit = 10,
2567         .clkr = {
2568                 .enable_reg = 0x0008,
2569                 .enable_mask = BIT(6),
2570                 .hw.init = &(struct clk_init_data){
2571                         .name = "mmss_imem_ahb_clk",
2572                         .ops = &clk_branch_ops,
2573                 },
2574         },
2575 };
2576
2577 static struct clk_branch jpegd_ahb_clk = {
2578         .halt_reg = 0x01dc,
2579         .halt_bit = 7,
2580         .clkr = {
2581                 .enable_reg = 0x0008,
2582                 .enable_mask = BIT(21),
2583                 .hw.init = &(struct clk_init_data){
2584                         .name = "jpegd_ahb_clk",
2585                         .ops = &clk_branch_ops,
2586                 },
2587         },
2588 };
2589
2590 static struct clk_branch mdp_ahb_clk = {
2591         .halt_reg = 0x01dc,
2592         .halt_bit = 11,
2593         .clkr = {
2594                 .enable_reg = 0x0008,
2595                 .enable_mask = BIT(10),
2596                 .hw.init = &(struct clk_init_data){
2597                         .name = "mdp_ahb_clk",
2598                         .ops = &clk_branch_ops,
2599                 },
2600         },
2601 };
2602
2603 static struct clk_branch rot_ahb_clk = {
2604         .halt_reg = 0x01dc,
2605         .halt_bit = 13,
2606         .clkr = {
2607                 .enable_reg = 0x0008,
2608                 .enable_mask = BIT(12),
2609                 .hw.init = &(struct clk_init_data){
2610                         .name = "rot_ahb_clk",
2611                         .ops = &clk_branch_ops,
2612                 },
2613         },
2614 };
2615
2616 static struct clk_branch smmu_ahb_clk = {
2617         .hwcg_reg = 0x0008,
2618         .hwcg_bit = 26,
2619         .halt_reg = 0x01dc,
2620         .halt_bit = 22,
2621         .clkr = {
2622                 .enable_reg = 0x0008,
2623                 .enable_mask = BIT(15),
2624                 .hw.init = &(struct clk_init_data){
2625                         .name = "smmu_ahb_clk",
2626                         .ops = &clk_branch_ops,
2627                 },
2628         },
2629 };
2630
2631 static struct clk_branch tv_enc_ahb_clk = {
2632         .halt_reg = 0x01dc,
2633         .halt_bit = 23,
2634         .clkr = {
2635                 .enable_reg = 0x0008,
2636                 .enable_mask = BIT(25),
2637                 .hw.init = &(struct clk_init_data){
2638                         .name = "tv_enc_ahb_clk",
2639                         .ops = &clk_branch_ops,
2640                 },
2641         },
2642 };
2643
2644 static struct clk_branch vcap_ahb_clk = {
2645         .halt_reg = 0x0240,
2646         .halt_bit = 23,
2647         .clkr = {
2648                 .enable_reg = 0x0248,
2649                 .enable_mask = BIT(1),
2650                 .hw.init = &(struct clk_init_data){
2651                         .name = "vcap_ahb_clk",
2652                         .ops = &clk_branch_ops,
2653                 },
2654         },
2655 };
2656
2657 static struct clk_branch vcodec_ahb_clk = {
2658         .hwcg_reg = 0x0038,
2659         .hwcg_bit = 26,
2660         .halt_reg = 0x01dc,
2661         .halt_bit = 12,
2662         .clkr = {
2663                 .enable_reg = 0x0008,
2664                 .enable_mask = BIT(11),
2665                 .hw.init = &(struct clk_init_data){
2666                         .name = "vcodec_ahb_clk",
2667                         .ops = &clk_branch_ops,
2668                 },
2669         },
2670 };
2671
2672 static struct clk_branch vfe_ahb_clk = {
2673         .halt_reg = 0x01dc,
2674         .halt_bit = 14,
2675         .clkr = {
2676                 .enable_reg = 0x0008,
2677                 .enable_mask = BIT(13),
2678                 .hw.init = &(struct clk_init_data){
2679                         .name = "vfe_ahb_clk",
2680                         .ops = &clk_branch_ops,
2681                 },
2682         },
2683 };
2684
2685 static struct clk_branch vpe_ahb_clk = {
2686         .halt_reg = 0x01dc,
2687         .halt_bit = 15,
2688         .clkr = {
2689                 .enable_reg = 0x0008,
2690                 .enable_mask = BIT(16),
2691                 .hw.init = &(struct clk_init_data){
2692                         .name = "vpe_ahb_clk",
2693                         .ops = &clk_branch_ops,
2694                 },
2695         },
2696 };
2697
2698 static struct clk_regmap *mmcc_msm8960_clks[] = {
2699         [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2700         [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2701         [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2702         [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2703         [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2704         [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2705         [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2706         [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2707         [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2708         [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2709         [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2710         [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2711         [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2712         [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2713         [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2714         [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2715         [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2716         [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2717         [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2718         [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2719         [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2720         [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2721         [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2722         [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2723         [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2724         [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2725         [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2726         [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2727         [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2728         [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2729         [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2730         [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2731         [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2732         [CSI0_SRC] = &csi0_src.clkr,
2733         [CSI0_CLK] = &csi0_clk.clkr,
2734         [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2735         [CSI1_SRC] = &csi1_src.clkr,
2736         [CSI1_CLK] = &csi1_clk.clkr,
2737         [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2738         [CSI2_SRC] = &csi2_src.clkr,
2739         [CSI2_CLK] = &csi2_clk.clkr,
2740         [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2741         [DSI_SRC] = &dsi1_src.clkr,
2742         [DSI_CLK] = &dsi1_clk.clkr,
2743         [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2744         [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2745         [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2746         [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2747         [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2748         [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2749         [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2750         [GFX2D0_SRC] = &gfx2d0_src.clkr,
2751         [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2752         [GFX2D1_SRC] = &gfx2d1_src.clkr,
2753         [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2754         [GFX3D_SRC] = &gfx3d_src.clkr,
2755         [GFX3D_CLK] = &gfx3d_clk.clkr,
2756         [IJPEG_SRC] = &ijpeg_src.clkr,
2757         [IJPEG_CLK] = &ijpeg_clk.clkr,
2758         [JPEGD_SRC] = &jpegd_src.clkr,
2759         [JPEGD_CLK] = &jpegd_clk.clkr,
2760         [MDP_SRC] = &mdp_src.clkr,
2761         [MDP_CLK] = &mdp_clk.clkr,
2762         [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2763         [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr,
2764         [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr,
2765         [DSI2_SRC] = &dsi2_src.clkr,
2766         [DSI2_CLK] = &dsi2_clk.clkr,
2767         [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr,
2768         [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr,
2769         [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr,
2770         [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr,
2771         [DSI1_ESC_SRC] = &dsi1_esc_src.clkr,
2772         [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr,
2773         [DSI2_ESC_SRC] = &dsi2_esc_src.clkr,
2774         [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr,
2775         [ROT_SRC] = &rot_src.clkr,
2776         [ROT_CLK] = &rot_clk.clkr,
2777         [TV_ENC_CLK] = &tv_enc_clk.clkr,
2778         [TV_DAC_CLK] = &tv_dac_clk.clkr,
2779         [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2780         [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2781         [TV_SRC] = &tv_src.clkr,
2782         [VCODEC_SRC] = &vcodec_src.clkr,
2783         [VCODEC_CLK] = &vcodec_clk.clkr,
2784         [VFE_SRC] = &vfe_src.clkr,
2785         [VFE_CLK] = &vfe_clk.clkr,
2786         [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2787         [VPE_SRC] = &vpe_src.clkr,
2788         [VPE_CLK] = &vpe_clk.clkr,
2789         [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr,
2790         [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr,
2791         [CAMCLK0_SRC] = &camclk0_src.clkr,
2792         [CAMCLK0_CLK] = &camclk0_clk.clkr,
2793         [CAMCLK1_SRC] = &camclk1_src.clkr,
2794         [CAMCLK1_CLK] = &camclk1_clk.clkr,
2795         [CAMCLK2_SRC] = &camclk2_src.clkr,
2796         [CAMCLK2_CLK] = &camclk2_clk.clkr,
2797         [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2798         [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2799         [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2800         [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2801         [PLL2] = &pll2.clkr,
2802 };
2803
2804 static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2805         [VPE_AXI_RESET] = { 0x0208, 15 },
2806         [IJPEG_AXI_RESET] = { 0x0208, 14 },
2807         [MPD_AXI_RESET] = { 0x0208, 13 },
2808         [VFE_AXI_RESET] = { 0x0208, 9 },
2809         [SP_AXI_RESET] = { 0x0208, 8 },
2810         [VCODEC_AXI_RESET] = { 0x0208, 7 },
2811         [ROT_AXI_RESET] = { 0x0208, 6 },
2812         [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2813         [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2814         [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2815         [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2816         [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2817         [FAB_S0_AXI_RESET] = { 0x0208 },
2818         [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2819         [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2820         [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2821         [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2822         [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2823         [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2824         [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2825         [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2826         [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2827         [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2828         [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2829         [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2830         [APU_AHB_RESET] = { 0x020c, 18 },
2831         [CSI_AHB_RESET] = { 0x020c, 17 },
2832         [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2833         [VPE_AHB_RESET] = { 0x020c, 14 },
2834         [FABRIC_AHB_RESET] = { 0x020c, 13 },
2835         [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2836         [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2837         [GFX3D_AHB_RESET] = { 0x020c, 10 },
2838         [HDMI_AHB_RESET] = { 0x020c, 9 },
2839         [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2840         [IJPEG_AHB_RESET] = { 0x020c, 7 },
2841         [DSI_M_AHB_RESET] = { 0x020c, 6 },
2842         [DSI_S_AHB_RESET] = { 0x020c, 5 },
2843         [JPEGD_AHB_RESET] = { 0x020c, 4 },
2844         [MDP_AHB_RESET] = { 0x020c, 3 },
2845         [ROT_AHB_RESET] = { 0x020c, 2 },
2846         [VCODEC_AHB_RESET] = { 0x020c, 1 },
2847         [VFE_AHB_RESET] = { 0x020c, 0 },
2848         [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2849         [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2850         [CSIPHY2_RESET] = { 0x0210, 29 },
2851         [CSI_PIX1_RESET] = { 0x0210, 28 },
2852         [CSIPHY0_RESET] = { 0x0210, 27 },
2853         [CSIPHY1_RESET] = { 0x0210, 26 },
2854         [DSI2_RESET] = { 0x0210, 25 },
2855         [VFE_CSI_RESET] = { 0x0210, 24 },
2856         [MDP_RESET] = { 0x0210, 21 },
2857         [AMP_RESET] = { 0x0210, 20 },
2858         [JPEGD_RESET] = { 0x0210, 19 },
2859         [CSI1_RESET] = { 0x0210, 18 },
2860         [VPE_RESET] = { 0x0210, 17 },
2861         [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2862         [VFE_RESET] = { 0x0210, 15 },
2863         [GFX2D0_RESET] = { 0x0210, 14 },
2864         [GFX2D1_RESET] = { 0x0210, 13 },
2865         [GFX3D_RESET] = { 0x0210, 12 },
2866         [HDMI_RESET] = { 0x0210, 11 },
2867         [MMSS_IMEM_RESET] = { 0x0210, 10 },
2868         [IJPEG_RESET] = { 0x0210, 9 },
2869         [CSI0_RESET] = { 0x0210, 8 },
2870         [DSI_RESET] = { 0x0210, 7 },
2871         [VCODEC_RESET] = { 0x0210, 6 },
2872         [MDP_TV_RESET] = { 0x0210, 4 },
2873         [MDP_VSYNC_RESET] = { 0x0210, 3 },
2874         [ROT_RESET] = { 0x0210, 2 },
2875         [TV_HDMI_RESET] = { 0x0210, 1 },
2876         [TV_ENC_RESET] = { 0x0210 },
2877         [CSI2_RESET] = { 0x0214, 2 },
2878         [CSI_RDI1_RESET] = { 0x0214, 1 },
2879         [CSI_RDI2_RESET] = { 0x0214 },
2880 };
2881
2882 static struct clk_regmap *mmcc_apq8064_clks[] = {
2883         [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2884         [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2885         [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2886         [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2887         [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2888         [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2889         [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2890         [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2891         [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2892         [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2893         [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2894         [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2895         [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2896         [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2897         [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2898         [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2899         [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2900         [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2901         [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2902         [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2903         [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2904         [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2905         [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2906         [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2907         [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2908         [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2909         [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2910         [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2911         [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2912         [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2913         [CSI0_SRC] = &csi0_src.clkr,
2914         [CSI0_CLK] = &csi0_clk.clkr,
2915         [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2916         [CSI1_SRC] = &csi1_src.clkr,
2917         [CSI1_CLK] = &csi1_clk.clkr,
2918         [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2919         [CSI2_SRC] = &csi2_src.clkr,
2920         [CSI2_CLK] = &csi2_clk.clkr,
2921         [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2922         [DSI_SRC] = &dsi1_src.clkr,
2923         [DSI_CLK] = &dsi1_clk.clkr,
2924         [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2925         [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2926         [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2927         [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2928         [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2929         [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2930         [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2931         [GFX3D_SRC] = &gfx3d_src.clkr,
2932         [GFX3D_CLK] = &gfx3d_clk.clkr,
2933         [IJPEG_SRC] = &ijpeg_src.clkr,
2934         [IJPEG_CLK] = &ijpeg_clk.clkr,
2935         [JPEGD_SRC] = &jpegd_src.clkr,
2936         [JPEGD_CLK] = &jpegd_clk.clkr,
2937         [MDP_SRC] = &mdp_src.clkr,
2938         [MDP_CLK] = &mdp_clk.clkr,
2939         [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2940         [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr,
2941         [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr,
2942         [DSI2_SRC] = &dsi2_src.clkr,
2943         [DSI2_CLK] = &dsi2_clk.clkr,
2944         [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr,
2945         [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr,
2946         [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr,
2947         [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr,
2948         [DSI1_ESC_SRC] = &dsi1_esc_src.clkr,
2949         [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr,
2950         [DSI2_ESC_SRC] = &dsi2_esc_src.clkr,
2951         [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr,
2952         [ROT_SRC] = &rot_src.clkr,
2953         [ROT_CLK] = &rot_clk.clkr,
2954         [TV_DAC_CLK] = &tv_dac_clk.clkr,
2955         [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2956         [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2957         [TV_SRC] = &tv_src.clkr,
2958         [VCODEC_SRC] = &vcodec_src.clkr,
2959         [VCODEC_CLK] = &vcodec_clk.clkr,
2960         [VFE_SRC] = &vfe_src.clkr,
2961         [VFE_CLK] = &vfe_clk.clkr,
2962         [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2963         [VPE_SRC] = &vpe_src.clkr,
2964         [VPE_CLK] = &vpe_clk.clkr,
2965         [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr,
2966         [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr,
2967         [CAMCLK0_SRC] = &camclk0_src.clkr,
2968         [CAMCLK0_CLK] = &camclk0_clk.clkr,
2969         [CAMCLK1_SRC] = &camclk1_src.clkr,
2970         [CAMCLK1_CLK] = &camclk1_clk.clkr,
2971         [CAMCLK2_SRC] = &camclk2_src.clkr,
2972         [CAMCLK2_CLK] = &camclk2_clk.clkr,
2973         [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2974         [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2975         [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2976         [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2977         [PLL2] = &pll2.clkr,
2978         [RGB_TV_CLK] = &rgb_tv_clk.clkr,
2979         [NPL_TV_CLK] = &npl_tv_clk.clkr,
2980         [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr,
2981         [VCAP_AXI_CLK] = &vcap_axi_clk.clkr,
2982         [VCAP_SRC] = &vcap_src.clkr,
2983         [VCAP_CLK] = &vcap_clk.clkr,
2984         [VCAP_NPL_CLK] = &vcap_npl_clk.clkr,
2985         [PLL15] = &pll15.clkr,
2986 };
2987
2988 static const struct qcom_reset_map mmcc_apq8064_resets[] = {
2989         [GFX3D_AXI_RESET] = { 0x0208, 17 },
2990         [VCAP_AXI_RESET] = { 0x0208, 16 },
2991         [VPE_AXI_RESET] = { 0x0208, 15 },
2992         [IJPEG_AXI_RESET] = { 0x0208, 14 },
2993         [MPD_AXI_RESET] = { 0x0208, 13 },
2994         [VFE_AXI_RESET] = { 0x0208, 9 },
2995         [SP_AXI_RESET] = { 0x0208, 8 },
2996         [VCODEC_AXI_RESET] = { 0x0208, 7 },
2997         [ROT_AXI_RESET] = { 0x0208, 6 },
2998         [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2999         [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
3000         [FAB_S3_AXI_RESET] = { 0x0208, 3 },
3001         [FAB_S2_AXI_RESET] = { 0x0208, 2 },
3002         [FAB_S1_AXI_RESET] = { 0x0208, 1 },
3003         [FAB_S0_AXI_RESET] = { 0x0208 },
3004         [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
3005         [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
3006         [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
3007         [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
3008         [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
3009         [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
3010         [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
3011         [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
3012         [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
3013         [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
3014         [APU_AHB_RESET] = { 0x020c, 18 },
3015         [CSI_AHB_RESET] = { 0x020c, 17 },
3016         [TV_ENC_AHB_RESET] = { 0x020c, 15 },
3017         [VPE_AHB_RESET] = { 0x020c, 14 },
3018         [FABRIC_AHB_RESET] = { 0x020c, 13 },
3019         [GFX3D_AHB_RESET] = { 0x020c, 10 },
3020         [HDMI_AHB_RESET] = { 0x020c, 9 },
3021         [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
3022         [IJPEG_AHB_RESET] = { 0x020c, 7 },
3023         [DSI_M_AHB_RESET] = { 0x020c, 6 },
3024         [DSI_S_AHB_RESET] = { 0x020c, 5 },
3025         [JPEGD_AHB_RESET] = { 0x020c, 4 },
3026         [MDP_AHB_RESET] = { 0x020c, 3 },
3027         [ROT_AHB_RESET] = { 0x020c, 2 },
3028         [VCODEC_AHB_RESET] = { 0x020c, 1 },
3029         [VFE_AHB_RESET] = { 0x020c, 0 },
3030         [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
3031         [VCAP_AHB_RESET] = { 0x0200, 2 },
3032         [DSI2_M_AHB_RESET] = { 0x0200, 1 },
3033         [DSI2_S_AHB_RESET] = { 0x0200, 0 },
3034         [CSIPHY2_RESET] = { 0x0210, 31 },
3035         [CSI_PIX1_RESET] = { 0x0210, 30 },
3036         [CSIPHY0_RESET] = { 0x0210, 29 },
3037         [CSIPHY1_RESET] = { 0x0210, 28 },
3038         [CSI_RDI_RESET] = { 0x0210, 27 },
3039         [CSI_PIX_RESET] = { 0x0210, 26 },
3040         [DSI2_RESET] = { 0x0210, 25 },
3041         [VFE_CSI_RESET] = { 0x0210, 24 },
3042         [MDP_RESET] = { 0x0210, 21 },
3043         [AMP_RESET] = { 0x0210, 20 },
3044         [JPEGD_RESET] = { 0x0210, 19 },
3045         [CSI1_RESET] = { 0x0210, 18 },
3046         [VPE_RESET] = { 0x0210, 17 },
3047         [MMSS_FABRIC_RESET] = { 0x0210, 16 },
3048         [VFE_RESET] = { 0x0210, 15 },
3049         [GFX3D_RESET] = { 0x0210, 12 },
3050         [HDMI_RESET] = { 0x0210, 11 },
3051         [MMSS_IMEM_RESET] = { 0x0210, 10 },
3052         [IJPEG_RESET] = { 0x0210, 9 },
3053         [CSI0_RESET] = { 0x0210, 8 },
3054         [DSI_RESET] = { 0x0210, 7 },
3055         [VCODEC_RESET] = { 0x0210, 6 },
3056         [MDP_TV_RESET] = { 0x0210, 4 },
3057         [MDP_VSYNC_RESET] = { 0x0210, 3 },
3058         [ROT_RESET] = { 0x0210, 2 },
3059         [TV_HDMI_RESET] = { 0x0210, 1 },
3060         [VCAP_NPL_RESET] = { 0x0214, 4 },
3061         [VCAP_RESET] = { 0x0214, 3 },
3062         [CSI2_RESET] = { 0x0214, 2 },
3063         [CSI_RDI1_RESET] = { 0x0214, 1 },
3064         [CSI_RDI2_RESET] = { 0x0214 },
3065 };
3066
3067 static const struct regmap_config mmcc_msm8960_regmap_config = {
3068         .reg_bits       = 32,
3069         .reg_stride     = 4,
3070         .val_bits       = 32,
3071         .max_register   = 0x334,
3072         .fast_io        = true,
3073 };
3074
3075 static const struct regmap_config mmcc_apq8064_regmap_config = {
3076         .reg_bits       = 32,
3077         .reg_stride     = 4,
3078         .val_bits       = 32,
3079         .max_register   = 0x350,
3080         .fast_io        = true,
3081 };
3082
3083 static const struct qcom_cc_desc mmcc_msm8960_desc = {
3084         .config = &mmcc_msm8960_regmap_config,
3085         .clks = mmcc_msm8960_clks,
3086         .num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
3087         .resets = mmcc_msm8960_resets,
3088         .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
3089 };
3090
3091 static const struct qcom_cc_desc mmcc_apq8064_desc = {
3092         .config = &mmcc_apq8064_regmap_config,
3093         .clks = mmcc_apq8064_clks,
3094         .num_clks = ARRAY_SIZE(mmcc_apq8064_clks),
3095         .resets = mmcc_apq8064_resets,
3096         .num_resets = ARRAY_SIZE(mmcc_apq8064_resets),
3097 };
3098
3099 static const struct of_device_id mmcc_msm8960_match_table[] = {
3100         { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc },
3101         { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc },
3102         { }
3103 };
3104 MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
3105
3106 static int mmcc_msm8960_probe(struct platform_device *pdev)
3107 {
3108         const struct of_device_id *match;
3109         struct regmap *regmap;
3110         bool is_8064;
3111         struct device *dev = &pdev->dev;
3112
3113         match = of_match_device(mmcc_msm8960_match_table, dev);
3114         if (!match)
3115                 return -EINVAL;
3116
3117         is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064");
3118         if (is_8064) {
3119                 gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064;
3120                 gfx3d_src.clkr.hw.init = &gfx3d_8064_init;
3121                 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
3122                 gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
3123         }
3124
3125         regmap = qcom_cc_map(pdev, match->data);
3126         if (IS_ERR(regmap))
3127                 return PTR_ERR(regmap);
3128
3129         clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
3130
3131         return qcom_cc_really_probe(pdev, match->data, regmap);
3132 }
3133
3134 static struct platform_driver mmcc_msm8960_driver = {
3135         .probe          = mmcc_msm8960_probe,
3136         .driver         = {
3137                 .name   = "mmcc-msm8960",
3138                 .of_match_table = mmcc_msm8960_match_table,
3139         },
3140 };
3141
3142 module_platform_driver(mmcc_msm8960_driver);
3143
3144 MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
3145 MODULE_LICENSE("GPL v2");
3146 MODULE_ALIAS("platform:mmcc-msm8960");