1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
16 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
19 #include "clk-regmap.h"
22 #include "clk-branch.h"
23 #include "clk-regmap-divider.h"
24 #include "clk-regmap-mux.h"
27 static struct clk_pll pll4 = {
35 .clkr.hw.init = &(struct clk_init_data){
37 .parent_data = &(const struct clk_parent_data) {
38 .fw_name = "pxo", .name = "pxo_board",
45 static const struct pll_config pll4_config = {
50 .vco_mask = BIT(17) | BIT(16),
52 .pre_div_mask = BIT(19),
54 .post_div_mask = BIT(21) | BIT(20),
55 .mn_ena_mask = BIT(22),
56 .main_output_mask = BIT(23),
64 static const struct parent_map lcc_pxo_pll4_map[] = {
69 static const struct clk_parent_data lcc_pxo_pll4[] = {
70 { .fw_name = "pxo", .name = "pxo_board" },
71 { .fw_name = "pll4_vote", .name = "pll4_vote" },
74 static struct freq_tbl clk_tbl_aif_mi2s[] = {
75 { 1024000, P_PLL4, 4, 1, 96 },
76 { 1411200, P_PLL4, 4, 2, 139 },
77 { 1536000, P_PLL4, 4, 1, 64 },
78 { 2048000, P_PLL4, 4, 1, 48 },
79 { 2116800, P_PLL4, 4, 2, 93 },
80 { 2304000, P_PLL4, 4, 2, 85 },
81 { 2822400, P_PLL4, 4, 6, 209 },
82 { 3072000, P_PLL4, 4, 1, 32 },
83 { 3175200, P_PLL4, 4, 1, 31 },
84 { 4096000, P_PLL4, 4, 1, 24 },
85 { 4233600, P_PLL4, 4, 9, 209 },
86 { 4608000, P_PLL4, 4, 3, 64 },
87 { 5644800, P_PLL4, 4, 12, 209 },
88 { 6144000, P_PLL4, 4, 1, 16 },
89 { 6350400, P_PLL4, 4, 2, 31 },
90 { 8192000, P_PLL4, 4, 1, 12 },
91 { 8467200, P_PLL4, 4, 18, 209 },
92 { 9216000, P_PLL4, 4, 3, 32 },
93 { 11289600, P_PLL4, 4, 24, 209 },
94 { 12288000, P_PLL4, 4, 1, 8 },
95 { 12700800, P_PLL4, 4, 27, 209 },
96 { 13824000, P_PLL4, 4, 9, 64 },
97 { 16384000, P_PLL4, 4, 1, 6 },
98 { 16934400, P_PLL4, 4, 41, 238 },
99 { 18432000, P_PLL4, 4, 3, 16 },
100 { 22579200, P_PLL4, 2, 24, 209 },
101 { 24576000, P_PLL4, 4, 1, 4 },
102 { 27648000, P_PLL4, 4, 9, 32 },
103 { 33868800, P_PLL4, 4, 41, 119 },
104 { 36864000, P_PLL4, 4, 3, 8 },
105 { 45158400, P_PLL4, 1, 24, 209 },
106 { 49152000, P_PLL4, 4, 1, 2 },
107 { 50803200, P_PLL4, 1, 27, 209 },
111 static struct clk_rcg mi2s_osr_src = {
116 .mnctr_reset_bit = 7,
117 .mnctr_mode_shift = 5,
128 .parent_map = lcc_pxo_pll4_map,
130 .freq_tbl = clk_tbl_aif_mi2s,
133 .enable_mask = BIT(9),
134 .hw.init = &(struct clk_init_data){
135 .name = "mi2s_osr_src",
136 .parent_data = lcc_pxo_pll4,
137 .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
139 .flags = CLK_SET_RATE_GATE,
144 static struct clk_branch mi2s_osr_clk = {
147 .halt_check = BRANCH_HALT_ENABLE,
150 .enable_mask = BIT(17),
151 .hw.init = &(struct clk_init_data){
152 .name = "mi2s_osr_clk",
153 .parent_hws = (const struct clk_hw*[]) {
154 &mi2s_osr_src.clkr.hw,
157 .ops = &clk_branch_ops,
158 .flags = CLK_SET_RATE_PARENT,
163 static struct clk_regmap_div mi2s_div_clk = {
168 .hw.init = &(struct clk_init_data){
169 .name = "mi2s_div_clk",
170 .parent_hws = (const struct clk_hw*[]) {
171 &mi2s_osr_src.clkr.hw,
174 .ops = &clk_regmap_div_ops,
179 static struct clk_branch mi2s_bit_div_clk = {
182 .halt_check = BRANCH_HALT_ENABLE,
185 .enable_mask = BIT(15),
186 .hw.init = &(struct clk_init_data){
187 .name = "mi2s_bit_div_clk",
188 .parent_hws = (const struct clk_hw*[]) {
189 &mi2s_div_clk.clkr.hw,
192 .ops = &clk_branch_ops,
193 .flags = CLK_SET_RATE_PARENT,
198 static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = {
199 { .hw = &mi2s_bit_div_clk.clkr.hw, },
200 { .fw_name = "mi2s_codec", .name = "mi2s_codec_clk" },
203 static struct clk_regmap_mux mi2s_bit_clk = {
208 .hw.init = &(struct clk_init_data){
209 .name = "mi2s_bit_clk",
210 .parent_data = lcc_mi2s_bit_div_codec_clk,
211 .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk),
212 .ops = &clk_regmap_mux_closest_ops,
213 .flags = CLK_SET_RATE_PARENT,
218 static struct freq_tbl clk_tbl_pcm[] = {
219 { 64000, P_PLL4, 4, 1, 1536 },
220 { 128000, P_PLL4, 4, 1, 768 },
221 { 256000, P_PLL4, 4, 1, 384 },
222 { 512000, P_PLL4, 4, 1, 192 },
223 { 1024000, P_PLL4, 4, 1, 96 },
224 { 2048000, P_PLL4, 4, 1, 48 },
228 static struct clk_rcg pcm_src = {
233 .mnctr_reset_bit = 7,
234 .mnctr_mode_shift = 5,
245 .parent_map = lcc_pxo_pll4_map,
247 .freq_tbl = clk_tbl_pcm,
250 .enable_mask = BIT(9),
251 .hw.init = &(struct clk_init_data){
253 .parent_data = lcc_pxo_pll4,
254 .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
256 .flags = CLK_SET_RATE_GATE,
261 static struct clk_branch pcm_clk_out = {
264 .halt_check = BRANCH_HALT_ENABLE,
267 .enable_mask = BIT(11),
268 .hw.init = &(struct clk_init_data){
269 .name = "pcm_clk_out",
270 .parent_hws = (const struct clk_hw*[]) {
274 .ops = &clk_branch_ops,
275 .flags = CLK_SET_RATE_PARENT,
280 static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = {
281 { .hw = &pcm_clk_out.clkr.hw, },
282 { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
285 static struct clk_regmap_mux pcm_clk = {
290 .hw.init = &(struct clk_init_data){
292 .parent_data = lcc_pcm_clk_out_codec_clk,
293 .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk),
294 .ops = &clk_regmap_mux_closest_ops,
295 .flags = CLK_SET_RATE_PARENT,
300 static struct freq_tbl clk_tbl_aif_osr[] = {
301 { 2822400, P_PLL4, 1, 147, 20480 },
302 { 4096000, P_PLL4, 1, 1, 96 },
303 { 5644800, P_PLL4, 1, 147, 10240 },
304 { 6144000, P_PLL4, 1, 1, 64 },
305 { 11289600, P_PLL4, 1, 147, 5120 },
306 { 12288000, P_PLL4, 1, 1, 32 },
307 { 22579200, P_PLL4, 1, 147, 2560 },
308 { 24576000, P_PLL4, 1, 1, 16 },
312 static struct clk_rcg spdif_src = {
317 .mnctr_reset_bit = 7,
318 .mnctr_mode_shift = 5,
329 .parent_map = lcc_pxo_pll4_map,
331 .freq_tbl = clk_tbl_aif_osr,
334 .enable_mask = BIT(9),
335 .hw.init = &(struct clk_init_data){
337 .parent_data = lcc_pxo_pll4,
338 .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
340 .flags = CLK_SET_RATE_GATE,
345 static struct clk_branch spdif_clk = {
348 .halt_check = BRANCH_HALT_ENABLE,
351 .enable_mask = BIT(12),
352 .hw.init = &(struct clk_init_data){
354 .parent_hws = (const struct clk_hw*[]) {
358 .ops = &clk_branch_ops,
359 .flags = CLK_SET_RATE_PARENT,
364 static struct freq_tbl clk_tbl_ahbix[] = {
365 { 131072000, P_PLL4, 1, 1, 3 },
369 static struct clk_rcg ahbix_clk = {
374 .mnctr_reset_bit = 7,
375 .mnctr_mode_shift = 5,
386 .parent_map = lcc_pxo_pll4_map,
388 .freq_tbl = clk_tbl_ahbix,
391 .enable_mask = BIT(11),
392 .hw.init = &(struct clk_init_data){
394 .parent_data = lcc_pxo_pll4,
395 .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
396 .ops = &clk_rcg_lcc_ops,
401 static struct clk_regmap *lcc_ipq806x_clks[] = {
403 [MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
404 [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
405 [MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
406 [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
407 [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
408 [PCM_SRC] = &pcm_src.clkr,
409 [PCM_CLK_OUT] = &pcm_clk_out.clkr,
410 [PCM_CLK] = &pcm_clk.clkr,
411 [SPDIF_SRC] = &spdif_src.clkr,
412 [SPDIF_CLK] = &spdif_clk.clkr,
413 [AHBIX_CLK] = &ahbix_clk.clkr,
416 static const struct qcom_reset_map lcc_ipq806x_resets[] = {
417 [LCC_PCM_RESET] = { 0x54, 13 },
420 static const struct regmap_config lcc_ipq806x_regmap_config = {
424 .max_register = 0xfc,
428 static const struct qcom_cc_desc lcc_ipq806x_desc = {
429 .config = &lcc_ipq806x_regmap_config,
430 .clks = lcc_ipq806x_clks,
431 .num_clks = ARRAY_SIZE(lcc_ipq806x_clks),
432 .resets = lcc_ipq806x_resets,
433 .num_resets = ARRAY_SIZE(lcc_ipq806x_resets),
436 static const struct of_device_id lcc_ipq806x_match_table[] = {
437 { .compatible = "qcom,lcc-ipq8064" },
440 MODULE_DEVICE_TABLE(of, lcc_ipq806x_match_table);
442 static int lcc_ipq806x_probe(struct platform_device *pdev)
445 struct regmap *regmap;
447 regmap = qcom_cc_map(pdev, &lcc_ipq806x_desc);
449 return PTR_ERR(regmap);
451 /* Configure the rate of PLL4 if the bootloader hasn't already */
452 regmap_read(regmap, 0x0, &val);
454 clk_pll_configure_sr(&pll4, regmap, &pll4_config, true);
455 /* Enable PLL4 source on the LPASS Primary PLL Mux */
456 regmap_write(regmap, 0xc4, 0x1);
458 return qcom_cc_really_probe(pdev, &lcc_ipq806x_desc, regmap);
461 static struct platform_driver lcc_ipq806x_driver = {
462 .probe = lcc_ipq806x_probe,
464 .name = "lcc-ipq806x",
465 .of_match_table = lcc_ipq806x_match_table,
468 module_platform_driver(lcc_ipq806x_driver);
470 MODULE_DESCRIPTION("QCOM LCC IPQ806x Driver");
471 MODULE_LICENSE("GPL v2");
472 MODULE_ALIAS("platform:lcc-ipq806x");