1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 #include <linux/kernel.h>
5 #include <linux/init.h>
6 #include <linux/module.h>
7 #include <linux/platform_device.h>
11 #include <linux/of_device.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/slab.h>
16 #include "clk-krait.h"
28 static unsigned int sec_mux_map[] = {
33 static unsigned int pri_mux_map[] = {
40 * Notifier function for switching the muxes to safe parent
41 * while the hfpll is getting reprogrammed.
43 static int krait_notifier_cb(struct notifier_block *nb,
48 struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk,
50 /* Switch to safe parent */
51 if (event == PRE_RATE_CHANGE) {
52 mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw);
53 ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel);
54 mux->reparent = false;
56 * By the time POST_RATE_CHANGE notifier is called,
57 * clk framework itself would have changed the parent for the new rate.
58 * Only otherwise, put back to the old parent.
60 } else if (event == POST_RATE_CHANGE) {
62 ret = krait_mux_clk_ops.set_parent(&mux->hw,
66 return notifier_from_errno(ret);
69 static int krait_notifier_register(struct device *dev, struct clk *clk,
70 struct krait_mux_clk *mux)
74 mux->clk_nb.notifier_call = krait_notifier_cb;
75 ret = devm_clk_notifier_register(dev, clk, &mux->clk_nb);
77 dev_err(dev, "failed to register clock notifier: %d\n", ret);
82 static struct clk_hw *
83 krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
85 struct krait_div2_clk *div;
86 static struct clk_parent_data p_data[1];
87 struct clk_init_data init = {
88 .num_parents = ARRAY_SIZE(p_data),
89 .ops = &krait_div2_clk_ops,
90 .flags = CLK_SET_RATE_PARENT,
96 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
98 return ERR_PTR(-ENOMEM);
103 div->offset = offset;
104 div->hw.init = &init;
106 init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
108 return ERR_PTR(-ENOMEM);
110 init.parent_data = p_data;
111 parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
113 clk = ERR_PTR(-ENOMEM);
114 goto err_parent_name;
117 p_data[0].fw_name = parent_name;
118 p_data[0].name = parent_name;
120 ret = devm_clk_hw_register(dev, &div->hw);
128 /* clk-krait ignore any rate change if mux is not flagged as enabled */
130 for_each_online_cpu(cpu)
131 clk_prepare_enable(div->hw.clk);
133 clk_prepare_enable(div->hw.clk);
143 static struct clk_hw *
144 krait_add_sec_mux(struct device *dev, int id, const char *s,
145 unsigned int offset, bool unique_aux)
148 struct krait_mux_clk *mux;
149 static struct clk_parent_data sec_mux_list[2] = {
150 { .name = "qsb", .fw_name = "qsb" },
153 struct clk_init_data init = {
154 .parent_data = sec_mux_list,
155 .num_parents = ARRAY_SIZE(sec_mux_list),
156 .ops = &krait_mux_clk_ops,
157 .flags = CLK_SET_RATE_PARENT,
162 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
164 return ERR_PTR(-ENOMEM);
166 mux->offset = offset;
170 mux->parent_map = sec_mux_map;
171 mux->hw.init = &init;
174 /* Checking for qcom,krait-cc-v1 or qcom,krait-cc-v2 is not
175 * enough to limit this to apq/ipq8064. Directly check machine
176 * compatible to correctly handle this errata.
178 if (of_machine_is_compatible("qcom,ipq8064") ||
179 of_machine_is_compatible("qcom,apq8064"))
180 mux->disable_sec_src_gating = true;
182 init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
184 return ERR_PTR(-ENOMEM);
187 parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
189 clk = ERR_PTR(-ENOMEM);
192 sec_mux_list[1].fw_name = parent_name;
193 sec_mux_list[1].name = parent_name;
195 sec_mux_list[1].name = "apu_aux";
198 ret = devm_clk_hw_register(dev, &mux->hw);
206 ret = krait_notifier_register(dev, mux->hw.clk, mux);
212 /* clk-krait ignore any rate change if mux is not flagged as enabled */
214 for_each_online_cpu(cpu)
215 clk_prepare_enable(mux->hw.clk);
217 clk_prepare_enable(mux->hw.clk);
227 static struct clk_hw *
228 krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *sec_mux,
229 int id, const char *s, unsigned int offset)
232 struct krait_mux_clk *mux;
233 static struct clk_parent_data p_data[3];
234 struct clk_init_data init = {
235 .parent_data = p_data,
236 .num_parents = ARRAY_SIZE(p_data),
237 .ops = &krait_mux_clk_ops,
238 .flags = CLK_SET_RATE_PARENT,
243 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
245 return ERR_PTR(-ENOMEM);
249 mux->offset = offset;
251 mux->parent_map = pri_mux_map;
252 mux->hw.init = &init;
255 init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
257 return ERR_PTR(-ENOMEM);
259 hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
261 clk = ERR_PTR(-ENOMEM);
265 p_data[0].fw_name = hfpll_name;
266 p_data[0].name = hfpll_name;
268 p_data[1].hw = hfpll_div;
269 p_data[2].hw = sec_mux;
271 ret = devm_clk_hw_register(dev, &mux->hw);
279 ret = krait_notifier_register(dev, mux->hw.clk, mux);
290 /* id < 0 for L2, otherwise id == physical CPU number */
291 static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux)
293 struct clk_hw *hfpll_div, *sec_mux, *pri_mux;
299 offset = 0x4501 + (0x1000 * id);
300 s = p = kasprintf(GFP_KERNEL, "%d", id);
302 return ERR_PTR(-ENOMEM);
308 hfpll_div = krait_add_div(dev, id, s, offset);
309 if (IS_ERR(hfpll_div)) {
314 sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux);
315 if (IS_ERR(sec_mux)) {
320 pri_mux = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset);
327 static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
329 unsigned int idx = clkspec->args[0];
330 struct clk **clks = data;
332 if (idx >= clks_max) {
333 pr_err("%s: invalid clock index %d\n", __func__, idx);
334 return ERR_PTR(-EINVAL);
337 return clks[idx] ? : ERR_PTR(-ENODEV);
340 static const struct of_device_id krait_cc_match_table[] = {
341 { .compatible = "qcom,krait-cc-v1", (void *)1UL },
342 { .compatible = "qcom,krait-cc-v2" },
345 MODULE_DEVICE_TABLE(of, krait_cc_match_table);
347 static int krait_cc_probe(struct platform_device *pdev)
349 struct device *dev = &pdev->dev;
350 const struct of_device_id *id;
351 unsigned long cur_rate, aux_rate;
353 struct clk_hw *mux, *l2_pri_mux;
354 struct clk *clk, **clks;
356 id = of_match_device(krait_cc_match_table, dev);
360 /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
361 clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
366 clk = clk_register_fixed_factor(dev, "acpu_aux",
367 "gpll0_vote", 0, 1, 2);
372 /* Krait configurations have at most 4 CPUs and one L2 */
373 clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL);
377 for_each_possible_cpu(cpu) {
378 mux = krait_add_clks(dev, cpu, id->data);
381 clks[cpu] = mux->clk;
384 l2_pri_mux = krait_add_clks(dev, -1, id->data);
385 if (IS_ERR(l2_pri_mux))
386 return PTR_ERR(l2_pri_mux);
387 clks[l2_mux] = l2_pri_mux->clk;
390 * We don't want the CPU or L2 clocks to be turned off at late init
391 * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
392 * refcount of these clocks. Any cpufreq/hotplug manager can assume
393 * that the clocks have already been prepared and enabled by the time
396 for_each_online_cpu(cpu) {
397 clk_prepare_enable(clks[l2_mux]);
398 WARN(clk_prepare_enable(clks[cpu]),
399 "Unable to turn on CPU%d clock", cpu);
403 * Force reinit of HFPLLs and muxes to overwrite any potential
404 * incorrect configuration of HFPLLs and muxes by the bootloader.
405 * While at it, also make sure the cores are running at known rates
406 * and print the current rate.
408 * The clocks are set to aux clock rate first to make sure the
409 * secondary mux is not sourcing off of QSB. The rate is then set to
410 * two different rates to force a HFPLL reinit under all
413 cur_rate = clk_get_rate(clks[l2_mux]);
414 aux_rate = 384000000;
415 if (cur_rate < aux_rate) {
416 pr_info("L2 @ Undefined rate. Forcing new rate.\n");
419 clk_set_rate(clks[l2_mux], aux_rate);
420 clk_set_rate(clks[l2_mux], 2);
421 clk_set_rate(clks[l2_mux], cur_rate);
422 pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
423 for_each_possible_cpu(cpu) {
425 cur_rate = clk_get_rate(clk);
426 if (cur_rate < aux_rate) {
427 pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
431 clk_set_rate(clk, aux_rate);
432 clk_set_rate(clk, 2);
433 clk_set_rate(clk, cur_rate);
434 pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
437 of_clk_add_provider(dev->of_node, krait_of_get, clks);
442 static struct platform_driver krait_cc_driver = {
443 .probe = krait_cc_probe,
446 .of_match_table = krait_cc_match_table,
449 module_platform_driver(krait_cc_driver);
451 MODULE_DESCRIPTION("Krait CPU Clock Driver");
452 MODULE_LICENSE("GPL v2");
453 MODULE_ALIAS("platform:krait-cc");