1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
12 #include <dt-bindings/clock/qcom,gpucc-sm6350.h>
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
18 #include "clk-regmap.h"
22 #define CX_GMU_CBCR_SLEEP_MASK 0xF
23 #define CX_GMU_CBCR_SLEEP_SHIFT 4
24 #define CX_GMU_CBCR_WAKE_MASK 0xF
25 #define CX_GMU_CBCR_WAKE_SHIFT 8
31 P_GPU_CC_PLL0_OUT_MAIN,
32 P_GPU_CC_PLL0_OUT_ODD,
33 P_GPU_CC_PLL1_OUT_EVEN,
34 P_GPU_CC_PLL1_OUT_MAIN,
35 P_GPU_CC_PLL1_OUT_ODD,
39 static const struct pll_vco fabia_vco[] = {
40 { 249600000, 2000000000, 0 },
43 /* 506MHz Configuration*/
44 static const struct alpha_pll_config gpu_cc_pll0_config = {
47 .config_ctl_val = 0x20485699,
48 .config_ctl_hi_val = 0x00002067,
49 .test_ctl_val = 0x40000000,
50 .test_ctl_hi_val = 0x00000002,
51 .user_ctl_val = 0x00000001,
52 .user_ctl_hi_val = 0x00004805,
55 static struct clk_alpha_pll gpu_cc_pll0 = {
57 .vco_table = fabia_vco,
58 .num_vco = ARRAY_SIZE(fabia_vco),
59 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
61 .hw.init = &(struct clk_init_data){
62 .name = "gpu_cc_pll0",
63 .parent_data = &(const struct clk_parent_data){
67 .ops = &clk_alpha_pll_fabia_ops,
72 static struct clk_fixed_factor crc_div = {
75 .hw.init = &(struct clk_init_data){
77 .parent_hws = (const struct clk_hw*[]){
81 .flags = CLK_SET_RATE_PARENT,
82 .ops = &clk_fixed_factor_ops,
86 /* 514MHz Configuration*/
87 static const struct alpha_pll_config gpu_cc_pll1_config = {
90 .config_ctl_val = 0x20485699,
91 .config_ctl_hi_val = 0x00002067,
92 .test_ctl_val = 0x40000000,
93 .test_ctl_hi_val = 0x00000002,
94 .user_ctl_val = 0x00000001,
95 .user_ctl_hi_val = 0x00004805,
98 static struct clk_alpha_pll gpu_cc_pll1 = {
100 .vco_table = fabia_vco,
101 .num_vco = ARRAY_SIZE(fabia_vco),
102 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
104 .hw.init = &(struct clk_init_data){
105 .name = "gpu_cc_pll1",
106 .parent_data = &(const struct clk_parent_data){
107 .fw_name = "bi_tcxo",
110 .ops = &clk_alpha_pll_fabia_ops,
115 static const struct parent_map gpu_cc_parent_map_0[] = {
117 { P_GPU_CC_PLL0_OUT_MAIN, 1 },
118 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
119 { P_GPLL0_OUT_MAIN, 5 },
120 { P_GPLL0_OUT_MAIN_DIV, 6 },
123 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
124 { .fw_name = "bi_tcxo" },
125 { .hw = &gpu_cc_pll0.clkr.hw },
126 { .hw = &gpu_cc_pll1.clkr.hw },
127 { .fw_name = "gcc_gpu_gpll0_clk" },
128 { .fw_name = "gcc_gpu_gpll0_div_clk" },
131 static const struct parent_map gpu_cc_parent_map_1[] = {
134 { P_GPU_CC_PLL0_OUT_ODD, 2 },
135 { P_GPU_CC_PLL1_OUT_EVEN, 3 },
136 { P_GPU_CC_PLL1_OUT_ODD, 4 },
137 { P_GPLL0_OUT_MAIN, 5 },
140 static const struct clk_parent_data gpu_cc_parent_data_1[] = {
141 { .fw_name = "bi_tcxo" },
142 { .hw = &crc_div.hw },
143 { .hw = &gpu_cc_pll0.clkr.hw },
144 { .hw = &gpu_cc_pll1.clkr.hw },
145 { .hw = &gpu_cc_pll1.clkr.hw },
146 { .fw_name = "gcc_gpu_gpll0_clk" },
149 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
150 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
154 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
158 .parent_map = gpu_cc_parent_map_0,
159 .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
160 .clkr.hw.init = &(struct clk_init_data){
161 .name = "gpu_cc_gmu_clk_src",
162 .parent_data = gpu_cc_parent_data_0,
163 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
164 .flags = CLK_SET_RATE_PARENT,
165 .ops = &clk_rcg2_ops,
169 static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
170 F(253000000, P_CRC_DIV, 1, 0, 0),
171 F(355000000, P_CRC_DIV, 1, 0, 0),
172 F(430000000, P_CRC_DIV, 1, 0, 0),
173 F(565000000, P_CRC_DIV, 1, 0, 0),
174 F(650000000, P_CRC_DIV, 1, 0, 0),
175 F(800000000, P_CRC_DIV, 1, 0, 0),
176 F(825000000, P_CRC_DIV, 1, 0, 0),
177 F(850000000, P_CRC_DIV, 1, 0, 0),
181 static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
185 .parent_map = gpu_cc_parent_map_1,
186 .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
187 .clkr.hw.init = &(struct clk_init_data){
188 .name = "gpu_cc_gx_gfx3d_clk_src",
189 .parent_data = gpu_cc_parent_data_1,
190 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
191 .flags = CLK_SET_RATE_PARENT,
192 .ops = &clk_rcg2_ops,
196 static struct clk_branch gpu_cc_acd_ahb_clk = {
198 .halt_check = BRANCH_HALT,
200 .enable_reg = 0x1168,
201 .enable_mask = BIT(0),
202 .hw.init = &(struct clk_init_data){
203 .name = "gpu_cc_acd_ahb_clk",
204 .ops = &clk_branch2_ops,
209 static struct clk_branch gpu_cc_acd_cxo_clk = {
211 .halt_check = BRANCH_HALT,
213 .enable_reg = 0x1164,
214 .enable_mask = BIT(0),
215 .hw.init = &(struct clk_init_data){
216 .name = "gpu_cc_acd_cxo_clk",
217 .ops = &clk_branch2_ops,
222 static struct clk_branch gpu_cc_ahb_clk = {
224 .halt_check = BRANCH_HALT_DELAY,
226 .enable_reg = 0x1078,
227 .enable_mask = BIT(0),
228 .hw.init = &(struct clk_init_data){
229 .name = "gpu_cc_ahb_clk",
230 .flags = CLK_IS_CRITICAL,
231 .ops = &clk_branch2_ops,
236 static struct clk_branch gpu_cc_crc_ahb_clk = {
238 .halt_check = BRANCH_HALT_DELAY,
240 .enable_reg = 0x107c,
241 .enable_mask = BIT(0),
242 .hw.init = &(struct clk_init_data){
243 .name = "gpu_cc_crc_ahb_clk",
244 .ops = &clk_branch2_ops,
249 static struct clk_branch gpu_cc_cx_gfx3d_clk = {
251 .halt_check = BRANCH_HALT_DELAY,
253 .enable_reg = 0x10a4,
254 .enable_mask = BIT(0),
255 .hw.init = &(struct clk_init_data){
256 .name = "gpu_cc_cx_gfx3d_clk",
257 .parent_hws = (const struct clk_hw*[]){
258 &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
261 .flags = CLK_SET_RATE_PARENT,
262 .ops = &clk_branch2_ops,
267 static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = {
269 .halt_check = BRANCH_HALT_DELAY,
271 .enable_reg = 0x10a8,
272 .enable_mask = BIT(0),
273 .hw.init = &(struct clk_init_data){
274 .name = "gpu_cc_cx_gfx3d_slv_clk",
275 .parent_hws = (const struct clk_hw*[]){
276 &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
279 .flags = CLK_SET_RATE_PARENT,
280 .ops = &clk_branch2_ops,
285 static struct clk_branch gpu_cc_cx_gmu_clk = {
287 .halt_check = BRANCH_HALT,
289 .enable_reg = 0x1098,
290 .enable_mask = BIT(0),
291 .hw.init = &(struct clk_init_data){
292 .name = "gpu_cc_cx_gmu_clk",
293 .parent_hws = (const struct clk_hw*[]){
294 &gpu_cc_gmu_clk_src.clkr.hw,
297 .flags = CLK_SET_RATE_PARENT,
298 .ops = &clk_branch2_ops,
303 static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
305 .halt_check = BRANCH_HALT_DELAY,
307 .enable_reg = 0x108c,
308 .enable_mask = BIT(0),
309 .hw.init = &(struct clk_init_data){
310 .name = "gpu_cc_cx_snoc_dvm_clk",
311 .ops = &clk_branch2_ops,
316 static struct clk_branch gpu_cc_cxo_aon_clk = {
318 .halt_check = BRANCH_HALT_DELAY,
320 .enable_reg = 0x1004,
321 .enable_mask = BIT(0),
322 .hw.init = &(struct clk_init_data){
323 .name = "gpu_cc_cxo_aon_clk",
324 .ops = &clk_branch2_ops,
329 static struct clk_branch gpu_cc_cxo_clk = {
331 .halt_check = BRANCH_HALT,
333 .enable_reg = 0x109c,
334 .enable_mask = BIT(0),
335 .hw.init = &(struct clk_init_data){
336 .name = "gpu_cc_cxo_clk",
337 .ops = &clk_branch2_ops,
342 static struct clk_branch gpu_cc_gx_cxo_clk = {
344 .halt_check = BRANCH_HALT,
346 .enable_reg = 0x1060,
347 .enable_mask = BIT(0),
348 .hw.init = &(struct clk_init_data){
349 .name = "gpu_cc_gx_cxo_clk",
350 .ops = &clk_branch2_ops,
355 static struct clk_branch gpu_cc_gx_gfx3d_clk = {
357 .halt_check = BRANCH_HALT_SKIP,
359 .enable_reg = 0x1054,
360 .enable_mask = BIT(0),
361 .hw.init = &(struct clk_init_data){
362 .name = "gpu_cc_gx_gfx3d_clk",
363 .parent_hws = (const struct clk_hw*[]){
364 &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
367 .flags = CLK_SET_RATE_PARENT,
368 .ops = &clk_branch2_ops,
373 static struct clk_branch gpu_cc_gx_gmu_clk = {
375 .halt_check = BRANCH_HALT,
377 .enable_reg = 0x1064,
378 .enable_mask = BIT(0),
379 .hw.init = &(struct clk_init_data){
380 .name = "gpu_cc_gx_gmu_clk",
381 .parent_hws = (const struct clk_hw*[]){
382 &gpu_cc_gmu_clk_src.clkr.hw,
385 .flags = CLK_SET_RATE_PARENT,
386 .ops = &clk_branch2_ops,
391 static struct clk_branch gpu_cc_gx_vsense_clk = {
393 .halt_check = BRANCH_HALT_DELAY,
395 .enable_reg = 0x1058,
396 .enable_mask = BIT(0),
397 .hw.init = &(struct clk_init_data){
398 .name = "gpu_cc_gx_vsense_clk",
399 .ops = &clk_branch2_ops,
404 static struct gdsc gpu_cx_gdsc = {
406 .gds_hw_ctrl = 0x1540,
408 .name = "gpu_cx_gdsc",
410 .pwrsts = PWRSTS_OFF_ON,
414 static struct gdsc gpu_gx_gdsc = {
416 .clamp_io_ctrl = 0x1508,
418 .name = "gpu_gx_gdsc",
419 .power_on = gdsc_gx_do_nothing_enable,
421 .pwrsts = PWRSTS_OFF_ON,
422 .flags = CLAMP_IO | POLL_CFG_GDSCR,
425 static struct clk_hw *gpu_cc_sm6350_hws[] = {
426 [GPU_CC_CRC_DIV] = &crc_div.hw,
429 static struct clk_regmap *gpu_cc_sm6350_clocks[] = {
430 [GPU_CC_ACD_AHB_CLK] = &gpu_cc_acd_ahb_clk.clkr,
431 [GPU_CC_ACD_CXO_CLK] = &gpu_cc_acd_cxo_clk.clkr,
432 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
433 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
434 [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
435 [GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr,
436 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
437 [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
438 [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
439 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
440 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
441 [GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
442 [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
443 [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
444 [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
445 [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
446 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
447 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
450 static struct gdsc *gpu_cc_sm6350_gdscs[] = {
451 [GPU_CX_GDSC] = &gpu_cx_gdsc,
452 [GPU_GX_GDSC] = &gpu_gx_gdsc,
455 static const struct regmap_config gpu_cc_sm6350_regmap_config = {
459 .max_register = 0x8008,
463 static const struct qcom_cc_desc gpu_cc_sm6350_desc = {
464 .config = &gpu_cc_sm6350_regmap_config,
465 .clk_hws = gpu_cc_sm6350_hws,
466 .num_clk_hws = ARRAY_SIZE(gpu_cc_sm6350_hws),
467 .clks = gpu_cc_sm6350_clocks,
468 .num_clks = ARRAY_SIZE(gpu_cc_sm6350_clocks),
469 .gdscs = gpu_cc_sm6350_gdscs,
470 .num_gdscs = ARRAY_SIZE(gpu_cc_sm6350_gdscs),
473 static const struct of_device_id gpu_cc_sm6350_match_table[] = {
474 { .compatible = "qcom,sm6350-gpucc" },
477 MODULE_DEVICE_TABLE(of, gpu_cc_sm6350_match_table);
479 static int gpu_cc_sm6350_probe(struct platform_device *pdev)
481 struct regmap *regmap;
482 unsigned int value, mask;
484 regmap = qcom_cc_map(pdev, &gpu_cc_sm6350_desc);
486 return PTR_ERR(regmap);
488 clk_fabia_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
489 clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
491 /* Configure gpu_cc_cx_gmu_clk with recommended wakeup/sleep settings */
492 mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
493 mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
494 value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
495 regmap_update_bits(regmap, 0x1098, mask, value);
497 return qcom_cc_really_probe(pdev, &gpu_cc_sm6350_desc, regmap);
500 static struct platform_driver gpu_cc_sm6350_driver = {
501 .probe = gpu_cc_sm6350_probe,
503 .name = "sm6350-gpucc",
504 .of_match_table = gpu_cc_sm6350_match_table,
508 static int __init gpu_cc_sm6350_init(void)
510 return platform_driver_register(&gpu_cc_sm6350_driver);
512 core_initcall(gpu_cc_sm6350_init);
514 static void __exit gpu_cc_sm6350_exit(void)
516 platform_driver_unregister(&gpu_cc_sm6350_driver);
518 module_exit(gpu_cc_sm6350_exit);
520 MODULE_DESCRIPTION("QTI GPU_CC LAGOON Driver");
521 MODULE_LICENSE("GPL v2");