1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
6 #include <linux/bitops.h>
7 #include <linux/delay.h>
9 #include <linux/jiffies.h>
10 #include <linux/kernel.h>
11 #include <linux/ktime.h>
12 #include <linux/pm_domain.h>
13 #include <linux/regmap.h>
14 #include <linux/reset-controller.h>
15 #include <linux/slab.h>
18 #define PWR_ON_MASK BIT(31)
19 #define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
20 #define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
21 #define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
22 #define SW_OVERRIDE_MASK BIT(2)
23 #define HW_CONTROL_MASK BIT(1)
24 #define SW_COLLAPSE_MASK BIT(0)
25 #define GMEM_CLAMP_IO_MASK BIT(0)
26 #define GMEM_RESET_MASK BIT(4)
29 #define GDSC_POWER_UP_COMPLETE BIT(16)
30 #define GDSC_POWER_DOWN_COMPLETE BIT(15)
31 #define CFG_GDSCR_OFFSET 0x4
33 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
34 #define EN_REST_WAIT_VAL (0x2 << 20)
35 #define EN_FEW_WAIT_VAL (0x8 << 16)
36 #define CLK_DIS_WAIT_VAL (0x2 << 12)
38 #define RETAIN_MEM BIT(14)
39 #define RETAIN_PERIPH BIT(13)
41 #define TIMEOUT_US 500
43 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
50 /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
51 static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
57 if (sc->flags & POLL_CFG_GDSCR)
58 reg = sc->gdscr + CFG_GDSCR_OFFSET;
59 else if (sc->gds_hw_ctrl)
60 reg = sc->gds_hw_ctrl;
64 ret = regmap_read(sc->regmap, reg, &val);
68 if (sc->flags & POLL_CFG_GDSCR) {
71 return !!(val & GDSC_POWER_UP_COMPLETE);
73 return !!(val & GDSC_POWER_DOWN_COMPLETE);
79 return !!(val & PWR_ON_MASK);
81 return !(val & PWR_ON_MASK);
87 static int gdsc_hwctrl(struct gdsc *sc, bool en)
89 u32 val = en ? HW_CONTROL_MASK : 0;
91 return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
94 static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
100 if (gdsc_check_status(sc, status))
102 } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
104 if (gdsc_check_status(sc, status))
110 static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
113 u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
115 ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
119 /* If disabling votable gdscs, don't poll on status */
120 if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
122 * Add a short delay here to ensure that an enable
123 * right after it was disabled does not put it in an
130 if (sc->gds_hw_ctrl) {
132 * The gds hw controller asserts/de-asserts the status bit soon
133 * after it receives a power on/off request from a master.
134 * The controller then takes around 8 xo cycles to start its
135 * internal state machine and update the status bit. During
136 * this time, the status bit does not reflect the true status
138 * Add a delay of 1 us between writing to the SW_COLLAPSE bit
139 * and polling the status bit.
144 return gdsc_poll_status(sc, status);
147 static inline int gdsc_deassert_reset(struct gdsc *sc)
151 for (i = 0; i < sc->reset_count; i++)
152 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
156 static inline int gdsc_assert_reset(struct gdsc *sc)
160 for (i = 0; i < sc->reset_count; i++)
161 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
165 static inline void gdsc_force_mem_on(struct gdsc *sc)
168 u32 mask = RETAIN_MEM | RETAIN_PERIPH;
170 for (i = 0; i < sc->cxc_count; i++)
171 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
174 static inline void gdsc_clear_mem_on(struct gdsc *sc)
177 u32 mask = RETAIN_MEM | RETAIN_PERIPH;
179 for (i = 0; i < sc->cxc_count; i++)
180 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
183 static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
185 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
186 GMEM_CLAMP_IO_MASK, 0);
189 static inline void gdsc_assert_clamp_io(struct gdsc *sc)
191 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
192 GMEM_CLAMP_IO_MASK, 1);
195 static inline void gdsc_assert_reset_aon(struct gdsc *sc)
197 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
200 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
203 static int gdsc_enable(struct generic_pm_domain *domain)
205 struct gdsc *sc = domain_to_gdsc(domain);
208 if (sc->pwrsts == PWRSTS_ON)
209 return gdsc_deassert_reset(sc);
211 if (sc->flags & SW_RESET) {
212 gdsc_assert_reset(sc);
214 gdsc_deassert_reset(sc);
217 if (sc->flags & CLAMP_IO) {
218 if (sc->flags & AON_RESET)
219 gdsc_assert_reset_aon(sc);
220 gdsc_deassert_clamp_io(sc);
223 ret = gdsc_toggle_logic(sc, GDSC_ON);
227 if (sc->pwrsts & PWRSTS_OFF)
228 gdsc_force_mem_on(sc);
231 * If clocks to this power domain were already on, they will take an
232 * additional 4 clock cycles to re-enable after the power domain is
233 * enabled. Delay to account for this. A delay is also needed to ensure
234 * clocks are not enabled within 400ns of enabling power to the
239 /* Turn on HW trigger mode if supported */
240 if (sc->flags & HW_CTRL) {
241 ret = gdsc_hwctrl(sc, true);
245 * Wait for the GDSC to go through a power down and
246 * up cycle. In case a firmware ends up polling status
247 * bits for the gdsc, it might read an 'on' status before
248 * the GDSC can finish the power cycle.
249 * We wait 1us before returning to ensure the firmware
250 * can't immediately poll the status bits.
258 static int gdsc_disable(struct generic_pm_domain *domain)
260 struct gdsc *sc = domain_to_gdsc(domain);
263 if (sc->pwrsts == PWRSTS_ON)
264 return gdsc_assert_reset(sc);
266 /* Turn off HW trigger mode if supported */
267 if (sc->flags & HW_CTRL) {
268 ret = gdsc_hwctrl(sc, false);
272 * Wait for the GDSC to go through a power down and
273 * up cycle. In case we end up polling status
274 * bits for the gdsc before the power cycle is completed
275 * it might read an 'on' status wrongly.
279 ret = gdsc_poll_status(sc, GDSC_ON);
284 if (sc->pwrsts & PWRSTS_OFF)
285 gdsc_clear_mem_on(sc);
287 ret = gdsc_toggle_logic(sc, GDSC_OFF);
291 if (sc->flags & CLAMP_IO)
292 gdsc_assert_clamp_io(sc);
297 static int gdsc_init(struct gdsc *sc)
303 * Disable HW trigger: collapse/restore occur based on registers writes.
304 * Disable SW override: Use hardware state-machine for sequencing.
305 * Configure wait time between states.
307 mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
308 EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
309 val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
310 ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
314 /* Force gdsc ON if only ON state is supported */
315 if (sc->pwrsts == PWRSTS_ON) {
316 ret = gdsc_toggle_logic(sc, GDSC_ON);
321 on = gdsc_check_status(sc, GDSC_ON);
326 * Votable GDSCs can be ON due to Vote from other masters.
327 * If a Votable GDSC is ON, make sure we have a Vote.
329 if ((sc->flags & VOTABLE) && on)
330 gdsc_enable(&sc->pd);
332 /* If ALWAYS_ON GDSCs are not ON, turn them ON */
333 if (sc->flags & ALWAYS_ON) {
335 gdsc_enable(&sc->pd);
337 sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
340 if (on || (sc->pwrsts & PWRSTS_RET))
341 gdsc_force_mem_on(sc);
343 gdsc_clear_mem_on(sc);
345 if (!sc->pd.power_off)
346 sc->pd.power_off = gdsc_disable;
347 if (!sc->pd.power_on)
348 sc->pd.power_on = gdsc_enable;
349 pm_genpd_init(&sc->pd, NULL, !on);
354 int gdsc_register(struct gdsc_desc *desc,
355 struct reset_controller_dev *rcdev, struct regmap *regmap)
358 struct genpd_onecell_data *data;
359 struct device *dev = desc->dev;
360 struct gdsc **scs = desc->scs;
361 size_t num = desc->num;
363 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
367 data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
372 data->num_domains = num;
373 for (i = 0; i < num; i++) {
376 scs[i]->regmap = regmap;
377 scs[i]->rcdev = rcdev;
378 ret = gdsc_init(scs[i]);
381 data->domains[i] = &scs[i]->pd;
385 for (i = 0; i < num; i++) {
389 pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
392 return of_genpd_add_provider_onecell(dev->of_node, data);
395 void gdsc_unregister(struct gdsc_desc *desc)
398 struct device *dev = desc->dev;
399 struct gdsc **scs = desc->scs;
400 size_t num = desc->num;
402 /* Remove subdomains */
403 for (i = 0; i < num; i++) {
407 pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
409 of_genpd_del_provider(dev->of_node);