1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2021, Linaro Limited
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
12 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
25 P_CORE_BI_PLL_TEST_SE,
33 P_UFS_CARD_RX_SYMBOL_0_CLK,
34 P_UFS_CARD_RX_SYMBOL_1_CLK,
35 P_UFS_CARD_TX_SYMBOL_0_CLK,
36 P_UFS_PHY_RX_SYMBOL_0_CLK,
37 P_UFS_PHY_RX_SYMBOL_1_CLK,
38 P_UFS_PHY_TX_SYMBOL_0_CLK,
39 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
40 P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,
43 static struct clk_alpha_pll gcc_gpll0 = {
45 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
47 .enable_reg = 0x52018,
48 .enable_mask = BIT(0),
49 .hw.init = &(struct clk_init_data){
51 .parent_data = &(const struct clk_parent_data){
55 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
60 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
65 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
68 .post_div_table = post_div_table_gcc_gpll0_out_even,
69 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
71 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
72 .clkr.hw.init = &(struct clk_init_data){
73 .name = "gcc_gpll0_out_even",
74 .parent_hws = (const struct clk_hw*[]){
78 .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,
82 static struct clk_alpha_pll gcc_gpll4 = {
84 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
86 .enable_reg = 0x52018,
87 .enable_mask = BIT(4),
88 .hw.init = &(struct clk_init_data){
90 .parent_data = &(const struct clk_parent_data){
95 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
100 static struct clk_alpha_pll gcc_gpll9 = {
102 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
104 .enable_reg = 0x52018,
105 .enable_mask = BIT(9),
106 .hw.init = &(struct clk_init_data){
108 .parent_data = &(const struct clk_parent_data){
109 .fw_name = "bi_tcxo",
113 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
118 static const struct parent_map gcc_parent_map_0[] = {
120 { P_GCC_GPLL0_OUT_MAIN, 1 },
121 { P_GCC_GPLL0_OUT_EVEN, 6 },
122 { P_CORE_BI_PLL_TEST_SE, 7 },
125 static const struct clk_parent_data gcc_parent_data_0[] = {
126 { .fw_name = "bi_tcxo" },
127 { .hw = &gcc_gpll0.clkr.hw },
128 { .hw = &gcc_gpll0_out_even.clkr.hw },
129 { .fw_name = "core_bi_pll_test_se" },
132 static const struct parent_map gcc_parent_map_1[] = {
134 { P_GCC_GPLL0_OUT_MAIN, 1 },
136 { P_GCC_GPLL0_OUT_EVEN, 6 },
137 { P_CORE_BI_PLL_TEST_SE, 7 },
140 static const struct clk_parent_data gcc_parent_data_1[] = {
141 { .fw_name = "bi_tcxo" },
142 { .hw = &gcc_gpll0.clkr.hw },
143 { .fw_name = "sleep_clk" },
144 { .hw = &gcc_gpll0_out_even.clkr.hw },
145 { .fw_name = "core_bi_pll_test_se" },
148 static const struct parent_map gcc_parent_map_2[] = {
151 { P_CORE_BI_PLL_TEST_SE, 7 },
154 static const struct clk_parent_data gcc_parent_data_2[] = {
155 { .fw_name = "bi_tcxo" },
156 { .fw_name = "sleep_clk" },
157 { .fw_name = "core_bi_pll_test_se" },
160 static const struct parent_map gcc_parent_map_3[] = {
162 { P_CORE_BI_PLL_TEST_SE, 7 },
165 static const struct clk_parent_data gcc_parent_data_3[] = {
166 { .fw_name = "bi_tcxo" },
167 { .fw_name = "core_bi_pll_test_se" },
170 static const struct parent_map gcc_parent_map_4[] = {
171 { P_PCIE_0_PIPE_CLK, 0 },
175 static const struct clk_parent_data gcc_parent_data_4[] = {
176 { .fw_name = "pcie_0_pipe_clk", },
177 { .fw_name = "bi_tcxo" },
180 static const struct parent_map gcc_parent_map_5[] = {
181 { P_PCIE_1_PIPE_CLK, 0 },
185 static const struct clk_parent_data gcc_parent_data_5[] = {
186 { .fw_name = "pcie_1_pipe_clk" },
187 { .fw_name = "bi_tcxo" },
190 static const struct parent_map gcc_parent_map_6[] = {
192 { P_GCC_GPLL0_OUT_MAIN, 1 },
193 { P_GCC_GPLL9_OUT_MAIN, 2 },
194 { P_GCC_GPLL4_OUT_MAIN, 5 },
195 { P_GCC_GPLL0_OUT_EVEN, 6 },
196 { P_CORE_BI_PLL_TEST_SE, 7 },
199 static const struct clk_parent_data gcc_parent_data_6[] = {
200 { .fw_name = "bi_tcxo" },
201 { .hw = &gcc_gpll0.clkr.hw },
202 { .hw = &gcc_gpll9.clkr.hw },
203 { .hw = &gcc_gpll4.clkr.hw },
204 { .hw = &gcc_gpll0_out_even.clkr.hw },
205 { .fw_name = "core_bi_pll_test_se" },
208 static const struct parent_map gcc_parent_map_7[] = {
209 { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
213 static const struct clk_parent_data gcc_parent_data_7[] = {
214 { .fw_name = "ufs_card_rx_symbol_0_clk" },
215 { .fw_name = "bi_tcxo" },
218 static const struct parent_map gcc_parent_map_8[] = {
219 { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
223 static const struct clk_parent_data gcc_parent_data_8[] = {
224 { .fw_name = "ufs_card_rx_symbol_1_clk" },
225 { .fw_name = "bi_tcxo" },
228 static const struct parent_map gcc_parent_map_9[] = {
229 { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
233 static const struct clk_parent_data gcc_parent_data_9[] = {
234 { .fw_name = "ufs_card_tx_symbol_0_clk" },
235 { .fw_name = "bi_tcxo" },
238 static const struct parent_map gcc_parent_map_10[] = {
239 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
243 static const struct clk_parent_data gcc_parent_data_10[] = {
244 { .fw_name = "ufs_phy_rx_symbol_0_clk" },
245 { .fw_name = "bi_tcxo" },
248 static const struct parent_map gcc_parent_map_11[] = {
249 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
253 static const struct clk_parent_data gcc_parent_data_11[] = {
254 { .fw_name = "ufs_phy_rx_symbol_1_clk" },
255 { .fw_name = "bi_tcxo" },
258 static const struct parent_map gcc_parent_map_12[] = {
259 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
263 static const struct clk_parent_data gcc_parent_data_12[] = {
264 { .fw_name = "ufs_phy_tx_symbol_0_clk" },
265 { .fw_name = "bi_tcxo" },
268 static const struct parent_map gcc_parent_map_13[] = {
269 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
270 { P_CORE_BI_PLL_TEST_SE, 1 },
274 static const struct clk_parent_data gcc_parent_data_13[] = {
275 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
276 { .fw_name = "core_bi_pll_test_se" },
277 { .fw_name = "bi_tcxo" },
280 static const struct parent_map gcc_parent_map_14[] = {
281 { P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 },
282 { P_CORE_BI_PLL_TEST_SE, 1 },
286 static const struct clk_parent_data gcc_parent_data_14[] = {
287 { .fw_name = "usb3_uni_phy_sec_gcc_usb30_pipe_clk" },
288 { .fw_name = "core_bi_pll_test_se" },
289 { .fw_name = "bi_tcxo" },
292 static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
296 .parent_map = gcc_parent_map_4,
298 .hw.init = &(struct clk_init_data){
299 .name = "gcc_pcie_0_pipe_clk_src",
300 .parent_data = gcc_parent_data_4,
301 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
302 .ops = &clk_regmap_mux_closest_ops,
307 static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
311 .parent_map = gcc_parent_map_5,
313 .hw.init = &(struct clk_init_data){
314 .name = "gcc_pcie_1_pipe_clk_src",
315 .parent_data = gcc_parent_data_5,
316 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
317 .ops = &clk_regmap_mux_closest_ops,
322 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = {
326 .parent_map = gcc_parent_map_7,
328 .hw.init = &(struct clk_init_data){
329 .name = "gcc_ufs_card_rx_symbol_0_clk_src",
330 .parent_data = gcc_parent_data_7,
331 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
332 .ops = &clk_regmap_mux_closest_ops,
337 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = {
341 .parent_map = gcc_parent_map_8,
343 .hw.init = &(struct clk_init_data){
344 .name = "gcc_ufs_card_rx_symbol_1_clk_src",
345 .parent_data = gcc_parent_data_8,
346 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
347 .ops = &clk_regmap_mux_closest_ops,
352 static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = {
356 .parent_map = gcc_parent_map_9,
358 .hw.init = &(struct clk_init_data){
359 .name = "gcc_ufs_card_tx_symbol_0_clk_src",
360 .parent_data = gcc_parent_data_9,
361 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
362 .ops = &clk_regmap_mux_closest_ops,
367 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
371 .parent_map = gcc_parent_map_10,
373 .hw.init = &(struct clk_init_data){
374 .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
375 .parent_data = gcc_parent_data_10,
376 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
377 .ops = &clk_regmap_mux_closest_ops,
382 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
386 .parent_map = gcc_parent_map_11,
388 .hw.init = &(struct clk_init_data){
389 .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
390 .parent_data = gcc_parent_data_11,
391 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
392 .ops = &clk_regmap_mux_closest_ops,
397 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
401 .parent_map = gcc_parent_map_12,
403 .hw.init = &(struct clk_init_data){
404 .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
405 .parent_data = gcc_parent_data_12,
406 .num_parents = ARRAY_SIZE(gcc_parent_data_12),
407 .ops = &clk_regmap_mux_closest_ops,
412 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
416 .parent_map = gcc_parent_map_13,
418 .hw.init = &(struct clk_init_data){
419 .name = "gcc_usb3_prim_phy_pipe_clk_src",
420 .parent_data = gcc_parent_data_13,
421 .num_parents = ARRAY_SIZE(gcc_parent_data_13),
422 .ops = &clk_regmap_mux_closest_ops,
427 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
431 .parent_map = gcc_parent_map_14,
433 .hw.init = &(struct clk_init_data){
434 .name = "gcc_usb3_sec_phy_pipe_clk_src",
435 .parent_data = gcc_parent_data_14,
436 .num_parents = ARRAY_SIZE(gcc_parent_data_14),
437 .ops = &clk_regmap_mux_closest_ops,
442 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
443 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
444 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
445 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
449 static struct clk_rcg2 gcc_gp1_clk_src = {
453 .parent_map = gcc_parent_map_1,
454 .freq_tbl = ftbl_gcc_gp1_clk_src,
455 .clkr.hw.init = &(struct clk_init_data){
456 .name = "gcc_gp1_clk_src",
457 .parent_data = gcc_parent_data_1,
458 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
459 .flags = CLK_SET_RATE_PARENT,
460 .ops = &clk_rcg2_ops,
464 static struct clk_rcg2 gcc_gp2_clk_src = {
468 .parent_map = gcc_parent_map_1,
469 .freq_tbl = ftbl_gcc_gp1_clk_src,
470 .clkr.hw.init = &(struct clk_init_data){
471 .name = "gcc_gp2_clk_src",
472 .parent_data = gcc_parent_data_1,
473 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
474 .flags = CLK_SET_RATE_PARENT,
475 .ops = &clk_rcg2_ops,
479 static struct clk_rcg2 gcc_gp3_clk_src = {
483 .parent_map = gcc_parent_map_1,
484 .freq_tbl = ftbl_gcc_gp1_clk_src,
485 .clkr.hw.init = &(struct clk_init_data){
486 .name = "gcc_gp3_clk_src",
487 .parent_data = gcc_parent_data_1,
488 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
489 .flags = CLK_SET_RATE_PARENT,
490 .ops = &clk_rcg2_ops,
494 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
495 F(9600000, P_BI_TCXO, 2, 0, 0),
496 F(19200000, P_BI_TCXO, 1, 0, 0),
500 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
504 .parent_map = gcc_parent_map_2,
505 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
506 .clkr.hw.init = &(struct clk_init_data){
507 .name = "gcc_pcie_0_aux_clk_src",
508 .parent_data = gcc_parent_data_2,
509 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
510 .flags = CLK_SET_RATE_PARENT,
511 .ops = &clk_rcg2_ops,
515 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
516 F(19200000, P_BI_TCXO, 1, 0, 0),
517 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
521 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
525 .parent_map = gcc_parent_map_0,
526 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
527 .clkr.hw.init = &(struct clk_init_data){
528 .name = "gcc_pcie_0_phy_rchng_clk_src",
529 .parent_data = gcc_parent_data_0,
530 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
531 .flags = CLK_SET_RATE_PARENT,
532 .ops = &clk_rcg2_ops,
536 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
540 .parent_map = gcc_parent_map_2,
541 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
542 .clkr.hw.init = &(struct clk_init_data){
543 .name = "gcc_pcie_1_aux_clk_src",
544 .parent_data = gcc_parent_data_2,
545 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
546 .flags = CLK_SET_RATE_PARENT,
547 .ops = &clk_rcg2_ops,
551 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
555 .parent_map = gcc_parent_map_0,
556 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
557 .clkr.hw.init = &(struct clk_init_data){
558 .name = "gcc_pcie_1_phy_rchng_clk_src",
559 .parent_data = gcc_parent_data_0,
560 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
561 .flags = CLK_SET_RATE_PARENT,
562 .ops = &clk_rcg2_ops,
566 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
567 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
571 static struct clk_rcg2 gcc_pdm2_clk_src = {
575 .parent_map = gcc_parent_map_0,
576 .freq_tbl = ftbl_gcc_pdm2_clk_src,
577 .clkr.hw.init = &(struct clk_init_data){
578 .name = "gcc_pdm2_clk_src",
579 .parent_data = gcc_parent_data_0,
580 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
581 .flags = CLK_SET_RATE_PARENT,
582 .ops = &clk_rcg2_ops,
586 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
587 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
588 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
589 F(19200000, P_BI_TCXO, 1, 0, 0),
590 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
591 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
592 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
593 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
594 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
595 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
596 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
597 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
601 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
602 .name = "gcc_qupv3_wrap0_s0_clk_src",
603 .parent_data = gcc_parent_data_0,
604 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
605 .flags = CLK_SET_RATE_PARENT,
606 .ops = &clk_rcg2_ops,
609 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
613 .parent_map = gcc_parent_map_0,
614 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
615 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
618 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
619 .name = "gcc_qupv3_wrap0_s1_clk_src",
620 .parent_data = gcc_parent_data_0,
621 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
622 .flags = CLK_SET_RATE_PARENT,
623 .ops = &clk_rcg2_ops,
626 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
630 .parent_map = gcc_parent_map_0,
631 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
632 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
635 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
636 .name = "gcc_qupv3_wrap0_s2_clk_src",
637 .parent_data = gcc_parent_data_0,
638 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
639 .flags = CLK_SET_RATE_PARENT,
640 .ops = &clk_rcg2_ops,
643 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
647 .parent_map = gcc_parent_map_0,
648 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
649 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
652 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
653 .name = "gcc_qupv3_wrap0_s3_clk_src",
654 .parent_data = gcc_parent_data_0,
655 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
656 .flags = CLK_SET_RATE_PARENT,
657 .ops = &clk_rcg2_ops,
660 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
664 .parent_map = gcc_parent_map_0,
665 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
666 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
669 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
670 .name = "gcc_qupv3_wrap0_s4_clk_src",
671 .parent_data = gcc_parent_data_0,
672 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
673 .flags = CLK_SET_RATE_PARENT,
674 .ops = &clk_rcg2_ops,
677 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
681 .parent_map = gcc_parent_map_0,
682 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
683 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
686 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
687 .name = "gcc_qupv3_wrap0_s5_clk_src",
688 .parent_data = gcc_parent_data_0,
689 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
690 .flags = CLK_SET_RATE_PARENT,
691 .ops = &clk_rcg2_ops,
694 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
698 .parent_map = gcc_parent_map_0,
699 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
700 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
703 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
704 .name = "gcc_qupv3_wrap0_s6_clk_src",
705 .parent_data = gcc_parent_data_0,
706 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
707 .flags = CLK_SET_RATE_PARENT,
708 .ops = &clk_rcg2_ops,
711 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
715 .parent_map = gcc_parent_map_0,
716 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
717 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
720 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
721 .name = "gcc_qupv3_wrap0_s7_clk_src",
722 .parent_data = gcc_parent_data_0,
723 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
724 .flags = CLK_SET_RATE_PARENT,
725 .ops = &clk_rcg2_ops,
728 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
732 .parent_map = gcc_parent_map_0,
733 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
734 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
737 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
738 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
739 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
740 F(19200000, P_BI_TCXO, 1, 0, 0),
741 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
742 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
743 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
744 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
745 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
746 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
747 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
748 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
749 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
750 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
751 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
752 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
756 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
757 .name = "gcc_qupv3_wrap1_s0_clk_src",
758 .parent_data = gcc_parent_data_0,
759 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
760 .flags = CLK_SET_RATE_PARENT,
761 .ops = &clk_rcg2_ops,
764 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
768 .parent_map = gcc_parent_map_0,
769 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
770 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
773 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
774 .name = "gcc_qupv3_wrap1_s1_clk_src",
775 .parent_data = gcc_parent_data_0,
776 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
777 .flags = CLK_SET_RATE_PARENT,
778 .ops = &clk_rcg2_ops,
781 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
785 .parent_map = gcc_parent_map_0,
786 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
787 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
790 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
791 .name = "gcc_qupv3_wrap1_s2_clk_src",
792 .parent_data = gcc_parent_data_0,
793 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
794 .flags = CLK_SET_RATE_PARENT,
795 .ops = &clk_rcg2_ops,
798 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
802 .parent_map = gcc_parent_map_0,
803 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
804 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
807 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
808 .name = "gcc_qupv3_wrap1_s3_clk_src",
809 .parent_data = gcc_parent_data_0,
810 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
811 .flags = CLK_SET_RATE_PARENT,
812 .ops = &clk_rcg2_ops,
815 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
819 .parent_map = gcc_parent_map_0,
820 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
821 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
824 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
825 .name = "gcc_qupv3_wrap1_s4_clk_src",
826 .parent_data = gcc_parent_data_0,
827 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
828 .flags = CLK_SET_RATE_PARENT,
829 .ops = &clk_rcg2_ops,
832 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
836 .parent_map = gcc_parent_map_0,
837 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
838 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
841 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
842 .name = "gcc_qupv3_wrap1_s5_clk_src",
843 .parent_data = gcc_parent_data_0,
844 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
845 .flags = CLK_SET_RATE_PARENT,
846 .ops = &clk_rcg2_ops,
849 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
853 .parent_map = gcc_parent_map_0,
854 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
855 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
858 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
859 .name = "gcc_qupv3_wrap2_s0_clk_src",
860 .parent_data = gcc_parent_data_0,
861 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
862 .flags = CLK_SET_RATE_PARENT,
863 .ops = &clk_rcg2_ops,
866 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
870 .parent_map = gcc_parent_map_0,
871 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
872 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
875 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
876 .name = "gcc_qupv3_wrap2_s1_clk_src",
877 .parent_data = gcc_parent_data_0,
878 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
879 .flags = CLK_SET_RATE_PARENT,
880 .ops = &clk_rcg2_ops,
883 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
887 .parent_map = gcc_parent_map_0,
888 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
889 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
892 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
893 .name = "gcc_qupv3_wrap2_s2_clk_src",
894 .parent_data = gcc_parent_data_0,
895 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
896 .flags = CLK_SET_RATE_PARENT,
897 .ops = &clk_rcg2_ops,
900 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
904 .parent_map = gcc_parent_map_0,
905 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
906 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
909 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
910 .name = "gcc_qupv3_wrap2_s3_clk_src",
911 .parent_data = gcc_parent_data_0,
912 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
913 .flags = CLK_SET_RATE_PARENT,
914 .ops = &clk_rcg2_ops,
917 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
921 .parent_map = gcc_parent_map_0,
922 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
923 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
926 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
927 .name = "gcc_qupv3_wrap2_s4_clk_src",
928 .parent_data = gcc_parent_data_0,
929 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
930 .flags = CLK_SET_RATE_PARENT,
931 .ops = &clk_rcg2_ops,
934 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
938 .parent_map = gcc_parent_map_0,
939 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
940 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
943 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
944 .name = "gcc_qupv3_wrap2_s5_clk_src",
945 .parent_data = gcc_parent_data_0,
946 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
947 .flags = CLK_SET_RATE_PARENT,
948 .ops = &clk_rcg2_ops,
951 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
955 .parent_map = gcc_parent_map_0,
956 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
957 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
960 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
961 F(400000, P_BI_TCXO, 12, 1, 4),
962 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
963 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
964 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
965 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
969 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
973 .parent_map = gcc_parent_map_6,
974 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
975 .clkr.hw.init = &(struct clk_init_data){
976 .name = "gcc_sdcc2_apps_clk_src",
977 .parent_data = gcc_parent_data_6,
978 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
979 .flags = CLK_SET_RATE_PARENT,
980 .ops = &clk_rcg2_floor_ops,
984 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
985 F(400000, P_BI_TCXO, 12, 1, 4),
986 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
987 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
991 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
995 .parent_map = gcc_parent_map_0,
996 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
997 .clkr.hw.init = &(struct clk_init_data){
998 .name = "gcc_sdcc4_apps_clk_src",
999 .parent_data = gcc_parent_data_0,
1000 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1001 .flags = CLK_SET_RATE_PARENT,
1002 .ops = &clk_rcg2_floor_ops,
1006 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
1007 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1008 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1009 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1010 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1014 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
1015 .cmd_rcgr = 0x75024,
1018 .parent_map = gcc_parent_map_0,
1019 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1020 .clkr.hw.init = &(struct clk_init_data){
1021 .name = "gcc_ufs_card_axi_clk_src",
1022 .parent_data = gcc_parent_data_0,
1023 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1024 .flags = CLK_SET_RATE_PARENT,
1025 .ops = &clk_rcg2_ops,
1029 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
1030 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1031 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1032 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1036 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
1037 .cmd_rcgr = 0x7506c,
1040 .parent_map = gcc_parent_map_0,
1041 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1042 .clkr.hw.init = &(struct clk_init_data){
1043 .name = "gcc_ufs_card_ice_core_clk_src",
1044 .parent_data = gcc_parent_data_0,
1045 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1046 .flags = CLK_SET_RATE_PARENT,
1047 .ops = &clk_rcg2_ops,
1051 static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
1052 F(19200000, P_BI_TCXO, 1, 0, 0),
1056 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
1057 .cmd_rcgr = 0x750a0,
1060 .parent_map = gcc_parent_map_3,
1061 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1062 .clkr.hw.init = &(struct clk_init_data){
1063 .name = "gcc_ufs_card_phy_aux_clk_src",
1064 .parent_data = gcc_parent_data_3,
1065 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1066 .flags = CLK_SET_RATE_PARENT,
1067 .ops = &clk_rcg2_ops,
1071 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
1072 .cmd_rcgr = 0x75084,
1075 .parent_map = gcc_parent_map_0,
1076 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1077 .clkr.hw.init = &(struct clk_init_data){
1078 .name = "gcc_ufs_card_unipro_core_clk_src",
1079 .parent_data = gcc_parent_data_0,
1080 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1081 .flags = CLK_SET_RATE_PARENT,
1082 .ops = &clk_rcg2_ops,
1086 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1087 .cmd_rcgr = 0x77024,
1090 .parent_map = gcc_parent_map_0,
1091 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1092 .clkr.hw.init = &(struct clk_init_data){
1093 .name = "gcc_ufs_phy_axi_clk_src",
1094 .parent_data = gcc_parent_data_0,
1095 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1096 .flags = CLK_SET_RATE_PARENT,
1097 .ops = &clk_rcg2_ops,
1101 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1102 .cmd_rcgr = 0x7706c,
1105 .parent_map = gcc_parent_map_0,
1106 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1107 .clkr.hw.init = &(struct clk_init_data){
1108 .name = "gcc_ufs_phy_ice_core_clk_src",
1109 .parent_data = gcc_parent_data_0,
1110 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1111 .flags = CLK_SET_RATE_PARENT,
1112 .ops = &clk_rcg2_ops,
1116 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1117 .cmd_rcgr = 0x770a0,
1120 .parent_map = gcc_parent_map_3,
1121 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1122 .clkr.hw.init = &(struct clk_init_data){
1123 .name = "gcc_ufs_phy_phy_aux_clk_src",
1124 .parent_data = gcc_parent_data_3,
1125 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1126 .flags = CLK_SET_RATE_PARENT,
1127 .ops = &clk_rcg2_ops,
1131 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1132 .cmd_rcgr = 0x77084,
1135 .parent_map = gcc_parent_map_0,
1136 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1137 .clkr.hw.init = &(struct clk_init_data){
1138 .name = "gcc_ufs_phy_unipro_core_clk_src",
1139 .parent_data = gcc_parent_data_0,
1140 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1141 .flags = CLK_SET_RATE_PARENT,
1142 .ops = &clk_rcg2_ops,
1146 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1147 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1148 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1149 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1150 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1154 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1158 .parent_map = gcc_parent_map_0,
1159 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1160 .clkr.hw.init = &(struct clk_init_data){
1161 .name = "gcc_usb30_prim_master_clk_src",
1162 .parent_data = gcc_parent_data_0,
1163 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1164 .flags = CLK_SET_RATE_PARENT,
1165 .ops = &clk_rcg2_ops,
1169 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1173 .parent_map = gcc_parent_map_0,
1174 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1175 .clkr.hw.init = &(struct clk_init_data){
1176 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1177 .parent_data = gcc_parent_data_0,
1178 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1179 .flags = CLK_SET_RATE_PARENT,
1180 .ops = &clk_rcg2_ops,
1184 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1185 .cmd_rcgr = 0x10020,
1188 .parent_map = gcc_parent_map_0,
1189 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1190 .clkr.hw.init = &(struct clk_init_data){
1191 .name = "gcc_usb30_sec_master_clk_src",
1192 .parent_data = gcc_parent_data_0,
1193 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1194 .flags = CLK_SET_RATE_PARENT,
1195 .ops = &clk_rcg2_ops,
1199 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1200 .cmd_rcgr = 0x10038,
1203 .parent_map = gcc_parent_map_0,
1204 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1205 .clkr.hw.init = &(struct clk_init_data){
1206 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1207 .parent_data = gcc_parent_data_0,
1208 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1209 .flags = CLK_SET_RATE_PARENT,
1210 .ops = &clk_rcg2_ops,
1214 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1218 .parent_map = gcc_parent_map_2,
1219 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1220 .clkr.hw.init = &(struct clk_init_data){
1221 .name = "gcc_usb3_prim_phy_aux_clk_src",
1222 .parent_data = gcc_parent_data_2,
1223 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1224 .flags = CLK_SET_RATE_PARENT,
1225 .ops = &clk_rcg2_ops,
1229 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1230 .cmd_rcgr = 0x10064,
1233 .parent_map = gcc_parent_map_2,
1234 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1235 .clkr.hw.init = &(struct clk_init_data){
1236 .name = "gcc_usb3_sec_phy_aux_clk_src",
1237 .parent_data = gcc_parent_data_2,
1238 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1239 .flags = CLK_SET_RATE_PARENT,
1240 .ops = &clk_rcg2_ops,
1244 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1248 .clkr.hw.init = &(struct clk_init_data) {
1249 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1250 .parent_hws = (const struct clk_hw*[]){
1251 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1254 .flags = CLK_SET_RATE_PARENT,
1255 .ops = &clk_regmap_div_ro_ops,
1259 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
1263 .clkr.hw.init = &(struct clk_init_data) {
1264 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
1265 .parent_hws = (const struct clk_hw*[]){
1266 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
1269 .flags = CLK_SET_RATE_PARENT,
1270 .ops = &clk_regmap_div_ro_ops,
1274 /* external clocks so add BRANCH_HALT_SKIP */
1275 static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1276 .halt_reg = 0x6b080,
1277 .halt_check = BRANCH_HALT_SKIP,
1279 .enable_reg = 0x52000,
1280 .enable_mask = BIT(12),
1281 .hw.init = &(struct clk_init_data){
1282 .name = "gcc_aggre_noc_pcie_0_axi_clk",
1283 .ops = &clk_branch2_ops,
1288 /* external clocks so add BRANCH_HALT_SKIP */
1289 static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
1290 .halt_reg = 0x8d084,
1291 .halt_check = BRANCH_HALT_SKIP,
1293 .enable_reg = 0x52000,
1294 .enable_mask = BIT(11),
1295 .hw.init = &(struct clk_init_data){
1296 .name = "gcc_aggre_noc_pcie_1_axi_clk",
1297 .ops = &clk_branch2_ops,
1302 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1303 .halt_reg = 0x9000c,
1304 .halt_check = BRANCH_HALT_VOTED,
1305 .hwcg_reg = 0x9000c,
1308 .enable_reg = 0x52000,
1309 .enable_mask = BIT(18),
1310 .hw.init = &(struct clk_init_data){
1311 .name = "gcc_aggre_noc_pcie_tbu_clk",
1312 .ops = &clk_branch2_ops,
1317 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1318 .halt_reg = 0x750cc,
1319 .halt_check = BRANCH_HALT_VOTED,
1320 .hwcg_reg = 0x750cc,
1323 .enable_reg = 0x750cc,
1324 .enable_mask = BIT(0),
1325 .hw.init = &(struct clk_init_data){
1326 .name = "gcc_aggre_ufs_card_axi_clk",
1327 .parent_hws = (const struct clk_hw*[]){
1328 &gcc_ufs_card_axi_clk_src.clkr.hw,
1331 .flags = CLK_SET_RATE_PARENT,
1332 .ops = &clk_branch2_ops,
1337 static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1338 .halt_reg = 0x750cc,
1339 .halt_check = BRANCH_HALT_VOTED,
1340 .hwcg_reg = 0x750cc,
1343 .enable_reg = 0x750cc,
1344 .enable_mask = BIT(1),
1345 .hw.init = &(struct clk_init_data){
1346 .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1347 .parent_hws = (const struct clk_hw*[]){
1348 &gcc_ufs_card_axi_clk_src.clkr.hw,
1351 .flags = CLK_SET_RATE_PARENT,
1352 .ops = &clk_branch2_ops,
1357 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1358 .halt_reg = 0x770cc,
1359 .halt_check = BRANCH_HALT_VOTED,
1360 .hwcg_reg = 0x770cc,
1363 .enable_reg = 0x770cc,
1364 .enable_mask = BIT(0),
1365 .hw.init = &(struct clk_init_data){
1366 .name = "gcc_aggre_ufs_phy_axi_clk",
1367 .parent_hws = (const struct clk_hw*[]){
1368 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1371 .flags = CLK_SET_RATE_PARENT,
1372 .ops = &clk_branch2_ops,
1377 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1378 .halt_reg = 0x770cc,
1379 .halt_check = BRANCH_HALT_VOTED,
1380 .hwcg_reg = 0x770cc,
1383 .enable_reg = 0x770cc,
1384 .enable_mask = BIT(1),
1385 .hw.init = &(struct clk_init_data){
1386 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1387 .parent_hws = (const struct clk_hw*[]){
1388 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1391 .flags = CLK_SET_RATE_PARENT,
1392 .ops = &clk_branch2_ops,
1397 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1399 .halt_check = BRANCH_HALT_VOTED,
1403 .enable_reg = 0xf080,
1404 .enable_mask = BIT(0),
1405 .hw.init = &(struct clk_init_data){
1406 .name = "gcc_aggre_usb3_prim_axi_clk",
1407 .parent_hws = (const struct clk_hw*[]){
1408 &gcc_usb30_prim_master_clk_src.clkr.hw,
1411 .flags = CLK_SET_RATE_PARENT,
1412 .ops = &clk_branch2_ops,
1417 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1418 .halt_reg = 0x10080,
1419 .halt_check = BRANCH_HALT_VOTED,
1420 .hwcg_reg = 0x10080,
1423 .enable_reg = 0x10080,
1424 .enable_mask = BIT(0),
1425 .hw.init = &(struct clk_init_data){
1426 .name = "gcc_aggre_usb3_sec_axi_clk",
1427 .parent_hws = (const struct clk_hw*[]){
1428 &gcc_usb30_sec_master_clk_src.clkr.hw,
1431 .flags = CLK_SET_RATE_PARENT,
1432 .ops = &clk_branch2_ops,
1437 static struct clk_branch gcc_boot_rom_ahb_clk = {
1438 .halt_reg = 0x38004,
1439 .halt_check = BRANCH_HALT_VOTED,
1440 .hwcg_reg = 0x38004,
1443 .enable_reg = 0x52000,
1444 .enable_mask = BIT(10),
1445 .hw.init = &(struct clk_init_data){
1446 .name = "gcc_boot_rom_ahb_clk",
1447 .ops = &clk_branch2_ops,
1452 /* external clocks so add BRANCH_HALT_SKIP */
1453 static struct clk_branch gcc_camera_hf_axi_clk = {
1454 .halt_reg = 0x26010,
1455 .halt_check = BRANCH_HALT_SKIP,
1456 .hwcg_reg = 0x26010,
1459 .enable_reg = 0x26010,
1460 .enable_mask = BIT(0),
1461 .hw.init = &(struct clk_init_data){
1462 .name = "gcc_camera_hf_axi_clk",
1463 .ops = &clk_branch2_ops,
1468 /* external clocks so add BRANCH_HALT_SKIP */
1469 static struct clk_branch gcc_camera_sf_axi_clk = {
1470 .halt_reg = 0x26014,
1471 .halt_check = BRANCH_HALT_SKIP,
1472 .hwcg_reg = 0x26014,
1475 .enable_reg = 0x26014,
1476 .enable_mask = BIT(0),
1477 .hw.init = &(struct clk_init_data){
1478 .name = "gcc_camera_sf_axi_clk",
1479 .ops = &clk_branch2_ops,
1484 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1486 .halt_check = BRANCH_HALT_VOTED,
1490 .enable_reg = 0xf07c,
1491 .enable_mask = BIT(0),
1492 .hw.init = &(struct clk_init_data){
1493 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1494 .parent_hws = (const struct clk_hw*[]){
1495 &gcc_usb30_prim_master_clk_src.clkr.hw,
1498 .flags = CLK_SET_RATE_PARENT,
1499 .ops = &clk_branch2_ops,
1504 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1505 .halt_reg = 0x1007c,
1506 .halt_check = BRANCH_HALT_VOTED,
1507 .hwcg_reg = 0x1007c,
1510 .enable_reg = 0x1007c,
1511 .enable_mask = BIT(0),
1512 .hw.init = &(struct clk_init_data){
1513 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1514 .parent_hws = (const struct clk_hw*[]){
1515 &gcc_usb30_sec_master_clk_src.clkr.hw,
1518 .flags = CLK_SET_RATE_PARENT,
1519 .ops = &clk_branch2_ops,
1524 /* external clocks so add BRANCH_HALT_SKIP */
1525 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1526 .halt_reg = 0x71154,
1527 .halt_check = BRANCH_HALT_SKIP,
1528 .hwcg_reg = 0x71154,
1531 .enable_reg = 0x71154,
1532 .enable_mask = BIT(0),
1533 .hw.init = &(struct clk_init_data){
1534 .name = "gcc_ddrss_gpu_axi_clk",
1535 .ops = &clk_branch2_aon_ops,
1540 /* external clocks so add BRANCH_HALT_SKIP */
1541 static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
1542 .halt_reg = 0x8d080,
1543 .halt_check = BRANCH_HALT_SKIP,
1544 .hwcg_reg = 0x8d080,
1547 .enable_reg = 0x52000,
1548 .enable_mask = BIT(19),
1549 .hw.init = &(struct clk_init_data){
1550 .name = "gcc_ddrss_pcie_sf_tbu_clk",
1551 .ops = &clk_branch2_ops,
1556 /* external clocks so add BRANCH_HALT_SKIP */
1557 static struct clk_branch gcc_disp_hf_axi_clk = {
1558 .halt_reg = 0x2700c,
1559 .halt_check = BRANCH_HALT_SKIP,
1560 .hwcg_reg = 0x2700c,
1563 .enable_reg = 0x2700c,
1564 .enable_mask = BIT(0),
1565 .hw.init = &(struct clk_init_data){
1566 .name = "gcc_disp_hf_axi_clk",
1567 .ops = &clk_branch2_ops,
1572 /* external clocks so add BRANCH_HALT_SKIP */
1573 static struct clk_branch gcc_disp_sf_axi_clk = {
1574 .halt_reg = 0x27014,
1575 .halt_check = BRANCH_HALT_SKIP,
1576 .hwcg_reg = 0x27014,
1579 .enable_reg = 0x27014,
1580 .enable_mask = BIT(0),
1581 .hw.init = &(struct clk_init_data){
1582 .name = "gcc_disp_sf_axi_clk",
1583 .ops = &clk_branch2_ops,
1588 static struct clk_branch gcc_gp1_clk = {
1589 .halt_reg = 0x64000,
1590 .halt_check = BRANCH_HALT,
1592 .enable_reg = 0x64000,
1593 .enable_mask = BIT(0),
1594 .hw.init = &(struct clk_init_data){
1595 .name = "gcc_gp1_clk",
1596 .parent_hws = (const struct clk_hw*[]){
1597 &gcc_gp1_clk_src.clkr.hw,
1600 .flags = CLK_SET_RATE_PARENT,
1601 .ops = &clk_branch2_ops,
1606 static struct clk_branch gcc_gp2_clk = {
1607 .halt_reg = 0x65000,
1608 .halt_check = BRANCH_HALT,
1610 .enable_reg = 0x65000,
1611 .enable_mask = BIT(0),
1612 .hw.init = &(struct clk_init_data){
1613 .name = "gcc_gp2_clk",
1614 .parent_hws = (const struct clk_hw*[]){
1615 &gcc_gp2_clk_src.clkr.hw,
1618 .flags = CLK_SET_RATE_PARENT,
1619 .ops = &clk_branch2_ops,
1624 static struct clk_branch gcc_gp3_clk = {
1625 .halt_reg = 0x66000,
1626 .halt_check = BRANCH_HALT,
1628 .enable_reg = 0x66000,
1629 .enable_mask = BIT(0),
1630 .hw.init = &(struct clk_init_data){
1631 .name = "gcc_gp3_clk",
1632 .parent_hws = (const struct clk_hw*[]){
1633 &gcc_gp3_clk_src.clkr.hw,
1636 .flags = CLK_SET_RATE_PARENT,
1637 .ops = &clk_branch2_ops,
1642 /* Clock ON depends on external parent clock, so don't poll */
1643 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1644 .halt_check = BRANCH_HALT_DELAY,
1646 .enable_reg = 0x52000,
1647 .enable_mask = BIT(15),
1648 .hw.init = &(struct clk_init_data){
1649 .name = "gcc_gpu_gpll0_clk_src",
1650 .parent_hws = (const struct clk_hw*[]){
1654 .flags = CLK_SET_RATE_PARENT,
1655 .ops = &clk_branch2_ops,
1660 /* Clock ON depends on external parent clock, so don't poll */
1661 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1662 .halt_check = BRANCH_HALT_DELAY,
1664 .enable_reg = 0x52000,
1665 .enable_mask = BIT(16),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "gcc_gpu_gpll0_div_clk_src",
1668 .parent_hws = (const struct clk_hw*[]){
1669 &gcc_gpll0_out_even.clkr.hw,
1672 .flags = CLK_SET_RATE_PARENT,
1673 .ops = &clk_branch2_ops,
1678 static struct clk_branch gcc_gpu_iref_en = {
1679 .halt_reg = 0x8c014,
1680 .halt_check = BRANCH_HALT,
1682 .enable_reg = 0x8c014,
1683 .enable_mask = BIT(0),
1684 .hw.init = &(struct clk_init_data){
1685 .name = "gcc_gpu_iref_en",
1686 .ops = &clk_branch2_ops,
1691 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1692 .halt_reg = 0x7100c,
1693 .halt_check = BRANCH_HALT_VOTED,
1694 .hwcg_reg = 0x7100c,
1697 .enable_reg = 0x7100c,
1698 .enable_mask = BIT(0),
1699 .hw.init = &(struct clk_init_data){
1700 .name = "gcc_gpu_memnoc_gfx_clk",
1701 .ops = &clk_branch2_aon_ops,
1706 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1707 .halt_reg = 0x71018,
1708 .halt_check = BRANCH_HALT,
1710 .enable_reg = 0x71018,
1711 .enable_mask = BIT(0),
1712 .hw.init = &(struct clk_init_data){
1713 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1714 .ops = &clk_branch2_aon_ops,
1719 static struct clk_branch gcc_pcie0_phy_rchng_clk = {
1720 .halt_reg = 0x6b038,
1721 .halt_check = BRANCH_HALT_VOTED,
1723 .enable_reg = 0x52000,
1724 .enable_mask = BIT(22),
1725 .hw.init = &(struct clk_init_data){
1726 .name = "gcc_pcie0_phy_rchng_clk",
1727 .parent_hws = (const struct clk_hw*[]){
1728 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1731 .flags = CLK_SET_RATE_PARENT,
1732 .ops = &clk_branch2_ops,
1737 static struct clk_branch gcc_pcie1_phy_rchng_clk = {
1738 .halt_reg = 0x8d038,
1739 .halt_check = BRANCH_HALT_VOTED,
1741 .enable_reg = 0x52000,
1742 .enable_mask = BIT(23),
1743 .hw.init = &(struct clk_init_data){
1744 .name = "gcc_pcie1_phy_rchng_clk",
1745 .parent_hws = (const struct clk_hw*[]){
1746 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1749 .flags = CLK_SET_RATE_PARENT,
1750 .ops = &clk_branch2_ops,
1755 static struct clk_branch gcc_pcie_0_aux_clk = {
1756 .halt_reg = 0x6b028,
1757 .halt_check = BRANCH_HALT_VOTED,
1759 .enable_reg = 0x52008,
1760 .enable_mask = BIT(3),
1761 .hw.init = &(struct clk_init_data){
1762 .name = "gcc_pcie_0_aux_clk",
1763 .parent_hws = (const struct clk_hw*[]){
1764 &gcc_pcie_0_aux_clk_src.clkr.hw,
1767 .flags = CLK_SET_RATE_PARENT,
1768 .ops = &clk_branch2_ops,
1773 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1774 .halt_reg = 0x6b024,
1775 .halt_check = BRANCH_HALT_VOTED,
1776 .hwcg_reg = 0x6b024,
1779 .enable_reg = 0x52008,
1780 .enable_mask = BIT(2),
1781 .hw.init = &(struct clk_init_data){
1782 .name = "gcc_pcie_0_cfg_ahb_clk",
1783 .ops = &clk_branch2_ops,
1788 static struct clk_branch gcc_pcie_0_clkref_en = {
1789 .halt_reg = 0x8c004,
1790 .halt_check = BRANCH_HALT,
1792 .enable_reg = 0x8c004,
1793 .enable_mask = BIT(0),
1794 .hw.init = &(struct clk_init_data){
1795 .name = "gcc_pcie_0_clkref_en",
1796 .ops = &clk_branch2_ops,
1801 /* external clocks so add BRANCH_HALT_SKIP */
1802 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1803 .halt_reg = 0x6b01c,
1804 .halt_check = BRANCH_HALT_SKIP,
1805 .hwcg_reg = 0x6b01c,
1808 .enable_reg = 0x52008,
1809 .enable_mask = BIT(1),
1810 .hw.init = &(struct clk_init_data){
1811 .name = "gcc_pcie_0_mstr_axi_clk",
1812 .ops = &clk_branch2_ops,
1817 /* external clocks so add BRANCH_HALT_SKIP */
1818 static struct clk_branch gcc_pcie_0_pipe_clk = {
1819 .halt_reg = 0x6b030,
1820 .halt_check = BRANCH_HALT_SKIP,
1822 .enable_reg = 0x52008,
1823 .enable_mask = BIT(4),
1824 .hw.init = &(struct clk_init_data){
1825 .name = "gcc_pcie_0_pipe_clk",
1826 .parent_hws = (const struct clk_hw*[]){
1827 &gcc_pcie_0_pipe_clk_src.clkr.hw,
1830 .flags = CLK_SET_RATE_PARENT,
1831 .ops = &clk_branch2_ops,
1836 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1837 .halt_reg = 0x6b014,
1838 .halt_check = BRANCH_HALT_VOTED,
1839 .hwcg_reg = 0x6b014,
1842 .enable_reg = 0x52008,
1843 .enable_mask = BIT(0),
1844 .hw.init = &(struct clk_init_data){
1845 .name = "gcc_pcie_0_slv_axi_clk",
1846 .ops = &clk_branch2_ops,
1851 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1852 .halt_reg = 0x6b010,
1853 .halt_check = BRANCH_HALT_VOTED,
1855 .enable_reg = 0x52008,
1856 .enable_mask = BIT(5),
1857 .hw.init = &(struct clk_init_data){
1858 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1859 .ops = &clk_branch2_ops,
1864 static struct clk_branch gcc_pcie_1_aux_clk = {
1865 .halt_reg = 0x8d028,
1866 .halt_check = BRANCH_HALT_VOTED,
1868 .enable_reg = 0x52000,
1869 .enable_mask = BIT(29),
1870 .hw.init = &(struct clk_init_data){
1871 .name = "gcc_pcie_1_aux_clk",
1872 .parent_hws = (const struct clk_hw*[]){
1873 &gcc_pcie_1_aux_clk_src.clkr.hw,
1876 .flags = CLK_SET_RATE_PARENT,
1877 .ops = &clk_branch2_ops,
1882 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1883 .halt_reg = 0x8d024,
1884 .halt_check = BRANCH_HALT_VOTED,
1885 .hwcg_reg = 0x8d024,
1888 .enable_reg = 0x52000,
1889 .enable_mask = BIT(28),
1890 .hw.init = &(struct clk_init_data){
1891 .name = "gcc_pcie_1_cfg_ahb_clk",
1892 .ops = &clk_branch2_ops,
1897 static struct clk_branch gcc_pcie_1_clkref_en = {
1898 .halt_reg = 0x8c008,
1899 .halt_check = BRANCH_HALT,
1901 .enable_reg = 0x8c008,
1902 .enable_mask = BIT(0),
1903 .hw.init = &(struct clk_init_data){
1904 .name = "gcc_pcie_1_clkref_en",
1905 .ops = &clk_branch2_ops,
1910 /* external clocks so add BRANCH_HALT_SKIP */
1911 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1912 .halt_reg = 0x8d01c,
1913 .halt_check = BRANCH_HALT_SKIP,
1914 .hwcg_reg = 0x8d01c,
1917 .enable_reg = 0x52000,
1918 .enable_mask = BIT(27),
1919 .hw.init = &(struct clk_init_data){
1920 .name = "gcc_pcie_1_mstr_axi_clk",
1921 .ops = &clk_branch2_ops,
1926 /* external clocks so add BRANCH_HALT_SKIP */
1927 static struct clk_branch gcc_pcie_1_pipe_clk = {
1928 .halt_reg = 0x8d030,
1929 .halt_check = BRANCH_HALT_SKIP,
1931 .enable_reg = 0x52000,
1932 .enable_mask = BIT(30),
1933 .hw.init = &(struct clk_init_data){
1934 .name = "gcc_pcie_1_pipe_clk",
1935 .parent_hws = (const struct clk_hw*[]){
1936 &gcc_pcie_1_pipe_clk_src.clkr.hw,
1939 .flags = CLK_SET_RATE_PARENT,
1940 .ops = &clk_branch2_ops,
1945 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1946 .halt_reg = 0x8d014,
1947 .halt_check = BRANCH_HALT_VOTED,
1948 .hwcg_reg = 0x8d014,
1951 .enable_reg = 0x52000,
1952 .enable_mask = BIT(26),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "gcc_pcie_1_slv_axi_clk",
1955 .ops = &clk_branch2_ops,
1960 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1961 .halt_reg = 0x8d010,
1962 .halt_check = BRANCH_HALT_VOTED,
1964 .enable_reg = 0x52000,
1965 .enable_mask = BIT(25),
1966 .hw.init = &(struct clk_init_data){
1967 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1968 .ops = &clk_branch2_ops,
1973 static struct clk_branch gcc_pdm2_clk = {
1974 .halt_reg = 0x3300c,
1975 .halt_check = BRANCH_HALT,
1977 .enable_reg = 0x3300c,
1978 .enable_mask = BIT(0),
1979 .hw.init = &(struct clk_init_data){
1980 .name = "gcc_pdm2_clk",
1981 .parent_hws = (const struct clk_hw*[]){
1982 &gcc_pdm2_clk_src.clkr.hw,
1985 .flags = CLK_SET_RATE_PARENT,
1986 .ops = &clk_branch2_ops,
1991 static struct clk_branch gcc_pdm_ahb_clk = {
1992 .halt_reg = 0x33004,
1993 .halt_check = BRANCH_HALT_VOTED,
1994 .hwcg_reg = 0x33004,
1997 .enable_reg = 0x33004,
1998 .enable_mask = BIT(0),
1999 .hw.init = &(struct clk_init_data){
2000 .name = "gcc_pdm_ahb_clk",
2001 .ops = &clk_branch2_ops,
2006 static struct clk_branch gcc_pdm_xo4_clk = {
2007 .halt_reg = 0x33008,
2008 .halt_check = BRANCH_HALT,
2010 .enable_reg = 0x33008,
2011 .enable_mask = BIT(0),
2012 .hw.init = &(struct clk_init_data){
2013 .name = "gcc_pdm_xo4_clk",
2014 .ops = &clk_branch2_ops,
2019 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2020 .halt_reg = 0x26008,
2021 .halt_check = BRANCH_HALT_VOTED,
2022 .hwcg_reg = 0x26008,
2025 .enable_reg = 0x26008,
2026 .enable_mask = BIT(0),
2027 .hw.init = &(struct clk_init_data){
2028 .name = "gcc_qmip_camera_nrt_ahb_clk",
2029 .ops = &clk_branch2_ops,
2034 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2035 .halt_reg = 0x2600c,
2036 .halt_check = BRANCH_HALT_VOTED,
2037 .hwcg_reg = 0x2600c,
2040 .enable_reg = 0x2600c,
2041 .enable_mask = BIT(0),
2042 .hw.init = &(struct clk_init_data){
2043 .name = "gcc_qmip_camera_rt_ahb_clk",
2044 .ops = &clk_branch2_ops,
2049 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2050 .halt_reg = 0x27008,
2051 .halt_check = BRANCH_HALT_VOTED,
2052 .hwcg_reg = 0x27008,
2055 .enable_reg = 0x27008,
2056 .enable_mask = BIT(0),
2057 .hw.init = &(struct clk_init_data){
2058 .name = "gcc_qmip_disp_ahb_clk",
2059 .ops = &clk_branch2_ops,
2064 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2065 .halt_reg = 0x28008,
2066 .halt_check = BRANCH_HALT_VOTED,
2067 .hwcg_reg = 0x28008,
2070 .enable_reg = 0x28008,
2071 .enable_mask = BIT(0),
2072 .hw.init = &(struct clk_init_data){
2073 .name = "gcc_qmip_video_cvp_ahb_clk",
2074 .ops = &clk_branch2_ops,
2079 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2080 .halt_reg = 0x2800c,
2081 .halt_check = BRANCH_HALT_VOTED,
2082 .hwcg_reg = 0x2800c,
2085 .enable_reg = 0x2800c,
2086 .enable_mask = BIT(0),
2087 .hw.init = &(struct clk_init_data){
2088 .name = "gcc_qmip_video_vcodec_ahb_clk",
2089 .ops = &clk_branch2_ops,
2094 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2095 .halt_reg = 0x23008,
2096 .halt_check = BRANCH_HALT_VOTED,
2098 .enable_reg = 0x52008,
2099 .enable_mask = BIT(9),
2100 .hw.init = &(struct clk_init_data){
2101 .name = "gcc_qupv3_wrap0_core_2x_clk",
2102 .ops = &clk_branch2_ops,
2107 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2108 .halt_reg = 0x23000,
2109 .halt_check = BRANCH_HALT_VOTED,
2111 .enable_reg = 0x52008,
2112 .enable_mask = BIT(8),
2113 .hw.init = &(struct clk_init_data){
2114 .name = "gcc_qupv3_wrap0_core_clk",
2115 .ops = &clk_branch2_ops,
2120 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2121 .halt_reg = 0x1700c,
2122 .halt_check = BRANCH_HALT_VOTED,
2124 .enable_reg = 0x52008,
2125 .enable_mask = BIT(10),
2126 .hw.init = &(struct clk_init_data){
2127 .name = "gcc_qupv3_wrap0_s0_clk",
2128 .parent_hws = (const struct clk_hw*[]){
2129 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2132 .flags = CLK_SET_RATE_PARENT,
2133 .ops = &clk_branch2_ops,
2138 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2139 .halt_reg = 0x1713c,
2140 .halt_check = BRANCH_HALT_VOTED,
2142 .enable_reg = 0x52008,
2143 .enable_mask = BIT(11),
2144 .hw.init = &(struct clk_init_data){
2145 .name = "gcc_qupv3_wrap0_s1_clk",
2146 .parent_hws = (const struct clk_hw*[]){
2147 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2150 .flags = CLK_SET_RATE_PARENT,
2151 .ops = &clk_branch2_ops,
2156 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2157 .halt_reg = 0x1726c,
2158 .halt_check = BRANCH_HALT_VOTED,
2160 .enable_reg = 0x52008,
2161 .enable_mask = BIT(12),
2162 .hw.init = &(struct clk_init_data){
2163 .name = "gcc_qupv3_wrap0_s2_clk",
2164 .parent_hws = (const struct clk_hw*[]){
2165 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2168 .flags = CLK_SET_RATE_PARENT,
2169 .ops = &clk_branch2_ops,
2174 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2175 .halt_reg = 0x1739c,
2176 .halt_check = BRANCH_HALT_VOTED,
2178 .enable_reg = 0x52008,
2179 .enable_mask = BIT(13),
2180 .hw.init = &(struct clk_init_data){
2181 .name = "gcc_qupv3_wrap0_s3_clk",
2182 .parent_hws = (const struct clk_hw*[]){
2183 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2186 .flags = CLK_SET_RATE_PARENT,
2187 .ops = &clk_branch2_ops,
2192 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2193 .halt_reg = 0x174cc,
2194 .halt_check = BRANCH_HALT_VOTED,
2196 .enable_reg = 0x52008,
2197 .enable_mask = BIT(14),
2198 .hw.init = &(struct clk_init_data){
2199 .name = "gcc_qupv3_wrap0_s4_clk",
2200 .parent_hws = (const struct clk_hw*[]){
2201 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2204 .flags = CLK_SET_RATE_PARENT,
2205 .ops = &clk_branch2_ops,
2210 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2211 .halt_reg = 0x175fc,
2212 .halt_check = BRANCH_HALT_VOTED,
2214 .enable_reg = 0x52008,
2215 .enable_mask = BIT(15),
2216 .hw.init = &(struct clk_init_data){
2217 .name = "gcc_qupv3_wrap0_s5_clk",
2218 .parent_hws = (const struct clk_hw*[]){
2219 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2222 .flags = CLK_SET_RATE_PARENT,
2223 .ops = &clk_branch2_ops,
2228 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2229 .halt_reg = 0x1772c,
2230 .halt_check = BRANCH_HALT_VOTED,
2232 .enable_reg = 0x52008,
2233 .enable_mask = BIT(16),
2234 .hw.init = &(struct clk_init_data){
2235 .name = "gcc_qupv3_wrap0_s6_clk",
2236 .parent_hws = (const struct clk_hw*[]){
2237 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2240 .flags = CLK_SET_RATE_PARENT,
2241 .ops = &clk_branch2_ops,
2246 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2247 .halt_reg = 0x1785c,
2248 .halt_check = BRANCH_HALT_VOTED,
2250 .enable_reg = 0x52008,
2251 .enable_mask = BIT(17),
2252 .hw.init = &(struct clk_init_data){
2253 .name = "gcc_qupv3_wrap0_s7_clk",
2254 .parent_hws = (const struct clk_hw*[]){
2255 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2258 .flags = CLK_SET_RATE_PARENT,
2259 .ops = &clk_branch2_ops,
2264 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2265 .halt_reg = 0x23140,
2266 .halt_check = BRANCH_HALT_VOTED,
2268 .enable_reg = 0x52008,
2269 .enable_mask = BIT(18),
2270 .hw.init = &(struct clk_init_data){
2271 .name = "gcc_qupv3_wrap1_core_2x_clk",
2272 .ops = &clk_branch2_ops,
2277 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2278 .halt_reg = 0x23138,
2279 .halt_check = BRANCH_HALT_VOTED,
2281 .enable_reg = 0x52008,
2282 .enable_mask = BIT(19),
2283 .hw.init = &(struct clk_init_data){
2284 .name = "gcc_qupv3_wrap1_core_clk",
2285 .ops = &clk_branch2_ops,
2290 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2291 .halt_reg = 0x18004,
2292 .halt_check = BRANCH_HALT_VOTED,
2293 .hwcg_reg = 0x18004,
2296 .enable_reg = 0x52008,
2297 .enable_mask = BIT(20),
2298 .hw.init = &(struct clk_init_data){
2299 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2300 .ops = &clk_branch2_ops,
2305 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2306 .halt_reg = 0x18008,
2307 .halt_check = BRANCH_HALT_VOTED,
2308 .hwcg_reg = 0x18008,
2311 .enable_reg = 0x52008,
2312 .enable_mask = BIT(21),
2313 .hw.init = &(struct clk_init_data){
2314 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2315 .ops = &clk_branch2_ops,
2320 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2321 .halt_reg = 0x1800c,
2322 .halt_check = BRANCH_HALT_VOTED,
2324 .enable_reg = 0x52008,
2325 .enable_mask = BIT(22),
2326 .hw.init = &(struct clk_init_data){
2327 .name = "gcc_qupv3_wrap1_s0_clk",
2328 .parent_hws = (const struct clk_hw*[]){
2329 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2332 .flags = CLK_SET_RATE_PARENT,
2333 .ops = &clk_branch2_ops,
2338 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2339 .halt_reg = 0x1813c,
2340 .halt_check = BRANCH_HALT_VOTED,
2342 .enable_reg = 0x52008,
2343 .enable_mask = BIT(23),
2344 .hw.init = &(struct clk_init_data){
2345 .name = "gcc_qupv3_wrap1_s1_clk",
2346 .parent_hws = (const struct clk_hw*[]){
2347 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2350 .flags = CLK_SET_RATE_PARENT,
2351 .ops = &clk_branch2_ops,
2356 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2357 .halt_reg = 0x1826c,
2358 .halt_check = BRANCH_HALT_VOTED,
2360 .enable_reg = 0x52008,
2361 .enable_mask = BIT(24),
2362 .hw.init = &(struct clk_init_data){
2363 .name = "gcc_qupv3_wrap1_s2_clk",
2364 .parent_hws = (const struct clk_hw*[]){
2365 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2368 .flags = CLK_SET_RATE_PARENT,
2369 .ops = &clk_branch2_ops,
2374 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2375 .halt_reg = 0x1839c,
2376 .halt_check = BRANCH_HALT_VOTED,
2378 .enable_reg = 0x52008,
2379 .enable_mask = BIT(25),
2380 .hw.init = &(struct clk_init_data){
2381 .name = "gcc_qupv3_wrap1_s3_clk",
2382 .parent_hws = (const struct clk_hw*[]){
2383 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2386 .flags = CLK_SET_RATE_PARENT,
2387 .ops = &clk_branch2_ops,
2392 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2393 .halt_reg = 0x184cc,
2394 .halt_check = BRANCH_HALT_VOTED,
2396 .enable_reg = 0x52008,
2397 .enable_mask = BIT(26),
2398 .hw.init = &(struct clk_init_data){
2399 .name = "gcc_qupv3_wrap1_s4_clk",
2400 .parent_hws = (const struct clk_hw*[]){
2401 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2404 .flags = CLK_SET_RATE_PARENT,
2405 .ops = &clk_branch2_ops,
2410 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2411 .halt_reg = 0x185fc,
2412 .halt_check = BRANCH_HALT_VOTED,
2414 .enable_reg = 0x52008,
2415 .enable_mask = BIT(27),
2416 .hw.init = &(struct clk_init_data){
2417 .name = "gcc_qupv3_wrap1_s5_clk",
2418 .parent_hws = (const struct clk_hw*[]){
2419 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2422 .flags = CLK_SET_RATE_PARENT,
2423 .ops = &clk_branch2_ops,
2428 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
2429 .halt_reg = 0x23278,
2430 .halt_check = BRANCH_HALT_VOTED,
2432 .enable_reg = 0x52010,
2433 .enable_mask = BIT(3),
2434 .hw.init = &(struct clk_init_data){
2435 .name = "gcc_qupv3_wrap2_core_2x_clk",
2436 .ops = &clk_branch2_ops,
2441 static struct clk_branch gcc_qupv3_wrap2_core_clk = {
2442 .halt_reg = 0x23270,
2443 .halt_check = BRANCH_HALT_VOTED,
2445 .enable_reg = 0x52010,
2446 .enable_mask = BIT(0),
2447 .hw.init = &(struct clk_init_data){
2448 .name = "gcc_qupv3_wrap2_core_clk",
2449 .ops = &clk_branch2_ops,
2454 static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2455 .halt_reg = 0x1e00c,
2456 .halt_check = BRANCH_HALT_VOTED,
2458 .enable_reg = 0x52010,
2459 .enable_mask = BIT(4),
2460 .hw.init = &(struct clk_init_data){
2461 .name = "gcc_qupv3_wrap2_s0_clk",
2462 .parent_hws = (const struct clk_hw*[]){
2463 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
2466 .flags = CLK_SET_RATE_PARENT,
2467 .ops = &clk_branch2_ops,
2472 static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2473 .halt_reg = 0x1e13c,
2474 .halt_check = BRANCH_HALT_VOTED,
2476 .enable_reg = 0x52010,
2477 .enable_mask = BIT(5),
2478 .hw.init = &(struct clk_init_data){
2479 .name = "gcc_qupv3_wrap2_s1_clk",
2480 .parent_hws = (const struct clk_hw*[]){
2481 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
2484 .flags = CLK_SET_RATE_PARENT,
2485 .ops = &clk_branch2_ops,
2490 static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2491 .halt_reg = 0x1e26c,
2492 .halt_check = BRANCH_HALT_VOTED,
2494 .enable_reg = 0x52010,
2495 .enable_mask = BIT(6),
2496 .hw.init = &(struct clk_init_data){
2497 .name = "gcc_qupv3_wrap2_s2_clk",
2498 .parent_hws = (const struct clk_hw*[]){
2499 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2502 .flags = CLK_SET_RATE_PARENT,
2503 .ops = &clk_branch2_ops,
2508 static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2509 .halt_reg = 0x1e39c,
2510 .halt_check = BRANCH_HALT_VOTED,
2512 .enable_reg = 0x52010,
2513 .enable_mask = BIT(7),
2514 .hw.init = &(struct clk_init_data){
2515 .name = "gcc_qupv3_wrap2_s3_clk",
2516 .parent_hws = (const struct clk_hw*[]){
2517 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2520 .flags = CLK_SET_RATE_PARENT,
2521 .ops = &clk_branch2_ops,
2526 static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2527 .halt_reg = 0x1e4cc,
2528 .halt_check = BRANCH_HALT_VOTED,
2530 .enable_reg = 0x52010,
2531 .enable_mask = BIT(8),
2532 .hw.init = &(struct clk_init_data){
2533 .name = "gcc_qupv3_wrap2_s4_clk",
2534 .parent_hws = (const struct clk_hw*[]){
2535 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
2538 .flags = CLK_SET_RATE_PARENT,
2539 .ops = &clk_branch2_ops,
2544 static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2545 .halt_reg = 0x1e5fc,
2546 .halt_check = BRANCH_HALT_VOTED,
2548 .enable_reg = 0x52010,
2549 .enable_mask = BIT(9),
2550 .hw.init = &(struct clk_init_data){
2551 .name = "gcc_qupv3_wrap2_s5_clk",
2552 .parent_hws = (const struct clk_hw*[]){
2553 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
2556 .flags = CLK_SET_RATE_PARENT,
2557 .ops = &clk_branch2_ops,
2562 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2563 .halt_reg = 0x17004,
2564 .halt_check = BRANCH_HALT_VOTED,
2565 .hwcg_reg = 0x17004,
2568 .enable_reg = 0x52008,
2569 .enable_mask = BIT(6),
2570 .hw.init = &(struct clk_init_data){
2571 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2572 .ops = &clk_branch2_ops,
2577 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2578 .halt_reg = 0x17008,
2579 .halt_check = BRANCH_HALT_VOTED,
2580 .hwcg_reg = 0x17008,
2583 .enable_reg = 0x52008,
2584 .enable_mask = BIT(7),
2585 .hw.init = &(struct clk_init_data){
2586 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2587 .ops = &clk_branch2_ops,
2592 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2593 .halt_reg = 0x1e004,
2594 .halt_check = BRANCH_HALT_VOTED,
2595 .hwcg_reg = 0x1e004,
2598 .enable_reg = 0x52010,
2599 .enable_mask = BIT(2),
2600 .hw.init = &(struct clk_init_data){
2601 .name = "gcc_qupv3_wrap_2_m_ahb_clk",
2602 .ops = &clk_branch2_ops,
2607 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2608 .halt_reg = 0x1e008,
2609 .halt_check = BRANCH_HALT_VOTED,
2610 .hwcg_reg = 0x1e008,
2613 .enable_reg = 0x52010,
2614 .enable_mask = BIT(1),
2615 .hw.init = &(struct clk_init_data){
2616 .name = "gcc_qupv3_wrap_2_s_ahb_clk",
2617 .ops = &clk_branch2_ops,
2622 static struct clk_branch gcc_sdcc2_ahb_clk = {
2623 .halt_reg = 0x14008,
2624 .halt_check = BRANCH_HALT,
2626 .enable_reg = 0x14008,
2627 .enable_mask = BIT(0),
2628 .hw.init = &(struct clk_init_data){
2629 .name = "gcc_sdcc2_ahb_clk",
2630 .ops = &clk_branch2_ops,
2635 static struct clk_branch gcc_sdcc2_apps_clk = {
2636 .halt_reg = 0x14004,
2637 .halt_check = BRANCH_HALT,
2639 .enable_reg = 0x14004,
2640 .enable_mask = BIT(0),
2641 .hw.init = &(struct clk_init_data){
2642 .name = "gcc_sdcc2_apps_clk",
2643 .parent_hws = (const struct clk_hw*[]){
2644 &gcc_sdcc2_apps_clk_src.clkr.hw,
2647 .flags = CLK_SET_RATE_PARENT,
2648 .ops = &clk_branch2_ops,
2653 static struct clk_branch gcc_sdcc4_ahb_clk = {
2654 .halt_reg = 0x16008,
2655 .halt_check = BRANCH_HALT,
2657 .enable_reg = 0x16008,
2658 .enable_mask = BIT(0),
2659 .hw.init = &(struct clk_init_data){
2660 .name = "gcc_sdcc4_ahb_clk",
2661 .ops = &clk_branch2_ops,
2666 static struct clk_branch gcc_sdcc4_apps_clk = {
2667 .halt_reg = 0x16004,
2668 .halt_check = BRANCH_HALT,
2670 .enable_reg = 0x16004,
2671 .enable_mask = BIT(0),
2672 .hw.init = &(struct clk_init_data){
2673 .name = "gcc_sdcc4_apps_clk",
2674 .parent_hws = (const struct clk_hw*[]){
2675 &gcc_sdcc4_apps_clk_src.clkr.hw,
2678 .flags = CLK_SET_RATE_PARENT,
2679 .ops = &clk_branch2_ops,
2684 static struct clk_branch gcc_throttle_pcie_ahb_clk = {
2686 .halt_check = BRANCH_HALT,
2688 .enable_reg = 0x9044,
2689 .enable_mask = BIT(0),
2690 .hw.init = &(struct clk_init_data){
2691 .name = "gcc_throttle_pcie_ahb_clk",
2692 .ops = &clk_branch2_ops,
2697 static struct clk_branch gcc_ufs_1_clkref_en = {
2698 .halt_reg = 0x8c000,
2699 .halt_check = BRANCH_HALT,
2701 .enable_reg = 0x8c000,
2702 .enable_mask = BIT(0),
2703 .hw.init = &(struct clk_init_data){
2704 .name = "gcc_ufs_1_clkref_en",
2705 .ops = &clk_branch2_ops,
2710 static struct clk_branch gcc_ufs_card_ahb_clk = {
2711 .halt_reg = 0x75018,
2712 .halt_check = BRANCH_HALT_VOTED,
2713 .hwcg_reg = 0x75018,
2716 .enable_reg = 0x75018,
2717 .enable_mask = BIT(0),
2718 .hw.init = &(struct clk_init_data){
2719 .name = "gcc_ufs_card_ahb_clk",
2720 .ops = &clk_branch2_ops,
2725 static struct clk_branch gcc_ufs_card_axi_clk = {
2726 .halt_reg = 0x75010,
2727 .halt_check = BRANCH_HALT_VOTED,
2728 .hwcg_reg = 0x75010,
2731 .enable_reg = 0x75010,
2732 .enable_mask = BIT(0),
2733 .hw.init = &(struct clk_init_data){
2734 .name = "gcc_ufs_card_axi_clk",
2735 .parent_hws = (const struct clk_hw*[]){
2736 &gcc_ufs_card_axi_clk_src.clkr.hw,
2739 .flags = CLK_SET_RATE_PARENT,
2740 .ops = &clk_branch2_ops,
2745 static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
2746 .halt_reg = 0x75010,
2747 .halt_check = BRANCH_HALT_VOTED,
2748 .hwcg_reg = 0x75010,
2751 .enable_reg = 0x75010,
2752 .enable_mask = BIT(1),
2753 .hw.init = &(struct clk_init_data){
2754 .name = "gcc_ufs_card_axi_hw_ctl_clk",
2755 .parent_hws = (const struct clk_hw*[]){
2756 &gcc_ufs_card_axi_clk_src.clkr.hw,
2759 .flags = CLK_SET_RATE_PARENT,
2760 .ops = &clk_branch2_ops,
2765 static struct clk_branch gcc_ufs_card_ice_core_clk = {
2766 .halt_reg = 0x75064,
2767 .halt_check = BRANCH_HALT_VOTED,
2768 .hwcg_reg = 0x75064,
2771 .enable_reg = 0x75064,
2772 .enable_mask = BIT(0),
2773 .hw.init = &(struct clk_init_data){
2774 .name = "gcc_ufs_card_ice_core_clk",
2775 .parent_hws = (const struct clk_hw*[]){
2776 &gcc_ufs_card_ice_core_clk_src.clkr.hw,
2779 .flags = CLK_SET_RATE_PARENT,
2780 .ops = &clk_branch2_ops,
2785 static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
2786 .halt_reg = 0x75064,
2787 .halt_check = BRANCH_HALT_VOTED,
2788 .hwcg_reg = 0x75064,
2791 .enable_reg = 0x75064,
2792 .enable_mask = BIT(1),
2793 .hw.init = &(struct clk_init_data){
2794 .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
2795 .parent_hws = (const struct clk_hw*[]){
2796 &gcc_ufs_card_ice_core_clk_src.clkr.hw,
2799 .flags = CLK_SET_RATE_PARENT,
2800 .ops = &clk_branch2_ops,
2805 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2806 .halt_reg = 0x7509c,
2807 .halt_check = BRANCH_HALT_VOTED,
2808 .hwcg_reg = 0x7509c,
2811 .enable_reg = 0x7509c,
2812 .enable_mask = BIT(0),
2813 .hw.init = &(struct clk_init_data){
2814 .name = "gcc_ufs_card_phy_aux_clk",
2815 .parent_hws = (const struct clk_hw*[]){
2816 &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2819 .flags = CLK_SET_RATE_PARENT,
2820 .ops = &clk_branch2_ops,
2825 static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
2826 .halt_reg = 0x7509c,
2827 .halt_check = BRANCH_HALT_VOTED,
2828 .hwcg_reg = 0x7509c,
2831 .enable_reg = 0x7509c,
2832 .enable_mask = BIT(1),
2833 .hw.init = &(struct clk_init_data){
2834 .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
2835 .parent_hws = (const struct clk_hw*[]){
2836 &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2839 .flags = CLK_SET_RATE_PARENT,
2840 .ops = &clk_branch2_ops,
2845 /* Clock ON depends on external parent clock, so don't poll */
2846 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2847 .halt_reg = 0x75020,
2848 .halt_check = BRANCH_HALT_DELAY,
2850 .enable_reg = 0x75020,
2851 .enable_mask = BIT(0),
2852 .hw.init = &(struct clk_init_data){
2853 .name = "gcc_ufs_card_rx_symbol_0_clk",
2854 .parent_hws = (const struct clk_hw*[]){
2855 &gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw,
2858 .flags = CLK_SET_RATE_PARENT,
2859 .ops = &clk_branch2_ops,
2864 /* Clock ON depends on external parent clock, so don't poll */
2865 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2866 .halt_reg = 0x750b8,
2867 .halt_check = BRANCH_HALT_DELAY,
2869 .enable_reg = 0x750b8,
2870 .enable_mask = BIT(0),
2871 .hw.init = &(struct clk_init_data){
2872 .name = "gcc_ufs_card_rx_symbol_1_clk",
2873 .parent_hws = (const struct clk_hw*[]){
2874 &gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw,
2877 .flags = CLK_SET_RATE_PARENT,
2878 .ops = &clk_branch2_ops,
2883 /* Clock ON depends on external parent clock, so don't poll */
2884 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2885 .halt_reg = 0x7501c,
2886 .halt_check = BRANCH_HALT_DELAY,
2888 .enable_reg = 0x7501c,
2889 .enable_mask = BIT(0),
2890 .hw.init = &(struct clk_init_data){
2891 .name = "gcc_ufs_card_tx_symbol_0_clk",
2892 .parent_hws = (const struct clk_hw*[]){
2893 &gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw,
2896 .flags = CLK_SET_RATE_PARENT,
2897 .ops = &clk_branch2_ops,
2902 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2903 .halt_reg = 0x7505c,
2904 .halt_check = BRANCH_HALT_VOTED,
2905 .hwcg_reg = 0x7505c,
2908 .enable_reg = 0x7505c,
2909 .enable_mask = BIT(0),
2910 .hw.init = &(struct clk_init_data){
2911 .name = "gcc_ufs_card_unipro_core_clk",
2912 .parent_hws = (const struct clk_hw*[]){
2913 &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2916 .flags = CLK_SET_RATE_PARENT,
2917 .ops = &clk_branch2_ops,
2922 static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
2923 .halt_reg = 0x7505c,
2924 .halt_check = BRANCH_HALT_VOTED,
2925 .hwcg_reg = 0x7505c,
2928 .enable_reg = 0x7505c,
2929 .enable_mask = BIT(1),
2930 .hw.init = &(struct clk_init_data){
2931 .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
2932 .parent_hws = (const struct clk_hw*[]){
2933 &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2936 .flags = CLK_SET_RATE_PARENT,
2937 .ops = &clk_branch2_ops,
2942 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2943 .halt_reg = 0x77018,
2944 .halt_check = BRANCH_HALT_VOTED,
2945 .hwcg_reg = 0x77018,
2948 .enable_reg = 0x77018,
2949 .enable_mask = BIT(0),
2950 .hw.init = &(struct clk_init_data){
2951 .name = "gcc_ufs_phy_ahb_clk",
2952 .ops = &clk_branch2_ops,
2957 static struct clk_branch gcc_ufs_phy_axi_clk = {
2958 .halt_reg = 0x77010,
2959 .halt_check = BRANCH_HALT_VOTED,
2960 .hwcg_reg = 0x77010,
2963 .enable_reg = 0x77010,
2964 .enable_mask = BIT(0),
2965 .hw.init = &(struct clk_init_data){
2966 .name = "gcc_ufs_phy_axi_clk",
2967 .parent_hws = (const struct clk_hw*[]){
2968 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2971 .flags = CLK_SET_RATE_PARENT,
2972 .ops = &clk_branch2_ops,
2977 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2978 .halt_reg = 0x77010,
2979 .halt_check = BRANCH_HALT_VOTED,
2980 .hwcg_reg = 0x77010,
2983 .enable_reg = 0x77010,
2984 .enable_mask = BIT(1),
2985 .hw.init = &(struct clk_init_data){
2986 .name = "gcc_ufs_phy_axi_hw_ctl_clk",
2987 .parent_hws = (const struct clk_hw*[]){
2988 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2991 .flags = CLK_SET_RATE_PARENT,
2992 .ops = &clk_branch2_ops,
2997 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2998 .halt_reg = 0x77064,
2999 .halt_check = BRANCH_HALT_VOTED,
3000 .hwcg_reg = 0x77064,
3003 .enable_reg = 0x77064,
3004 .enable_mask = BIT(0),
3005 .hw.init = &(struct clk_init_data){
3006 .name = "gcc_ufs_phy_ice_core_clk",
3007 .parent_hws = (const struct clk_hw*[]){
3008 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3011 .flags = CLK_SET_RATE_PARENT,
3012 .ops = &clk_branch2_ops,
3017 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
3018 .halt_reg = 0x77064,
3019 .halt_check = BRANCH_HALT_VOTED,
3020 .hwcg_reg = 0x77064,
3023 .enable_reg = 0x77064,
3024 .enable_mask = BIT(1),
3025 .hw.init = &(struct clk_init_data){
3026 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
3027 .parent_hws = (const struct clk_hw*[]){
3028 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3031 .flags = CLK_SET_RATE_PARENT,
3032 .ops = &clk_branch2_ops,
3037 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3038 .halt_reg = 0x7709c,
3039 .halt_check = BRANCH_HALT_VOTED,
3040 .hwcg_reg = 0x7709c,
3043 .enable_reg = 0x7709c,
3044 .enable_mask = BIT(0),
3045 .hw.init = &(struct clk_init_data){
3046 .name = "gcc_ufs_phy_phy_aux_clk",
3047 .parent_hws = (const struct clk_hw*[]){
3048 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3051 .flags = CLK_SET_RATE_PARENT,
3052 .ops = &clk_branch2_ops,
3057 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3058 .halt_reg = 0x7709c,
3059 .halt_check = BRANCH_HALT_VOTED,
3060 .hwcg_reg = 0x7709c,
3063 .enable_reg = 0x7709c,
3064 .enable_mask = BIT(1),
3065 .hw.init = &(struct clk_init_data){
3066 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
3067 .parent_hws = (const struct clk_hw*[]){
3068 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3071 .flags = CLK_SET_RATE_PARENT,
3072 .ops = &clk_branch2_ops,
3077 /* Clock ON depends on external parent clock, so don't poll */
3078 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3079 .halt_reg = 0x77020,
3080 .halt_check = BRANCH_HALT_DELAY,
3082 .enable_reg = 0x77020,
3083 .enable_mask = BIT(0),
3084 .hw.init = &(struct clk_init_data){
3085 .name = "gcc_ufs_phy_rx_symbol_0_clk",
3086 .parent_hws = (const struct clk_hw*[]){
3087 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
3090 .flags = CLK_SET_RATE_PARENT,
3091 .ops = &clk_branch2_ops,
3096 /* Clock ON depends on external parent clock, so don't poll */
3097 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
3098 .halt_reg = 0x770b8,
3099 .halt_check = BRANCH_HALT_DELAY,
3101 .enable_reg = 0x770b8,
3102 .enable_mask = BIT(0),
3103 .hw.init = &(struct clk_init_data){
3104 .name = "gcc_ufs_phy_rx_symbol_1_clk",
3105 .parent_hws = (const struct clk_hw*[]){
3106 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
3109 .flags = CLK_SET_RATE_PARENT,
3110 .ops = &clk_branch2_ops,
3115 /* Clock ON depends on external parent clock, so don't poll */
3116 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3117 .halt_reg = 0x7701c,
3118 .halt_check = BRANCH_HALT_DELAY,
3120 .enable_reg = 0x7701c,
3121 .enable_mask = BIT(0),
3122 .hw.init = &(struct clk_init_data){
3123 .name = "gcc_ufs_phy_tx_symbol_0_clk",
3124 .parent_hws = (const struct clk_hw*[]){
3125 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
3128 .flags = CLK_SET_RATE_PARENT,
3129 .ops = &clk_branch2_ops,
3134 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3135 .halt_reg = 0x7705c,
3136 .halt_check = BRANCH_HALT_VOTED,
3137 .hwcg_reg = 0x7705c,
3140 .enable_reg = 0x7705c,
3141 .enable_mask = BIT(0),
3142 .hw.init = &(struct clk_init_data){
3143 .name = "gcc_ufs_phy_unipro_core_clk",
3144 .parent_hws = (const struct clk_hw*[]){
3145 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3148 .flags = CLK_SET_RATE_PARENT,
3149 .ops = &clk_branch2_ops,
3154 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3155 .halt_reg = 0x7705c,
3156 .halt_check = BRANCH_HALT_VOTED,
3157 .hwcg_reg = 0x7705c,
3160 .enable_reg = 0x7705c,
3161 .enable_mask = BIT(1),
3162 .hw.init = &(struct clk_init_data){
3163 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3164 .parent_hws = (const struct clk_hw*[]){
3165 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3168 .flags = CLK_SET_RATE_PARENT,
3169 .ops = &clk_branch2_ops,
3174 static struct clk_branch gcc_usb30_prim_master_clk = {
3176 .halt_check = BRANCH_HALT,
3178 .enable_reg = 0xf010,
3179 .enable_mask = BIT(0),
3180 .hw.init = &(struct clk_init_data){
3181 .name = "gcc_usb30_prim_master_clk",
3182 .parent_hws = (const struct clk_hw*[]){
3183 &gcc_usb30_prim_master_clk_src.clkr.hw,
3186 .flags = CLK_SET_RATE_PARENT,
3187 .ops = &clk_branch2_ops,
3192 static struct clk_branch gcc_usb30_prim_master_clk__force_mem_core_on = {
3194 .halt_check = BRANCH_HALT,
3196 .enable_reg = 0xf010,
3197 .enable_mask = BIT(14),
3198 .hw.init = &(struct clk_init_data){
3199 .name = "gcc_usb30_prim_master_clk__force_mem_core_on",
3200 .ops = &clk_branch_simple_ops,
3205 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3207 .halt_check = BRANCH_HALT,
3209 .enable_reg = 0xf01c,
3210 .enable_mask = BIT(0),
3211 .hw.init = &(struct clk_init_data){
3212 .name = "gcc_usb30_prim_mock_utmi_clk",
3213 .parent_hws = (const struct clk_hw*[]){
3214 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
3217 .flags = CLK_SET_RATE_PARENT,
3218 .ops = &clk_branch2_ops,
3223 static struct clk_branch gcc_usb30_prim_sleep_clk = {
3225 .halt_check = BRANCH_HALT,
3227 .enable_reg = 0xf018,
3228 .enable_mask = BIT(0),
3229 .hw.init = &(struct clk_init_data){
3230 .name = "gcc_usb30_prim_sleep_clk",
3231 .ops = &clk_branch2_ops,
3236 static struct clk_branch gcc_usb30_sec_master_clk = {
3237 .halt_reg = 0x10010,
3238 .halt_check = BRANCH_HALT,
3240 .enable_reg = 0x10010,
3241 .enable_mask = BIT(0),
3242 .hw.init = &(struct clk_init_data){
3243 .name = "gcc_usb30_sec_master_clk",
3244 .parent_hws = (const struct clk_hw*[]){
3245 &gcc_usb30_sec_master_clk_src.clkr.hw,
3248 .flags = CLK_SET_RATE_PARENT,
3249 .ops = &clk_branch2_ops,
3254 static struct clk_branch gcc_usb30_sec_master_clk__force_mem_core_on = {
3255 .halt_reg = 0x10010,
3256 .halt_check = BRANCH_HALT,
3258 .enable_reg = 0x10010,
3259 .enable_mask = BIT(14),
3260 .hw.init = &(struct clk_init_data){
3261 .name = "gcc_usb30_sec_master_clk__force_mem_core_on",
3262 .ops = &clk_branch_simple_ops,
3267 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3268 .halt_reg = 0x1001c,
3269 .halt_check = BRANCH_HALT,
3271 .enable_reg = 0x1001c,
3272 .enable_mask = BIT(0),
3273 .hw.init = &(struct clk_init_data){
3274 .name = "gcc_usb30_sec_mock_utmi_clk",
3275 .parent_hws = (const struct clk_hw*[]){
3276 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
3279 .flags = CLK_SET_RATE_PARENT,
3280 .ops = &clk_branch2_ops,
3285 static struct clk_branch gcc_usb30_sec_sleep_clk = {
3286 .halt_reg = 0x10018,
3287 .halt_check = BRANCH_HALT,
3289 .enable_reg = 0x10018,
3290 .enable_mask = BIT(0),
3291 .hw.init = &(struct clk_init_data){
3292 .name = "gcc_usb30_sec_sleep_clk",
3293 .ops = &clk_branch2_ops,
3298 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3300 .halt_check = BRANCH_HALT,
3302 .enable_reg = 0xf054,
3303 .enable_mask = BIT(0),
3304 .hw.init = &(struct clk_init_data){
3305 .name = "gcc_usb3_prim_phy_aux_clk",
3306 .parent_hws = (const struct clk_hw*[]){
3307 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3310 .flags = CLK_SET_RATE_PARENT,
3311 .ops = &clk_branch2_ops,
3316 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3318 .halt_check = BRANCH_HALT,
3320 .enable_reg = 0xf058,
3321 .enable_mask = BIT(0),
3322 .hw.init = &(struct clk_init_data){
3323 .name = "gcc_usb3_prim_phy_com_aux_clk",
3324 .parent_hws = (const struct clk_hw*[]){
3325 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3328 .flags = CLK_SET_RATE_PARENT,
3329 .ops = &clk_branch2_ops,
3334 /* Clock ON depends on external parent clock, so don't poll */
3335 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3337 .halt_check = BRANCH_HALT_DELAY,
3341 .enable_reg = 0xf05c,
3342 .enable_mask = BIT(0),
3343 .hw.init = &(struct clk_init_data){
3344 .name = "gcc_usb3_prim_phy_pipe_clk",
3345 .parent_hws = (const struct clk_hw*[]){
3346 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
3349 .flags = CLK_SET_RATE_PARENT,
3350 .ops = &clk_branch2_ops,
3355 static struct clk_branch gcc_usb3_sec_clkref_en = {
3356 .halt_reg = 0x8c010,
3357 .halt_check = BRANCH_HALT,
3359 .enable_reg = 0x8c010,
3360 .enable_mask = BIT(0),
3361 .hw.init = &(struct clk_init_data){
3362 .name = "gcc_usb3_sec_clkref_en",
3363 .ops = &clk_branch2_ops,
3368 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3369 .halt_reg = 0x10054,
3370 .halt_check = BRANCH_HALT,
3372 .enable_reg = 0x10054,
3373 .enable_mask = BIT(0),
3374 .hw.init = &(struct clk_init_data){
3375 .name = "gcc_usb3_sec_phy_aux_clk",
3376 .parent_hws = (const struct clk_hw*[]){
3377 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3380 .flags = CLK_SET_RATE_PARENT,
3381 .ops = &clk_branch2_ops,
3386 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3387 .halt_reg = 0x10058,
3388 .halt_check = BRANCH_HALT,
3390 .enable_reg = 0x10058,
3391 .enable_mask = BIT(0),
3392 .hw.init = &(struct clk_init_data){
3393 .name = "gcc_usb3_sec_phy_com_aux_clk",
3394 .parent_hws = (const struct clk_hw*[]){
3395 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3398 .flags = CLK_SET_RATE_PARENT,
3399 .ops = &clk_branch2_ops,
3404 /* Clock ON depends on external parent clock, so don't poll */
3405 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3406 .halt_reg = 0x1005c,
3407 .halt_check = BRANCH_HALT_DELAY,
3409 .enable_reg = 0x1005c,
3410 .enable_mask = BIT(0),
3411 .hw.init = &(struct clk_init_data){
3412 .name = "gcc_usb3_sec_phy_pipe_clk",
3413 .parent_hws = (const struct clk_hw*[]){
3414 &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
3417 .flags = CLK_SET_RATE_PARENT,
3418 .ops = &clk_branch2_ops,
3423 /* external clocks so add BRANCH_HALT_SKIP */
3424 static struct clk_branch gcc_video_axi0_clk = {
3425 .halt_reg = 0x28010,
3426 .halt_check = BRANCH_HALT_SKIP,
3427 .hwcg_reg = 0x28010,
3430 .enable_reg = 0x28010,
3431 .enable_mask = BIT(0),
3432 .hw.init = &(struct clk_init_data){
3433 .name = "gcc_video_axi0_clk",
3434 .ops = &clk_branch2_ops,
3439 /* external clocks so add BRANCH_HALT_SKIP */
3440 static struct clk_branch gcc_video_axi1_clk = {
3441 .halt_reg = 0x28018,
3442 .halt_check = BRANCH_HALT_SKIP,
3443 .hwcg_reg = 0x28018,
3446 .enable_reg = 0x28018,
3447 .enable_mask = BIT(0),
3448 .hw.init = &(struct clk_init_data){
3449 .name = "gcc_video_axi1_clk",
3450 .ops = &clk_branch2_ops,
3455 static struct gdsc pcie_0_gdsc = {
3458 .name = "pcie_0_gdsc",
3460 .pwrsts = PWRSTS_OFF_ON,
3463 static struct gdsc pcie_1_gdsc = {
3466 .name = "pcie_1_gdsc",
3468 .pwrsts = PWRSTS_OFF_ON,
3471 static struct gdsc ufs_card_gdsc = {
3474 .name = "ufs_card_gdsc",
3476 .pwrsts = PWRSTS_OFF_ON,
3479 static struct gdsc ufs_phy_gdsc = {
3482 .name = "ufs_phy_gdsc",
3484 .pwrsts = PWRSTS_OFF_ON,
3487 static struct gdsc usb30_prim_gdsc = {
3490 .name = "usb30_prim_gdsc",
3492 .pwrsts = PWRSTS_OFF_ON,
3495 static struct gdsc usb30_sec_gdsc = {
3498 .name = "usb30_sec_gdsc",
3500 .pwrsts = PWRSTS_OFF_ON,
3503 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3506 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3508 .pwrsts = PWRSTS_OFF_ON,
3512 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3515 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3517 .pwrsts = PWRSTS_OFF_ON,
3521 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
3524 .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
3526 .pwrsts = PWRSTS_OFF_ON,
3530 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = {
3533 .name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc",
3535 .pwrsts = PWRSTS_OFF_ON,
3539 static struct clk_regmap *gcc_sm8350_clocks[] = {
3540 [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
3541 [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
3542 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3543 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3544 [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
3545 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3546 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3547 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3548 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3549 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3550 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3551 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3552 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3553 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3554 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3555 [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
3556 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3557 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3558 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3559 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3560 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3561 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3562 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3563 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3564 [GCC_GPLL0] = &gcc_gpll0.clkr,
3565 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3566 [GCC_GPLL4] = &gcc_gpll4.clkr,
3567 [GCC_GPLL9] = &gcc_gpll9.clkr,
3568 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3569 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3570 [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
3571 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3572 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3573 [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
3574 [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
3575 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3576 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3577 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3578 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
3579 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3580 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3581 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3582 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3583 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3584 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3585 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3586 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3587 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3588 [GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,
3589 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3590 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3591 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3592 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3593 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3594 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3595 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3596 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3597 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3598 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3599 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3600 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3601 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3602 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3603 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3604 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3605 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3606 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3607 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3608 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3609 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3610 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3611 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3612 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3613 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3614 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3615 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3616 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3617 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3618 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3619 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3620 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3621 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3622 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3623 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3624 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3625 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3626 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3627 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3628 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3629 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3630 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3631 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3632 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3633 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3634 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3635 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3636 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
3637 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
3638 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3639 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3640 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3641 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3642 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3643 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3644 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3645 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3646 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3647 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3648 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3649 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3650 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3651 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3652 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3653 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3654 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3655 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3656 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3657 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3658 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3659 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3660 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3661 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3662 [GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
3663 [GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr,
3664 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3665 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3666 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3667 [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
3668 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3669 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3670 [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
3671 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3672 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3673 [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
3674 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3675 [GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr,
3676 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3677 [GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr,
3678 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3679 [GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr,
3680 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3681 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
3682 [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
3683 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3684 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3685 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3686 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3687 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3688 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3689 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3690 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3691 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3692 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3693 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3694 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3695 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3696 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3697 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3698 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3699 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3700 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3701 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3702 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3703 [GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON] =
3704 &gcc_usb30_prim_master_clk__force_mem_core_on.clkr,
3705 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3706 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3707 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3708 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3709 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3710 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3711 [GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON] =
3712 &gcc_usb30_sec_master_clk__force_mem_core_on.clkr,
3713 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3714 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3715 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3716 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
3717 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3718 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3719 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3720 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3721 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3722 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3723 [GCC_USB3_SEC_CLKREF_EN] = &gcc_usb3_sec_clkref_en.clkr,
3724 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3725 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3726 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3727 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3728 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
3729 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3730 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3733 static struct gdsc *gcc_sm8350_gdscs[] = {
3734 [PCIE_0_GDSC] = &pcie_0_gdsc,
3735 [PCIE_1_GDSC] = &pcie_1_gdsc,
3736 [UFS_CARD_GDSC] = &ufs_card_gdsc,
3737 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3738 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3739 [USB30_SEC_GDSC] = &usb30_sec_gdsc,
3740 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3741 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3742 [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
3743 [HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc,
3746 static const struct qcom_reset_map gcc_sm8350_resets[] = {
3747 [GCC_CAMERA_BCR] = { 0x26000 },
3748 [GCC_DISPLAY_BCR] = { 0x27000 },
3749 [GCC_GPU_BCR] = { 0x71000 },
3750 [GCC_MMSS_BCR] = { 0xb000 },
3751 [GCC_PCIE_0_BCR] = { 0x6b000 },
3752 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3753 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3754 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3755 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3756 [GCC_PCIE_1_BCR] = { 0x8d000 },
3757 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3758 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3759 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3760 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
3761 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3762 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3763 [GCC_PDM_BCR] = { 0x33000 },
3764 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3765 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3766 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3767 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3768 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3769 [GCC_SDCC2_BCR] = { 0x14000 },
3770 [GCC_SDCC4_BCR] = { 0x16000 },
3771 [GCC_UFS_CARD_BCR] = { 0x75000 },
3772 [GCC_UFS_PHY_BCR] = { 0x77000 },
3773 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3774 [GCC_USB30_SEC_BCR] = { 0x10000 },
3775 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3776 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3777 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3778 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3779 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3780 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3781 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3782 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 },
3783 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 },
3784 [GCC_VIDEO_BCR] = { 0x28000 },
3787 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3788 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3789 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3790 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3791 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3792 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3793 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3794 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3795 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3796 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3797 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3798 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3799 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3800 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3801 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3802 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
3803 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
3804 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
3805 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
3806 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
3807 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
3810 static const struct regmap_config gcc_sm8350_regmap_config = {
3814 .max_register = 0x9c100,
3818 static const struct qcom_cc_desc gcc_sm8350_desc = {
3819 .config = &gcc_sm8350_regmap_config,
3820 .clks = gcc_sm8350_clocks,
3821 .num_clks = ARRAY_SIZE(gcc_sm8350_clocks),
3822 .resets = gcc_sm8350_resets,
3823 .num_resets = ARRAY_SIZE(gcc_sm8350_resets),
3824 .gdscs = gcc_sm8350_gdscs,
3825 .num_gdscs = ARRAY_SIZE(gcc_sm8350_gdscs),
3828 static const struct of_device_id gcc_sm8350_match_table[] = {
3829 { .compatible = "qcom,gcc-sm8350" },
3832 MODULE_DEVICE_TABLE(of, gcc_sm8350_match_table);
3834 static int gcc_sm8350_probe(struct platform_device *pdev)
3836 struct regmap *regmap;
3839 regmap = qcom_cc_map(pdev, &gcc_sm8350_desc);
3840 if (IS_ERR(regmap)) {
3841 dev_err(&pdev->dev, "Failed to map gcc registers\n");
3842 return PTR_ERR(regmap);
3846 * Keep the critical clock always-On
3847 * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK,
3848 * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK
3850 regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
3851 regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0));
3852 regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
3853 regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0));
3854 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
3855 regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
3856 regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0));
3858 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
3862 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
3863 regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
3865 return qcom_cc_really_probe(pdev, &gcc_sm8350_desc, regmap);
3868 static struct platform_driver gcc_sm8350_driver = {
3869 .probe = gcc_sm8350_probe,
3871 .name = "sm8350-gcc",
3872 .of_match_table = gcc_sm8350_match_table,
3876 static int __init gcc_sm8350_init(void)
3878 return platform_driver_register(&gcc_sm8350_driver);
3880 subsys_initcall(gcc_sm8350_init);
3882 static void __exit gcc_sm8350_exit(void)
3884 platform_driver_unregister(&gcc_sm8350_driver);
3886 module_exit(gcc_sm8350_exit);
3888 MODULE_DESCRIPTION("QTI GCC SM8350 Driver");
3889 MODULE_LICENSE("GPL v2");