1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2021, Linaro Limited
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
12 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
32 P_UFS_CARD_RX_SYMBOL_0_CLK,
33 P_UFS_CARD_RX_SYMBOL_1_CLK,
34 P_UFS_CARD_TX_SYMBOL_0_CLK,
35 P_UFS_PHY_RX_SYMBOL_0_CLK,
36 P_UFS_PHY_RX_SYMBOL_1_CLK,
37 P_UFS_PHY_TX_SYMBOL_0_CLK,
38 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
39 P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,
42 static struct clk_alpha_pll gcc_gpll0 = {
44 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
46 .enable_reg = 0x52018,
47 .enable_mask = BIT(0),
48 .hw.init = &(struct clk_init_data){
50 .parent_data = &(const struct clk_parent_data){
54 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
59 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
64 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
67 .post_div_table = post_div_table_gcc_gpll0_out_even,
68 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
70 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
71 .clkr.hw.init = &(struct clk_init_data){
72 .name = "gcc_gpll0_out_even",
73 .parent_hws = (const struct clk_hw*[]){
77 .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,
81 static struct clk_alpha_pll gcc_gpll4 = {
83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
85 .enable_reg = 0x52018,
86 .enable_mask = BIT(4),
87 .hw.init = &(struct clk_init_data){
89 .parent_data = &(const struct clk_parent_data){
94 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
99 static struct clk_alpha_pll gcc_gpll9 = {
101 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
103 .enable_reg = 0x52018,
104 .enable_mask = BIT(9),
105 .hw.init = &(struct clk_init_data){
107 .parent_data = &(const struct clk_parent_data){
108 .fw_name = "bi_tcxo",
112 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
117 static const struct parent_map gcc_parent_map_0[] = {
119 { P_GCC_GPLL0_OUT_MAIN, 1 },
120 { P_GCC_GPLL0_OUT_EVEN, 6 },
123 static const struct clk_parent_data gcc_parent_data_0[] = {
124 { .fw_name = "bi_tcxo" },
125 { .hw = &gcc_gpll0.clkr.hw },
126 { .hw = &gcc_gpll0_out_even.clkr.hw },
129 static const struct parent_map gcc_parent_map_1[] = {
131 { P_GCC_GPLL0_OUT_MAIN, 1 },
133 { P_GCC_GPLL0_OUT_EVEN, 6 },
136 static const struct clk_parent_data gcc_parent_data_1[] = {
137 { .fw_name = "bi_tcxo" },
138 { .hw = &gcc_gpll0.clkr.hw },
139 { .fw_name = "sleep_clk" },
140 { .hw = &gcc_gpll0_out_even.clkr.hw },
143 static const struct parent_map gcc_parent_map_2[] = {
148 static const struct clk_parent_data gcc_parent_data_2[] = {
149 { .fw_name = "bi_tcxo" },
150 { .fw_name = "sleep_clk" },
153 static const struct parent_map gcc_parent_map_3[] = {
157 static const struct clk_parent_data gcc_parent_data_3[] = {
158 { .fw_name = "bi_tcxo" },
161 static const struct parent_map gcc_parent_map_4[] = {
162 { P_PCIE_0_PIPE_CLK, 0 },
166 static const struct clk_parent_data gcc_parent_data_4[] = {
167 { .fw_name = "pcie_0_pipe_clk", },
168 { .fw_name = "bi_tcxo" },
171 static const struct parent_map gcc_parent_map_5[] = {
172 { P_PCIE_1_PIPE_CLK, 0 },
176 static const struct clk_parent_data gcc_parent_data_5[] = {
177 { .fw_name = "pcie_1_pipe_clk" },
178 { .fw_name = "bi_tcxo" },
181 static const struct parent_map gcc_parent_map_6[] = {
183 { P_GCC_GPLL0_OUT_MAIN, 1 },
184 { P_GCC_GPLL9_OUT_MAIN, 2 },
185 { P_GCC_GPLL4_OUT_MAIN, 5 },
186 { P_GCC_GPLL0_OUT_EVEN, 6 },
189 static const struct clk_parent_data gcc_parent_data_6[] = {
190 { .fw_name = "bi_tcxo" },
191 { .hw = &gcc_gpll0.clkr.hw },
192 { .hw = &gcc_gpll9.clkr.hw },
193 { .hw = &gcc_gpll4.clkr.hw },
194 { .hw = &gcc_gpll0_out_even.clkr.hw },
197 static const struct parent_map gcc_parent_map_7[] = {
198 { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
202 static const struct clk_parent_data gcc_parent_data_7[] = {
203 { .fw_name = "ufs_card_rx_symbol_0_clk" },
204 { .fw_name = "bi_tcxo" },
207 static const struct parent_map gcc_parent_map_8[] = {
208 { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
212 static const struct clk_parent_data gcc_parent_data_8[] = {
213 { .fw_name = "ufs_card_rx_symbol_1_clk" },
214 { .fw_name = "bi_tcxo" },
217 static const struct parent_map gcc_parent_map_9[] = {
218 { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
222 static const struct clk_parent_data gcc_parent_data_9[] = {
223 { .fw_name = "ufs_card_tx_symbol_0_clk" },
224 { .fw_name = "bi_tcxo" },
227 static const struct parent_map gcc_parent_map_10[] = {
228 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
232 static const struct clk_parent_data gcc_parent_data_10[] = {
233 { .fw_name = "ufs_phy_rx_symbol_0_clk" },
234 { .fw_name = "bi_tcxo" },
237 static const struct parent_map gcc_parent_map_11[] = {
238 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
242 static const struct clk_parent_data gcc_parent_data_11[] = {
243 { .fw_name = "ufs_phy_rx_symbol_1_clk" },
244 { .fw_name = "bi_tcxo" },
247 static const struct parent_map gcc_parent_map_12[] = {
248 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
252 static const struct clk_parent_data gcc_parent_data_12[] = {
253 { .fw_name = "ufs_phy_tx_symbol_0_clk" },
254 { .fw_name = "bi_tcxo" },
257 static const struct parent_map gcc_parent_map_13[] = {
258 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
262 static const struct clk_parent_data gcc_parent_data_13[] = {
263 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
264 { .fw_name = "bi_tcxo" },
267 static const struct parent_map gcc_parent_map_14[] = {
268 { P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 },
272 static const struct clk_parent_data gcc_parent_data_14[] = {
273 { .fw_name = "usb3_uni_phy_sec_gcc_usb30_pipe_clk" },
274 { .fw_name = "bi_tcxo" },
277 static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
281 .parent_map = gcc_parent_map_4,
283 .hw.init = &(struct clk_init_data){
284 .name = "gcc_pcie_0_pipe_clk_src",
285 .parent_data = gcc_parent_data_4,
286 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
287 .ops = &clk_regmap_mux_closest_ops,
292 static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
296 .parent_map = gcc_parent_map_5,
298 .hw.init = &(struct clk_init_data){
299 .name = "gcc_pcie_1_pipe_clk_src",
300 .parent_data = gcc_parent_data_5,
301 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
302 .ops = &clk_regmap_mux_closest_ops,
307 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = {
311 .parent_map = gcc_parent_map_7,
313 .hw.init = &(struct clk_init_data){
314 .name = "gcc_ufs_card_rx_symbol_0_clk_src",
315 .parent_data = gcc_parent_data_7,
316 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
317 .ops = &clk_regmap_mux_closest_ops,
322 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = {
326 .parent_map = gcc_parent_map_8,
328 .hw.init = &(struct clk_init_data){
329 .name = "gcc_ufs_card_rx_symbol_1_clk_src",
330 .parent_data = gcc_parent_data_8,
331 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
332 .ops = &clk_regmap_mux_closest_ops,
337 static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = {
341 .parent_map = gcc_parent_map_9,
343 .hw.init = &(struct clk_init_data){
344 .name = "gcc_ufs_card_tx_symbol_0_clk_src",
345 .parent_data = gcc_parent_data_9,
346 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
347 .ops = &clk_regmap_mux_closest_ops,
352 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
356 .parent_map = gcc_parent_map_10,
358 .hw.init = &(struct clk_init_data){
359 .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
360 .parent_data = gcc_parent_data_10,
361 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
362 .ops = &clk_regmap_mux_closest_ops,
367 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
371 .parent_map = gcc_parent_map_11,
373 .hw.init = &(struct clk_init_data){
374 .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
375 .parent_data = gcc_parent_data_11,
376 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
377 .ops = &clk_regmap_mux_closest_ops,
382 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
386 .parent_map = gcc_parent_map_12,
388 .hw.init = &(struct clk_init_data){
389 .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
390 .parent_data = gcc_parent_data_12,
391 .num_parents = ARRAY_SIZE(gcc_parent_data_12),
392 .ops = &clk_regmap_mux_closest_ops,
397 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
401 .parent_map = gcc_parent_map_13,
403 .hw.init = &(struct clk_init_data){
404 .name = "gcc_usb3_prim_phy_pipe_clk_src",
405 .parent_data = gcc_parent_data_13,
406 .num_parents = ARRAY_SIZE(gcc_parent_data_13),
407 .ops = &clk_regmap_mux_closest_ops,
412 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
416 .parent_map = gcc_parent_map_14,
418 .hw.init = &(struct clk_init_data){
419 .name = "gcc_usb3_sec_phy_pipe_clk_src",
420 .parent_data = gcc_parent_data_14,
421 .num_parents = ARRAY_SIZE(gcc_parent_data_14),
422 .ops = &clk_regmap_mux_closest_ops,
427 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
428 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
429 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
430 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
434 static struct clk_rcg2 gcc_gp1_clk_src = {
438 .parent_map = gcc_parent_map_1,
439 .freq_tbl = ftbl_gcc_gp1_clk_src,
440 .clkr.hw.init = &(struct clk_init_data){
441 .name = "gcc_gp1_clk_src",
442 .parent_data = gcc_parent_data_1,
443 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
444 .flags = CLK_SET_RATE_PARENT,
445 .ops = &clk_rcg2_ops,
449 static struct clk_rcg2 gcc_gp2_clk_src = {
453 .parent_map = gcc_parent_map_1,
454 .freq_tbl = ftbl_gcc_gp1_clk_src,
455 .clkr.hw.init = &(struct clk_init_data){
456 .name = "gcc_gp2_clk_src",
457 .parent_data = gcc_parent_data_1,
458 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
459 .flags = CLK_SET_RATE_PARENT,
460 .ops = &clk_rcg2_ops,
464 static struct clk_rcg2 gcc_gp3_clk_src = {
468 .parent_map = gcc_parent_map_1,
469 .freq_tbl = ftbl_gcc_gp1_clk_src,
470 .clkr.hw.init = &(struct clk_init_data){
471 .name = "gcc_gp3_clk_src",
472 .parent_data = gcc_parent_data_1,
473 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
474 .flags = CLK_SET_RATE_PARENT,
475 .ops = &clk_rcg2_ops,
479 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
480 F(9600000, P_BI_TCXO, 2, 0, 0),
481 F(19200000, P_BI_TCXO, 1, 0, 0),
485 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
489 .parent_map = gcc_parent_map_2,
490 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
491 .clkr.hw.init = &(struct clk_init_data){
492 .name = "gcc_pcie_0_aux_clk_src",
493 .parent_data = gcc_parent_data_2,
494 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
495 .flags = CLK_SET_RATE_PARENT,
496 .ops = &clk_rcg2_ops,
500 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
501 F(19200000, P_BI_TCXO, 1, 0, 0),
502 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
506 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
510 .parent_map = gcc_parent_map_0,
511 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
512 .clkr.hw.init = &(struct clk_init_data){
513 .name = "gcc_pcie_0_phy_rchng_clk_src",
514 .parent_data = gcc_parent_data_0,
515 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
516 .flags = CLK_SET_RATE_PARENT,
517 .ops = &clk_rcg2_ops,
521 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
525 .parent_map = gcc_parent_map_2,
526 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
527 .clkr.hw.init = &(struct clk_init_data){
528 .name = "gcc_pcie_1_aux_clk_src",
529 .parent_data = gcc_parent_data_2,
530 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
531 .flags = CLK_SET_RATE_PARENT,
532 .ops = &clk_rcg2_ops,
536 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
540 .parent_map = gcc_parent_map_0,
541 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
542 .clkr.hw.init = &(struct clk_init_data){
543 .name = "gcc_pcie_1_phy_rchng_clk_src",
544 .parent_data = gcc_parent_data_0,
545 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
546 .flags = CLK_SET_RATE_PARENT,
547 .ops = &clk_rcg2_ops,
551 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
552 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
556 static struct clk_rcg2 gcc_pdm2_clk_src = {
560 .parent_map = gcc_parent_map_0,
561 .freq_tbl = ftbl_gcc_pdm2_clk_src,
562 .clkr.hw.init = &(struct clk_init_data){
563 .name = "gcc_pdm2_clk_src",
564 .parent_data = gcc_parent_data_0,
565 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
566 .flags = CLK_SET_RATE_PARENT,
567 .ops = &clk_rcg2_ops,
571 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
572 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
573 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
574 F(19200000, P_BI_TCXO, 1, 0, 0),
575 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
576 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
577 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
578 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
579 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
580 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
581 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
582 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
586 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
587 .name = "gcc_qupv3_wrap0_s0_clk_src",
588 .parent_data = gcc_parent_data_0,
589 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
590 .flags = CLK_SET_RATE_PARENT,
591 .ops = &clk_rcg2_ops,
594 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
598 .parent_map = gcc_parent_map_0,
599 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
600 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
603 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
604 .name = "gcc_qupv3_wrap0_s1_clk_src",
605 .parent_data = gcc_parent_data_0,
606 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
607 .flags = CLK_SET_RATE_PARENT,
608 .ops = &clk_rcg2_ops,
611 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
615 .parent_map = gcc_parent_map_0,
616 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
617 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
620 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
621 .name = "gcc_qupv3_wrap0_s2_clk_src",
622 .parent_data = gcc_parent_data_0,
623 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
624 .flags = CLK_SET_RATE_PARENT,
625 .ops = &clk_rcg2_ops,
628 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
632 .parent_map = gcc_parent_map_0,
633 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
634 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
637 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
638 .name = "gcc_qupv3_wrap0_s3_clk_src",
639 .parent_data = gcc_parent_data_0,
640 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
641 .flags = CLK_SET_RATE_PARENT,
642 .ops = &clk_rcg2_ops,
645 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
649 .parent_map = gcc_parent_map_0,
650 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
651 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
654 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
655 .name = "gcc_qupv3_wrap0_s4_clk_src",
656 .parent_data = gcc_parent_data_0,
657 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
658 .flags = CLK_SET_RATE_PARENT,
659 .ops = &clk_rcg2_ops,
662 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
666 .parent_map = gcc_parent_map_0,
667 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
668 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
671 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
672 .name = "gcc_qupv3_wrap0_s5_clk_src",
673 .parent_data = gcc_parent_data_0,
674 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
675 .flags = CLK_SET_RATE_PARENT,
676 .ops = &clk_rcg2_ops,
679 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
683 .parent_map = gcc_parent_map_0,
684 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
685 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
688 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
689 .name = "gcc_qupv3_wrap0_s6_clk_src",
690 .parent_data = gcc_parent_data_0,
691 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
692 .flags = CLK_SET_RATE_PARENT,
693 .ops = &clk_rcg2_ops,
696 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
700 .parent_map = gcc_parent_map_0,
701 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
702 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
705 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
706 .name = "gcc_qupv3_wrap0_s7_clk_src",
707 .parent_data = gcc_parent_data_0,
708 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
709 .flags = CLK_SET_RATE_PARENT,
710 .ops = &clk_rcg2_ops,
713 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
717 .parent_map = gcc_parent_map_0,
718 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
719 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
722 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
723 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
724 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
725 F(19200000, P_BI_TCXO, 1, 0, 0),
726 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
727 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
728 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
729 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
730 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
731 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
732 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
733 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
734 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
735 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
736 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
737 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
741 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
742 .name = "gcc_qupv3_wrap1_s0_clk_src",
743 .parent_data = gcc_parent_data_0,
744 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
745 .flags = CLK_SET_RATE_PARENT,
746 .ops = &clk_rcg2_ops,
749 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
753 .parent_map = gcc_parent_map_0,
754 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
755 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
758 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
759 .name = "gcc_qupv3_wrap1_s1_clk_src",
760 .parent_data = gcc_parent_data_0,
761 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
762 .flags = CLK_SET_RATE_PARENT,
763 .ops = &clk_rcg2_ops,
766 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
770 .parent_map = gcc_parent_map_0,
771 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
772 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
775 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
776 .name = "gcc_qupv3_wrap1_s2_clk_src",
777 .parent_data = gcc_parent_data_0,
778 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
779 .flags = CLK_SET_RATE_PARENT,
780 .ops = &clk_rcg2_ops,
783 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
787 .parent_map = gcc_parent_map_0,
788 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
789 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
792 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
793 .name = "gcc_qupv3_wrap1_s3_clk_src",
794 .parent_data = gcc_parent_data_0,
795 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
796 .flags = CLK_SET_RATE_PARENT,
797 .ops = &clk_rcg2_ops,
800 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
804 .parent_map = gcc_parent_map_0,
805 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
806 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
809 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
810 .name = "gcc_qupv3_wrap1_s4_clk_src",
811 .parent_data = gcc_parent_data_0,
812 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
813 .flags = CLK_SET_RATE_PARENT,
814 .ops = &clk_rcg2_ops,
817 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
821 .parent_map = gcc_parent_map_0,
822 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
823 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
826 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
827 .name = "gcc_qupv3_wrap1_s5_clk_src",
828 .parent_data = gcc_parent_data_0,
829 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
830 .flags = CLK_SET_RATE_PARENT,
831 .ops = &clk_rcg2_ops,
834 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
838 .parent_map = gcc_parent_map_0,
839 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
840 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
843 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
844 .name = "gcc_qupv3_wrap2_s0_clk_src",
845 .parent_data = gcc_parent_data_0,
846 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
847 .flags = CLK_SET_RATE_PARENT,
848 .ops = &clk_rcg2_ops,
851 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
855 .parent_map = gcc_parent_map_0,
856 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
857 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
860 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
861 .name = "gcc_qupv3_wrap2_s1_clk_src",
862 .parent_data = gcc_parent_data_0,
863 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
864 .flags = CLK_SET_RATE_PARENT,
865 .ops = &clk_rcg2_ops,
868 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
872 .parent_map = gcc_parent_map_0,
873 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
874 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
877 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
878 .name = "gcc_qupv3_wrap2_s2_clk_src",
879 .parent_data = gcc_parent_data_0,
880 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
881 .flags = CLK_SET_RATE_PARENT,
882 .ops = &clk_rcg2_ops,
885 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
889 .parent_map = gcc_parent_map_0,
890 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
891 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
894 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
895 .name = "gcc_qupv3_wrap2_s3_clk_src",
896 .parent_data = gcc_parent_data_0,
897 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
898 .flags = CLK_SET_RATE_PARENT,
899 .ops = &clk_rcg2_ops,
902 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
906 .parent_map = gcc_parent_map_0,
907 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
908 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
911 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
912 .name = "gcc_qupv3_wrap2_s4_clk_src",
913 .parent_data = gcc_parent_data_0,
914 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
915 .flags = CLK_SET_RATE_PARENT,
916 .ops = &clk_rcg2_ops,
919 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
923 .parent_map = gcc_parent_map_0,
924 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
925 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
928 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
929 .name = "gcc_qupv3_wrap2_s5_clk_src",
930 .parent_data = gcc_parent_data_0,
931 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
932 .flags = CLK_SET_RATE_PARENT,
933 .ops = &clk_rcg2_ops,
936 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
940 .parent_map = gcc_parent_map_0,
941 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
942 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
945 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
946 F(400000, P_BI_TCXO, 12, 1, 4),
947 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
948 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
949 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
950 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
954 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
958 .parent_map = gcc_parent_map_6,
959 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
960 .clkr.hw.init = &(struct clk_init_data){
961 .name = "gcc_sdcc2_apps_clk_src",
962 .parent_data = gcc_parent_data_6,
963 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
964 .flags = CLK_SET_RATE_PARENT,
965 .ops = &clk_rcg2_floor_ops,
969 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
970 F(400000, P_BI_TCXO, 12, 1, 4),
971 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
972 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
976 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
980 .parent_map = gcc_parent_map_0,
981 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
982 .clkr.hw.init = &(struct clk_init_data){
983 .name = "gcc_sdcc4_apps_clk_src",
984 .parent_data = gcc_parent_data_0,
985 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
986 .flags = CLK_SET_RATE_PARENT,
987 .ops = &clk_rcg2_floor_ops,
991 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
992 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
993 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
994 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
995 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
999 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
1000 .cmd_rcgr = 0x75024,
1003 .parent_map = gcc_parent_map_0,
1004 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1005 .clkr.hw.init = &(struct clk_init_data){
1006 .name = "gcc_ufs_card_axi_clk_src",
1007 .parent_data = gcc_parent_data_0,
1008 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1009 .flags = CLK_SET_RATE_PARENT,
1010 .ops = &clk_rcg2_ops,
1014 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
1015 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1016 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1017 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1021 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
1022 .cmd_rcgr = 0x7506c,
1025 .parent_map = gcc_parent_map_0,
1026 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1027 .clkr.hw.init = &(struct clk_init_data){
1028 .name = "gcc_ufs_card_ice_core_clk_src",
1029 .parent_data = gcc_parent_data_0,
1030 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1031 .flags = CLK_SET_RATE_PARENT,
1032 .ops = &clk_rcg2_ops,
1036 static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
1037 F(19200000, P_BI_TCXO, 1, 0, 0),
1041 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
1042 .cmd_rcgr = 0x750a0,
1045 .parent_map = gcc_parent_map_3,
1046 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1047 .clkr.hw.init = &(struct clk_init_data){
1048 .name = "gcc_ufs_card_phy_aux_clk_src",
1049 .parent_data = gcc_parent_data_3,
1050 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1051 .flags = CLK_SET_RATE_PARENT,
1052 .ops = &clk_rcg2_ops,
1056 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
1057 .cmd_rcgr = 0x75084,
1060 .parent_map = gcc_parent_map_0,
1061 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1062 .clkr.hw.init = &(struct clk_init_data){
1063 .name = "gcc_ufs_card_unipro_core_clk_src",
1064 .parent_data = gcc_parent_data_0,
1065 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1066 .flags = CLK_SET_RATE_PARENT,
1067 .ops = &clk_rcg2_ops,
1071 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1072 .cmd_rcgr = 0x77024,
1075 .parent_map = gcc_parent_map_0,
1076 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1077 .clkr.hw.init = &(struct clk_init_data){
1078 .name = "gcc_ufs_phy_axi_clk_src",
1079 .parent_data = gcc_parent_data_0,
1080 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1081 .flags = CLK_SET_RATE_PARENT,
1082 .ops = &clk_rcg2_ops,
1086 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1087 .cmd_rcgr = 0x7706c,
1090 .parent_map = gcc_parent_map_0,
1091 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1092 .clkr.hw.init = &(struct clk_init_data){
1093 .name = "gcc_ufs_phy_ice_core_clk_src",
1094 .parent_data = gcc_parent_data_0,
1095 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1096 .flags = CLK_SET_RATE_PARENT,
1097 .ops = &clk_rcg2_ops,
1101 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1102 .cmd_rcgr = 0x770a0,
1105 .parent_map = gcc_parent_map_3,
1106 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1107 .clkr.hw.init = &(struct clk_init_data){
1108 .name = "gcc_ufs_phy_phy_aux_clk_src",
1109 .parent_data = gcc_parent_data_3,
1110 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1111 .flags = CLK_SET_RATE_PARENT,
1112 .ops = &clk_rcg2_ops,
1116 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1117 .cmd_rcgr = 0x77084,
1120 .parent_map = gcc_parent_map_0,
1121 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1122 .clkr.hw.init = &(struct clk_init_data){
1123 .name = "gcc_ufs_phy_unipro_core_clk_src",
1124 .parent_data = gcc_parent_data_0,
1125 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1126 .flags = CLK_SET_RATE_PARENT,
1127 .ops = &clk_rcg2_ops,
1131 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1132 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1133 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1134 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1135 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1139 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1143 .parent_map = gcc_parent_map_0,
1144 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1145 .clkr.hw.init = &(struct clk_init_data){
1146 .name = "gcc_usb30_prim_master_clk_src",
1147 .parent_data = gcc_parent_data_0,
1148 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1149 .flags = CLK_SET_RATE_PARENT,
1150 .ops = &clk_rcg2_ops,
1154 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1158 .parent_map = gcc_parent_map_0,
1159 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1160 .clkr.hw.init = &(struct clk_init_data){
1161 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1162 .parent_data = gcc_parent_data_0,
1163 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1164 .flags = CLK_SET_RATE_PARENT,
1165 .ops = &clk_rcg2_ops,
1169 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1170 .cmd_rcgr = 0x10020,
1173 .parent_map = gcc_parent_map_0,
1174 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1175 .clkr.hw.init = &(struct clk_init_data){
1176 .name = "gcc_usb30_sec_master_clk_src",
1177 .parent_data = gcc_parent_data_0,
1178 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1179 .flags = CLK_SET_RATE_PARENT,
1180 .ops = &clk_rcg2_ops,
1184 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1185 .cmd_rcgr = 0x10038,
1188 .parent_map = gcc_parent_map_0,
1189 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1190 .clkr.hw.init = &(struct clk_init_data){
1191 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1192 .parent_data = gcc_parent_data_0,
1193 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1194 .flags = CLK_SET_RATE_PARENT,
1195 .ops = &clk_rcg2_ops,
1199 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1203 .parent_map = gcc_parent_map_2,
1204 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1205 .clkr.hw.init = &(struct clk_init_data){
1206 .name = "gcc_usb3_prim_phy_aux_clk_src",
1207 .parent_data = gcc_parent_data_2,
1208 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1209 .flags = CLK_SET_RATE_PARENT,
1210 .ops = &clk_rcg2_ops,
1214 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1215 .cmd_rcgr = 0x10064,
1218 .parent_map = gcc_parent_map_2,
1219 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1220 .clkr.hw.init = &(struct clk_init_data){
1221 .name = "gcc_usb3_sec_phy_aux_clk_src",
1222 .parent_data = gcc_parent_data_2,
1223 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1224 .flags = CLK_SET_RATE_PARENT,
1225 .ops = &clk_rcg2_ops,
1229 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1233 .clkr.hw.init = &(struct clk_init_data) {
1234 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1235 .parent_hws = (const struct clk_hw*[]){
1236 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1239 .flags = CLK_SET_RATE_PARENT,
1240 .ops = &clk_regmap_div_ro_ops,
1244 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
1248 .clkr.hw.init = &(struct clk_init_data) {
1249 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
1250 .parent_hws = (const struct clk_hw*[]){
1251 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
1254 .flags = CLK_SET_RATE_PARENT,
1255 .ops = &clk_regmap_div_ro_ops,
1259 /* external clocks so add BRANCH_HALT_SKIP */
1260 static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1261 .halt_reg = 0x6b080,
1262 .halt_check = BRANCH_HALT_SKIP,
1264 .enable_reg = 0x52000,
1265 .enable_mask = BIT(12),
1266 .hw.init = &(struct clk_init_data){
1267 .name = "gcc_aggre_noc_pcie_0_axi_clk",
1268 .ops = &clk_branch2_ops,
1273 /* external clocks so add BRANCH_HALT_SKIP */
1274 static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
1275 .halt_reg = 0x8d084,
1276 .halt_check = BRANCH_HALT_SKIP,
1278 .enable_reg = 0x52000,
1279 .enable_mask = BIT(11),
1280 .hw.init = &(struct clk_init_data){
1281 .name = "gcc_aggre_noc_pcie_1_axi_clk",
1282 .ops = &clk_branch2_ops,
1287 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1288 .halt_reg = 0x9000c,
1289 .halt_check = BRANCH_HALT_VOTED,
1290 .hwcg_reg = 0x9000c,
1293 .enable_reg = 0x52000,
1294 .enable_mask = BIT(18),
1295 .hw.init = &(struct clk_init_data){
1296 .name = "gcc_aggre_noc_pcie_tbu_clk",
1297 .ops = &clk_branch2_ops,
1302 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1303 .halt_reg = 0x750cc,
1304 .halt_check = BRANCH_HALT_VOTED,
1305 .hwcg_reg = 0x750cc,
1308 .enable_reg = 0x750cc,
1309 .enable_mask = BIT(0),
1310 .hw.init = &(struct clk_init_data){
1311 .name = "gcc_aggre_ufs_card_axi_clk",
1312 .parent_hws = (const struct clk_hw*[]){
1313 &gcc_ufs_card_axi_clk_src.clkr.hw,
1316 .flags = CLK_SET_RATE_PARENT,
1317 .ops = &clk_branch2_ops,
1322 static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1323 .halt_reg = 0x750cc,
1324 .halt_check = BRANCH_HALT_VOTED,
1325 .hwcg_reg = 0x750cc,
1328 .enable_reg = 0x750cc,
1329 .enable_mask = BIT(1),
1330 .hw.init = &(struct clk_init_data){
1331 .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1332 .parent_hws = (const struct clk_hw*[]){
1333 &gcc_ufs_card_axi_clk_src.clkr.hw,
1336 .flags = CLK_SET_RATE_PARENT,
1337 .ops = &clk_branch2_ops,
1342 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1343 .halt_reg = 0x770cc,
1344 .halt_check = BRANCH_HALT_VOTED,
1345 .hwcg_reg = 0x770cc,
1348 .enable_reg = 0x770cc,
1349 .enable_mask = BIT(0),
1350 .hw.init = &(struct clk_init_data){
1351 .name = "gcc_aggre_ufs_phy_axi_clk",
1352 .parent_hws = (const struct clk_hw*[]){
1353 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1356 .flags = CLK_SET_RATE_PARENT,
1357 .ops = &clk_branch2_ops,
1362 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1363 .halt_reg = 0x770cc,
1364 .halt_check = BRANCH_HALT_VOTED,
1365 .hwcg_reg = 0x770cc,
1368 .enable_reg = 0x770cc,
1369 .enable_mask = BIT(1),
1370 .hw.init = &(struct clk_init_data){
1371 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1372 .parent_hws = (const struct clk_hw*[]){
1373 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1376 .flags = CLK_SET_RATE_PARENT,
1377 .ops = &clk_branch2_ops,
1382 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1384 .halt_check = BRANCH_HALT_VOTED,
1388 .enable_reg = 0xf080,
1389 .enable_mask = BIT(0),
1390 .hw.init = &(struct clk_init_data){
1391 .name = "gcc_aggre_usb3_prim_axi_clk",
1392 .parent_hws = (const struct clk_hw*[]){
1393 &gcc_usb30_prim_master_clk_src.clkr.hw,
1396 .flags = CLK_SET_RATE_PARENT,
1397 .ops = &clk_branch2_ops,
1402 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1403 .halt_reg = 0x10080,
1404 .halt_check = BRANCH_HALT_VOTED,
1405 .hwcg_reg = 0x10080,
1408 .enable_reg = 0x10080,
1409 .enable_mask = BIT(0),
1410 .hw.init = &(struct clk_init_data){
1411 .name = "gcc_aggre_usb3_sec_axi_clk",
1412 .parent_hws = (const struct clk_hw*[]){
1413 &gcc_usb30_sec_master_clk_src.clkr.hw,
1416 .flags = CLK_SET_RATE_PARENT,
1417 .ops = &clk_branch2_ops,
1422 static struct clk_branch gcc_boot_rom_ahb_clk = {
1423 .halt_reg = 0x38004,
1424 .halt_check = BRANCH_HALT_VOTED,
1425 .hwcg_reg = 0x38004,
1428 .enable_reg = 0x52000,
1429 .enable_mask = BIT(10),
1430 .hw.init = &(struct clk_init_data){
1431 .name = "gcc_boot_rom_ahb_clk",
1432 .ops = &clk_branch2_ops,
1437 /* external clocks so add BRANCH_HALT_SKIP */
1438 static struct clk_branch gcc_camera_hf_axi_clk = {
1439 .halt_reg = 0x26010,
1440 .halt_check = BRANCH_HALT_SKIP,
1441 .hwcg_reg = 0x26010,
1444 .enable_reg = 0x26010,
1445 .enable_mask = BIT(0),
1446 .hw.init = &(struct clk_init_data){
1447 .name = "gcc_camera_hf_axi_clk",
1448 .ops = &clk_branch2_ops,
1453 /* external clocks so add BRANCH_HALT_SKIP */
1454 static struct clk_branch gcc_camera_sf_axi_clk = {
1455 .halt_reg = 0x26014,
1456 .halt_check = BRANCH_HALT_SKIP,
1457 .hwcg_reg = 0x26014,
1460 .enable_reg = 0x26014,
1461 .enable_mask = BIT(0),
1462 .hw.init = &(struct clk_init_data){
1463 .name = "gcc_camera_sf_axi_clk",
1464 .ops = &clk_branch2_ops,
1469 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1471 .halt_check = BRANCH_HALT_VOTED,
1475 .enable_reg = 0xf07c,
1476 .enable_mask = BIT(0),
1477 .hw.init = &(struct clk_init_data){
1478 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1479 .parent_hws = (const struct clk_hw*[]){
1480 &gcc_usb30_prim_master_clk_src.clkr.hw,
1483 .flags = CLK_SET_RATE_PARENT,
1484 .ops = &clk_branch2_ops,
1489 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1490 .halt_reg = 0x1007c,
1491 .halt_check = BRANCH_HALT_VOTED,
1492 .hwcg_reg = 0x1007c,
1495 .enable_reg = 0x1007c,
1496 .enable_mask = BIT(0),
1497 .hw.init = &(struct clk_init_data){
1498 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1499 .parent_hws = (const struct clk_hw*[]){
1500 &gcc_usb30_sec_master_clk_src.clkr.hw,
1503 .flags = CLK_SET_RATE_PARENT,
1504 .ops = &clk_branch2_ops,
1509 /* external clocks so add BRANCH_HALT_SKIP */
1510 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1511 .halt_reg = 0x71154,
1512 .halt_check = BRANCH_HALT_SKIP,
1513 .hwcg_reg = 0x71154,
1516 .enable_reg = 0x71154,
1517 .enable_mask = BIT(0),
1518 .hw.init = &(struct clk_init_data){
1519 .name = "gcc_ddrss_gpu_axi_clk",
1520 .ops = &clk_branch2_aon_ops,
1525 /* external clocks so add BRANCH_HALT_SKIP */
1526 static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
1527 .halt_reg = 0x8d080,
1528 .halt_check = BRANCH_HALT_SKIP,
1529 .hwcg_reg = 0x8d080,
1532 .enable_reg = 0x52000,
1533 .enable_mask = BIT(19),
1534 .hw.init = &(struct clk_init_data){
1535 .name = "gcc_ddrss_pcie_sf_tbu_clk",
1536 .ops = &clk_branch2_ops,
1541 /* external clocks so add BRANCH_HALT_SKIP */
1542 static struct clk_branch gcc_disp_hf_axi_clk = {
1543 .halt_reg = 0x2700c,
1544 .halt_check = BRANCH_HALT_SKIP,
1545 .hwcg_reg = 0x2700c,
1548 .enable_reg = 0x2700c,
1549 .enable_mask = BIT(0),
1550 .hw.init = &(struct clk_init_data){
1551 .name = "gcc_disp_hf_axi_clk",
1552 .ops = &clk_branch2_ops,
1557 /* external clocks so add BRANCH_HALT_SKIP */
1558 static struct clk_branch gcc_disp_sf_axi_clk = {
1559 .halt_reg = 0x27014,
1560 .halt_check = BRANCH_HALT_SKIP,
1561 .hwcg_reg = 0x27014,
1564 .enable_reg = 0x27014,
1565 .enable_mask = BIT(0),
1566 .hw.init = &(struct clk_init_data){
1567 .name = "gcc_disp_sf_axi_clk",
1568 .ops = &clk_branch2_ops,
1573 static struct clk_branch gcc_gp1_clk = {
1574 .halt_reg = 0x64000,
1575 .halt_check = BRANCH_HALT,
1577 .enable_reg = 0x64000,
1578 .enable_mask = BIT(0),
1579 .hw.init = &(struct clk_init_data){
1580 .name = "gcc_gp1_clk",
1581 .parent_hws = (const struct clk_hw*[]){
1582 &gcc_gp1_clk_src.clkr.hw,
1585 .flags = CLK_SET_RATE_PARENT,
1586 .ops = &clk_branch2_ops,
1591 static struct clk_branch gcc_gp2_clk = {
1592 .halt_reg = 0x65000,
1593 .halt_check = BRANCH_HALT,
1595 .enable_reg = 0x65000,
1596 .enable_mask = BIT(0),
1597 .hw.init = &(struct clk_init_data){
1598 .name = "gcc_gp2_clk",
1599 .parent_hws = (const struct clk_hw*[]){
1600 &gcc_gp2_clk_src.clkr.hw,
1603 .flags = CLK_SET_RATE_PARENT,
1604 .ops = &clk_branch2_ops,
1609 static struct clk_branch gcc_gp3_clk = {
1610 .halt_reg = 0x66000,
1611 .halt_check = BRANCH_HALT,
1613 .enable_reg = 0x66000,
1614 .enable_mask = BIT(0),
1615 .hw.init = &(struct clk_init_data){
1616 .name = "gcc_gp3_clk",
1617 .parent_hws = (const struct clk_hw*[]){
1618 &gcc_gp3_clk_src.clkr.hw,
1621 .flags = CLK_SET_RATE_PARENT,
1622 .ops = &clk_branch2_ops,
1627 /* Clock ON depends on external parent clock, so don't poll */
1628 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1629 .halt_check = BRANCH_HALT_DELAY,
1631 .enable_reg = 0x52000,
1632 .enable_mask = BIT(15),
1633 .hw.init = &(struct clk_init_data){
1634 .name = "gcc_gpu_gpll0_clk_src",
1635 .parent_hws = (const struct clk_hw*[]){
1639 .flags = CLK_SET_RATE_PARENT,
1640 .ops = &clk_branch2_ops,
1645 /* Clock ON depends on external parent clock, so don't poll */
1646 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1647 .halt_check = BRANCH_HALT_DELAY,
1649 .enable_reg = 0x52000,
1650 .enable_mask = BIT(16),
1651 .hw.init = &(struct clk_init_data){
1652 .name = "gcc_gpu_gpll0_div_clk_src",
1653 .parent_hws = (const struct clk_hw*[]){
1654 &gcc_gpll0_out_even.clkr.hw,
1657 .flags = CLK_SET_RATE_PARENT,
1658 .ops = &clk_branch2_ops,
1663 static struct clk_branch gcc_gpu_iref_en = {
1664 .halt_reg = 0x8c014,
1665 .halt_check = BRANCH_HALT,
1667 .enable_reg = 0x8c014,
1668 .enable_mask = BIT(0),
1669 .hw.init = &(struct clk_init_data){
1670 .name = "gcc_gpu_iref_en",
1671 .ops = &clk_branch2_ops,
1676 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1677 .halt_reg = 0x7100c,
1678 .halt_check = BRANCH_HALT_VOTED,
1679 .hwcg_reg = 0x7100c,
1682 .enable_reg = 0x7100c,
1683 .enable_mask = BIT(0),
1684 .hw.init = &(struct clk_init_data){
1685 .name = "gcc_gpu_memnoc_gfx_clk",
1686 .ops = &clk_branch2_aon_ops,
1691 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1692 .halt_reg = 0x71018,
1693 .halt_check = BRANCH_HALT,
1695 .enable_reg = 0x71018,
1696 .enable_mask = BIT(0),
1697 .hw.init = &(struct clk_init_data){
1698 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1699 .ops = &clk_branch2_aon_ops,
1704 static struct clk_branch gcc_pcie0_phy_rchng_clk = {
1705 .halt_reg = 0x6b038,
1706 .halt_check = BRANCH_HALT_VOTED,
1708 .enable_reg = 0x52000,
1709 .enable_mask = BIT(22),
1710 .hw.init = &(struct clk_init_data){
1711 .name = "gcc_pcie0_phy_rchng_clk",
1712 .parent_hws = (const struct clk_hw*[]){
1713 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1716 .flags = CLK_SET_RATE_PARENT,
1717 .ops = &clk_branch2_ops,
1722 static struct clk_branch gcc_pcie1_phy_rchng_clk = {
1723 .halt_reg = 0x8d038,
1724 .halt_check = BRANCH_HALT_VOTED,
1726 .enable_reg = 0x52000,
1727 .enable_mask = BIT(23),
1728 .hw.init = &(struct clk_init_data){
1729 .name = "gcc_pcie1_phy_rchng_clk",
1730 .parent_hws = (const struct clk_hw*[]){
1731 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1734 .flags = CLK_SET_RATE_PARENT,
1735 .ops = &clk_branch2_ops,
1740 static struct clk_branch gcc_pcie_0_aux_clk = {
1741 .halt_reg = 0x6b028,
1742 .halt_check = BRANCH_HALT_VOTED,
1744 .enable_reg = 0x52008,
1745 .enable_mask = BIT(3),
1746 .hw.init = &(struct clk_init_data){
1747 .name = "gcc_pcie_0_aux_clk",
1748 .parent_hws = (const struct clk_hw*[]){
1749 &gcc_pcie_0_aux_clk_src.clkr.hw,
1752 .flags = CLK_SET_RATE_PARENT,
1753 .ops = &clk_branch2_ops,
1758 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1759 .halt_reg = 0x6b024,
1760 .halt_check = BRANCH_HALT_VOTED,
1761 .hwcg_reg = 0x6b024,
1764 .enable_reg = 0x52008,
1765 .enable_mask = BIT(2),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "gcc_pcie_0_cfg_ahb_clk",
1768 .ops = &clk_branch2_ops,
1773 static struct clk_branch gcc_pcie_0_clkref_en = {
1774 .halt_reg = 0x8c004,
1775 .halt_check = BRANCH_HALT,
1777 .enable_reg = 0x8c004,
1778 .enable_mask = BIT(0),
1779 .hw.init = &(struct clk_init_data){
1780 .name = "gcc_pcie_0_clkref_en",
1781 .ops = &clk_branch2_ops,
1786 /* external clocks so add BRANCH_HALT_SKIP */
1787 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1788 .halt_reg = 0x6b01c,
1789 .halt_check = BRANCH_HALT_SKIP,
1790 .hwcg_reg = 0x6b01c,
1793 .enable_reg = 0x52008,
1794 .enable_mask = BIT(1),
1795 .hw.init = &(struct clk_init_data){
1796 .name = "gcc_pcie_0_mstr_axi_clk",
1797 .ops = &clk_branch2_ops,
1802 /* external clocks so add BRANCH_HALT_SKIP */
1803 static struct clk_branch gcc_pcie_0_pipe_clk = {
1804 .halt_reg = 0x6b030,
1805 .halt_check = BRANCH_HALT_SKIP,
1807 .enable_reg = 0x52008,
1808 .enable_mask = BIT(4),
1809 .hw.init = &(struct clk_init_data){
1810 .name = "gcc_pcie_0_pipe_clk",
1811 .parent_hws = (const struct clk_hw*[]){
1812 &gcc_pcie_0_pipe_clk_src.clkr.hw,
1815 .flags = CLK_SET_RATE_PARENT,
1816 .ops = &clk_branch2_ops,
1821 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1822 .halt_reg = 0x6b014,
1823 .halt_check = BRANCH_HALT_VOTED,
1824 .hwcg_reg = 0x6b014,
1827 .enable_reg = 0x52008,
1828 .enable_mask = BIT(0),
1829 .hw.init = &(struct clk_init_data){
1830 .name = "gcc_pcie_0_slv_axi_clk",
1831 .ops = &clk_branch2_ops,
1836 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1837 .halt_reg = 0x6b010,
1838 .halt_check = BRANCH_HALT_VOTED,
1840 .enable_reg = 0x52008,
1841 .enable_mask = BIT(5),
1842 .hw.init = &(struct clk_init_data){
1843 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1844 .ops = &clk_branch2_ops,
1849 static struct clk_branch gcc_pcie_1_aux_clk = {
1850 .halt_reg = 0x8d028,
1851 .halt_check = BRANCH_HALT_VOTED,
1853 .enable_reg = 0x52000,
1854 .enable_mask = BIT(29),
1855 .hw.init = &(struct clk_init_data){
1856 .name = "gcc_pcie_1_aux_clk",
1857 .parent_hws = (const struct clk_hw*[]){
1858 &gcc_pcie_1_aux_clk_src.clkr.hw,
1861 .flags = CLK_SET_RATE_PARENT,
1862 .ops = &clk_branch2_ops,
1867 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1868 .halt_reg = 0x8d024,
1869 .halt_check = BRANCH_HALT_VOTED,
1870 .hwcg_reg = 0x8d024,
1873 .enable_reg = 0x52000,
1874 .enable_mask = BIT(28),
1875 .hw.init = &(struct clk_init_data){
1876 .name = "gcc_pcie_1_cfg_ahb_clk",
1877 .ops = &clk_branch2_ops,
1882 static struct clk_branch gcc_pcie_1_clkref_en = {
1883 .halt_reg = 0x8c008,
1884 .halt_check = BRANCH_HALT,
1886 .enable_reg = 0x8c008,
1887 .enable_mask = BIT(0),
1888 .hw.init = &(struct clk_init_data){
1889 .name = "gcc_pcie_1_clkref_en",
1890 .ops = &clk_branch2_ops,
1895 /* external clocks so add BRANCH_HALT_SKIP */
1896 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1897 .halt_reg = 0x8d01c,
1898 .halt_check = BRANCH_HALT_SKIP,
1899 .hwcg_reg = 0x8d01c,
1902 .enable_reg = 0x52000,
1903 .enable_mask = BIT(27),
1904 .hw.init = &(struct clk_init_data){
1905 .name = "gcc_pcie_1_mstr_axi_clk",
1906 .ops = &clk_branch2_ops,
1911 /* external clocks so add BRANCH_HALT_SKIP */
1912 static struct clk_branch gcc_pcie_1_pipe_clk = {
1913 .halt_reg = 0x8d030,
1914 .halt_check = BRANCH_HALT_SKIP,
1916 .enable_reg = 0x52000,
1917 .enable_mask = BIT(30),
1918 .hw.init = &(struct clk_init_data){
1919 .name = "gcc_pcie_1_pipe_clk",
1920 .parent_hws = (const struct clk_hw*[]){
1921 &gcc_pcie_1_pipe_clk_src.clkr.hw,
1924 .flags = CLK_SET_RATE_PARENT,
1925 .ops = &clk_branch2_ops,
1930 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1931 .halt_reg = 0x8d014,
1932 .halt_check = BRANCH_HALT_VOTED,
1933 .hwcg_reg = 0x8d014,
1936 .enable_reg = 0x52000,
1937 .enable_mask = BIT(26),
1938 .hw.init = &(struct clk_init_data){
1939 .name = "gcc_pcie_1_slv_axi_clk",
1940 .ops = &clk_branch2_ops,
1945 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1946 .halt_reg = 0x8d010,
1947 .halt_check = BRANCH_HALT_VOTED,
1949 .enable_reg = 0x52000,
1950 .enable_mask = BIT(25),
1951 .hw.init = &(struct clk_init_data){
1952 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1953 .ops = &clk_branch2_ops,
1958 static struct clk_branch gcc_pdm2_clk = {
1959 .halt_reg = 0x3300c,
1960 .halt_check = BRANCH_HALT,
1962 .enable_reg = 0x3300c,
1963 .enable_mask = BIT(0),
1964 .hw.init = &(struct clk_init_data){
1965 .name = "gcc_pdm2_clk",
1966 .parent_hws = (const struct clk_hw*[]){
1967 &gcc_pdm2_clk_src.clkr.hw,
1970 .flags = CLK_SET_RATE_PARENT,
1971 .ops = &clk_branch2_ops,
1976 static struct clk_branch gcc_pdm_ahb_clk = {
1977 .halt_reg = 0x33004,
1978 .halt_check = BRANCH_HALT_VOTED,
1979 .hwcg_reg = 0x33004,
1982 .enable_reg = 0x33004,
1983 .enable_mask = BIT(0),
1984 .hw.init = &(struct clk_init_data){
1985 .name = "gcc_pdm_ahb_clk",
1986 .ops = &clk_branch2_ops,
1991 static struct clk_branch gcc_pdm_xo4_clk = {
1992 .halt_reg = 0x33008,
1993 .halt_check = BRANCH_HALT,
1995 .enable_reg = 0x33008,
1996 .enable_mask = BIT(0),
1997 .hw.init = &(struct clk_init_data){
1998 .name = "gcc_pdm_xo4_clk",
1999 .ops = &clk_branch2_ops,
2004 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2005 .halt_reg = 0x26008,
2006 .halt_check = BRANCH_HALT_VOTED,
2007 .hwcg_reg = 0x26008,
2010 .enable_reg = 0x26008,
2011 .enable_mask = BIT(0),
2012 .hw.init = &(struct clk_init_data){
2013 .name = "gcc_qmip_camera_nrt_ahb_clk",
2014 .ops = &clk_branch2_ops,
2019 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2020 .halt_reg = 0x2600c,
2021 .halt_check = BRANCH_HALT_VOTED,
2022 .hwcg_reg = 0x2600c,
2025 .enable_reg = 0x2600c,
2026 .enable_mask = BIT(0),
2027 .hw.init = &(struct clk_init_data){
2028 .name = "gcc_qmip_camera_rt_ahb_clk",
2029 .ops = &clk_branch2_ops,
2034 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2035 .halt_reg = 0x27008,
2036 .halt_check = BRANCH_HALT_VOTED,
2037 .hwcg_reg = 0x27008,
2040 .enable_reg = 0x27008,
2041 .enable_mask = BIT(0),
2042 .hw.init = &(struct clk_init_data){
2043 .name = "gcc_qmip_disp_ahb_clk",
2044 .ops = &clk_branch2_ops,
2049 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2050 .halt_reg = 0x28008,
2051 .halt_check = BRANCH_HALT_VOTED,
2052 .hwcg_reg = 0x28008,
2055 .enable_reg = 0x28008,
2056 .enable_mask = BIT(0),
2057 .hw.init = &(struct clk_init_data){
2058 .name = "gcc_qmip_video_cvp_ahb_clk",
2059 .ops = &clk_branch2_ops,
2064 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2065 .halt_reg = 0x2800c,
2066 .halt_check = BRANCH_HALT_VOTED,
2067 .hwcg_reg = 0x2800c,
2070 .enable_reg = 0x2800c,
2071 .enable_mask = BIT(0),
2072 .hw.init = &(struct clk_init_data){
2073 .name = "gcc_qmip_video_vcodec_ahb_clk",
2074 .ops = &clk_branch2_ops,
2079 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2080 .halt_reg = 0x23008,
2081 .halt_check = BRANCH_HALT_VOTED,
2083 .enable_reg = 0x52008,
2084 .enable_mask = BIT(9),
2085 .hw.init = &(struct clk_init_data){
2086 .name = "gcc_qupv3_wrap0_core_2x_clk",
2087 .ops = &clk_branch2_ops,
2092 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2093 .halt_reg = 0x23000,
2094 .halt_check = BRANCH_HALT_VOTED,
2096 .enable_reg = 0x52008,
2097 .enable_mask = BIT(8),
2098 .hw.init = &(struct clk_init_data){
2099 .name = "gcc_qupv3_wrap0_core_clk",
2100 .ops = &clk_branch2_ops,
2105 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2106 .halt_reg = 0x1700c,
2107 .halt_check = BRANCH_HALT_VOTED,
2109 .enable_reg = 0x52008,
2110 .enable_mask = BIT(10),
2111 .hw.init = &(struct clk_init_data){
2112 .name = "gcc_qupv3_wrap0_s0_clk",
2113 .parent_hws = (const struct clk_hw*[]){
2114 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2117 .flags = CLK_SET_RATE_PARENT,
2118 .ops = &clk_branch2_ops,
2123 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2124 .halt_reg = 0x1713c,
2125 .halt_check = BRANCH_HALT_VOTED,
2127 .enable_reg = 0x52008,
2128 .enable_mask = BIT(11),
2129 .hw.init = &(struct clk_init_data){
2130 .name = "gcc_qupv3_wrap0_s1_clk",
2131 .parent_hws = (const struct clk_hw*[]){
2132 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2135 .flags = CLK_SET_RATE_PARENT,
2136 .ops = &clk_branch2_ops,
2141 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2142 .halt_reg = 0x1726c,
2143 .halt_check = BRANCH_HALT_VOTED,
2145 .enable_reg = 0x52008,
2146 .enable_mask = BIT(12),
2147 .hw.init = &(struct clk_init_data){
2148 .name = "gcc_qupv3_wrap0_s2_clk",
2149 .parent_hws = (const struct clk_hw*[]){
2150 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2153 .flags = CLK_SET_RATE_PARENT,
2154 .ops = &clk_branch2_ops,
2159 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2160 .halt_reg = 0x1739c,
2161 .halt_check = BRANCH_HALT_VOTED,
2163 .enable_reg = 0x52008,
2164 .enable_mask = BIT(13),
2165 .hw.init = &(struct clk_init_data){
2166 .name = "gcc_qupv3_wrap0_s3_clk",
2167 .parent_hws = (const struct clk_hw*[]){
2168 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2171 .flags = CLK_SET_RATE_PARENT,
2172 .ops = &clk_branch2_ops,
2177 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2178 .halt_reg = 0x174cc,
2179 .halt_check = BRANCH_HALT_VOTED,
2181 .enable_reg = 0x52008,
2182 .enable_mask = BIT(14),
2183 .hw.init = &(struct clk_init_data){
2184 .name = "gcc_qupv3_wrap0_s4_clk",
2185 .parent_hws = (const struct clk_hw*[]){
2186 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2189 .flags = CLK_SET_RATE_PARENT,
2190 .ops = &clk_branch2_ops,
2195 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2196 .halt_reg = 0x175fc,
2197 .halt_check = BRANCH_HALT_VOTED,
2199 .enable_reg = 0x52008,
2200 .enable_mask = BIT(15),
2201 .hw.init = &(struct clk_init_data){
2202 .name = "gcc_qupv3_wrap0_s5_clk",
2203 .parent_hws = (const struct clk_hw*[]){
2204 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2207 .flags = CLK_SET_RATE_PARENT,
2208 .ops = &clk_branch2_ops,
2213 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2214 .halt_reg = 0x1772c,
2215 .halt_check = BRANCH_HALT_VOTED,
2217 .enable_reg = 0x52008,
2218 .enable_mask = BIT(16),
2219 .hw.init = &(struct clk_init_data){
2220 .name = "gcc_qupv3_wrap0_s6_clk",
2221 .parent_hws = (const struct clk_hw*[]){
2222 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2225 .flags = CLK_SET_RATE_PARENT,
2226 .ops = &clk_branch2_ops,
2231 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2232 .halt_reg = 0x1785c,
2233 .halt_check = BRANCH_HALT_VOTED,
2235 .enable_reg = 0x52008,
2236 .enable_mask = BIT(17),
2237 .hw.init = &(struct clk_init_data){
2238 .name = "gcc_qupv3_wrap0_s7_clk",
2239 .parent_hws = (const struct clk_hw*[]){
2240 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2243 .flags = CLK_SET_RATE_PARENT,
2244 .ops = &clk_branch2_ops,
2249 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2250 .halt_reg = 0x23140,
2251 .halt_check = BRANCH_HALT_VOTED,
2253 .enable_reg = 0x52008,
2254 .enable_mask = BIT(18),
2255 .hw.init = &(struct clk_init_data){
2256 .name = "gcc_qupv3_wrap1_core_2x_clk",
2257 .ops = &clk_branch2_ops,
2262 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2263 .halt_reg = 0x23138,
2264 .halt_check = BRANCH_HALT_VOTED,
2266 .enable_reg = 0x52008,
2267 .enable_mask = BIT(19),
2268 .hw.init = &(struct clk_init_data){
2269 .name = "gcc_qupv3_wrap1_core_clk",
2270 .ops = &clk_branch2_ops,
2275 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2276 .halt_reg = 0x18004,
2277 .halt_check = BRANCH_HALT_VOTED,
2278 .hwcg_reg = 0x18004,
2281 .enable_reg = 0x52008,
2282 .enable_mask = BIT(20),
2283 .hw.init = &(struct clk_init_data){
2284 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2285 .ops = &clk_branch2_ops,
2290 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2291 .halt_reg = 0x18008,
2292 .halt_check = BRANCH_HALT_VOTED,
2293 .hwcg_reg = 0x18008,
2296 .enable_reg = 0x52008,
2297 .enable_mask = BIT(21),
2298 .hw.init = &(struct clk_init_data){
2299 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2300 .ops = &clk_branch2_ops,
2305 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2306 .halt_reg = 0x1800c,
2307 .halt_check = BRANCH_HALT_VOTED,
2309 .enable_reg = 0x52008,
2310 .enable_mask = BIT(22),
2311 .hw.init = &(struct clk_init_data){
2312 .name = "gcc_qupv3_wrap1_s0_clk",
2313 .parent_hws = (const struct clk_hw*[]){
2314 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2317 .flags = CLK_SET_RATE_PARENT,
2318 .ops = &clk_branch2_ops,
2323 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2324 .halt_reg = 0x1813c,
2325 .halt_check = BRANCH_HALT_VOTED,
2327 .enable_reg = 0x52008,
2328 .enable_mask = BIT(23),
2329 .hw.init = &(struct clk_init_data){
2330 .name = "gcc_qupv3_wrap1_s1_clk",
2331 .parent_hws = (const struct clk_hw*[]){
2332 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2335 .flags = CLK_SET_RATE_PARENT,
2336 .ops = &clk_branch2_ops,
2341 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2342 .halt_reg = 0x1826c,
2343 .halt_check = BRANCH_HALT_VOTED,
2345 .enable_reg = 0x52008,
2346 .enable_mask = BIT(24),
2347 .hw.init = &(struct clk_init_data){
2348 .name = "gcc_qupv3_wrap1_s2_clk",
2349 .parent_hws = (const struct clk_hw*[]){
2350 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2353 .flags = CLK_SET_RATE_PARENT,
2354 .ops = &clk_branch2_ops,
2359 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2360 .halt_reg = 0x1839c,
2361 .halt_check = BRANCH_HALT_VOTED,
2363 .enable_reg = 0x52008,
2364 .enable_mask = BIT(25),
2365 .hw.init = &(struct clk_init_data){
2366 .name = "gcc_qupv3_wrap1_s3_clk",
2367 .parent_hws = (const struct clk_hw*[]){
2368 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2371 .flags = CLK_SET_RATE_PARENT,
2372 .ops = &clk_branch2_ops,
2377 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2378 .halt_reg = 0x184cc,
2379 .halt_check = BRANCH_HALT_VOTED,
2381 .enable_reg = 0x52008,
2382 .enable_mask = BIT(26),
2383 .hw.init = &(struct clk_init_data){
2384 .name = "gcc_qupv3_wrap1_s4_clk",
2385 .parent_hws = (const struct clk_hw*[]){
2386 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2389 .flags = CLK_SET_RATE_PARENT,
2390 .ops = &clk_branch2_ops,
2395 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2396 .halt_reg = 0x185fc,
2397 .halt_check = BRANCH_HALT_VOTED,
2399 .enable_reg = 0x52008,
2400 .enable_mask = BIT(27),
2401 .hw.init = &(struct clk_init_data){
2402 .name = "gcc_qupv3_wrap1_s5_clk",
2403 .parent_hws = (const struct clk_hw*[]){
2404 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2407 .flags = CLK_SET_RATE_PARENT,
2408 .ops = &clk_branch2_ops,
2413 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
2414 .halt_reg = 0x23278,
2415 .halt_check = BRANCH_HALT_VOTED,
2417 .enable_reg = 0x52010,
2418 .enable_mask = BIT(3),
2419 .hw.init = &(struct clk_init_data){
2420 .name = "gcc_qupv3_wrap2_core_2x_clk",
2421 .ops = &clk_branch2_ops,
2426 static struct clk_branch gcc_qupv3_wrap2_core_clk = {
2427 .halt_reg = 0x23270,
2428 .halt_check = BRANCH_HALT_VOTED,
2430 .enable_reg = 0x52010,
2431 .enable_mask = BIT(0),
2432 .hw.init = &(struct clk_init_data){
2433 .name = "gcc_qupv3_wrap2_core_clk",
2434 .ops = &clk_branch2_ops,
2439 static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2440 .halt_reg = 0x1e00c,
2441 .halt_check = BRANCH_HALT_VOTED,
2443 .enable_reg = 0x52010,
2444 .enable_mask = BIT(4),
2445 .hw.init = &(struct clk_init_data){
2446 .name = "gcc_qupv3_wrap2_s0_clk",
2447 .parent_hws = (const struct clk_hw*[]){
2448 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
2451 .flags = CLK_SET_RATE_PARENT,
2452 .ops = &clk_branch2_ops,
2457 static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2458 .halt_reg = 0x1e13c,
2459 .halt_check = BRANCH_HALT_VOTED,
2461 .enable_reg = 0x52010,
2462 .enable_mask = BIT(5),
2463 .hw.init = &(struct clk_init_data){
2464 .name = "gcc_qupv3_wrap2_s1_clk",
2465 .parent_hws = (const struct clk_hw*[]){
2466 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
2469 .flags = CLK_SET_RATE_PARENT,
2470 .ops = &clk_branch2_ops,
2475 static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2476 .halt_reg = 0x1e26c,
2477 .halt_check = BRANCH_HALT_VOTED,
2479 .enable_reg = 0x52010,
2480 .enable_mask = BIT(6),
2481 .hw.init = &(struct clk_init_data){
2482 .name = "gcc_qupv3_wrap2_s2_clk",
2483 .parent_hws = (const struct clk_hw*[]){
2484 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2487 .flags = CLK_SET_RATE_PARENT,
2488 .ops = &clk_branch2_ops,
2493 static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2494 .halt_reg = 0x1e39c,
2495 .halt_check = BRANCH_HALT_VOTED,
2497 .enable_reg = 0x52010,
2498 .enable_mask = BIT(7),
2499 .hw.init = &(struct clk_init_data){
2500 .name = "gcc_qupv3_wrap2_s3_clk",
2501 .parent_hws = (const struct clk_hw*[]){
2502 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2505 .flags = CLK_SET_RATE_PARENT,
2506 .ops = &clk_branch2_ops,
2511 static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2512 .halt_reg = 0x1e4cc,
2513 .halt_check = BRANCH_HALT_VOTED,
2515 .enable_reg = 0x52010,
2516 .enable_mask = BIT(8),
2517 .hw.init = &(struct clk_init_data){
2518 .name = "gcc_qupv3_wrap2_s4_clk",
2519 .parent_hws = (const struct clk_hw*[]){
2520 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
2523 .flags = CLK_SET_RATE_PARENT,
2524 .ops = &clk_branch2_ops,
2529 static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2530 .halt_reg = 0x1e5fc,
2531 .halt_check = BRANCH_HALT_VOTED,
2533 .enable_reg = 0x52010,
2534 .enable_mask = BIT(9),
2535 .hw.init = &(struct clk_init_data){
2536 .name = "gcc_qupv3_wrap2_s5_clk",
2537 .parent_hws = (const struct clk_hw*[]){
2538 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
2541 .flags = CLK_SET_RATE_PARENT,
2542 .ops = &clk_branch2_ops,
2547 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2548 .halt_reg = 0x17004,
2549 .halt_check = BRANCH_HALT_VOTED,
2550 .hwcg_reg = 0x17004,
2553 .enable_reg = 0x52008,
2554 .enable_mask = BIT(6),
2555 .hw.init = &(struct clk_init_data){
2556 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2557 .ops = &clk_branch2_ops,
2562 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2563 .halt_reg = 0x17008,
2564 .halt_check = BRANCH_HALT_VOTED,
2565 .hwcg_reg = 0x17008,
2568 .enable_reg = 0x52008,
2569 .enable_mask = BIT(7),
2570 .hw.init = &(struct clk_init_data){
2571 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2572 .ops = &clk_branch2_ops,
2577 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2578 .halt_reg = 0x1e004,
2579 .halt_check = BRANCH_HALT_VOTED,
2580 .hwcg_reg = 0x1e004,
2583 .enable_reg = 0x52010,
2584 .enable_mask = BIT(2),
2585 .hw.init = &(struct clk_init_data){
2586 .name = "gcc_qupv3_wrap_2_m_ahb_clk",
2587 .ops = &clk_branch2_ops,
2592 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2593 .halt_reg = 0x1e008,
2594 .halt_check = BRANCH_HALT_VOTED,
2595 .hwcg_reg = 0x1e008,
2598 .enable_reg = 0x52010,
2599 .enable_mask = BIT(1),
2600 .hw.init = &(struct clk_init_data){
2601 .name = "gcc_qupv3_wrap_2_s_ahb_clk",
2602 .ops = &clk_branch2_ops,
2607 static struct clk_branch gcc_sdcc2_ahb_clk = {
2608 .halt_reg = 0x14008,
2609 .halt_check = BRANCH_HALT,
2611 .enable_reg = 0x14008,
2612 .enable_mask = BIT(0),
2613 .hw.init = &(struct clk_init_data){
2614 .name = "gcc_sdcc2_ahb_clk",
2615 .ops = &clk_branch2_ops,
2620 static struct clk_branch gcc_sdcc2_apps_clk = {
2621 .halt_reg = 0x14004,
2622 .halt_check = BRANCH_HALT,
2624 .enable_reg = 0x14004,
2625 .enable_mask = BIT(0),
2626 .hw.init = &(struct clk_init_data){
2627 .name = "gcc_sdcc2_apps_clk",
2628 .parent_hws = (const struct clk_hw*[]){
2629 &gcc_sdcc2_apps_clk_src.clkr.hw,
2632 .flags = CLK_SET_RATE_PARENT,
2633 .ops = &clk_branch2_ops,
2638 static struct clk_branch gcc_sdcc4_ahb_clk = {
2639 .halt_reg = 0x16008,
2640 .halt_check = BRANCH_HALT,
2642 .enable_reg = 0x16008,
2643 .enable_mask = BIT(0),
2644 .hw.init = &(struct clk_init_data){
2645 .name = "gcc_sdcc4_ahb_clk",
2646 .ops = &clk_branch2_ops,
2651 static struct clk_branch gcc_sdcc4_apps_clk = {
2652 .halt_reg = 0x16004,
2653 .halt_check = BRANCH_HALT,
2655 .enable_reg = 0x16004,
2656 .enable_mask = BIT(0),
2657 .hw.init = &(struct clk_init_data){
2658 .name = "gcc_sdcc4_apps_clk",
2659 .parent_hws = (const struct clk_hw*[]){
2660 &gcc_sdcc4_apps_clk_src.clkr.hw,
2663 .flags = CLK_SET_RATE_PARENT,
2664 .ops = &clk_branch2_ops,
2669 static struct clk_branch gcc_throttle_pcie_ahb_clk = {
2671 .halt_check = BRANCH_HALT,
2673 .enable_reg = 0x9044,
2674 .enable_mask = BIT(0),
2675 .hw.init = &(struct clk_init_data){
2676 .name = "gcc_throttle_pcie_ahb_clk",
2677 .ops = &clk_branch2_ops,
2682 static struct clk_branch gcc_ufs_1_clkref_en = {
2683 .halt_reg = 0x8c000,
2684 .halt_check = BRANCH_HALT,
2686 .enable_reg = 0x8c000,
2687 .enable_mask = BIT(0),
2688 .hw.init = &(struct clk_init_data){
2689 .name = "gcc_ufs_1_clkref_en",
2690 .ops = &clk_branch2_ops,
2695 static struct clk_branch gcc_ufs_card_ahb_clk = {
2696 .halt_reg = 0x75018,
2697 .halt_check = BRANCH_HALT_VOTED,
2698 .hwcg_reg = 0x75018,
2701 .enable_reg = 0x75018,
2702 .enable_mask = BIT(0),
2703 .hw.init = &(struct clk_init_data){
2704 .name = "gcc_ufs_card_ahb_clk",
2705 .ops = &clk_branch2_ops,
2710 static struct clk_branch gcc_ufs_card_axi_clk = {
2711 .halt_reg = 0x75010,
2712 .halt_check = BRANCH_HALT_VOTED,
2713 .hwcg_reg = 0x75010,
2716 .enable_reg = 0x75010,
2717 .enable_mask = BIT(0),
2718 .hw.init = &(struct clk_init_data){
2719 .name = "gcc_ufs_card_axi_clk",
2720 .parent_hws = (const struct clk_hw*[]){
2721 &gcc_ufs_card_axi_clk_src.clkr.hw,
2724 .flags = CLK_SET_RATE_PARENT,
2725 .ops = &clk_branch2_ops,
2730 static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
2731 .halt_reg = 0x75010,
2732 .halt_check = BRANCH_HALT_VOTED,
2733 .hwcg_reg = 0x75010,
2736 .enable_reg = 0x75010,
2737 .enable_mask = BIT(1),
2738 .hw.init = &(struct clk_init_data){
2739 .name = "gcc_ufs_card_axi_hw_ctl_clk",
2740 .parent_hws = (const struct clk_hw*[]){
2741 &gcc_ufs_card_axi_clk_src.clkr.hw,
2744 .flags = CLK_SET_RATE_PARENT,
2745 .ops = &clk_branch2_ops,
2750 static struct clk_branch gcc_ufs_card_ice_core_clk = {
2751 .halt_reg = 0x75064,
2752 .halt_check = BRANCH_HALT_VOTED,
2753 .hwcg_reg = 0x75064,
2756 .enable_reg = 0x75064,
2757 .enable_mask = BIT(0),
2758 .hw.init = &(struct clk_init_data){
2759 .name = "gcc_ufs_card_ice_core_clk",
2760 .parent_hws = (const struct clk_hw*[]){
2761 &gcc_ufs_card_ice_core_clk_src.clkr.hw,
2764 .flags = CLK_SET_RATE_PARENT,
2765 .ops = &clk_branch2_ops,
2770 static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
2771 .halt_reg = 0x75064,
2772 .halt_check = BRANCH_HALT_VOTED,
2773 .hwcg_reg = 0x75064,
2776 .enable_reg = 0x75064,
2777 .enable_mask = BIT(1),
2778 .hw.init = &(struct clk_init_data){
2779 .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
2780 .parent_hws = (const struct clk_hw*[]){
2781 &gcc_ufs_card_ice_core_clk_src.clkr.hw,
2784 .flags = CLK_SET_RATE_PARENT,
2785 .ops = &clk_branch2_ops,
2790 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2791 .halt_reg = 0x7509c,
2792 .halt_check = BRANCH_HALT_VOTED,
2793 .hwcg_reg = 0x7509c,
2796 .enable_reg = 0x7509c,
2797 .enable_mask = BIT(0),
2798 .hw.init = &(struct clk_init_data){
2799 .name = "gcc_ufs_card_phy_aux_clk",
2800 .parent_hws = (const struct clk_hw*[]){
2801 &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2804 .flags = CLK_SET_RATE_PARENT,
2805 .ops = &clk_branch2_ops,
2810 static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
2811 .halt_reg = 0x7509c,
2812 .halt_check = BRANCH_HALT_VOTED,
2813 .hwcg_reg = 0x7509c,
2816 .enable_reg = 0x7509c,
2817 .enable_mask = BIT(1),
2818 .hw.init = &(struct clk_init_data){
2819 .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
2820 .parent_hws = (const struct clk_hw*[]){
2821 &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2824 .flags = CLK_SET_RATE_PARENT,
2825 .ops = &clk_branch2_ops,
2830 /* Clock ON depends on external parent clock, so don't poll */
2831 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2832 .halt_reg = 0x75020,
2833 .halt_check = BRANCH_HALT_DELAY,
2835 .enable_reg = 0x75020,
2836 .enable_mask = BIT(0),
2837 .hw.init = &(struct clk_init_data){
2838 .name = "gcc_ufs_card_rx_symbol_0_clk",
2839 .parent_hws = (const struct clk_hw*[]){
2840 &gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw,
2843 .flags = CLK_SET_RATE_PARENT,
2844 .ops = &clk_branch2_ops,
2849 /* Clock ON depends on external parent clock, so don't poll */
2850 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2851 .halt_reg = 0x750b8,
2852 .halt_check = BRANCH_HALT_DELAY,
2854 .enable_reg = 0x750b8,
2855 .enable_mask = BIT(0),
2856 .hw.init = &(struct clk_init_data){
2857 .name = "gcc_ufs_card_rx_symbol_1_clk",
2858 .parent_hws = (const struct clk_hw*[]){
2859 &gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw,
2862 .flags = CLK_SET_RATE_PARENT,
2863 .ops = &clk_branch2_ops,
2868 /* Clock ON depends on external parent clock, so don't poll */
2869 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2870 .halt_reg = 0x7501c,
2871 .halt_check = BRANCH_HALT_DELAY,
2873 .enable_reg = 0x7501c,
2874 .enable_mask = BIT(0),
2875 .hw.init = &(struct clk_init_data){
2876 .name = "gcc_ufs_card_tx_symbol_0_clk",
2877 .parent_hws = (const struct clk_hw*[]){
2878 &gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw,
2881 .flags = CLK_SET_RATE_PARENT,
2882 .ops = &clk_branch2_ops,
2887 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2888 .halt_reg = 0x7505c,
2889 .halt_check = BRANCH_HALT_VOTED,
2890 .hwcg_reg = 0x7505c,
2893 .enable_reg = 0x7505c,
2894 .enable_mask = BIT(0),
2895 .hw.init = &(struct clk_init_data){
2896 .name = "gcc_ufs_card_unipro_core_clk",
2897 .parent_hws = (const struct clk_hw*[]){
2898 &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2901 .flags = CLK_SET_RATE_PARENT,
2902 .ops = &clk_branch2_ops,
2907 static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
2908 .halt_reg = 0x7505c,
2909 .halt_check = BRANCH_HALT_VOTED,
2910 .hwcg_reg = 0x7505c,
2913 .enable_reg = 0x7505c,
2914 .enable_mask = BIT(1),
2915 .hw.init = &(struct clk_init_data){
2916 .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
2917 .parent_hws = (const struct clk_hw*[]){
2918 &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2921 .flags = CLK_SET_RATE_PARENT,
2922 .ops = &clk_branch2_ops,
2927 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2928 .halt_reg = 0x77018,
2929 .halt_check = BRANCH_HALT_VOTED,
2930 .hwcg_reg = 0x77018,
2933 .enable_reg = 0x77018,
2934 .enable_mask = BIT(0),
2935 .hw.init = &(struct clk_init_data){
2936 .name = "gcc_ufs_phy_ahb_clk",
2937 .ops = &clk_branch2_ops,
2942 static struct clk_branch gcc_ufs_phy_axi_clk = {
2943 .halt_reg = 0x77010,
2944 .halt_check = BRANCH_HALT_VOTED,
2945 .hwcg_reg = 0x77010,
2948 .enable_reg = 0x77010,
2949 .enable_mask = BIT(0),
2950 .hw.init = &(struct clk_init_data){
2951 .name = "gcc_ufs_phy_axi_clk",
2952 .parent_hws = (const struct clk_hw*[]){
2953 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2956 .flags = CLK_SET_RATE_PARENT,
2957 .ops = &clk_branch2_ops,
2962 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2963 .halt_reg = 0x77010,
2964 .halt_check = BRANCH_HALT_VOTED,
2965 .hwcg_reg = 0x77010,
2968 .enable_reg = 0x77010,
2969 .enable_mask = BIT(1),
2970 .hw.init = &(struct clk_init_data){
2971 .name = "gcc_ufs_phy_axi_hw_ctl_clk",
2972 .parent_hws = (const struct clk_hw*[]){
2973 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2976 .flags = CLK_SET_RATE_PARENT,
2977 .ops = &clk_branch2_ops,
2982 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2983 .halt_reg = 0x77064,
2984 .halt_check = BRANCH_HALT_VOTED,
2985 .hwcg_reg = 0x77064,
2988 .enable_reg = 0x77064,
2989 .enable_mask = BIT(0),
2990 .hw.init = &(struct clk_init_data){
2991 .name = "gcc_ufs_phy_ice_core_clk",
2992 .parent_hws = (const struct clk_hw*[]){
2993 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2996 .flags = CLK_SET_RATE_PARENT,
2997 .ops = &clk_branch2_ops,
3002 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
3003 .halt_reg = 0x77064,
3004 .halt_check = BRANCH_HALT_VOTED,
3005 .hwcg_reg = 0x77064,
3008 .enable_reg = 0x77064,
3009 .enable_mask = BIT(1),
3010 .hw.init = &(struct clk_init_data){
3011 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
3012 .parent_hws = (const struct clk_hw*[]){
3013 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3016 .flags = CLK_SET_RATE_PARENT,
3017 .ops = &clk_branch2_ops,
3022 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3023 .halt_reg = 0x7709c,
3024 .halt_check = BRANCH_HALT_VOTED,
3025 .hwcg_reg = 0x7709c,
3028 .enable_reg = 0x7709c,
3029 .enable_mask = BIT(0),
3030 .hw.init = &(struct clk_init_data){
3031 .name = "gcc_ufs_phy_phy_aux_clk",
3032 .parent_hws = (const struct clk_hw*[]){
3033 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3036 .flags = CLK_SET_RATE_PARENT,
3037 .ops = &clk_branch2_ops,
3042 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3043 .halt_reg = 0x7709c,
3044 .halt_check = BRANCH_HALT_VOTED,
3045 .hwcg_reg = 0x7709c,
3048 .enable_reg = 0x7709c,
3049 .enable_mask = BIT(1),
3050 .hw.init = &(struct clk_init_data){
3051 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
3052 .parent_hws = (const struct clk_hw*[]){
3053 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3056 .flags = CLK_SET_RATE_PARENT,
3057 .ops = &clk_branch2_ops,
3062 /* Clock ON depends on external parent clock, so don't poll */
3063 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3064 .halt_reg = 0x77020,
3065 .halt_check = BRANCH_HALT_DELAY,
3067 .enable_reg = 0x77020,
3068 .enable_mask = BIT(0),
3069 .hw.init = &(struct clk_init_data){
3070 .name = "gcc_ufs_phy_rx_symbol_0_clk",
3071 .parent_hws = (const struct clk_hw*[]){
3072 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
3075 .flags = CLK_SET_RATE_PARENT,
3076 .ops = &clk_branch2_ops,
3081 /* Clock ON depends on external parent clock, so don't poll */
3082 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
3083 .halt_reg = 0x770b8,
3084 .halt_check = BRANCH_HALT_DELAY,
3086 .enable_reg = 0x770b8,
3087 .enable_mask = BIT(0),
3088 .hw.init = &(struct clk_init_data){
3089 .name = "gcc_ufs_phy_rx_symbol_1_clk",
3090 .parent_hws = (const struct clk_hw*[]){
3091 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
3094 .flags = CLK_SET_RATE_PARENT,
3095 .ops = &clk_branch2_ops,
3100 /* Clock ON depends on external parent clock, so don't poll */
3101 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3102 .halt_reg = 0x7701c,
3103 .halt_check = BRANCH_HALT_DELAY,
3105 .enable_reg = 0x7701c,
3106 .enable_mask = BIT(0),
3107 .hw.init = &(struct clk_init_data){
3108 .name = "gcc_ufs_phy_tx_symbol_0_clk",
3109 .parent_hws = (const struct clk_hw*[]){
3110 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
3113 .flags = CLK_SET_RATE_PARENT,
3114 .ops = &clk_branch2_ops,
3119 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3120 .halt_reg = 0x7705c,
3121 .halt_check = BRANCH_HALT_VOTED,
3122 .hwcg_reg = 0x7705c,
3125 .enable_reg = 0x7705c,
3126 .enable_mask = BIT(0),
3127 .hw.init = &(struct clk_init_data){
3128 .name = "gcc_ufs_phy_unipro_core_clk",
3129 .parent_hws = (const struct clk_hw*[]){
3130 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3133 .flags = CLK_SET_RATE_PARENT,
3134 .ops = &clk_branch2_ops,
3139 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3140 .halt_reg = 0x7705c,
3141 .halt_check = BRANCH_HALT_VOTED,
3142 .hwcg_reg = 0x7705c,
3145 .enable_reg = 0x7705c,
3146 .enable_mask = BIT(1),
3147 .hw.init = &(struct clk_init_data){
3148 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3149 .parent_hws = (const struct clk_hw*[]){
3150 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3153 .flags = CLK_SET_RATE_PARENT,
3154 .ops = &clk_branch2_ops,
3159 static struct clk_branch gcc_usb30_prim_master_clk = {
3161 .halt_check = BRANCH_HALT,
3163 .enable_reg = 0xf010,
3164 .enable_mask = BIT(0),
3165 .hw.init = &(struct clk_init_data){
3166 .name = "gcc_usb30_prim_master_clk",
3167 .parent_hws = (const struct clk_hw*[]){
3168 &gcc_usb30_prim_master_clk_src.clkr.hw,
3171 .flags = CLK_SET_RATE_PARENT,
3172 .ops = &clk_branch2_ops,
3177 static struct clk_branch gcc_usb30_prim_master_clk__force_mem_core_on = {
3179 .halt_check = BRANCH_HALT,
3181 .enable_reg = 0xf010,
3182 .enable_mask = BIT(14),
3183 .hw.init = &(struct clk_init_data){
3184 .name = "gcc_usb30_prim_master_clk__force_mem_core_on",
3185 .ops = &clk_branch_simple_ops,
3190 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3192 .halt_check = BRANCH_HALT,
3194 .enable_reg = 0xf01c,
3195 .enable_mask = BIT(0),
3196 .hw.init = &(struct clk_init_data){
3197 .name = "gcc_usb30_prim_mock_utmi_clk",
3198 .parent_hws = (const struct clk_hw*[]){
3199 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
3202 .flags = CLK_SET_RATE_PARENT,
3203 .ops = &clk_branch2_ops,
3208 static struct clk_branch gcc_usb30_prim_sleep_clk = {
3210 .halt_check = BRANCH_HALT,
3212 .enable_reg = 0xf018,
3213 .enable_mask = BIT(0),
3214 .hw.init = &(struct clk_init_data){
3215 .name = "gcc_usb30_prim_sleep_clk",
3216 .ops = &clk_branch2_ops,
3221 static struct clk_branch gcc_usb30_sec_master_clk = {
3222 .halt_reg = 0x10010,
3223 .halt_check = BRANCH_HALT,
3225 .enable_reg = 0x10010,
3226 .enable_mask = BIT(0),
3227 .hw.init = &(struct clk_init_data){
3228 .name = "gcc_usb30_sec_master_clk",
3229 .parent_hws = (const struct clk_hw*[]){
3230 &gcc_usb30_sec_master_clk_src.clkr.hw,
3233 .flags = CLK_SET_RATE_PARENT,
3234 .ops = &clk_branch2_ops,
3239 static struct clk_branch gcc_usb30_sec_master_clk__force_mem_core_on = {
3240 .halt_reg = 0x10010,
3241 .halt_check = BRANCH_HALT,
3243 .enable_reg = 0x10010,
3244 .enable_mask = BIT(14),
3245 .hw.init = &(struct clk_init_data){
3246 .name = "gcc_usb30_sec_master_clk__force_mem_core_on",
3247 .ops = &clk_branch_simple_ops,
3252 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3253 .halt_reg = 0x1001c,
3254 .halt_check = BRANCH_HALT,
3256 .enable_reg = 0x1001c,
3257 .enable_mask = BIT(0),
3258 .hw.init = &(struct clk_init_data){
3259 .name = "gcc_usb30_sec_mock_utmi_clk",
3260 .parent_hws = (const struct clk_hw*[]){
3261 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
3264 .flags = CLK_SET_RATE_PARENT,
3265 .ops = &clk_branch2_ops,
3270 static struct clk_branch gcc_usb30_sec_sleep_clk = {
3271 .halt_reg = 0x10018,
3272 .halt_check = BRANCH_HALT,
3274 .enable_reg = 0x10018,
3275 .enable_mask = BIT(0),
3276 .hw.init = &(struct clk_init_data){
3277 .name = "gcc_usb30_sec_sleep_clk",
3278 .ops = &clk_branch2_ops,
3283 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3285 .halt_check = BRANCH_HALT,
3287 .enable_reg = 0xf054,
3288 .enable_mask = BIT(0),
3289 .hw.init = &(struct clk_init_data){
3290 .name = "gcc_usb3_prim_phy_aux_clk",
3291 .parent_hws = (const struct clk_hw*[]){
3292 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3295 .flags = CLK_SET_RATE_PARENT,
3296 .ops = &clk_branch2_ops,
3301 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3303 .halt_check = BRANCH_HALT,
3305 .enable_reg = 0xf058,
3306 .enable_mask = BIT(0),
3307 .hw.init = &(struct clk_init_data){
3308 .name = "gcc_usb3_prim_phy_com_aux_clk",
3309 .parent_hws = (const struct clk_hw*[]){
3310 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3313 .flags = CLK_SET_RATE_PARENT,
3314 .ops = &clk_branch2_ops,
3319 /* Clock ON depends on external parent clock, so don't poll */
3320 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3322 .halt_check = BRANCH_HALT_DELAY,
3326 .enable_reg = 0xf05c,
3327 .enable_mask = BIT(0),
3328 .hw.init = &(struct clk_init_data){
3329 .name = "gcc_usb3_prim_phy_pipe_clk",
3330 .parent_hws = (const struct clk_hw*[]){
3331 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
3334 .flags = CLK_SET_RATE_PARENT,
3335 .ops = &clk_branch2_ops,
3340 static struct clk_branch gcc_usb3_sec_clkref_en = {
3341 .halt_reg = 0x8c010,
3342 .halt_check = BRANCH_HALT,
3344 .enable_reg = 0x8c010,
3345 .enable_mask = BIT(0),
3346 .hw.init = &(struct clk_init_data){
3347 .name = "gcc_usb3_sec_clkref_en",
3348 .ops = &clk_branch2_ops,
3353 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3354 .halt_reg = 0x10054,
3355 .halt_check = BRANCH_HALT,
3357 .enable_reg = 0x10054,
3358 .enable_mask = BIT(0),
3359 .hw.init = &(struct clk_init_data){
3360 .name = "gcc_usb3_sec_phy_aux_clk",
3361 .parent_hws = (const struct clk_hw*[]){
3362 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3365 .flags = CLK_SET_RATE_PARENT,
3366 .ops = &clk_branch2_ops,
3371 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3372 .halt_reg = 0x10058,
3373 .halt_check = BRANCH_HALT,
3375 .enable_reg = 0x10058,
3376 .enable_mask = BIT(0),
3377 .hw.init = &(struct clk_init_data){
3378 .name = "gcc_usb3_sec_phy_com_aux_clk",
3379 .parent_hws = (const struct clk_hw*[]){
3380 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3383 .flags = CLK_SET_RATE_PARENT,
3384 .ops = &clk_branch2_ops,
3389 /* Clock ON depends on external parent clock, so don't poll */
3390 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3391 .halt_reg = 0x1005c,
3392 .halt_check = BRANCH_HALT_DELAY,
3394 .enable_reg = 0x1005c,
3395 .enable_mask = BIT(0),
3396 .hw.init = &(struct clk_init_data){
3397 .name = "gcc_usb3_sec_phy_pipe_clk",
3398 .parent_hws = (const struct clk_hw*[]){
3399 &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
3402 .flags = CLK_SET_RATE_PARENT,
3403 .ops = &clk_branch2_ops,
3408 /* external clocks so add BRANCH_HALT_SKIP */
3409 static struct clk_branch gcc_video_axi0_clk = {
3410 .halt_reg = 0x28010,
3411 .halt_check = BRANCH_HALT_SKIP,
3412 .hwcg_reg = 0x28010,
3415 .enable_reg = 0x28010,
3416 .enable_mask = BIT(0),
3417 .hw.init = &(struct clk_init_data){
3418 .name = "gcc_video_axi0_clk",
3419 .ops = &clk_branch2_ops,
3424 /* external clocks so add BRANCH_HALT_SKIP */
3425 static struct clk_branch gcc_video_axi1_clk = {
3426 .halt_reg = 0x28018,
3427 .halt_check = BRANCH_HALT_SKIP,
3428 .hwcg_reg = 0x28018,
3431 .enable_reg = 0x28018,
3432 .enable_mask = BIT(0),
3433 .hw.init = &(struct clk_init_data){
3434 .name = "gcc_video_axi1_clk",
3435 .ops = &clk_branch2_ops,
3440 static struct gdsc pcie_0_gdsc = {
3443 .name = "pcie_0_gdsc",
3445 .pwrsts = PWRSTS_OFF_ON,
3448 static struct gdsc pcie_1_gdsc = {
3451 .name = "pcie_1_gdsc",
3453 .pwrsts = PWRSTS_OFF_ON,
3456 static struct gdsc ufs_card_gdsc = {
3459 .name = "ufs_card_gdsc",
3461 .pwrsts = PWRSTS_OFF_ON,
3464 static struct gdsc ufs_phy_gdsc = {
3467 .name = "ufs_phy_gdsc",
3469 .pwrsts = PWRSTS_OFF_ON,
3472 static struct gdsc usb30_prim_gdsc = {
3475 .name = "usb30_prim_gdsc",
3477 .pwrsts = PWRSTS_OFF_ON,
3480 static struct gdsc usb30_sec_gdsc = {
3483 .name = "usb30_sec_gdsc",
3485 .pwrsts = PWRSTS_OFF_ON,
3488 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3491 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3493 .pwrsts = PWRSTS_OFF_ON,
3497 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3500 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3502 .pwrsts = PWRSTS_OFF_ON,
3506 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
3509 .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
3511 .pwrsts = PWRSTS_OFF_ON,
3515 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = {
3518 .name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc",
3520 .pwrsts = PWRSTS_OFF_ON,
3524 static struct clk_regmap *gcc_sm8350_clocks[] = {
3525 [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
3526 [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
3527 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3528 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3529 [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
3530 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3531 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3532 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3533 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3534 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3535 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3536 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3537 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3538 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3539 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3540 [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
3541 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3542 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3543 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3544 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3545 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3546 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3547 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3548 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3549 [GCC_GPLL0] = &gcc_gpll0.clkr,
3550 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3551 [GCC_GPLL4] = &gcc_gpll4.clkr,
3552 [GCC_GPLL9] = &gcc_gpll9.clkr,
3553 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3554 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3555 [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
3556 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3557 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3558 [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
3559 [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
3560 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3561 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3562 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3563 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
3564 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3565 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3566 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3567 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3568 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3569 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3570 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3571 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3572 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3573 [GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,
3574 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3575 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3576 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3577 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3578 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3579 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3580 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3581 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3582 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3583 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3584 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3585 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3586 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3587 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3588 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3589 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3590 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3591 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3592 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3593 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3594 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3595 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3596 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3597 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3598 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3599 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3600 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3601 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3602 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3603 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3604 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3605 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3606 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3607 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3608 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3609 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3610 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3611 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3612 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3613 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3614 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3615 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3616 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3617 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3618 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3619 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3620 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3621 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
3622 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
3623 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3624 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3625 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3626 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3627 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3628 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3629 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3630 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3631 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3632 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3633 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3634 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3635 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3636 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3637 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3638 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3639 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3640 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3641 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3642 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3643 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3644 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3645 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3646 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3647 [GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
3648 [GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr,
3649 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3650 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3651 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3652 [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
3653 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3654 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3655 [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
3656 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3657 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3658 [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
3659 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3660 [GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr,
3661 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3662 [GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr,
3663 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3664 [GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr,
3665 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3666 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
3667 [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
3668 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3669 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3670 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3671 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3672 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3673 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3674 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3675 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3676 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3677 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3678 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3679 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3680 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3681 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3682 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3683 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3684 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3685 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3686 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3687 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3688 [GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON] =
3689 &gcc_usb30_prim_master_clk__force_mem_core_on.clkr,
3690 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3691 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3692 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3693 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3694 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3695 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3696 [GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON] =
3697 &gcc_usb30_sec_master_clk__force_mem_core_on.clkr,
3698 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3699 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3700 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3701 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
3702 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3703 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3704 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3705 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3706 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3707 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3708 [GCC_USB3_SEC_CLKREF_EN] = &gcc_usb3_sec_clkref_en.clkr,
3709 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3710 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3711 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3712 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3713 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
3714 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3715 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3718 static struct gdsc *gcc_sm8350_gdscs[] = {
3719 [PCIE_0_GDSC] = &pcie_0_gdsc,
3720 [PCIE_1_GDSC] = &pcie_1_gdsc,
3721 [UFS_CARD_GDSC] = &ufs_card_gdsc,
3722 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3723 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3724 [USB30_SEC_GDSC] = &usb30_sec_gdsc,
3725 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3726 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3727 [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
3728 [HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc,
3731 static const struct qcom_reset_map gcc_sm8350_resets[] = {
3732 [GCC_CAMERA_BCR] = { 0x26000 },
3733 [GCC_DISPLAY_BCR] = { 0x27000 },
3734 [GCC_GPU_BCR] = { 0x71000 },
3735 [GCC_MMSS_BCR] = { 0xb000 },
3736 [GCC_PCIE_0_BCR] = { 0x6b000 },
3737 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3738 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3739 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3740 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3741 [GCC_PCIE_1_BCR] = { 0x8d000 },
3742 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3743 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3744 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3745 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
3746 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3747 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3748 [GCC_PDM_BCR] = { 0x33000 },
3749 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3750 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3751 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3752 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3753 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3754 [GCC_SDCC2_BCR] = { 0x14000 },
3755 [GCC_SDCC4_BCR] = { 0x16000 },
3756 [GCC_UFS_CARD_BCR] = { 0x75000 },
3757 [GCC_UFS_PHY_BCR] = { 0x77000 },
3758 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3759 [GCC_USB30_SEC_BCR] = { 0x10000 },
3760 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3761 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3762 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3763 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3764 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3765 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3766 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3767 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 },
3768 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 },
3769 [GCC_VIDEO_BCR] = { 0x28000 },
3772 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3773 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3774 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3775 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3776 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3777 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3778 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3779 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3780 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3781 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3782 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3783 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3784 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3785 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3786 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3787 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
3788 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
3789 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
3790 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
3791 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
3792 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
3795 static const struct regmap_config gcc_sm8350_regmap_config = {
3799 .max_register = 0x9c100,
3803 static const struct qcom_cc_desc gcc_sm8350_desc = {
3804 .config = &gcc_sm8350_regmap_config,
3805 .clks = gcc_sm8350_clocks,
3806 .num_clks = ARRAY_SIZE(gcc_sm8350_clocks),
3807 .resets = gcc_sm8350_resets,
3808 .num_resets = ARRAY_SIZE(gcc_sm8350_resets),
3809 .gdscs = gcc_sm8350_gdscs,
3810 .num_gdscs = ARRAY_SIZE(gcc_sm8350_gdscs),
3813 static const struct of_device_id gcc_sm8350_match_table[] = {
3814 { .compatible = "qcom,gcc-sm8350" },
3817 MODULE_DEVICE_TABLE(of, gcc_sm8350_match_table);
3819 static int gcc_sm8350_probe(struct platform_device *pdev)
3821 struct regmap *regmap;
3824 regmap = qcom_cc_map(pdev, &gcc_sm8350_desc);
3825 if (IS_ERR(regmap)) {
3826 dev_err(&pdev->dev, "Failed to map gcc registers\n");
3827 return PTR_ERR(regmap);
3831 * Keep the critical clock always-On
3832 * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK,
3833 * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK
3835 regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
3836 regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0));
3837 regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
3838 regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0));
3839 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
3840 regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
3841 regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0));
3843 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
3847 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
3848 regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
3850 return qcom_cc_really_probe(pdev, &gcc_sm8350_desc, regmap);
3853 static struct platform_driver gcc_sm8350_driver = {
3854 .probe = gcc_sm8350_probe,
3856 .name = "sm8350-gcc",
3857 .of_match_table = gcc_sm8350_match_table,
3861 static int __init gcc_sm8350_init(void)
3863 return platform_driver_register(&gcc_sm8350_driver);
3865 subsys_initcall(gcc_sm8350_init);
3867 static void __exit gcc_sm8350_exit(void)
3869 platform_driver_unregister(&gcc_sm8350_driver);
3871 module_exit(gcc_sm8350_exit);
3873 MODULE_DESCRIPTION("QTI GCC SM8350 Driver");
3874 MODULE_LICENSE("GPL v2");