1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2018, Craig Tatlor.
7 #include <linux/kernel.h>
8 #include <linux/bitops.h>
10 #include <linux/platform_device.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/clk-provider.h>
15 #include <linux/regmap.h>
16 #include <linux/reset-controller.h>
18 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
21 #include "clk-regmap.h"
22 #include "clk-alpha-pll.h"
24 #include "clk-branch.h"
28 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
40 static struct clk_fixed_factor xo = {
43 .hw.init = &(struct clk_init_data){
45 .parent_data = &(const struct clk_parent_data) {
49 .ops = &clk_fixed_factor_ops,
53 static struct clk_alpha_pll gpll0_early = {
55 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
57 .enable_reg = 0x52000,
58 .enable_mask = BIT(0),
59 .hw.init = &(struct clk_init_data){
60 .name = "gpll0_early",
61 .parent_data = &(const struct clk_parent_data){
65 .ops = &clk_alpha_pll_ops,
70 static struct clk_fixed_factor gpll0_early_div = {
73 .hw.init = &(struct clk_init_data){
74 .name = "gpll0_early_div",
75 .parent_hws = (const struct clk_hw*[]){
79 .ops = &clk_fixed_factor_ops,
83 static struct clk_alpha_pll_postdiv gpll0 = {
85 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
86 .clkr.hw.init = &(struct clk_init_data){
88 .parent_hws = (const struct clk_hw*[]){
92 .ops = &clk_alpha_pll_postdiv_ops,
96 static struct clk_alpha_pll gpll1_early = {
98 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
100 .enable_reg = 0x52000,
101 .enable_mask = BIT(1),
102 .hw.init = &(struct clk_init_data){
103 .name = "gpll1_early",
104 .parent_data = &(const struct clk_parent_data){
108 .ops = &clk_alpha_pll_ops,
113 static struct clk_fixed_factor gpll1_early_div = {
116 .hw.init = &(struct clk_init_data){
117 .name = "gpll1_early_div",
118 .parent_hws = (const struct clk_hw*[]){
119 &gpll1_early.clkr.hw,
122 .ops = &clk_fixed_factor_ops,
126 static struct clk_alpha_pll_postdiv gpll1 = {
128 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
129 .clkr.hw.init = &(struct clk_init_data){
131 .parent_hws = (const struct clk_hw*[]){
132 &gpll1_early.clkr.hw,
135 .ops = &clk_alpha_pll_postdiv_ops,
139 static struct clk_alpha_pll gpll4_early = {
141 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
143 .enable_reg = 0x52000,
144 .enable_mask = BIT(4),
145 .hw.init = &(struct clk_init_data){
146 .name = "gpll4_early",
147 .parent_data = &(const struct clk_parent_data){
151 .ops = &clk_alpha_pll_ops,
156 static struct clk_alpha_pll_postdiv gpll4 = {
158 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
159 .clkr.hw.init = &(struct clk_init_data)
162 .parent_hws = (const struct clk_hw*[]){
163 &gpll4_early.clkr.hw,
166 .ops = &clk_alpha_pll_postdiv_ops,
170 static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = {
173 { P_GPLL0_EARLY_DIV, 6 },
176 static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div[] = {
178 { .hw = &gpll0.clkr.hw },
179 { .hw = &gpll0_early_div.hw },
182 static const struct parent_map gcc_parent_map_xo_gpll0[] = {
187 static const struct clk_parent_data gcc_parent_data_xo_gpll0[] = {
189 { .hw = &gpll0.clkr.hw },
192 static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {
196 { P_GPLL0_EARLY_DIV, 6 },
199 static const struct clk_parent_data gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div[] = {
201 { .hw = &gpll0.clkr.hw },
202 { .fw_name = "sleep_clk" },
203 { .hw = &gpll0_early_div.hw },
206 static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
211 static const struct clk_parent_data gcc_parent_data_xo_sleep_clk[] = {
213 { .fw_name = "sleep_clk" },
216 static const struct parent_map gcc_parent_map_xo_gpll4[] = {
221 static const struct clk_parent_data gcc_parent_data_xo_gpll4[] = {
223 { .hw = &gpll4.clkr.hw },
226 static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
229 { P_GPLL0_EARLY_DIV, 3 },
232 { P_GPLL1_EARLY_DIV, 6 },
235 static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
237 { .hw = &gpll0.clkr.hw },
238 { .hw = &gpll0_early_div.hw },
239 { .hw = &gpll1.clkr.hw },
240 { .hw = &gpll4.clkr.hw },
241 { .hw = &gpll1_early_div.hw },
244 static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {
248 { P_GPLL0_EARLY_DIV, 6 },
251 static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div[] = {
253 { .hw = &gpll0.clkr.hw },
254 { .hw = &gpll4.clkr.hw },
255 { .hw = &gpll0_early_div.hw },
258 static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {
261 { P_GPLL0_EARLY_DIV, 2 },
265 static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4[] = {
267 { .hw = &gpll0.clkr.hw },
268 { .hw = &gpll0_early_div.hw },
269 { .hw = &gpll4.clkr.hw },
272 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
273 F(19200000, P_XO, 1, 0, 0),
274 F(50000000, P_GPLL0, 12, 0, 0),
278 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
282 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
283 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
284 .clkr.hw.init = &(struct clk_init_data){
285 .name = "blsp1_qup1_i2c_apps_clk_src",
286 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
287 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
288 .ops = &clk_rcg2_ops,
292 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
293 F(960000, P_XO, 10, 1, 2),
294 F(4800000, P_XO, 4, 0, 0),
295 F(9600000, P_XO, 2, 0, 0),
296 F(15000000, P_GPLL0, 10, 1, 4),
297 F(19200000, P_XO, 1, 0, 0),
298 F(25000000, P_GPLL0, 12, 1, 2),
299 F(50000000, P_GPLL0, 12, 0, 0),
303 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
307 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
308 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
309 .clkr.hw.init = &(struct clk_init_data){
310 .name = "blsp1_qup1_spi_apps_clk_src",
311 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
312 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
313 .ops = &clk_rcg2_ops,
317 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
321 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
322 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
323 .clkr.hw.init = &(struct clk_init_data){
324 .name = "blsp1_qup2_i2c_apps_clk_src",
325 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
326 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
327 .ops = &clk_rcg2_ops,
331 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
335 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
336 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
337 .clkr.hw.init = &(struct clk_init_data){
338 .name = "blsp1_qup2_spi_apps_clk_src",
339 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
340 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
341 .ops = &clk_rcg2_ops,
345 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
349 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
350 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
351 .clkr.hw.init = &(struct clk_init_data){
352 .name = "blsp1_qup3_i2c_apps_clk_src",
353 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
354 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
355 .ops = &clk_rcg2_ops,
359 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
363 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
364 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
365 .clkr.hw.init = &(struct clk_init_data){
366 .name = "blsp1_qup3_spi_apps_clk_src",
367 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
368 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
369 .ops = &clk_rcg2_ops,
373 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
377 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
378 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
379 .clkr.hw.init = &(struct clk_init_data){
380 .name = "blsp1_qup4_i2c_apps_clk_src",
381 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
382 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
383 .ops = &clk_rcg2_ops,
387 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
391 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
392 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
393 .clkr.hw.init = &(struct clk_init_data){
394 .name = "blsp1_qup4_spi_apps_clk_src",
395 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
396 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
397 .ops = &clk_rcg2_ops,
401 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
402 F(3686400, P_GPLL0, 1, 96, 15625),
403 F(7372800, P_GPLL0, 1, 192, 15625),
404 F(14745600, P_GPLL0, 1, 384, 15625),
405 F(16000000, P_GPLL0, 5, 2, 15),
406 F(19200000, P_XO, 1, 0, 0),
407 F(24000000, P_GPLL0, 5, 1, 5),
408 F(32000000, P_GPLL0, 1, 4, 75),
409 F(40000000, P_GPLL0, 15, 0, 0),
410 F(46400000, P_GPLL0, 1, 29, 375),
411 F(48000000, P_GPLL0, 12.5, 0, 0),
412 F(51200000, P_GPLL0, 1, 32, 375),
413 F(56000000, P_GPLL0, 1, 7, 75),
414 F(58982400, P_GPLL0, 1, 1536, 15625),
415 F(60000000, P_GPLL0, 10, 0, 0),
416 F(63157895, P_GPLL0, 9.5, 0, 0),
420 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
424 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
425 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
426 .clkr.hw.init = &(struct clk_init_data){
427 .name = "blsp1_uart1_apps_clk_src",
428 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
429 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
430 .ops = &clk_rcg2_ops,
434 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
438 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
439 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
440 .clkr.hw.init = &(struct clk_init_data){
441 .name = "blsp1_uart2_apps_clk_src",
442 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
443 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
444 .ops = &clk_rcg2_ops,
448 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
452 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
453 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
454 .clkr.hw.init = &(struct clk_init_data){
455 .name = "blsp2_qup1_i2c_apps_clk_src",
456 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
457 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
458 .ops = &clk_rcg2_ops,
462 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
466 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
467 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
468 .clkr.hw.init = &(struct clk_init_data){
469 .name = "blsp2_qup1_spi_apps_clk_src",
470 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
471 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
472 .ops = &clk_rcg2_ops,
476 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
480 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
481 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
482 .clkr.hw.init = &(struct clk_init_data){
483 .name = "blsp2_qup2_i2c_apps_clk_src",
484 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
485 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
486 .ops = &clk_rcg2_ops,
490 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
494 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
495 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
496 .clkr.hw.init = &(struct clk_init_data){
497 .name = "blsp2_qup2_spi_apps_clk_src",
498 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
499 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
500 .ops = &clk_rcg2_ops,
504 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
508 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
509 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
510 .clkr.hw.init = &(struct clk_init_data){
511 .name = "blsp2_qup3_i2c_apps_clk_src",
512 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
513 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
514 .ops = &clk_rcg2_ops,
518 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
522 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
523 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
524 .clkr.hw.init = &(struct clk_init_data){
525 .name = "blsp2_qup3_spi_apps_clk_src",
526 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
527 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
528 .ops = &clk_rcg2_ops,
532 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
536 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
537 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
538 .clkr.hw.init = &(struct clk_init_data){
539 .name = "blsp2_qup4_i2c_apps_clk_src",
540 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
541 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
542 .ops = &clk_rcg2_ops,
546 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
550 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
551 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
552 .clkr.hw.init = &(struct clk_init_data){
553 .name = "blsp2_qup4_spi_apps_clk_src",
554 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
555 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
556 .ops = &clk_rcg2_ops,
560 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
564 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
565 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
566 .clkr.hw.init = &(struct clk_init_data){
567 .name = "blsp2_uart1_apps_clk_src",
568 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
569 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
570 .ops = &clk_rcg2_ops,
574 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
578 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
579 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
580 .clkr.hw.init = &(struct clk_init_data){
581 .name = "blsp2_uart2_apps_clk_src",
582 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
583 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
584 .ops = &clk_rcg2_ops,
588 static const struct freq_tbl ftbl_gp1_clk_src[] = {
589 F(19200000, P_XO, 1, 0, 0),
590 F(100000000, P_GPLL0, 6, 0, 0),
591 F(200000000, P_GPLL0, 3, 0, 0),
595 static struct clk_rcg2 gp1_clk_src = {
599 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
600 .freq_tbl = ftbl_gp1_clk_src,
601 .clkr.hw.init = &(struct clk_init_data){
602 .name = "gp1_clk_src",
603 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
604 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),
605 .ops = &clk_rcg2_ops,
609 static struct clk_rcg2 gp2_clk_src = {
613 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
614 .freq_tbl = ftbl_gp1_clk_src,
615 .clkr.hw.init = &(struct clk_init_data){
616 .name = "gp2_clk_src",
617 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
618 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),
619 .ops = &clk_rcg2_ops,
623 static struct clk_rcg2 gp3_clk_src = {
627 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
628 .freq_tbl = ftbl_gp1_clk_src,
629 .clkr.hw.init = &(struct clk_init_data){
630 .name = "gp3_clk_src",
631 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
632 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),
633 .ops = &clk_rcg2_ops,
637 static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
638 F(300000000, P_GPLL0, 2, 0, 0),
639 F(600000000, P_GPLL0, 1, 0, 0),
643 static struct clk_rcg2 hmss_gpll0_clk_src = {
647 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
648 .freq_tbl = ftbl_hmss_gpll0_clk_src,
649 .clkr.hw.init = &(struct clk_init_data){
650 .name = "hmss_gpll0_clk_src",
651 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
652 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
653 .ops = &clk_rcg2_ops,
657 static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = {
658 F(384000000, P_GPLL4, 4, 0, 0),
659 F(768000000, P_GPLL4, 2, 0, 0),
660 F(1536000000, P_GPLL4, 1, 0, 0),
664 static struct clk_rcg2 hmss_gpll4_clk_src = {
668 .parent_map = gcc_parent_map_xo_gpll4,
669 .freq_tbl = ftbl_hmss_gpll4_clk_src,
670 .clkr.hw.init = &(struct clk_init_data){
671 .name = "hmss_gpll4_clk_src",
672 .parent_data = gcc_parent_data_xo_gpll4,
673 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll4),
674 .ops = &clk_rcg2_ops,
678 static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
679 F(19200000, P_XO, 1, 0, 0),
683 static struct clk_rcg2 hmss_rbcpr_clk_src = {
687 .parent_map = gcc_parent_map_xo_gpll0,
688 .freq_tbl = ftbl_hmss_rbcpr_clk_src,
689 .clkr.hw.init = &(struct clk_init_data){
690 .name = "hmss_rbcpr_clk_src",
691 .parent_data = gcc_parent_data_xo_gpll0,
692 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0),
693 .ops = &clk_rcg2_ops,
697 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
698 F(60000000, P_GPLL0, 10, 0, 0),
702 static struct clk_rcg2 pdm2_clk_src = {
706 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
707 .freq_tbl = ftbl_pdm2_clk_src,
708 .clkr.hw.init = &(struct clk_init_data){
709 .name = "pdm2_clk_src",
710 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
711 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
712 .ops = &clk_rcg2_ops,
716 static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
717 F(19200000, P_XO, 1, 0, 0),
718 F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
719 F(160400000, P_GPLL1, 5, 0, 0),
720 F(267333333, P_GPLL1, 3, 0, 0),
724 static struct clk_rcg2 qspi_ser_clk_src = {
728 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
729 .freq_tbl = ftbl_qspi_ser_clk_src,
730 .clkr.hw.init = &(struct clk_init_data){
731 .name = "qspi_ser_clk_src",
732 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
733 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div),
734 .ops = &clk_rcg2_ops,
738 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
739 F(144000, P_XO, 16, 3, 25),
740 F(400000, P_XO, 12, 1, 4),
741 F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
742 F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
743 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
744 F(100000000, P_GPLL0, 6, 0, 0),
745 F(192000000, P_GPLL4, 8, 0, 0),
746 F(384000000, P_GPLL4, 4, 0, 0),
750 static struct clk_rcg2 sdcc1_apps_clk_src = {
754 .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
755 .freq_tbl = ftbl_sdcc1_apps_clk_src,
756 .clkr.hw.init = &(struct clk_init_data){
757 .name = "sdcc1_apps_clk_src",
758 .parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div,
759 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div),
760 .ops = &clk_rcg2_floor_ops,
764 static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
765 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
766 F(150000000, P_GPLL0, 4, 0, 0),
767 F(200000000, P_GPLL0, 3, 0, 0),
768 F(300000000, P_GPLL0, 2, 0, 0),
772 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
776 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
777 .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
778 .clkr.hw.init = &(struct clk_init_data){
779 .name = "sdcc1_ice_core_clk_src",
780 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
781 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
782 .ops = &clk_rcg2_ops,
786 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
787 F(144000, P_XO, 16, 3, 25),
788 F(400000, P_XO, 12, 1, 4),
789 F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
790 F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
791 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
792 F(100000000, P_GPLL0, 6, 0, 0),
793 F(192000000, P_GPLL4, 8, 0, 0),
794 F(200000000, P_GPLL0, 3, 0, 0),
798 static struct clk_rcg2 sdcc2_apps_clk_src = {
802 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
803 .freq_tbl = ftbl_sdcc2_apps_clk_src,
804 .clkr.hw.init = &(struct clk_init_data){
805 .name = "sdcc2_apps_clk_src",
806 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4,
807 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4),
808 .ops = &clk_rcg2_floor_ops,
812 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
813 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
814 F(100000000, P_GPLL0, 6, 0, 0),
815 F(150000000, P_GPLL0, 4, 0, 0),
816 F(200000000, P_GPLL0, 3, 0, 0),
817 F(240000000, P_GPLL0, 2.5, 0, 0),
821 static struct clk_rcg2 ufs_axi_clk_src = {
825 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
826 .freq_tbl = ftbl_ufs_axi_clk_src,
827 .clkr.hw.init = &(struct clk_init_data){
828 .name = "ufs_axi_clk_src",
829 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
830 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
831 .ops = &clk_rcg2_ops,
835 static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
836 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
837 F(150000000, P_GPLL0, 4, 0, 0),
838 F(300000000, P_GPLL0, 2, 0, 0),
842 static struct clk_rcg2 ufs_ice_core_clk_src = {
846 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
847 .freq_tbl = ftbl_ufs_ice_core_clk_src,
848 .clkr.hw.init = &(struct clk_init_data){
849 .name = "ufs_ice_core_clk_src",
850 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
851 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
852 .ops = &clk_rcg2_ops,
856 static struct clk_rcg2 ufs_phy_aux_clk_src = {
860 .parent_map = gcc_parent_map_xo_sleep_clk,
861 .freq_tbl = ftbl_hmss_rbcpr_clk_src,
862 .clkr.hw.init = &(struct clk_init_data){
863 .name = "ufs_phy_aux_clk_src",
864 .parent_data = gcc_parent_data_xo_sleep_clk,
865 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk),
866 .ops = &clk_rcg2_ops,
870 static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
871 F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
872 F(75000000, P_GPLL0, 8, 0, 0),
873 F(150000000, P_GPLL0, 4, 0, 0),
877 static struct clk_rcg2 ufs_unipro_core_clk_src = {
881 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
882 .freq_tbl = ftbl_ufs_unipro_core_clk_src,
883 .clkr.hw.init = &(struct clk_init_data){
884 .name = "ufs_unipro_core_clk_src",
885 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
886 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
887 .ops = &clk_rcg2_ops,
891 static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
892 F(19200000, P_XO, 1, 0, 0),
893 F(60000000, P_GPLL0, 10, 0, 0),
894 F(120000000, P_GPLL0, 5, 0, 0),
898 static struct clk_rcg2 usb20_master_clk_src = {
902 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
903 .freq_tbl = ftbl_usb20_master_clk_src,
904 .clkr.hw.init = &(struct clk_init_data){
905 .name = "usb20_master_clk_src",
906 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
907 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
908 .ops = &clk_rcg2_ops,
912 static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = {
913 F(19200000, P_XO, 1, 0, 0),
914 F(60000000, P_GPLL0, 10, 0, 0),
918 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
922 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
923 .freq_tbl = ftbl_usb20_mock_utmi_clk_src,
924 .clkr.hw.init = &(struct clk_init_data){
925 .name = "usb20_mock_utmi_clk_src",
926 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
927 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
928 .ops = &clk_rcg2_ops,
932 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
933 F(19200000, P_XO, 1, 0, 0),
934 F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
935 F(120000000, P_GPLL0, 5, 0, 0),
936 F(133333333, P_GPLL0, 4.5, 0, 0),
937 F(150000000, P_GPLL0, 4, 0, 0),
938 F(200000000, P_GPLL0, 3, 0, 0),
939 F(240000000, P_GPLL0, 2.5, 0, 0),
943 static struct clk_rcg2 usb30_master_clk_src = {
947 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
948 .freq_tbl = ftbl_usb30_master_clk_src,
949 .clkr.hw.init = &(struct clk_init_data){
950 .name = "usb30_master_clk_src",
951 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
952 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
953 .ops = &clk_rcg2_ops,
957 static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
958 F(19200000, P_XO, 1, 0, 0),
959 F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
960 F(60000000, P_GPLL0, 10, 0, 0),
964 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
968 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
969 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
970 .clkr.hw.init = &(struct clk_init_data){
971 .name = "usb30_mock_utmi_clk_src",
972 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
973 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
974 .ops = &clk_rcg2_ops,
978 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
979 F(1200000, P_XO, 16, 0, 0),
980 F(19200000, P_XO, 1, 0, 0),
984 static struct clk_rcg2 usb3_phy_aux_clk_src = {
988 .parent_map = gcc_parent_map_xo_sleep_clk,
989 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
990 .clkr.hw.init = &(struct clk_init_data){
991 .name = "usb3_phy_aux_clk_src",
992 .parent_data = gcc_parent_data_xo_sleep_clk,
993 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk),
994 .ops = &clk_rcg2_ops,
998 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
1000 .halt_check = BRANCH_HALT,
1002 .enable_reg = 0x75034,
1003 .enable_mask = BIT(0),
1004 .hw.init = &(struct clk_init_data){
1005 .name = "gcc_aggre2_ufs_axi_clk",
1006 .parent_hws = (const struct clk_hw*[]) {
1007 &ufs_axi_clk_src.clkr.hw,
1010 .ops = &clk_branch2_ops,
1015 static struct clk_branch gcc_aggre2_usb3_axi_clk = {
1017 .halt_check = BRANCH_HALT,
1019 .enable_reg = 0xf03c,
1020 .enable_mask = BIT(0),
1021 .hw.init = &(struct clk_init_data){
1022 .name = "gcc_aggre2_usb3_axi_clk",
1023 .parent_hws = (const struct clk_hw*[]) {
1024 &usb30_master_clk_src.clkr.hw,
1027 .ops = &clk_branch2_ops,
1032 static struct clk_branch gcc_bimc_gfx_clk = {
1033 .halt_reg = 0x7106c,
1034 .halt_check = BRANCH_VOTED,
1036 .enable_reg = 0x7106c,
1037 .enable_mask = BIT(0),
1038 .hw.init = &(struct clk_init_data){
1039 .name = "gcc_bimc_gfx_clk",
1040 .ops = &clk_branch2_ops,
1045 static struct clk_branch gcc_bimc_hmss_axi_clk = {
1046 .halt_reg = 0x48004,
1047 .halt_check = BRANCH_HALT_VOTED,
1049 .enable_reg = 0x52004,
1050 .enable_mask = BIT(22),
1051 .hw.init = &(struct clk_init_data){
1052 .name = "gcc_bimc_hmss_axi_clk",
1053 .ops = &clk_branch2_ops,
1058 static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
1059 .halt_reg = 0x4401c,
1060 .halt_check = BRANCH_HALT,
1062 .enable_reg = 0x4401c,
1063 .enable_mask = BIT(0),
1064 .hw.init = &(struct clk_init_data){
1065 .name = "gcc_bimc_mss_q6_axi_clk",
1066 .ops = &clk_branch2_ops,
1071 static struct clk_branch gcc_blsp1_ahb_clk = {
1072 .halt_reg = 0x17004,
1073 .halt_check = BRANCH_HALT_VOTED,
1075 .enable_reg = 0x52004,
1076 .enable_mask = BIT(17),
1077 .hw.init = &(struct clk_init_data){
1078 .name = "gcc_blsp1_ahb_clk",
1079 .ops = &clk_branch2_ops,
1084 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1085 .halt_reg = 0x19008,
1086 .halt_check = BRANCH_HALT,
1088 .enable_reg = 0x19008,
1089 .enable_mask = BIT(0),
1090 .hw.init = &(struct clk_init_data){
1091 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1092 .parent_hws = (const struct clk_hw*[]) {
1093 &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1096 .flags = CLK_SET_RATE_PARENT,
1097 .ops = &clk_branch2_ops,
1102 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1103 .halt_reg = 0x19004,
1104 .halt_check = BRANCH_HALT,
1106 .enable_reg = 0x19004,
1107 .enable_mask = BIT(0),
1108 .hw.init = &(struct clk_init_data){
1109 .name = "gcc_blsp1_qup1_spi_apps_clk",
1110 .parent_hws = (const struct clk_hw*[]) {
1111 &blsp1_qup1_spi_apps_clk_src.clkr.hw,
1114 .flags = CLK_SET_RATE_PARENT,
1115 .ops = &clk_branch2_ops,
1120 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1121 .halt_reg = 0x1b008,
1122 .halt_check = BRANCH_HALT,
1124 .enable_reg = 0x1b008,
1125 .enable_mask = BIT(0),
1126 .hw.init = &(struct clk_init_data){
1127 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1128 .parent_hws = (const struct clk_hw*[]) {
1129 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1132 .flags = CLK_SET_RATE_PARENT,
1133 .ops = &clk_branch2_ops,
1138 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1139 .halt_reg = 0x1b004,
1140 .halt_check = BRANCH_HALT,
1142 .enable_reg = 0x1b004,
1143 .enable_mask = BIT(0),
1144 .hw.init = &(struct clk_init_data){
1145 .name = "gcc_blsp1_qup2_spi_apps_clk",
1146 .parent_hws = (const struct clk_hw*[]) {
1147 &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1150 .flags = CLK_SET_RATE_PARENT,
1151 .ops = &clk_branch2_ops,
1156 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1157 .halt_reg = 0x1d008,
1158 .halt_check = BRANCH_HALT,
1160 .enable_reg = 0x1d008,
1161 .enable_mask = BIT(0),
1162 .hw.init = &(struct clk_init_data){
1163 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1164 .parent_hws = (const struct clk_hw*[]) {
1165 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1168 .flags = CLK_SET_RATE_PARENT,
1169 .ops = &clk_branch2_ops,
1174 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1175 .halt_reg = 0x1d004,
1176 .halt_check = BRANCH_HALT,
1178 .enable_reg = 0x1d004,
1179 .enable_mask = BIT(0),
1180 .hw.init = &(struct clk_init_data){
1181 .name = "gcc_blsp1_qup3_spi_apps_clk",
1182 .parent_hws = (const struct clk_hw*[]) {
1183 &blsp1_qup3_spi_apps_clk_src.clkr.hw,
1186 .flags = CLK_SET_RATE_PARENT,
1187 .ops = &clk_branch2_ops,
1192 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1193 .halt_reg = 0x1f008,
1194 .halt_check = BRANCH_HALT,
1196 .enable_reg = 0x1f008,
1197 .enable_mask = BIT(0),
1198 .hw.init = &(struct clk_init_data){
1199 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1200 .parent_hws = (const struct clk_hw*[]) {
1201 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1204 .flags = CLK_SET_RATE_PARENT,
1205 .ops = &clk_branch2_ops,
1210 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1211 .halt_reg = 0x1f004,
1212 .halt_check = BRANCH_HALT,
1214 .enable_reg = 0x1f004,
1215 .enable_mask = BIT(0),
1216 .hw.init = &(struct clk_init_data){
1217 .name = "gcc_blsp1_qup4_spi_apps_clk",
1218 .parent_hws = (const struct clk_hw*[]) {
1219 &blsp1_qup4_spi_apps_clk_src.clkr.hw,
1222 .flags = CLK_SET_RATE_PARENT,
1223 .ops = &clk_branch2_ops,
1228 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1229 .halt_reg = 0x1a004,
1230 .halt_check = BRANCH_HALT,
1232 .enable_reg = 0x1a004,
1233 .enable_mask = BIT(0),
1234 .hw.init = &(struct clk_init_data){
1235 .name = "gcc_blsp1_uart1_apps_clk",
1236 .parent_hws = (const struct clk_hw*[]) {
1237 &blsp1_uart1_apps_clk_src.clkr.hw,
1240 .flags = CLK_SET_RATE_PARENT,
1241 .ops = &clk_branch2_ops,
1246 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1247 .halt_reg = 0x1c004,
1248 .halt_check = BRANCH_HALT,
1250 .enable_reg = 0x1c004,
1251 .enable_mask = BIT(0),
1252 .hw.init = &(struct clk_init_data){
1253 .name = "gcc_blsp1_uart2_apps_clk",
1254 .parent_hws = (const struct clk_hw*[]) {
1255 &blsp1_uart2_apps_clk_src.clkr.hw,
1258 .flags = CLK_SET_RATE_PARENT,
1259 .ops = &clk_branch2_ops,
1264 static struct clk_branch gcc_blsp2_ahb_clk = {
1265 .halt_reg = 0x25004,
1266 .halt_check = BRANCH_HALT_VOTED,
1268 .enable_reg = 0x52004,
1269 .enable_mask = BIT(15),
1270 .hw.init = &(struct clk_init_data){
1271 .name = "gcc_blsp2_ahb_clk",
1272 .ops = &clk_branch2_ops,
1277 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1278 .halt_reg = 0x26008,
1279 .halt_check = BRANCH_HALT,
1281 .enable_reg = 0x26008,
1282 .enable_mask = BIT(0),
1283 .hw.init = &(struct clk_init_data){
1284 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1285 .parent_hws = (const struct clk_hw*[]) {
1286 &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
1289 .flags = CLK_SET_RATE_PARENT,
1290 .ops = &clk_branch2_ops,
1295 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1296 .halt_reg = 0x26004,
1297 .halt_check = BRANCH_HALT,
1299 .enable_reg = 0x26004,
1300 .enable_mask = BIT(0),
1301 .hw.init = &(struct clk_init_data){
1302 .name = "gcc_blsp2_qup1_spi_apps_clk",
1303 .parent_hws = (const struct clk_hw*[]) {
1304 &blsp2_qup1_spi_apps_clk_src.clkr.hw,
1307 .flags = CLK_SET_RATE_PARENT,
1308 .ops = &clk_branch2_ops,
1313 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1314 .halt_reg = 0x28008,
1315 .halt_check = BRANCH_HALT,
1317 .enable_reg = 0x28008,
1318 .enable_mask = BIT(0),
1319 .hw.init = &(struct clk_init_data){
1320 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1321 .parent_hws = (const struct clk_hw*[]) {
1322 &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
1325 .flags = CLK_SET_RATE_PARENT,
1326 .ops = &clk_branch2_ops,
1331 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1332 .halt_reg = 0x28004,
1333 .halt_check = BRANCH_HALT,
1335 .enable_reg = 0x28004,
1336 .enable_mask = BIT(0),
1337 .hw.init = &(struct clk_init_data){
1338 .name = "gcc_blsp2_qup2_spi_apps_clk",
1339 .parent_hws = (const struct clk_hw*[]) {
1340 &blsp2_qup2_spi_apps_clk_src.clkr.hw,
1343 .flags = CLK_SET_RATE_PARENT,
1344 .ops = &clk_branch2_ops,
1349 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1350 .halt_reg = 0x2a008,
1351 .halt_check = BRANCH_HALT,
1353 .enable_reg = 0x2a008,
1354 .enable_mask = BIT(0),
1355 .hw.init = &(struct clk_init_data){
1356 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1357 .parent_hws = (const struct clk_hw*[]) {
1358 &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
1361 .flags = CLK_SET_RATE_PARENT,
1362 .ops = &clk_branch2_ops,
1367 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1368 .halt_reg = 0x2a004,
1369 .halt_check = BRANCH_HALT,
1371 .enable_reg = 0x2a004,
1372 .enable_mask = BIT(0),
1373 .hw.init = &(struct clk_init_data){
1374 .name = "gcc_blsp2_qup3_spi_apps_clk",
1375 .parent_hws = (const struct clk_hw*[]) {
1376 &blsp2_qup3_spi_apps_clk_src.clkr.hw,
1379 .flags = CLK_SET_RATE_PARENT,
1380 .ops = &clk_branch2_ops,
1385 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1386 .halt_reg = 0x2c008,
1387 .halt_check = BRANCH_HALT,
1389 .enable_reg = 0x2c008,
1390 .enable_mask = BIT(0),
1391 .hw.init = &(struct clk_init_data){
1392 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1393 .parent_hws = (const struct clk_hw*[]) {
1394 &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
1397 .flags = CLK_SET_RATE_PARENT,
1398 .ops = &clk_branch2_ops,
1403 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1404 .halt_reg = 0x2c004,
1405 .halt_check = BRANCH_HALT,
1407 .enable_reg = 0x2c004,
1408 .enable_mask = BIT(0),
1409 .hw.init = &(struct clk_init_data){
1410 .name = "gcc_blsp2_qup4_spi_apps_clk",
1411 .parent_hws = (const struct clk_hw*[]) {
1412 &blsp2_qup4_spi_apps_clk_src.clkr.hw,
1415 .flags = CLK_SET_RATE_PARENT,
1416 .ops = &clk_branch2_ops,
1421 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1422 .halt_reg = 0x27004,
1423 .halt_check = BRANCH_HALT,
1425 .enable_reg = 0x27004,
1426 .enable_mask = BIT(0),
1427 .hw.init = &(struct clk_init_data){
1428 .name = "gcc_blsp2_uart1_apps_clk",
1429 .parent_hws = (const struct clk_hw*[]) {
1430 &blsp2_uart1_apps_clk_src.clkr.hw,
1433 .flags = CLK_SET_RATE_PARENT,
1434 .ops = &clk_branch2_ops,
1439 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1440 .halt_reg = 0x29004,
1441 .halt_check = BRANCH_HALT,
1443 .enable_reg = 0x29004,
1444 .enable_mask = BIT(0),
1445 .hw.init = &(struct clk_init_data){
1446 .name = "gcc_blsp2_uart2_apps_clk",
1447 .parent_hws = (const struct clk_hw*[]) {
1448 &blsp2_uart2_apps_clk_src.clkr.hw,
1451 .flags = CLK_SET_RATE_PARENT,
1452 .ops = &clk_branch2_ops,
1457 static struct clk_branch gcc_boot_rom_ahb_clk = {
1458 .halt_reg = 0x38004,
1459 .halt_check = BRANCH_HALT_VOTED,
1461 .enable_reg = 0x52004,
1462 .enable_mask = BIT(10),
1463 .hw.init = &(struct clk_init_data){
1464 .name = "gcc_boot_rom_ahb_clk",
1465 .ops = &clk_branch2_ops,
1470 static struct clk_branch gcc_cfg_noc_usb2_axi_clk = {
1472 .halt_check = BRANCH_HALT,
1474 .enable_reg = 0x5058,
1475 .enable_mask = BIT(0),
1476 .hw.init = &(struct clk_init_data){
1477 .name = "gcc_cfg_noc_usb2_axi_clk",
1478 .parent_hws = (const struct clk_hw*[]) {
1479 &usb20_master_clk_src.clkr.hw,
1482 .ops = &clk_branch2_ops,
1487 static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
1489 .halt_check = BRANCH_HALT,
1491 .enable_reg = 0x5018,
1492 .enable_mask = BIT(0),
1493 .hw.init = &(struct clk_init_data){
1494 .name = "gcc_cfg_noc_usb3_axi_clk",
1495 .parent_hws = (const struct clk_hw*[]) {
1496 &usb30_master_clk_src.clkr.hw,
1499 .ops = &clk_branch2_ops,
1504 static struct clk_branch gcc_dcc_ahb_clk = {
1505 .halt_reg = 0x84004,
1507 .enable_reg = 0x84004,
1508 .enable_mask = BIT(0),
1509 .hw.init = &(struct clk_init_data){
1510 .name = "gcc_dcc_ahb_clk",
1511 .ops = &clk_branch2_ops,
1516 static struct clk_branch gcc_gp1_clk = {
1517 .halt_reg = 0x64000,
1518 .halt_check = BRANCH_HALT,
1520 .enable_reg = 0x64000,
1521 .enable_mask = BIT(0),
1522 .hw.init = &(struct clk_init_data){
1523 .name = "gcc_gp1_clk",
1524 .parent_hws = (const struct clk_hw*[]) {
1525 &gp1_clk_src.clkr.hw,
1528 .flags = CLK_SET_RATE_PARENT,
1529 .ops = &clk_branch2_ops,
1534 static struct clk_branch gcc_gp2_clk = {
1535 .halt_reg = 0x65000,
1536 .halt_check = BRANCH_HALT,
1538 .enable_reg = 0x65000,
1539 .enable_mask = BIT(0),
1540 .hw.init = &(struct clk_init_data){
1541 .name = "gcc_gp2_clk",
1542 .parent_hws = (const struct clk_hw*[]) {
1543 &gp2_clk_src.clkr.hw,
1546 .flags = CLK_SET_RATE_PARENT,
1547 .ops = &clk_branch2_ops,
1552 static struct clk_branch gcc_gp3_clk = {
1553 .halt_reg = 0x66000,
1554 .halt_check = BRANCH_HALT,
1556 .enable_reg = 0x66000,
1557 .enable_mask = BIT(0),
1558 .hw.init = &(struct clk_init_data){
1559 .name = "gcc_gp3_clk",
1560 .parent_hws = (const struct clk_hw*[]) {
1561 &gp3_clk_src.clkr.hw,
1564 .flags = CLK_SET_RATE_PARENT,
1565 .ops = &clk_branch2_ops,
1570 static struct clk_branch gcc_gpu_bimc_gfx_clk = {
1571 .halt_reg = 0x71010,
1572 .halt_check = BRANCH_VOTED,
1574 .enable_reg = 0x71010,
1575 .enable_mask = BIT(0),
1576 .hw.init = &(struct clk_init_data){
1577 .name = "gcc_gpu_bimc_gfx_clk",
1578 .ops = &clk_branch2_ops,
1583 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1584 .halt_reg = 0x71004,
1585 .halt_check = BRANCH_VOTED,
1587 .enable_reg = 0x71004,
1588 .enable_mask = BIT(0),
1589 .hw.init = &(struct clk_init_data){
1590 .name = "gcc_gpu_cfg_ahb_clk",
1591 .ops = &clk_branch2_ops,
1592 .flags = CLK_IS_CRITICAL,
1597 static struct clk_branch gcc_gpu_gpll0_clk = {
1598 .halt_reg = 0x5200c,
1599 .halt_check = BRANCH_HALT_DELAY,
1601 .enable_reg = 0x5200c,
1602 .enable_mask = BIT(4),
1603 .hw.init = &(struct clk_init_data){
1604 .name = "gcc_gpu_gpll0_clk",
1605 .parent_hws = (const struct clk_hw*[]) {
1609 .ops = &clk_branch2_ops,
1614 static struct clk_branch gcc_gpu_gpll0_div_clk = {
1615 .halt_reg = 0x5200c,
1616 .halt_check = BRANCH_HALT_DELAY,
1618 .enable_reg = 0x5200c,
1619 .enable_mask = BIT(3),
1620 .hw.init = &(struct clk_init_data){
1621 .name = "gcc_gpu_gpll0_div_clk",
1622 .parent_hws = (const struct clk_hw*[]) {
1623 &gpll0_early_div.hw,
1626 .ops = &clk_branch2_ops,
1631 static struct clk_branch gcc_hmss_dvm_bus_clk = {
1632 .halt_reg = 0x4808c,
1633 .halt_check = BRANCH_HALT,
1635 .enable_reg = 0x4808c,
1636 .enable_mask = BIT(0),
1637 .hw.init = &(struct clk_init_data){
1638 .name = "gcc_hmss_dvm_bus_clk",
1639 .ops = &clk_branch2_ops,
1640 .flags = CLK_IGNORE_UNUSED,
1645 static struct clk_branch gcc_hmss_rbcpr_clk = {
1646 .halt_reg = 0x48008,
1647 .halt_check = BRANCH_HALT,
1649 .enable_reg = 0x48008,
1650 .enable_mask = BIT(0),
1651 .hw.init = &(struct clk_init_data){
1652 .name = "gcc_hmss_rbcpr_clk",
1653 .parent_hws = (const struct clk_hw*[]) {
1654 &hmss_rbcpr_clk_src.clkr.hw,
1657 .flags = CLK_SET_RATE_PARENT,
1658 .ops = &clk_branch2_ops,
1663 static struct clk_branch gcc_mmss_gpll0_clk = {
1664 .halt_reg = 0x5200c,
1665 .halt_check = BRANCH_HALT_DELAY,
1667 .enable_reg = 0x5200c,
1668 .enable_mask = BIT(1),
1669 .hw.init = &(struct clk_init_data){
1670 .name = "gcc_mmss_gpll0_clk",
1671 .parent_hws = (const struct clk_hw*[]) {
1675 .ops = &clk_branch2_ops,
1680 static struct clk_branch gcc_mmss_gpll0_div_clk = {
1681 .halt_reg = 0x5200c,
1682 .halt_check = BRANCH_HALT_DELAY,
1684 .enable_reg = 0x5200c,
1685 .enable_mask = BIT(0),
1686 .hw.init = &(struct clk_init_data){
1687 .name = "gcc_mmss_gpll0_div_clk",
1688 .parent_hws = (const struct clk_hw*[]) {
1689 &gpll0_early_div.hw,
1692 .ops = &clk_branch2_ops,
1697 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1699 .halt_check = BRANCH_HALT,
1701 .enable_reg = 0x9004,
1702 .enable_mask = BIT(0),
1703 .hw.init = &(struct clk_init_data){
1704 .name = "gcc_mmss_noc_cfg_ahb_clk",
1705 .ops = &clk_branch2_ops,
1707 * Any access to mmss depends on this clock.
1708 * Gating this clock has been shown to crash the system
1709 * when mmssnoc_axi_rpm_clk is inited in rpmcc.
1711 .flags = CLK_IS_CRITICAL,
1716 static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
1718 .halt_check = BRANCH_HALT,
1720 .enable_reg = 0x9000,
1721 .enable_mask = BIT(0),
1722 .hw.init = &(struct clk_init_data){
1723 .name = "gcc_mmss_sys_noc_axi_clk",
1724 .ops = &clk_branch2_ops,
1729 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1730 .halt_reg = 0x8a000,
1732 .enable_reg = 0x8a000,
1733 .enable_mask = BIT(0),
1734 .hw.init = &(struct clk_init_data){
1735 .name = "gcc_mss_cfg_ahb_clk",
1736 .ops = &clk_branch2_ops,
1741 static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
1742 .halt_reg = 0x8a004,
1743 .halt_check = BRANCH_HALT,
1744 .hwcg_reg = 0x8a004,
1747 .enable_reg = 0x8a004,
1748 .enable_mask = BIT(0),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "gcc_mss_mnoc_bimc_axi_clk",
1751 .ops = &clk_branch2_ops,
1756 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1757 .halt_reg = 0x8a040,
1759 .enable_reg = 0x8a040,
1760 .enable_mask = BIT(0),
1761 .hw.init = &(struct clk_init_data){
1762 .name = "gcc_mss_q6_bimc_axi_clk",
1763 .ops = &clk_branch2_ops,
1768 static struct clk_branch gcc_mss_snoc_axi_clk = {
1769 .halt_reg = 0x8a03c,
1771 .enable_reg = 0x8a03c,
1772 .enable_mask = BIT(0),
1773 .hw.init = &(struct clk_init_data){
1774 .name = "gcc_mss_snoc_axi_clk",
1775 .ops = &clk_branch2_ops,
1780 static struct clk_branch gcc_pdm2_clk = {
1781 .halt_reg = 0x3300c,
1782 .halt_check = BRANCH_HALT,
1784 .enable_reg = 0x3300c,
1785 .enable_mask = BIT(0),
1786 .hw.init = &(struct clk_init_data){
1787 .name = "gcc_pdm2_clk",
1788 .parent_hws = (const struct clk_hw*[]) {
1789 &pdm2_clk_src.clkr.hw,
1792 .flags = CLK_SET_RATE_PARENT,
1793 .ops = &clk_branch2_ops,
1798 static struct clk_branch gcc_pdm_ahb_clk = {
1799 .halt_reg = 0x33004,
1800 .halt_check = BRANCH_HALT,
1802 .enable_reg = 0x33004,
1803 .enable_mask = BIT(0),
1804 .hw.init = &(struct clk_init_data){
1805 .name = "gcc_pdm_ahb_clk",
1806 .ops = &clk_branch2_ops,
1811 static struct clk_branch gcc_prng_ahb_clk = {
1812 .halt_reg = 0x34004,
1813 .halt_check = BRANCH_HALT_VOTED,
1815 .enable_reg = 0x52004,
1816 .enable_mask = BIT(13),
1817 .hw.init = &(struct clk_init_data){
1818 .name = "gcc_prng_ahb_clk",
1819 .ops = &clk_branch2_ops,
1824 static struct clk_branch gcc_qspi_ahb_clk = {
1825 .halt_reg = 0x4d004,
1826 .halt_check = BRANCH_HALT,
1828 .enable_reg = 0x4d004,
1829 .enable_mask = BIT(0),
1830 .hw.init = &(struct clk_init_data){
1831 .name = "gcc_qspi_ahb_clk",
1832 .ops = &clk_branch2_ops,
1837 static struct clk_branch gcc_qspi_ser_clk = {
1838 .halt_reg = 0x4d008,
1839 .halt_check = BRANCH_HALT,
1841 .enable_reg = 0x4d008,
1842 .enable_mask = BIT(0),
1843 .hw.init = &(struct clk_init_data){
1844 .name = "gcc_qspi_ser_clk",
1845 .parent_hws = (const struct clk_hw*[]) {
1846 &qspi_ser_clk_src.clkr.hw,
1849 .flags = CLK_SET_RATE_PARENT,
1850 .ops = &clk_branch2_ops,
1855 static struct clk_branch gcc_rx0_usb2_clkref_clk = {
1856 .halt_reg = 0x88018,
1857 .halt_check = BRANCH_HALT_VOTED,
1859 .enable_reg = 0x88018,
1860 .enable_mask = BIT(0),
1861 .hw.init = &(struct clk_init_data){
1862 .name = "gcc_rx0_usb2_clkref_clk",
1863 .ops = &clk_branch2_ops,
1868 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
1869 .halt_reg = 0x88014,
1870 .halt_check = BRANCH_HALT_VOTED,
1872 .enable_reg = 0x88014,
1873 .enable_mask = BIT(0),
1874 .hw.init = &(struct clk_init_data){
1875 .name = "gcc_rx1_usb2_clkref_clk",
1876 .ops = &clk_branch2_ops,
1881 static struct clk_branch gcc_sdcc1_ahb_clk = {
1882 .halt_reg = 0x16008,
1883 .halt_check = BRANCH_HALT,
1885 .enable_reg = 0x16008,
1886 .enable_mask = BIT(0),
1887 .hw.init = &(struct clk_init_data){
1888 .name = "gcc_sdcc1_ahb_clk",
1889 .ops = &clk_branch2_ops,
1894 static struct clk_branch gcc_sdcc1_apps_clk = {
1895 .halt_reg = 0x16004,
1896 .halt_check = BRANCH_HALT,
1898 .enable_reg = 0x16004,
1899 .enable_mask = BIT(0),
1900 .hw.init = &(struct clk_init_data){
1901 .name = "gcc_sdcc1_apps_clk",
1902 .parent_hws = (const struct clk_hw*[]) {
1903 &sdcc1_apps_clk_src.clkr.hw,
1906 .flags = CLK_SET_RATE_PARENT,
1907 .ops = &clk_branch2_ops,
1912 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1913 .halt_reg = 0x1600c,
1914 .halt_check = BRANCH_HALT,
1916 .enable_reg = 0x1600c,
1917 .enable_mask = BIT(0),
1918 .hw.init = &(struct clk_init_data){
1919 .name = "gcc_sdcc1_ice_core_clk",
1920 .parent_hws = (const struct clk_hw*[]) {
1921 &sdcc1_ice_core_clk_src.clkr.hw,
1924 .flags = CLK_SET_RATE_PARENT,
1925 .ops = &clk_branch2_ops,
1930 static struct clk_branch gcc_sdcc2_ahb_clk = {
1931 .halt_reg = 0x14008,
1932 .halt_check = BRANCH_HALT,
1934 .enable_reg = 0x14008,
1935 .enable_mask = BIT(0),
1936 .hw.init = &(struct clk_init_data){
1937 .name = "gcc_sdcc2_ahb_clk",
1938 .ops = &clk_branch2_ops,
1943 static struct clk_branch gcc_sdcc2_apps_clk = {
1944 .halt_reg = 0x14004,
1945 .halt_check = BRANCH_HALT,
1947 .enable_reg = 0x14004,
1948 .enable_mask = BIT(0),
1949 .hw.init = &(struct clk_init_data){
1950 .name = "gcc_sdcc2_apps_clk",
1951 .parent_hws = (const struct clk_hw*[]) {
1952 &sdcc2_apps_clk_src.clkr.hw,
1955 .flags = CLK_SET_RATE_PARENT,
1956 .ops = &clk_branch2_ops,
1961 static struct clk_branch gcc_ufs_ahb_clk = {
1962 .halt_reg = 0x7500c,
1963 .halt_check = BRANCH_HALT,
1965 .enable_reg = 0x7500c,
1966 .enable_mask = BIT(0),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "gcc_ufs_ahb_clk",
1969 .ops = &clk_branch2_ops,
1974 static struct clk_branch gcc_ufs_axi_clk = {
1975 .halt_reg = 0x75008,
1976 .halt_check = BRANCH_HALT,
1978 .enable_reg = 0x75008,
1979 .enable_mask = BIT(0),
1980 .hw.init = &(struct clk_init_data){
1981 .name = "gcc_ufs_axi_clk",
1982 .parent_hws = (const struct clk_hw*[]) {
1983 &ufs_axi_clk_src.clkr.hw,
1986 .flags = CLK_SET_RATE_PARENT,
1987 .ops = &clk_branch2_ops,
1992 static struct clk_branch gcc_ufs_clkref_clk = {
1993 .halt_reg = 0x88008,
1994 .halt_check = BRANCH_HALT,
1996 .enable_reg = 0x88008,
1997 .enable_mask = BIT(0),
1998 .hw.init = &(struct clk_init_data){
1999 .name = "gcc_ufs_clkref_clk",
2000 .ops = &clk_branch2_ops,
2005 static struct clk_branch gcc_ufs_ice_core_clk = {
2006 .halt_reg = 0x7600c,
2007 .halt_check = BRANCH_HALT,
2009 .enable_reg = 0x7600c,
2010 .enable_mask = BIT(0),
2011 .hw.init = &(struct clk_init_data){
2012 .name = "gcc_ufs_ice_core_clk",
2013 .parent_hws = (const struct clk_hw*[]) {
2014 &ufs_ice_core_clk_src.clkr.hw,
2017 .flags = CLK_SET_RATE_PARENT,
2018 .ops = &clk_branch2_ops,
2023 static struct clk_branch gcc_ufs_phy_aux_clk = {
2024 .halt_reg = 0x76040,
2025 .halt_check = BRANCH_HALT,
2027 .enable_reg = 0x76040,
2028 .enable_mask = BIT(0),
2029 .hw.init = &(struct clk_init_data){
2030 .name = "gcc_ufs_phy_aux_clk",
2031 .parent_hws = (const struct clk_hw*[]) {
2032 &ufs_phy_aux_clk_src.clkr.hw,
2035 .flags = CLK_SET_RATE_PARENT,
2036 .ops = &clk_branch2_ops,
2041 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2042 .halt_reg = 0x75014,
2043 .halt_check = BRANCH_HALT_SKIP,
2045 .enable_reg = 0x75014,
2046 .enable_mask = BIT(0),
2047 .hw.init = &(struct clk_init_data){
2048 .name = "gcc_ufs_rx_symbol_0_clk",
2049 .ops = &clk_branch2_ops,
2054 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2055 .halt_reg = 0x7605c,
2056 .halt_check = BRANCH_HALT_SKIP,
2058 .enable_reg = 0x7605c,
2059 .enable_mask = BIT(0),
2060 .hw.init = &(struct clk_init_data){
2061 .name = "gcc_ufs_rx_symbol_1_clk",
2062 .ops = &clk_branch2_ops,
2067 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2068 .halt_reg = 0x75010,
2069 .halt_check = BRANCH_HALT_SKIP,
2071 .enable_reg = 0x75010,
2072 .enable_mask = BIT(0),
2073 .hw.init = &(struct clk_init_data){
2074 .name = "gcc_ufs_tx_symbol_0_clk",
2075 .ops = &clk_branch2_ops,
2080 static struct clk_branch gcc_ufs_unipro_core_clk = {
2081 .halt_reg = 0x76008,
2082 .halt_check = BRANCH_HALT,
2084 .enable_reg = 0x76008,
2085 .enable_mask = BIT(0),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "gcc_ufs_unipro_core_clk",
2088 .parent_hws = (const struct clk_hw*[]) {
2089 &ufs_unipro_core_clk_src.clkr.hw,
2091 .flags = CLK_SET_RATE_PARENT,
2093 .ops = &clk_branch2_ops,
2098 static struct clk_branch gcc_usb20_master_clk = {
2099 .halt_reg = 0x2f004,
2100 .halt_check = BRANCH_HALT,
2102 .enable_reg = 0x2f004,
2103 .enable_mask = BIT(0),
2104 .hw.init = &(struct clk_init_data){
2105 .name = "gcc_usb20_master_clk",
2106 .parent_hws = (const struct clk_hw*[]) {
2107 &usb20_master_clk_src.clkr.hw,
2109 .flags = CLK_SET_RATE_PARENT,
2111 .ops = &clk_branch2_ops,
2116 static struct clk_branch gcc_usb20_mock_utmi_clk = {
2117 .halt_reg = 0x2f00c,
2118 .halt_check = BRANCH_HALT,
2120 .enable_reg = 0x2f00c,
2121 .enable_mask = BIT(0),
2122 .hw.init = &(struct clk_init_data){
2123 .name = "gcc_usb20_mock_utmi_clk",
2124 .parent_hws = (const struct clk_hw*[]) {
2125 &usb20_mock_utmi_clk_src.clkr.hw,
2128 .flags = CLK_SET_RATE_PARENT,
2129 .ops = &clk_branch2_ops,
2134 static struct clk_branch gcc_usb20_sleep_clk = {
2135 .halt_reg = 0x2f008,
2136 .halt_check = BRANCH_HALT,
2138 .enable_reg = 0x2f008,
2139 .enable_mask = BIT(0),
2140 .hw.init = &(struct clk_init_data){
2141 .name = "gcc_usb20_sleep_clk",
2142 .ops = &clk_branch2_ops,
2147 static struct clk_branch gcc_usb30_master_clk = {
2149 .halt_check = BRANCH_HALT,
2151 .enable_reg = 0xf008,
2152 .enable_mask = BIT(0),
2153 .hw.init = &(struct clk_init_data){
2154 .name = "gcc_usb30_master_clk",
2155 .parent_hws = (const struct clk_hw*[]) {
2156 &usb30_master_clk_src.clkr.hw,
2159 .flags = CLK_SET_RATE_PARENT,
2160 .ops = &clk_branch2_ops,
2165 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2167 .halt_check = BRANCH_HALT,
2169 .enable_reg = 0xf010,
2170 .enable_mask = BIT(0),
2171 .hw.init = &(struct clk_init_data){
2172 .name = "gcc_usb30_mock_utmi_clk",
2173 .parent_hws = (const struct clk_hw*[]) {
2174 &usb30_mock_utmi_clk_src.clkr.hw,
2177 .flags = CLK_SET_RATE_PARENT,
2178 .ops = &clk_branch2_ops,
2183 static struct clk_branch gcc_usb30_sleep_clk = {
2185 .halt_check = BRANCH_HALT,
2187 .enable_reg = 0xf00c,
2188 .enable_mask = BIT(0),
2189 .hw.init = &(struct clk_init_data){
2190 .name = "gcc_usb30_sleep_clk",
2191 .ops = &clk_branch2_ops,
2196 static struct clk_branch gcc_usb3_clkref_clk = {
2197 .halt_reg = 0x8800c,
2198 .halt_check = BRANCH_HALT,
2200 .enable_reg = 0x8800c,
2201 .enable_mask = BIT(0),
2202 .hw.init = &(struct clk_init_data){
2203 .name = "gcc_usb3_clkref_clk",
2204 .ops = &clk_branch2_ops,
2209 static struct clk_branch gcc_usb3_phy_aux_clk = {
2210 .halt_reg = 0x50000,
2211 .halt_check = BRANCH_HALT,
2213 .enable_reg = 0x50000,
2214 .enable_mask = BIT(0),
2215 .hw.init = &(struct clk_init_data){
2216 .name = "gcc_usb3_phy_aux_clk",
2217 .parent_hws = (const struct clk_hw*[]) {
2218 &usb3_phy_aux_clk_src.clkr.hw,
2221 .flags = CLK_SET_RATE_PARENT,
2222 .ops = &clk_branch2_ops,
2227 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2228 .halt_reg = 0x50004,
2229 .halt_check = BRANCH_HALT_DELAY,
2231 .enable_reg = 0x50004,
2232 .enable_mask = BIT(0),
2233 .hw.init = &(struct clk_init_data){
2234 .name = "gcc_usb3_phy_pipe_clk",
2235 .ops = &clk_branch2_ops,
2240 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2241 .halt_reg = 0x6a004,
2242 .halt_check = BRANCH_HALT,
2244 .enable_reg = 0x6a004,
2245 .enable_mask = BIT(0),
2246 .hw.init = &(struct clk_init_data){
2247 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2248 .ops = &clk_branch2_ops,
2253 static struct gdsc ufs_gdsc = {
2259 .pwrsts = PWRSTS_OFF_ON,
2263 static struct gdsc usb_30_gdsc = {
2267 .name = "usb_30_gdsc",
2269 .pwrsts = PWRSTS_OFF_ON,
2273 static struct gdsc pcie_0_gdsc = {
2277 .name = "pcie_0_gdsc",
2279 .pwrsts = PWRSTS_OFF_ON,
2283 static struct clk_hw *gcc_sdm660_hws[] = {
2285 &gpll0_early_div.hw,
2286 &gpll1_early_div.hw,
2289 static struct clk_regmap *gcc_sdm660_clocks[] = {
2290 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2291 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2292 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2293 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2294 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2295 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2296 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2297 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2298 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2299 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2300 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2301 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2302 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2303 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2304 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2305 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2306 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2307 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2308 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2309 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2310 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
2311 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
2312 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2313 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
2314 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
2315 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2316 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2317 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2318 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2319 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2320 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2321 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2322 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2323 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2324 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2325 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2326 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2327 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2328 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2329 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2330 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2331 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2332 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2333 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2334 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2335 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2336 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2337 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2338 [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr,
2339 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
2340 [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
2341 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2342 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2343 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2344 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
2345 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2346 [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
2347 [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
2348 [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
2349 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
2350 [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
2351 [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
2352 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2353 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
2354 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2355 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
2356 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2357 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
2358 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2359 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2360 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2361 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
2362 [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
2363 [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr,
2364 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
2365 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2366 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2367 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2368 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2369 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2370 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2371 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2372 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
2373 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
2374 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
2375 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2376 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2377 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2378 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
2379 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
2380 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
2381 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
2382 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2383 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2384 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2385 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
2386 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2387 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2388 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2389 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2390 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2391 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2392 [GPLL0] = &gpll0.clkr,
2393 [GPLL0_EARLY] = &gpll0_early.clkr,
2394 [GPLL1] = &gpll1.clkr,
2395 [GPLL1_EARLY] = &gpll1_early.clkr,
2396 [GPLL4] = &gpll4.clkr,
2397 [GPLL4_EARLY] = &gpll4_early.clkr,
2398 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
2399 [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr,
2400 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
2401 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2402 [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
2403 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2404 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
2405 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2406 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2407 [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
2408 [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr,
2409 [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
2410 [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
2411 [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
2412 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2413 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2414 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2417 static struct gdsc *gcc_sdm660_gdscs[] = {
2418 [UFS_GDSC] = &ufs_gdsc,
2419 [USB_30_GDSC] = &usb_30_gdsc,
2420 [PCIE_0_GDSC] = &pcie_0_gdsc,
2423 static const struct qcom_reset_map gcc_sdm660_resets[] = {
2424 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
2425 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
2426 [GCC_UFS_BCR] = { 0x75000 },
2427 [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
2428 [GCC_USB3_PHY_BCR] = { 0x50020 },
2429 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
2430 [GCC_USB_20_BCR] = { 0x2f000 },
2431 [GCC_USB_30_BCR] = { 0xf000 },
2432 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2433 [GCC_MSS_RESTART] = { 0x79000 },
2436 static const struct regmap_config gcc_sdm660_regmap_config = {
2440 .max_register = 0x94000,
2444 static const struct qcom_cc_desc gcc_sdm660_desc = {
2445 .config = &gcc_sdm660_regmap_config,
2446 .clks = gcc_sdm660_clocks,
2447 .num_clks = ARRAY_SIZE(gcc_sdm660_clocks),
2448 .resets = gcc_sdm660_resets,
2449 .num_resets = ARRAY_SIZE(gcc_sdm660_resets),
2450 .gdscs = gcc_sdm660_gdscs,
2451 .num_gdscs = ARRAY_SIZE(gcc_sdm660_gdscs),
2452 .clk_hws = gcc_sdm660_hws,
2453 .num_clk_hws = ARRAY_SIZE(gcc_sdm660_hws),
2456 static const struct of_device_id gcc_sdm660_match_table[] = {
2457 { .compatible = "qcom,gcc-sdm630" },
2458 { .compatible = "qcom,gcc-sdm660" },
2461 MODULE_DEVICE_TABLE(of, gcc_sdm660_match_table);
2463 static int gcc_sdm660_probe(struct platform_device *pdev)
2466 struct regmap *regmap;
2468 regmap = qcom_cc_map(pdev, &gcc_sdm660_desc);
2470 return PTR_ERR(regmap);
2473 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
2474 * turned off by hardware during certain apps low power modes.
2476 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
2480 return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap);
2483 static struct platform_driver gcc_sdm660_driver = {
2484 .probe = gcc_sdm660_probe,
2486 .name = "gcc-sdm660",
2487 .of_match_table = gcc_sdm660_match_table,
2491 static int __init gcc_sdm660_init(void)
2493 return platform_driver_register(&gcc_sdm660_driver);
2495 core_initcall_sync(gcc_sdm660_init);
2497 static void __exit gcc_sdm660_exit(void)
2499 platform_driver_unregister(&gcc_sdm660_driver);
2501 module_exit(gcc_sdm660_exit);
2503 MODULE_LICENSE("GPL v2");
2504 MODULE_DESCRIPTION("QCOM GCC sdm660 Driver");