1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/regmap.h>
14 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
19 #include "clk-regmap.h"
35 static struct clk_alpha_pll gpll0 = {
37 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
39 .enable_reg = 0x52010,
40 .enable_mask = BIT(0),
41 .hw.init = &(struct clk_init_data){
43 .parent_data = &(const struct clk_parent_data){
48 .ops = &clk_alpha_pll_fixed_fabia_ops,
53 static const struct clk_div_table post_div_table_gpll0_out_even[] = {
58 static struct clk_alpha_pll_postdiv gpll0_out_even = {
61 .post_div_table = post_div_table_gpll0_out_even,
62 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
64 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
65 .clkr.hw.init = &(struct clk_init_data){
66 .name = "gpll0_out_even",
67 .parent_hws = (const struct clk_hw*[]){
71 .ops = &clk_alpha_pll_postdiv_fabia_ops,
75 static struct clk_fixed_factor gcc_pll0_main_div_cdiv = {
78 .hw.init = &(struct clk_init_data){
79 .name = "gcc_pll0_main_div_cdiv",
80 .parent_hws = (const struct clk_hw*[]){
84 .ops = &clk_fixed_factor_ops,
88 static struct clk_alpha_pll gpll1 = {
90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
92 .enable_reg = 0x52010,
93 .enable_mask = BIT(1),
94 .hw.init = &(struct clk_init_data){
96 .parent_data = &(const struct clk_parent_data){
101 .ops = &clk_alpha_pll_fixed_fabia_ops,
106 static struct clk_alpha_pll gpll4 = {
108 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
110 .enable_reg = 0x52010,
111 .enable_mask = BIT(4),
112 .hw.init = &(struct clk_init_data){
114 .parent_data = &(const struct clk_parent_data){
115 .fw_name = "bi_tcxo",
119 .ops = &clk_alpha_pll_fixed_fabia_ops,
124 static struct clk_alpha_pll gpll6 = {
126 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
128 .enable_reg = 0x52010,
129 .enable_mask = BIT(6),
130 .hw.init = &(struct clk_init_data){
132 .parent_data = &(const struct clk_parent_data){
133 .fw_name = "bi_tcxo",
137 .ops = &clk_alpha_pll_fixed_fabia_ops,
142 static struct clk_alpha_pll gpll7 = {
144 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
146 .enable_reg = 0x52010,
147 .enable_mask = BIT(7),
148 .hw.init = &(struct clk_init_data){
150 .parent_data = &(const struct clk_parent_data){
151 .fw_name = "bi_tcxo",
155 .ops = &clk_alpha_pll_fixed_fabia_ops,
160 static const struct parent_map gcc_parent_map_0[] = {
162 { P_GPLL0_OUT_MAIN, 1 },
163 { P_GPLL0_OUT_EVEN, 6 },
166 static const struct clk_parent_data gcc_parent_data_0[] = {
167 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
168 { .hw = &gpll0.clkr.hw },
169 { .hw = &gpll0_out_even.clkr.hw },
172 static const struct clk_parent_data gcc_parent_data_0_ao[] = {
173 { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
174 { .hw = &gpll0.clkr.hw },
175 { .hw = &gpll0_out_even.clkr.hw },
178 static const struct parent_map gcc_parent_map_1[] = {
180 { P_GPLL0_OUT_MAIN, 1 },
181 { P_GPLL6_OUT_MAIN, 2 },
182 { P_GPLL0_OUT_EVEN, 6 },
185 static const struct clk_parent_data gcc_parent_data_1[] = {
186 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
187 { .hw = &gpll0.clkr.hw },
188 { .hw = &gpll6.clkr.hw },
189 { .hw = &gpll0_out_even.clkr.hw },
192 static const struct parent_map gcc_parent_map_2[] = {
194 { P_GPLL0_OUT_MAIN, 1 },
195 { P_GPLL1_OUT_MAIN, 4 },
196 { P_GPLL4_OUT_MAIN, 5 },
197 { P_GPLL0_OUT_EVEN, 6 },
200 static const struct clk_parent_data gcc_parent_data_2[] = {
201 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
202 { .hw = &gpll0.clkr.hw },
203 { .hw = &gpll1.clkr.hw },
204 { .hw = &gpll4.clkr.hw },
205 { .hw = &gpll0_out_even.clkr.hw },
208 static const struct parent_map gcc_parent_map_3[] = {
210 { P_GPLL0_OUT_MAIN, 1 },
213 static const struct clk_parent_data gcc_parent_data_3[] = {
214 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
215 { .hw = &gpll0.clkr.hw },
218 static const struct parent_map gcc_parent_map_4[] = {
220 { P_GPLL0_OUT_MAIN, 1 },
222 { P_GPLL0_OUT_EVEN, 6 },
225 static const struct clk_parent_data gcc_parent_data_4[] = {
226 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
227 { .hw = &gpll0.clkr.hw },
228 { .fw_name = "sleep_clk", .name = "sleep_clk" },
229 { .hw = &gpll0_out_even.clkr.hw },
232 static const struct parent_map gcc_parent_map_5[] = {
234 { P_GPLL0_OUT_MAIN, 1 },
235 { P_GPLL7_OUT_MAIN, 3 },
236 { P_GPLL0_OUT_EVEN, 6 },
239 static const struct clk_parent_data gcc_parent_data_5[] = {
240 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
241 { .hw = &gpll0.clkr.hw },
242 { .hw = &gpll7.clkr.hw },
243 { .hw = &gpll0_out_even.clkr.hw },
246 static const struct parent_map gcc_parent_map_6[] = {
248 { P_GPLL0_OUT_MAIN, 1 },
252 static const struct clk_parent_data gcc_parent_data_6[] = {
253 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
254 { .hw = &gpll0.clkr.hw },
255 { .fw_name = "sleep_clk", .name = "sleep_clk" },
258 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
259 F(19200000, P_BI_TCXO, 1, 0, 0),
263 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
267 .parent_map = gcc_parent_map_0,
268 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
269 .clkr.hw.init = &(struct clk_init_data){
270 .name = "gcc_cpuss_ahb_clk_src",
271 .parent_data = gcc_parent_data_0_ao,
272 .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
273 .flags = CLK_SET_RATE_PARENT,
274 .ops = &clk_rcg2_ops,
278 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
279 F(19200000, P_BI_TCXO, 1, 0, 0),
280 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
281 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
282 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
283 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
287 static struct clk_rcg2 gcc_gp1_clk_src = {
291 .parent_map = gcc_parent_map_4,
292 .freq_tbl = ftbl_gcc_gp1_clk_src,
293 .clkr.hw.init = &(struct clk_init_data){
294 .name = "gcc_gp1_clk_src",
295 .parent_data = gcc_parent_data_4,
296 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
297 .ops = &clk_rcg2_ops,
301 static struct clk_rcg2 gcc_gp2_clk_src = {
305 .parent_map = gcc_parent_map_4,
306 .freq_tbl = ftbl_gcc_gp1_clk_src,
307 .clkr.hw.init = &(struct clk_init_data){
308 .name = "gcc_gp2_clk_src",
309 .parent_data = gcc_parent_data_4,
310 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
311 .ops = &clk_rcg2_ops,
315 static struct clk_rcg2 gcc_gp3_clk_src = {
319 .parent_map = gcc_parent_map_4,
320 .freq_tbl = ftbl_gcc_gp1_clk_src,
321 .clkr.hw.init = &(struct clk_init_data){
322 .name = "gcc_gp3_clk_src",
323 .parent_data = gcc_parent_data_4,
324 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
325 .ops = &clk_rcg2_ops,
329 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
330 F(19200000, P_BI_TCXO, 1, 0, 0),
331 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
335 static struct clk_rcg2 gcc_pdm2_clk_src = {
339 .parent_map = gcc_parent_map_0,
340 .freq_tbl = ftbl_gcc_pdm2_clk_src,
341 .clkr.hw.init = &(struct clk_init_data){
342 .name = "gcc_pdm2_clk_src",
343 .parent_data = gcc_parent_data_0,
344 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
345 .ops = &clk_rcg2_ops,
349 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
350 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
351 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
352 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
356 static struct clk_rcg2 gcc_qspi_core_clk_src = {
360 .parent_map = gcc_parent_map_2,
361 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
362 .clkr.hw.init = &(struct clk_init_data){
363 .name = "gcc_qspi_core_clk_src",
364 .parent_data = gcc_parent_data_2,
365 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
366 .ops = &clk_rcg2_ops,
370 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
371 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
372 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
373 F(19200000, P_BI_TCXO, 1, 0, 0),
374 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
375 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
376 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
377 F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
378 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
379 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
380 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
381 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
382 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
383 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
384 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
385 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
386 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
387 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
391 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
392 .name = "gcc_qupv3_wrap0_s0_clk_src",
393 .parent_data = gcc_parent_data_1,
394 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
395 .ops = &clk_rcg2_ops,
398 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
402 .parent_map = gcc_parent_map_1,
403 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
404 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
407 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
408 .name = "gcc_qupv3_wrap0_s1_clk_src",
409 .parent_data = gcc_parent_data_1,
410 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
411 .ops = &clk_rcg2_ops,
414 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
418 .parent_map = gcc_parent_map_1,
419 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
420 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
423 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
424 .name = "gcc_qupv3_wrap0_s2_clk_src",
425 .parent_data = gcc_parent_data_1,
426 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
427 .ops = &clk_rcg2_ops,
430 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
434 .parent_map = gcc_parent_map_1,
435 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
436 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
439 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
440 .name = "gcc_qupv3_wrap0_s3_clk_src",
441 .parent_data = gcc_parent_data_1,
442 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
443 .ops = &clk_rcg2_ops,
446 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
450 .parent_map = gcc_parent_map_1,
451 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
452 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
455 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
456 .name = "gcc_qupv3_wrap0_s4_clk_src",
457 .parent_data = gcc_parent_data_1,
458 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
459 .ops = &clk_rcg2_ops,
462 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
466 .parent_map = gcc_parent_map_1,
467 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
468 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
471 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
472 .name = "gcc_qupv3_wrap0_s5_clk_src",
473 .parent_data = gcc_parent_data_1,
474 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
475 .ops = &clk_rcg2_ops,
478 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
482 .parent_map = gcc_parent_map_1,
483 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
484 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
487 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
488 .name = "gcc_qupv3_wrap1_s0_clk_src",
489 .parent_data = gcc_parent_data_1,
490 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
491 .ops = &clk_rcg2_ops,
494 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
498 .parent_map = gcc_parent_map_1,
499 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
500 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
503 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
504 .name = "gcc_qupv3_wrap1_s1_clk_src",
505 .parent_data = gcc_parent_data_1,
506 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
507 .ops = &clk_rcg2_ops,
510 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
514 .parent_map = gcc_parent_map_1,
515 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
516 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
519 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
520 .name = "gcc_qupv3_wrap1_s2_clk_src",
521 .parent_data = gcc_parent_data_1,
522 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
523 .ops = &clk_rcg2_ops,
526 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
530 .parent_map = gcc_parent_map_1,
531 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
532 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
535 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
536 .name = "gcc_qupv3_wrap1_s3_clk_src",
537 .parent_data = gcc_parent_data_1,
538 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
539 .ops = &clk_rcg2_ops,
542 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
546 .parent_map = gcc_parent_map_1,
547 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
548 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
551 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
552 .name = "gcc_qupv3_wrap1_s4_clk_src",
553 .parent_data = gcc_parent_data_1,
554 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
555 .ops = &clk_rcg2_ops,
558 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
562 .parent_map = gcc_parent_map_1,
563 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
564 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
567 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
568 .name = "gcc_qupv3_wrap1_s5_clk_src",
569 .parent_data = gcc_parent_data_1,
570 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
571 .ops = &clk_rcg2_ops,
574 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
578 .parent_map = gcc_parent_map_1,
579 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
580 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
584 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
585 F(144000, P_BI_TCXO, 16, 3, 25),
586 F(400000, P_BI_TCXO, 12, 1, 4),
587 F(19200000, P_BI_TCXO, 1, 0, 0),
588 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
589 F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
590 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
591 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
592 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
593 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
597 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
601 .parent_map = gcc_parent_map_1,
602 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
603 .clkr.hw.init = &(struct clk_init_data){
604 .name = "gcc_sdcc1_apps_clk_src",
605 .parent_data = gcc_parent_data_1,
606 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
607 .ops = &clk_rcg2_floor_ops,
611 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
612 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
613 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
614 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
615 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
619 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
623 .parent_map = gcc_parent_map_0,
624 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
625 .clkr.hw.init = &(struct clk_init_data){
626 .name = "gcc_sdcc1_ice_core_clk_src",
627 .parent_data = gcc_parent_data_0,
628 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
629 .ops = &clk_rcg2_ops,
633 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
634 F(400000, P_BI_TCXO, 12, 1, 4),
635 F(9600000, P_BI_TCXO, 2, 0, 0),
636 F(19200000, P_BI_TCXO, 1, 0, 0),
637 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
638 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
639 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
640 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
644 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
648 .parent_map = gcc_parent_map_5,
649 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
650 .clkr.hw.init = &(struct clk_init_data){
651 .name = "gcc_sdcc2_apps_clk_src",
652 .parent_data = gcc_parent_data_5,
653 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
654 .ops = &clk_rcg2_floor_ops,
658 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
659 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
660 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
661 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
662 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
663 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
667 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
671 .parent_map = gcc_parent_map_0,
672 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
673 .clkr.hw.init = &(struct clk_init_data){
674 .name = "gcc_ufs_phy_axi_clk_src",
675 .parent_data = gcc_parent_data_0,
676 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
677 .ops = &clk_rcg2_ops,
681 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
682 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
683 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
684 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
685 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
689 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
693 .parent_map = gcc_parent_map_0,
694 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
695 .clkr.hw.init = &(struct clk_init_data){
696 .name = "gcc_ufs_phy_ice_core_clk_src",
697 .parent_data = gcc_parent_data_0,
698 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
699 .ops = &clk_rcg2_ops,
703 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
704 F(9600000, P_BI_TCXO, 2, 0, 0),
705 F(19200000, P_BI_TCXO, 1, 0, 0),
709 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
713 .parent_map = gcc_parent_map_3,
714 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
715 .clkr.hw.init = &(struct clk_init_data){
716 .name = "gcc_ufs_phy_phy_aux_clk_src",
717 .parent_data = gcc_parent_data_3,
718 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
719 .ops = &clk_rcg2_ops,
723 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
724 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
725 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
726 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
730 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
734 .parent_map = gcc_parent_map_0,
735 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
736 .clkr.hw.init = &(struct clk_init_data){
737 .name = "gcc_ufs_phy_unipro_core_clk_src",
738 .parent_data = gcc_parent_data_0,
739 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
740 .ops = &clk_rcg2_ops,
744 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
745 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
746 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
747 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
748 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
752 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
756 .parent_map = gcc_parent_map_0,
757 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
758 .clkr.hw.init = &(struct clk_init_data){
759 .name = "gcc_usb30_prim_master_clk_src",
760 .parent_data = gcc_parent_data_0,
761 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
762 .ops = &clk_rcg2_ops,
766 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
767 F(19200000, P_BI_TCXO, 1, 0, 0),
768 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
772 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
776 .parent_map = gcc_parent_map_0,
777 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
778 .clkr.hw.init = &(struct clk_init_data){
779 .name = "gcc_usb30_prim_mock_utmi_clk_src",
780 .parent_data = gcc_parent_data_0,
781 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
782 .ops = &clk_rcg2_ops,
786 static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
787 F(19200000, P_BI_TCXO, 1, 0, 0),
791 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
795 .parent_map = gcc_parent_map_6,
796 .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
797 .clkr.hw.init = &(struct clk_init_data){
798 .name = "gcc_usb3_prim_phy_aux_clk_src",
799 .parent_data = gcc_parent_data_6,
800 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
801 .ops = &clk_rcg2_ops,
805 static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
806 F(4800000, P_BI_TCXO, 4, 0, 0),
807 F(19200000, P_BI_TCXO, 1, 0, 0),
811 static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
815 .parent_map = gcc_parent_map_3,
816 .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
817 .clkr.hw.init = &(struct clk_init_data){
818 .name = "gcc_sec_ctrl_clk_src",
819 .parent_data = gcc_parent_data_3,
820 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
821 .ops = &clk_rcg2_ops,
825 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
827 .halt_check = BRANCH_HALT_DELAY,
831 .enable_reg = 0x82024,
832 .enable_mask = BIT(0),
833 .hw.init = &(struct clk_init_data){
834 .name = "gcc_aggre_ufs_phy_axi_clk",
835 .parent_hws = (const struct clk_hw*[]){
836 &gcc_ufs_phy_axi_clk_src.clkr.hw,
839 .flags = CLK_SET_RATE_PARENT,
840 .ops = &clk_branch2_ops,
845 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
847 .halt_check = BRANCH_HALT,
849 .enable_reg = 0x8201c,
850 .enable_mask = BIT(0),
851 .hw.init = &(struct clk_init_data){
852 .name = "gcc_aggre_usb3_prim_axi_clk",
853 .parent_hws = (const struct clk_hw*[]){
854 &gcc_usb30_prim_master_clk_src.clkr.hw,
857 .flags = CLK_SET_RATE_PARENT,
858 .ops = &clk_branch2_ops,
863 static struct clk_branch gcc_boot_rom_ahb_clk = {
865 .halt_check = BRANCH_HALT_VOTED,
869 .enable_reg = 0x52000,
870 .enable_mask = BIT(10),
871 .hw.init = &(struct clk_init_data){
872 .name = "gcc_boot_rom_ahb_clk",
873 .ops = &clk_branch2_ops,
878 static struct clk_branch gcc_camera_hf_axi_clk = {
880 .halt_check = BRANCH_HALT,
882 .enable_reg = 0xb020,
883 .enable_mask = BIT(0),
884 .hw.init = &(struct clk_init_data){
885 .name = "gcc_camera_hf_axi_clk",
886 .ops = &clk_branch2_ops,
891 static struct clk_branch gcc_camera_throttle_hf_axi_clk = {
893 .halt_check = BRANCH_HALT,
897 .enable_reg = 0xb080,
898 .enable_mask = BIT(0),
899 .hw.init = &(struct clk_init_data){
900 .name = "gcc_camera_throttle_hf_axi_clk",
901 .ops = &clk_branch2_ops,
906 static struct clk_branch gcc_ce1_ahb_clk = {
908 .halt_check = BRANCH_HALT_VOTED,
912 .enable_reg = 0x52000,
913 .enable_mask = BIT(3),
914 .hw.init = &(struct clk_init_data){
915 .name = "gcc_ce1_ahb_clk",
916 .ops = &clk_branch2_ops,
921 static struct clk_branch gcc_ce1_axi_clk = {
923 .halt_check = BRANCH_HALT_VOTED,
925 .enable_reg = 0x52000,
926 .enable_mask = BIT(4),
927 .hw.init = &(struct clk_init_data){
928 .name = "gcc_ce1_axi_clk",
929 .ops = &clk_branch2_ops,
934 static struct clk_branch gcc_ce1_clk = {
936 .halt_check = BRANCH_HALT_VOTED,
938 .enable_reg = 0x52000,
939 .enable_mask = BIT(5),
940 .hw.init = &(struct clk_init_data){
941 .name = "gcc_ce1_clk",
942 .ops = &clk_branch2_ops,
947 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
949 .halt_check = BRANCH_HALT,
951 .enable_reg = 0x502c,
952 .enable_mask = BIT(0),
953 .hw.init = &(struct clk_init_data){
954 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
955 .parent_hws = (const struct clk_hw*[]){
956 &gcc_usb30_prim_master_clk_src.clkr.hw,
959 .flags = CLK_SET_RATE_PARENT,
960 .ops = &clk_branch2_ops,
965 /* For CPUSS functionality the AHB clock needs to be left enabled */
966 static struct clk_branch gcc_cpuss_ahb_clk = {
968 .halt_check = BRANCH_HALT_VOTED,
970 .enable_reg = 0x52000,
971 .enable_mask = BIT(21),
972 .hw.init = &(struct clk_init_data){
973 .name = "gcc_cpuss_ahb_clk",
974 .parent_hws = (const struct clk_hw*[]){
975 &gcc_cpuss_ahb_clk_src.clkr.hw,
978 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
979 .ops = &clk_branch2_ops,
984 static struct clk_branch gcc_cpuss_rbcpr_clk = {
986 .halt_check = BRANCH_HALT,
988 .enable_reg = 0x48008,
989 .enable_mask = BIT(0),
990 .hw.init = &(struct clk_init_data){
991 .name = "gcc_cpuss_rbcpr_clk",
992 .ops = &clk_branch2_ops,
997 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
999 .halt_check = BRANCH_VOTED,
1001 .enable_reg = 0x4452c,
1002 .enable_mask = BIT(0),
1003 .hw.init = &(struct clk_init_data){
1004 .name = "gcc_ddrss_gpu_axi_clk",
1005 .ops = &clk_branch2_ops,
1010 static struct clk_branch gcc_disp_gpll0_clk_src = {
1011 .halt_check = BRANCH_HALT_DELAY,
1013 .enable_reg = 0x52000,
1014 .enable_mask = BIT(18),
1015 .hw.init = &(struct clk_init_data){
1016 .name = "gcc_disp_gpll0_clk_src",
1017 .parent_hws = (const struct clk_hw*[]){
1021 .ops = &clk_branch2_aon_ops,
1026 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1027 .halt_check = BRANCH_HALT_DELAY,
1029 .enable_reg = 0x52000,
1030 .enable_mask = BIT(19),
1031 .hw.init = &(struct clk_init_data){
1032 .name = "gcc_disp_gpll0_div_clk_src",
1033 .parent_hws = (const struct clk_hw*[]){
1034 &gcc_pll0_main_div_cdiv.hw,
1037 .ops = &clk_branch2_ops,
1042 static struct clk_branch gcc_disp_hf_axi_clk = {
1044 .halt_check = BRANCH_HALT,
1046 .enable_reg = 0xb024,
1047 .enable_mask = BIT(0),
1048 .hw.init = &(struct clk_init_data){
1049 .name = "gcc_disp_hf_axi_clk",
1050 .ops = &clk_branch2_ops,
1055 static struct clk_branch gcc_disp_throttle_hf_axi_clk = {
1057 .halt_check = BRANCH_HALT,
1061 .enable_reg = 0xb084,
1062 .enable_mask = BIT(0),
1063 .hw.init = &(struct clk_init_data){
1064 .name = "gcc_disp_throttle_hf_axi_clk",
1065 .ops = &clk_branch2_ops,
1070 static struct clk_branch gcc_gp1_clk = {
1071 .halt_reg = 0x64000,
1072 .halt_check = BRANCH_HALT,
1074 .enable_reg = 0x64000,
1075 .enable_mask = BIT(0),
1076 .hw.init = &(struct clk_init_data){
1077 .name = "gcc_gp1_clk",
1078 .parent_hws = (const struct clk_hw*[]){
1079 &gcc_gp1_clk_src.clkr.hw,
1082 .flags = CLK_SET_RATE_PARENT,
1083 .ops = &clk_branch2_ops,
1088 static struct clk_branch gcc_gp2_clk = {
1089 .halt_reg = 0x65000,
1090 .halt_check = BRANCH_HALT,
1092 .enable_reg = 0x65000,
1093 .enable_mask = BIT(0),
1094 .hw.init = &(struct clk_init_data){
1095 .name = "gcc_gp2_clk",
1096 .parent_hws = (const struct clk_hw*[]){
1097 &gcc_gp2_clk_src.clkr.hw,
1100 .flags = CLK_SET_RATE_PARENT,
1101 .ops = &clk_branch2_ops,
1106 static struct clk_branch gcc_gp3_clk = {
1107 .halt_reg = 0x66000,
1108 .halt_check = BRANCH_HALT,
1110 .enable_reg = 0x66000,
1111 .enable_mask = BIT(0),
1112 .hw.init = &(struct clk_init_data){
1113 .name = "gcc_gp3_clk",
1114 .parent_hws = (const struct clk_hw*[]){
1115 &gcc_gp3_clk_src.clkr.hw,
1118 .flags = CLK_SET_RATE_PARENT,
1119 .ops = &clk_branch2_ops,
1124 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1125 .halt_check = BRANCH_HALT_DELAY,
1127 .enable_reg = 0x52000,
1128 .enable_mask = BIT(15),
1129 .hw.init = &(struct clk_init_data){
1130 .name = "gcc_gpu_gpll0_clk_src",
1131 .parent_hws = (const struct clk_hw*[]){
1135 .ops = &clk_branch2_ops,
1140 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1141 .halt_check = BRANCH_HALT_DELAY,
1143 .enable_reg = 0x52000,
1144 .enable_mask = BIT(16),
1145 .hw.init = &(struct clk_init_data){
1146 .name = "gcc_gpu_gpll0_div_clk_src",
1147 .parent_hws = (const struct clk_hw*[]){
1148 &gcc_pll0_main_div_cdiv.hw,
1151 .ops = &clk_branch2_ops,
1156 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1157 .halt_reg = 0x7100c,
1158 .halt_check = BRANCH_VOTED,
1160 .enable_reg = 0x7100c,
1161 .enable_mask = BIT(0),
1162 .hw.init = &(struct clk_init_data){
1163 .name = "gcc_gpu_memnoc_gfx_clk",
1164 .ops = &clk_branch2_ops,
1169 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1170 .halt_reg = 0x71018,
1171 .halt_check = BRANCH_HALT,
1173 .enable_reg = 0x71018,
1174 .enable_mask = BIT(0),
1175 .hw.init = &(struct clk_init_data){
1176 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1177 .ops = &clk_branch2_ops,
1182 static struct clk_branch gcc_npu_axi_clk = {
1183 .halt_reg = 0x4d008,
1184 .halt_check = BRANCH_HALT,
1186 .enable_reg = 0x4d008,
1187 .enable_mask = BIT(0),
1188 .hw.init = &(struct clk_init_data){
1189 .name = "gcc_npu_axi_clk",
1190 .ops = &clk_branch2_ops,
1195 static struct clk_branch gcc_npu_bwmon_axi_clk = {
1196 .halt_reg = 0x73008,
1197 .halt_check = BRANCH_HALT,
1199 .enable_reg = 0x73008,
1200 .enable_mask = BIT(0),
1201 .hw.init = &(struct clk_init_data){
1202 .name = "gcc_npu_bwmon_axi_clk",
1203 .ops = &clk_branch2_ops,
1208 static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
1209 .halt_reg = 0x73018,
1210 .halt_check = BRANCH_HALT,
1212 .enable_reg = 0x73018,
1213 .enable_mask = BIT(0),
1214 .hw.init = &(struct clk_init_data){
1215 .name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
1216 .ops = &clk_branch2_ops,
1221 static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
1222 .halt_reg = 0x7301c,
1223 .halt_check = BRANCH_HALT,
1225 .enable_reg = 0x7301c,
1226 .enable_mask = BIT(0),
1227 .hw.init = &(struct clk_init_data){
1228 .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
1229 .ops = &clk_branch2_ops,
1234 static struct clk_branch gcc_npu_cfg_ahb_clk = {
1235 .halt_reg = 0x4d004,
1236 .halt_check = BRANCH_HALT,
1237 .hwcg_reg = 0x4d004,
1240 .enable_reg = 0x4d004,
1241 .enable_mask = BIT(0),
1242 .hw.init = &(struct clk_init_data){
1243 .name = "gcc_npu_cfg_ahb_clk",
1244 .ops = &clk_branch2_ops,
1249 static struct clk_branch gcc_npu_dma_clk = {
1250 .halt_reg = 0x4d1a0,
1251 .halt_check = BRANCH_HALT,
1252 .hwcg_reg = 0x4d1a0,
1255 .enable_reg = 0x4d1a0,
1256 .enable_mask = BIT(0),
1257 .hw.init = &(struct clk_init_data){
1258 .name = "gcc_npu_dma_clk",
1259 .ops = &clk_branch2_ops,
1264 static struct clk_branch gcc_npu_gpll0_clk_src = {
1265 .halt_check = BRANCH_HALT_DELAY,
1267 .enable_reg = 0x52000,
1268 .enable_mask = BIT(25),
1269 .hw.init = &(struct clk_init_data){
1270 .name = "gcc_npu_gpll0_clk_src",
1271 .parent_hws = (const struct clk_hw*[]){
1275 .ops = &clk_branch2_ops,
1280 static struct clk_branch gcc_npu_gpll0_div_clk_src = {
1281 .halt_check = BRANCH_HALT_DELAY,
1283 .enable_reg = 0x52000,
1284 .enable_mask = BIT(26),
1285 .hw.init = &(struct clk_init_data){
1286 .name = "gcc_npu_gpll0_div_clk_src",
1287 .parent_hws = (const struct clk_hw*[]){
1288 &gcc_pll0_main_div_cdiv.hw,
1291 .flags = CLK_SET_RATE_PARENT,
1292 .ops = &clk_branch2_ops,
1297 static struct clk_branch gcc_pdm2_clk = {
1298 .halt_reg = 0x3300c,
1299 .halt_check = BRANCH_HALT,
1301 .enable_reg = 0x3300c,
1302 .enable_mask = BIT(0),
1303 .hw.init = &(struct clk_init_data){
1304 .name = "gcc_pdm2_clk",
1305 .parent_hws = (const struct clk_hw*[]){
1306 &gcc_pdm2_clk_src.clkr.hw,
1309 .flags = CLK_SET_RATE_PARENT,
1310 .ops = &clk_branch2_ops,
1315 static struct clk_branch gcc_pdm_ahb_clk = {
1316 .halt_reg = 0x33004,
1317 .halt_check = BRANCH_HALT,
1318 .hwcg_reg = 0x33004,
1321 .enable_reg = 0x33004,
1322 .enable_mask = BIT(0),
1323 .hw.init = &(struct clk_init_data){
1324 .name = "gcc_pdm_ahb_clk",
1325 .ops = &clk_branch2_ops,
1330 static struct clk_branch gcc_pdm_xo4_clk = {
1331 .halt_reg = 0x33008,
1332 .halt_check = BRANCH_HALT,
1334 .enable_reg = 0x33008,
1335 .enable_mask = BIT(0),
1336 .hw.init = &(struct clk_init_data){
1337 .name = "gcc_pdm_xo4_clk",
1338 .ops = &clk_branch2_ops,
1343 static struct clk_branch gcc_prng_ahb_clk = {
1344 .halt_reg = 0x34004,
1345 .halt_check = BRANCH_HALT_VOTED,
1346 .hwcg_reg = 0x34004,
1349 .enable_reg = 0x52000,
1350 .enable_mask = BIT(13),
1351 .hw.init = &(struct clk_init_data){
1352 .name = "gcc_prng_ahb_clk",
1353 .ops = &clk_branch2_ops,
1358 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1359 .halt_reg = 0x4b004,
1360 .halt_check = BRANCH_HALT,
1361 .hwcg_reg = 0x4b004,
1364 .enable_reg = 0x4b004,
1365 .enable_mask = BIT(0),
1366 .hw.init = &(struct clk_init_data){
1367 .name = "gcc_qspi_cnoc_periph_ahb_clk",
1368 .ops = &clk_branch2_ops,
1373 static struct clk_branch gcc_qspi_core_clk = {
1374 .halt_reg = 0x4b008,
1375 .halt_check = BRANCH_HALT,
1377 .enable_reg = 0x4b008,
1378 .enable_mask = BIT(0),
1379 .hw.init = &(struct clk_init_data){
1380 .name = "gcc_qspi_core_clk",
1381 .parent_hws = (const struct clk_hw*[]){
1382 &gcc_qspi_core_clk_src.clkr.hw,
1385 .flags = CLK_SET_RATE_PARENT,
1386 .ops = &clk_branch2_ops,
1391 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1392 .halt_reg = 0x17014,
1393 .halt_check = BRANCH_HALT_VOTED,
1395 .enable_reg = 0x52008,
1396 .enable_mask = BIT(9),
1397 .hw.init = &(struct clk_init_data){
1398 .name = "gcc_qupv3_wrap0_core_2x_clk",
1399 .ops = &clk_branch2_ops,
1404 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1405 .halt_reg = 0x1700c,
1406 .halt_check = BRANCH_HALT_VOTED,
1408 .enable_reg = 0x52008,
1409 .enable_mask = BIT(8),
1410 .hw.init = &(struct clk_init_data){
1411 .name = "gcc_qupv3_wrap0_core_clk",
1412 .ops = &clk_branch2_ops,
1417 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1418 .halt_reg = 0x17030,
1419 .halt_check = BRANCH_HALT_VOTED,
1421 .enable_reg = 0x52008,
1422 .enable_mask = BIT(10),
1423 .hw.init = &(struct clk_init_data){
1424 .name = "gcc_qupv3_wrap0_s0_clk",
1425 .parent_hws = (const struct clk_hw*[]){
1426 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1429 .flags = CLK_SET_RATE_PARENT,
1430 .ops = &clk_branch2_ops,
1435 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1436 .halt_reg = 0x17160,
1437 .halt_check = BRANCH_HALT_VOTED,
1439 .enable_reg = 0x52008,
1440 .enable_mask = BIT(11),
1441 .hw.init = &(struct clk_init_data){
1442 .name = "gcc_qupv3_wrap0_s1_clk",
1443 .parent_hws = (const struct clk_hw*[]){
1444 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1447 .flags = CLK_SET_RATE_PARENT,
1448 .ops = &clk_branch2_ops,
1453 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1454 .halt_reg = 0x17290,
1455 .halt_check = BRANCH_HALT_VOTED,
1457 .enable_reg = 0x52008,
1458 .enable_mask = BIT(12),
1459 .hw.init = &(struct clk_init_data){
1460 .name = "gcc_qupv3_wrap0_s2_clk",
1461 .parent_hws = (const struct clk_hw*[]){
1462 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1465 .flags = CLK_SET_RATE_PARENT,
1466 .ops = &clk_branch2_ops,
1471 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1472 .halt_reg = 0x173c0,
1473 .halt_check = BRANCH_HALT_VOTED,
1475 .enable_reg = 0x52008,
1476 .enable_mask = BIT(13),
1477 .hw.init = &(struct clk_init_data){
1478 .name = "gcc_qupv3_wrap0_s3_clk",
1479 .parent_hws = (const struct clk_hw*[]){
1480 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1483 .flags = CLK_SET_RATE_PARENT,
1484 .ops = &clk_branch2_ops,
1489 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1490 .halt_reg = 0x174f0,
1491 .halt_check = BRANCH_HALT_VOTED,
1493 .enable_reg = 0x52008,
1494 .enable_mask = BIT(14),
1495 .hw.init = &(struct clk_init_data){
1496 .name = "gcc_qupv3_wrap0_s4_clk",
1497 .parent_hws = (const struct clk_hw*[]){
1498 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1501 .flags = CLK_SET_RATE_PARENT,
1502 .ops = &clk_branch2_ops,
1507 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
1508 .halt_reg = 0x17620,
1509 .halt_check = BRANCH_HALT_VOTED,
1511 .enable_reg = 0x52008,
1512 .enable_mask = BIT(15),
1513 .hw.init = &(struct clk_init_data){
1514 .name = "gcc_qupv3_wrap0_s5_clk",
1515 .parent_hws = (const struct clk_hw*[]){
1516 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1519 .flags = CLK_SET_RATE_PARENT,
1520 .ops = &clk_branch2_ops,
1525 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1526 .halt_reg = 0x18004,
1527 .halt_check = BRANCH_HALT_VOTED,
1529 .enable_reg = 0x52008,
1530 .enable_mask = BIT(18),
1531 .hw.init = &(struct clk_init_data){
1532 .name = "gcc_qupv3_wrap1_core_2x_clk",
1533 .ops = &clk_branch2_ops,
1538 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1539 .halt_reg = 0x18008,
1540 .halt_check = BRANCH_HALT_VOTED,
1542 .enable_reg = 0x52008,
1543 .enable_mask = BIT(19),
1544 .hw.init = &(struct clk_init_data){
1545 .name = "gcc_qupv3_wrap1_core_clk",
1546 .ops = &clk_branch2_ops,
1551 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1552 .halt_reg = 0x18014,
1553 .halt_check = BRANCH_HALT_VOTED,
1555 .enable_reg = 0x52008,
1556 .enable_mask = BIT(22),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "gcc_qupv3_wrap1_s0_clk",
1559 .parent_hws = (const struct clk_hw*[]){
1560 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1563 .flags = CLK_SET_RATE_PARENT,
1564 .ops = &clk_branch2_ops,
1569 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1570 .halt_reg = 0x18144,
1571 .halt_check = BRANCH_HALT_VOTED,
1573 .enable_reg = 0x52008,
1574 .enable_mask = BIT(23),
1575 .hw.init = &(struct clk_init_data){
1576 .name = "gcc_qupv3_wrap1_s1_clk",
1577 .parent_hws = (const struct clk_hw*[]){
1578 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1581 .flags = CLK_SET_RATE_PARENT,
1582 .ops = &clk_branch2_ops,
1587 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1588 .halt_reg = 0x18274,
1589 .halt_check = BRANCH_HALT_VOTED,
1591 .enable_reg = 0x52008,
1592 .enable_mask = BIT(24),
1593 .hw.init = &(struct clk_init_data){
1594 .name = "gcc_qupv3_wrap1_s2_clk",
1595 .parent_hws = (const struct clk_hw*[]){
1596 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1599 .flags = CLK_SET_RATE_PARENT,
1600 .ops = &clk_branch2_ops,
1605 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1606 .halt_reg = 0x183a4,
1607 .halt_check = BRANCH_HALT_VOTED,
1609 .enable_reg = 0x52008,
1610 .enable_mask = BIT(25),
1611 .hw.init = &(struct clk_init_data){
1612 .name = "gcc_qupv3_wrap1_s3_clk",
1613 .parent_hws = (const struct clk_hw*[]){
1614 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1617 .flags = CLK_SET_RATE_PARENT,
1618 .ops = &clk_branch2_ops,
1623 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
1624 .halt_reg = 0x184d4,
1625 .halt_check = BRANCH_HALT_VOTED,
1627 .enable_reg = 0x52008,
1628 .enable_mask = BIT(26),
1629 .hw.init = &(struct clk_init_data){
1630 .name = "gcc_qupv3_wrap1_s4_clk",
1631 .parent_hws = (const struct clk_hw*[]){
1632 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1635 .flags = CLK_SET_RATE_PARENT,
1636 .ops = &clk_branch2_ops,
1641 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
1642 .halt_reg = 0x18604,
1643 .halt_check = BRANCH_HALT_VOTED,
1645 .enable_reg = 0x52008,
1646 .enable_mask = BIT(27),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "gcc_qupv3_wrap1_s5_clk",
1649 .parent_hws = (const struct clk_hw*[]){
1650 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
1653 .flags = CLK_SET_RATE_PARENT,
1654 .ops = &clk_branch2_ops,
1659 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
1660 .halt_reg = 0x17004,
1661 .halt_check = BRANCH_HALT_VOTED,
1663 .enable_reg = 0x52008,
1664 .enable_mask = BIT(6),
1665 .hw.init = &(struct clk_init_data){
1666 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
1667 .ops = &clk_branch2_ops,
1672 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
1673 .halt_reg = 0x17008,
1674 .halt_check = BRANCH_HALT_VOTED,
1675 .hwcg_reg = 0x17008,
1678 .enable_reg = 0x52008,
1679 .enable_mask = BIT(7),
1680 .hw.init = &(struct clk_init_data){
1681 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
1682 .ops = &clk_branch2_ops,
1687 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
1688 .halt_reg = 0x1800c,
1689 .halt_check = BRANCH_HALT_VOTED,
1691 .enable_reg = 0x52008,
1692 .enable_mask = BIT(20),
1693 .hw.init = &(struct clk_init_data){
1694 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
1695 .ops = &clk_branch2_ops,
1700 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
1701 .halt_reg = 0x18010,
1702 .halt_check = BRANCH_HALT_VOTED,
1703 .hwcg_reg = 0x18010,
1706 .enable_reg = 0x52008,
1707 .enable_mask = BIT(21),
1708 .hw.init = &(struct clk_init_data){
1709 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
1710 .ops = &clk_branch2_ops,
1715 static struct clk_branch gcc_sdcc1_ahb_clk = {
1716 .halt_reg = 0x12008,
1717 .halt_check = BRANCH_HALT,
1719 .enable_reg = 0x12008,
1720 .enable_mask = BIT(0),
1721 .hw.init = &(struct clk_init_data){
1722 .name = "gcc_sdcc1_ahb_clk",
1723 .ops = &clk_branch2_ops,
1728 static struct clk_branch gcc_sdcc1_apps_clk = {
1729 .halt_reg = 0x1200c,
1730 .halt_check = BRANCH_HALT,
1732 .enable_reg = 0x1200c,
1733 .enable_mask = BIT(0),
1734 .hw.init = &(struct clk_init_data){
1735 .name = "gcc_sdcc1_apps_clk",
1736 .parent_hws = (const struct clk_hw*[]){
1737 &gcc_sdcc1_apps_clk_src.clkr.hw,
1740 .flags = CLK_SET_RATE_PARENT,
1741 .ops = &clk_branch2_ops,
1746 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1747 .halt_reg = 0x12040,
1748 .halt_check = BRANCH_HALT,
1750 .enable_reg = 0x12040,
1751 .enable_mask = BIT(0),
1752 .hw.init = &(struct clk_init_data){
1753 .name = "gcc_sdcc1_ice_core_clk",
1754 .parent_hws = (const struct clk_hw*[]){
1755 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
1758 .flags = CLK_SET_RATE_PARENT,
1759 .ops = &clk_branch2_ops,
1764 static struct clk_branch gcc_sdcc2_ahb_clk = {
1765 .halt_reg = 0x14008,
1766 .halt_check = BRANCH_HALT,
1768 .enable_reg = 0x14008,
1769 .enable_mask = BIT(0),
1770 .hw.init = &(struct clk_init_data){
1771 .name = "gcc_sdcc2_ahb_clk",
1772 .ops = &clk_branch2_ops,
1777 static struct clk_branch gcc_sdcc2_apps_clk = {
1778 .halt_reg = 0x14004,
1779 .halt_check = BRANCH_HALT,
1781 .enable_reg = 0x14004,
1782 .enable_mask = BIT(0),
1783 .hw.init = &(struct clk_init_data){
1784 .name = "gcc_sdcc2_apps_clk",
1785 .parent_hws = (const struct clk_hw*[]){
1786 &gcc_sdcc2_apps_clk_src.clkr.hw,
1789 .flags = CLK_SET_RATE_PARENT,
1790 .ops = &clk_branch2_ops,
1795 /* For CPUSS functionality the SYS NOC clock needs to be left enabled */
1796 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
1798 .halt_check = BRANCH_HALT_VOTED,
1800 .enable_reg = 0x52000,
1801 .enable_mask = BIT(0),
1802 .hw.init = &(struct clk_init_data){
1803 .name = "gcc_sys_noc_cpuss_ahb_clk",
1804 .parent_hws = (const struct clk_hw*[]){
1805 &gcc_cpuss_ahb_clk_src.clkr.hw,
1808 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1809 .ops = &clk_branch2_ops,
1814 static struct clk_branch gcc_ufs_mem_clkref_clk = {
1815 .halt_reg = 0x8c000,
1816 .halt_check = BRANCH_HALT,
1818 .enable_reg = 0x8c000,
1819 .enable_mask = BIT(0),
1820 .hw.init = &(struct clk_init_data){
1821 .name = "gcc_ufs_mem_clkref_clk",
1822 .ops = &clk_branch2_ops,
1827 static struct clk_branch gcc_ufs_phy_ahb_clk = {
1828 .halt_reg = 0x77014,
1829 .halt_check = BRANCH_HALT,
1830 .hwcg_reg = 0x77014,
1833 .enable_reg = 0x77014,
1834 .enable_mask = BIT(0),
1835 .hw.init = &(struct clk_init_data){
1836 .name = "gcc_ufs_phy_ahb_clk",
1837 .ops = &clk_branch2_ops,
1842 static struct clk_branch gcc_ufs_phy_axi_clk = {
1843 .halt_reg = 0x77038,
1844 .halt_check = BRANCH_HALT,
1845 .hwcg_reg = 0x77038,
1848 .enable_reg = 0x77038,
1849 .enable_mask = BIT(0),
1850 .hw.init = &(struct clk_init_data){
1851 .name = "gcc_ufs_phy_axi_clk",
1852 .parent_hws = (const struct clk_hw*[]){
1853 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1856 .flags = CLK_SET_RATE_PARENT,
1857 .ops = &clk_branch2_ops,
1862 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
1863 .halt_reg = 0x77090,
1864 .halt_check = BRANCH_HALT,
1865 .hwcg_reg = 0x77090,
1868 .enable_reg = 0x77090,
1869 .enable_mask = BIT(0),
1870 .hw.init = &(struct clk_init_data){
1871 .name = "gcc_ufs_phy_ice_core_clk",
1872 .parent_hws = (const struct clk_hw*[]){
1873 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
1876 .flags = CLK_SET_RATE_PARENT,
1877 .ops = &clk_branch2_ops,
1882 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
1883 .halt_reg = 0x77094,
1884 .halt_check = BRANCH_HALT,
1885 .hwcg_reg = 0x77094,
1888 .enable_reg = 0x77094,
1889 .enable_mask = BIT(0),
1890 .hw.init = &(struct clk_init_data){
1891 .name = "gcc_ufs_phy_phy_aux_clk",
1892 .parent_hws = (const struct clk_hw*[]){
1893 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
1896 .flags = CLK_SET_RATE_PARENT,
1897 .ops = &clk_branch2_ops,
1902 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
1903 .halt_reg = 0x7701c,
1904 .halt_check = BRANCH_HALT_SKIP,
1906 .enable_reg = 0x7701c,
1907 .enable_mask = BIT(0),
1908 .hw.init = &(struct clk_init_data){
1909 .name = "gcc_ufs_phy_rx_symbol_0_clk",
1910 .ops = &clk_branch2_ops,
1915 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
1916 .halt_reg = 0x77018,
1917 .halt_check = BRANCH_HALT_SKIP,
1919 .enable_reg = 0x77018,
1920 .enable_mask = BIT(0),
1921 .hw.init = &(struct clk_init_data){
1922 .name = "gcc_ufs_phy_tx_symbol_0_clk",
1923 .ops = &clk_branch2_ops,
1928 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
1929 .halt_reg = 0x7708c,
1930 .halt_check = BRANCH_HALT,
1931 .hwcg_reg = 0x7708c,
1934 .enable_reg = 0x7708c,
1935 .enable_mask = BIT(0),
1936 .hw.init = &(struct clk_init_data){
1937 .name = "gcc_ufs_phy_unipro_core_clk",
1938 .parent_hws = (const struct clk_hw*[]){
1939 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
1942 .flags = CLK_SET_RATE_PARENT,
1943 .ops = &clk_branch2_ops,
1948 static struct clk_branch gcc_usb30_prim_master_clk = {
1950 .halt_check = BRANCH_HALT,
1952 .enable_reg = 0xf010,
1953 .enable_mask = BIT(0),
1954 .hw.init = &(struct clk_init_data){
1955 .name = "gcc_usb30_prim_master_clk",
1956 .parent_hws = (const struct clk_hw*[]){
1957 &gcc_usb30_prim_master_clk_src.clkr.hw,
1960 .flags = CLK_SET_RATE_PARENT,
1961 .ops = &clk_branch2_ops,
1966 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
1968 .halt_check = BRANCH_HALT,
1970 .enable_reg = 0xf018,
1971 .enable_mask = BIT(0),
1972 .hw.init = &(struct clk_init_data){
1973 .name = "gcc_usb30_prim_mock_utmi_clk",
1974 .parent_hws = (const struct clk_hw*[]) {
1975 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1978 .flags = CLK_SET_RATE_PARENT,
1979 .ops = &clk_branch2_ops,
1984 static struct clk_branch gcc_usb30_prim_sleep_clk = {
1986 .halt_check = BRANCH_HALT,
1988 .enable_reg = 0xf014,
1989 .enable_mask = BIT(0),
1990 .hw.init = &(struct clk_init_data){
1991 .name = "gcc_usb30_prim_sleep_clk",
1992 .ops = &clk_branch2_ops,
1997 static struct clk_branch gcc_usb3_prim_clkref_clk = {
1998 .halt_reg = 0x8c010,
1999 .halt_check = BRANCH_HALT,
2001 .enable_reg = 0x8c010,
2002 .enable_mask = BIT(0),
2003 .hw.init = &(struct clk_init_data){
2004 .name = "gcc_usb3_prim_clkref_clk",
2005 .ops = &clk_branch2_ops,
2010 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2012 .halt_check = BRANCH_HALT,
2014 .enable_reg = 0xf050,
2015 .enable_mask = BIT(0),
2016 .hw.init = &(struct clk_init_data){
2017 .name = "gcc_usb3_prim_phy_aux_clk",
2018 .parent_hws = (const struct clk_hw*[]){
2019 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2022 .flags = CLK_SET_RATE_PARENT,
2023 .ops = &clk_branch2_ops,
2028 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2030 .halt_check = BRANCH_HALT,
2032 .enable_reg = 0xf054,
2033 .enable_mask = BIT(0),
2034 .hw.init = &(struct clk_init_data){
2035 .name = "gcc_usb3_prim_phy_com_aux_clk",
2036 .parent_hws = (const struct clk_hw*[]){
2037 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2040 .flags = CLK_SET_RATE_PARENT,
2041 .ops = &clk_branch2_ops,
2046 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2048 .halt_check = BRANCH_HALT_SKIP,
2050 .enable_reg = 0xf058,
2051 .enable_mask = BIT(0),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "gcc_usb3_prim_phy_pipe_clk",
2054 .ops = &clk_branch2_ops,
2059 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2060 .halt_reg = 0x6a004,
2061 .halt_check = BRANCH_HALT,
2062 .hwcg_reg = 0x6a004,
2065 .enable_reg = 0x6a004,
2066 .enable_mask = BIT(0),
2067 .hw.init = &(struct clk_init_data){
2068 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2069 .ops = &clk_branch2_ops,
2074 static struct clk_branch gcc_video_axi_clk = {
2076 .halt_check = BRANCH_HALT,
2078 .enable_reg = 0xb01c,
2079 .enable_mask = BIT(0),
2080 .hw.init = &(struct clk_init_data){
2081 .name = "gcc_video_axi_clk",
2082 .ops = &clk_branch2_ops,
2087 static struct clk_branch gcc_video_gpll0_div_clk_src = {
2088 .halt_check = BRANCH_HALT_DELAY,
2090 .enable_reg = 0x52000,
2091 .enable_mask = BIT(20),
2092 .hw.init = &(struct clk_init_data){
2093 .name = "gcc_video_gpll0_div_clk_src",
2094 .parent_hws = (const struct clk_hw*[]){
2095 &gcc_pll0_main_div_cdiv.hw,
2098 .flags = CLK_SET_RATE_PARENT,
2099 .ops = &clk_branch2_ops,
2104 static struct clk_branch gcc_video_throttle_axi_clk = {
2106 .halt_check = BRANCH_HALT,
2110 .enable_reg = 0xb07c,
2111 .enable_mask = BIT(0),
2112 .hw.init = &(struct clk_init_data){
2113 .name = "gcc_video_throttle_axi_clk",
2114 .ops = &clk_branch2_ops,
2119 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2120 .halt_reg = 0x8a000,
2121 .halt_check = BRANCH_HALT,
2123 .enable_reg = 0x8a000,
2124 .enable_mask = BIT(0),
2125 .hw.init = &(struct clk_init_data){
2126 .name = "gcc_mss_cfg_ahb_clk",
2127 .ops = &clk_branch2_ops,
2132 static struct clk_branch gcc_mss_mfab_axis_clk = {
2133 .halt_reg = 0x8a004,
2134 .halt_check = BRANCH_HALT_VOTED,
2136 .enable_reg = 0x8a004,
2137 .enable_mask = BIT(0),
2138 .hw.init = &(struct clk_init_data){
2139 .name = "gcc_mss_mfab_axis_clk",
2140 .ops = &clk_branch2_ops,
2145 static struct clk_branch gcc_mss_nav_axi_clk = {
2146 .halt_reg = 0x8a00c,
2147 .halt_check = BRANCH_HALT_VOTED,
2149 .enable_reg = 0x8a00c,
2150 .enable_mask = BIT(0),
2151 .hw.init = &(struct clk_init_data){
2152 .name = "gcc_mss_nav_axi_clk",
2153 .ops = &clk_branch2_ops,
2158 static struct clk_branch gcc_mss_snoc_axi_clk = {
2159 .halt_reg = 0x8a150,
2160 .halt_check = BRANCH_HALT,
2162 .enable_reg = 0x8a150,
2163 .enable_mask = BIT(0),
2164 .hw.init = &(struct clk_init_data){
2165 .name = "gcc_mss_snoc_axi_clk",
2166 .ops = &clk_branch2_ops,
2171 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
2172 .halt_reg = 0x8a154,
2173 .halt_check = BRANCH_HALT,
2175 .enable_reg = 0x8a154,
2176 .enable_mask = BIT(0),
2177 .hw.init = &(struct clk_init_data){
2178 .name = "gcc_mss_q6_memnoc_axi_clk",
2179 .ops = &clk_branch2_ops,
2184 static struct clk_branch gcc_lpass_cfg_noc_sway_clk = {
2185 .halt_reg = 0x47018,
2186 .halt_check = BRANCH_HALT_DELAY,
2188 .enable_reg = 0x47018,
2189 .enable_mask = BIT(0),
2190 .hw.init = &(struct clk_init_data){
2191 .name = "gcc_lpass_cfg_noc_sway_clk",
2192 .ops = &clk_branch2_ops,
2197 static struct gdsc ufs_phy_gdsc = {
2200 .name = "ufs_phy_gdsc",
2202 .pwrsts = PWRSTS_OFF_ON,
2205 static struct gdsc usb30_prim_gdsc = {
2208 .name = "usb30_prim_gdsc",
2210 .pwrsts = PWRSTS_RET_ON,
2213 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
2216 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
2218 .pwrsts = PWRSTS_OFF_ON,
2222 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
2225 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
2227 .pwrsts = PWRSTS_OFF_ON,
2231 static struct gdsc *gcc_sc7180_gdscs[] = {
2232 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
2233 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
2234 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
2235 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
2236 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] =
2237 &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
2241 static struct clk_hw *gcc_sc7180_hws[] = {
2242 [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw,
2245 static struct clk_regmap *gcc_sc7180_clocks[] = {
2246 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2247 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2248 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2249 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
2250 [GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr,
2251 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2252 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2253 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2254 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2255 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
2256 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
2257 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
2258 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2259 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
2260 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
2261 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
2262 [GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr,
2263 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2264 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2265 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2266 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2267 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2268 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2269 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
2270 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
2271 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2272 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2273 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
2274 [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
2275 [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
2276 [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
2277 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
2278 [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
2279 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
2280 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
2281 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2282 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2283 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2284 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2285 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2286 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
2287 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
2288 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
2289 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2290 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2291 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2292 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2293 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2294 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2295 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2296 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2297 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2298 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2299 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2300 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2301 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2302 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2303 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2304 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2305 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2306 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2307 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2308 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2309 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2310 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2311 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2312 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2313 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2314 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2315 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
2316 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
2317 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2318 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2319 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2320 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2321 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2322 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2323 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2324 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2325 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2326 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2327 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2328 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2329 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
2330 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
2331 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
2332 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
2333 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
2334 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
2335 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
2336 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
2337 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
2338 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
2339 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
2340 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
2341 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
2342 &gcc_ufs_phy_unipro_core_clk_src.clkr,
2343 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2344 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2345 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2346 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
2347 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2348 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2349 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
2350 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2351 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2352 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2353 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2354 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2355 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
2356 [GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr,
2357 [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
2358 [GPLL0] = &gpll0.clkr,
2359 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2360 [GPLL6] = &gpll6.clkr,
2361 [GPLL7] = &gpll7.clkr,
2362 [GPLL4] = &gpll4.clkr,
2363 [GPLL1] = &gpll1.clkr,
2364 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2365 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
2366 [GCC_MSS_NAV_AXI_CLK] = &gcc_mss_nav_axi_clk.clkr,
2367 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
2368 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
2369 [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
2370 [GCC_LPASS_CFG_NOC_SWAY_CLK] = &gcc_lpass_cfg_noc_sway_clk.clkr,
2373 static const struct qcom_reset_map gcc_sc7180_resets[] = {
2374 [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
2375 [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
2376 [GCC_UFS_PHY_BCR] = { 0x77000 },
2377 [GCC_USB30_PRIM_BCR] = { 0xf000 },
2378 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
2379 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
2380 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
2381 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
2382 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
2383 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
2384 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2387 static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2388 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2389 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2390 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2391 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2392 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2393 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2394 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2395 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2396 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2397 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2398 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2399 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
2402 static const struct regmap_config gcc_sc7180_regmap_config = {
2406 .max_register = 0x18208c,
2410 static const struct qcom_cc_desc gcc_sc7180_desc = {
2411 .config = &gcc_sc7180_regmap_config,
2412 .clk_hws = gcc_sc7180_hws,
2413 .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
2414 .clks = gcc_sc7180_clocks,
2415 .num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
2416 .resets = gcc_sc7180_resets,
2417 .num_resets = ARRAY_SIZE(gcc_sc7180_resets),
2418 .gdscs = gcc_sc7180_gdscs,
2419 .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
2422 static const struct of_device_id gcc_sc7180_match_table[] = {
2423 { .compatible = "qcom,gcc-sc7180" },
2426 MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
2428 static int gcc_sc7180_probe(struct platform_device *pdev)
2430 struct regmap *regmap;
2433 regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
2435 return PTR_ERR(regmap);
2438 * Disable the GPLL0 active input to MM blocks, NPU
2439 * and GPU via MISC registers.
2441 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
2442 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
2443 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
2446 * Keep the clocks always-ON
2447 * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK,
2448 * GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK
2450 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
2451 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
2452 regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
2453 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
2454 regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0));
2455 regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0));
2456 regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0));
2457 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
2459 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2460 ARRAY_SIZE(gcc_dfs_clocks));
2464 return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
2467 static struct platform_driver gcc_sc7180_driver = {
2468 .probe = gcc_sc7180_probe,
2470 .name = "gcc-sc7180",
2471 .of_match_table = gcc_sc7180_match_table,
2475 static int __init gcc_sc7180_init(void)
2477 return platform_driver_register(&gcc_sc7180_driver);
2479 core_initcall(gcc_sc7180_init);
2481 static void __exit gcc_sc7180_exit(void)
2483 platform_driver_unregister(&gcc_sc7180_driver);
2485 module_exit(gcc_sc7180_exit);
2487 MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
2488 MODULE_LICENSE("GPL v2");