1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
20 #include "clk-regmap.h"
21 #include "clk-alpha-pll.h"
24 #include "clk-branch.h"
30 P_CORE_BI_PLL_TEST_SE,
33 P_PLL0_EARLY_DIV_CLK_SRC,
38 static const struct parent_map gcc_parent_map_0[] = {
40 { P_GPLL0_OUT_MAIN, 1 },
41 { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
42 { P_CORE_BI_PLL_TEST_SE, 7 },
45 static const char * const gcc_parent_names_0[] = {
49 "core_bi_pll_test_se",
52 static const struct parent_map gcc_parent_map_1[] = {
54 { P_GPLL0_OUT_MAIN, 1 },
55 { P_CORE_BI_PLL_TEST_SE, 7 },
58 static const char * const gcc_parent_names_1[] = {
61 "core_bi_pll_test_se",
64 static const struct parent_map gcc_parent_map_2[] = {
66 { P_GPLL0_OUT_MAIN, 1 },
68 { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
69 { P_CORE_BI_PLL_TEST_SE, 7 },
72 static const char * const gcc_parent_names_2[] = {
77 "core_bi_pll_test_se",
80 static const struct parent_map gcc_parent_map_3[] = {
83 { P_CORE_BI_PLL_TEST_SE, 7 },
86 static const char * const gcc_parent_names_3[] = {
89 "core_bi_pll_test_se",
92 static const struct parent_map gcc_parent_map_4[] = {
94 { P_GPLL0_OUT_MAIN, 1 },
95 { P_GPLL4_OUT_MAIN, 5 },
96 { P_CORE_BI_PLL_TEST_SE, 7 },
99 static const char * const gcc_parent_names_4[] = {
103 "core_bi_pll_test_se",
106 static const struct parent_map gcc_parent_map_5[] = {
108 { P_GPLL0_OUT_MAIN, 1 },
109 { P_AUD_REF_CLK, 2 },
110 { P_CORE_BI_PLL_TEST_SE, 7 },
113 static const char * const gcc_parent_names_5[] = {
117 "core_bi_pll_test_se",
120 static struct clk_fixed_factor xo = {
123 .hw.init = &(struct clk_init_data){
125 .parent_names = (const char *[]){ "xo_board" },
127 .ops = &clk_fixed_factor_ops,
131 static struct pll_vco fabia_vco[] = {
132 { 250000000, 2000000000, 0 },
133 { 125000000, 1000000000, 1 },
136 static struct clk_alpha_pll gpll0 = {
138 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
139 .vco_table = fabia_vco,
140 .num_vco = ARRAY_SIZE(fabia_vco),
142 .enable_reg = 0x52000,
143 .enable_mask = BIT(0),
144 .hw.init = &(struct clk_init_data){
146 .parent_names = (const char *[]){ "xo" },
148 .ops = &clk_alpha_pll_ops,
153 static struct clk_alpha_pll_postdiv gpll0_out_even = {
155 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
156 .clkr.hw.init = &(struct clk_init_data){
157 .name = "gpll0_out_even",
158 .parent_names = (const char *[]){ "gpll0" },
160 .ops = &clk_alpha_pll_postdiv_ops,
164 static struct clk_alpha_pll_postdiv gpll0_out_main = {
166 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
167 .clkr.hw.init = &(struct clk_init_data){
168 .name = "gpll0_out_main",
169 .parent_names = (const char *[]){ "gpll0" },
171 .ops = &clk_alpha_pll_postdiv_ops,
175 static struct clk_alpha_pll_postdiv gpll0_out_odd = {
177 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
178 .clkr.hw.init = &(struct clk_init_data){
179 .name = "gpll0_out_odd",
180 .parent_names = (const char *[]){ "gpll0" },
182 .ops = &clk_alpha_pll_postdiv_ops,
186 static struct clk_alpha_pll_postdiv gpll0_out_test = {
188 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
189 .clkr.hw.init = &(struct clk_init_data){
190 .name = "gpll0_out_test",
191 .parent_names = (const char *[]){ "gpll0" },
193 .ops = &clk_alpha_pll_postdiv_ops,
197 static struct clk_alpha_pll gpll1 = {
199 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
200 .vco_table = fabia_vco,
201 .num_vco = ARRAY_SIZE(fabia_vco),
203 .enable_reg = 0x52000,
204 .enable_mask = BIT(1),
205 .hw.init = &(struct clk_init_data){
207 .parent_names = (const char *[]){ "xo" },
209 .ops = &clk_alpha_pll_ops,
214 static struct clk_alpha_pll_postdiv gpll1_out_even = {
216 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
217 .clkr.hw.init = &(struct clk_init_data){
218 .name = "gpll1_out_even",
219 .parent_names = (const char *[]){ "gpll1" },
221 .ops = &clk_alpha_pll_postdiv_ops,
225 static struct clk_alpha_pll_postdiv gpll1_out_main = {
227 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
228 .clkr.hw.init = &(struct clk_init_data){
229 .name = "gpll1_out_main",
230 .parent_names = (const char *[]){ "gpll1" },
232 .ops = &clk_alpha_pll_postdiv_ops,
236 static struct clk_alpha_pll_postdiv gpll1_out_odd = {
238 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
239 .clkr.hw.init = &(struct clk_init_data){
240 .name = "gpll1_out_odd",
241 .parent_names = (const char *[]){ "gpll1" },
243 .ops = &clk_alpha_pll_postdiv_ops,
247 static struct clk_alpha_pll_postdiv gpll1_out_test = {
249 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
250 .clkr.hw.init = &(struct clk_init_data){
251 .name = "gpll1_out_test",
252 .parent_names = (const char *[]){ "gpll1" },
254 .ops = &clk_alpha_pll_postdiv_ops,
258 static struct clk_alpha_pll gpll2 = {
260 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
261 .vco_table = fabia_vco,
262 .num_vco = ARRAY_SIZE(fabia_vco),
264 .enable_reg = 0x52000,
265 .enable_mask = BIT(2),
266 .hw.init = &(struct clk_init_data){
268 .parent_names = (const char *[]){ "xo" },
270 .ops = &clk_alpha_pll_ops,
275 static struct clk_alpha_pll_postdiv gpll2_out_even = {
277 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
278 .clkr.hw.init = &(struct clk_init_data){
279 .name = "gpll2_out_even",
280 .parent_names = (const char *[]){ "gpll2" },
282 .ops = &clk_alpha_pll_postdiv_ops,
286 static struct clk_alpha_pll_postdiv gpll2_out_main = {
288 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
289 .clkr.hw.init = &(struct clk_init_data){
290 .name = "gpll2_out_main",
291 .parent_names = (const char *[]){ "gpll2" },
293 .ops = &clk_alpha_pll_postdiv_ops,
297 static struct clk_alpha_pll_postdiv gpll2_out_odd = {
299 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
300 .clkr.hw.init = &(struct clk_init_data){
301 .name = "gpll2_out_odd",
302 .parent_names = (const char *[]){ "gpll2" },
304 .ops = &clk_alpha_pll_postdiv_ops,
308 static struct clk_alpha_pll_postdiv gpll2_out_test = {
310 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
311 .clkr.hw.init = &(struct clk_init_data){
312 .name = "gpll2_out_test",
313 .parent_names = (const char *[]){ "gpll2" },
315 .ops = &clk_alpha_pll_postdiv_ops,
319 static struct clk_alpha_pll gpll3 = {
321 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
322 .vco_table = fabia_vco,
323 .num_vco = ARRAY_SIZE(fabia_vco),
325 .enable_reg = 0x52000,
326 .enable_mask = BIT(3),
327 .hw.init = &(struct clk_init_data){
329 .parent_names = (const char *[]){ "xo" },
331 .ops = &clk_alpha_pll_ops,
336 static struct clk_alpha_pll_postdiv gpll3_out_even = {
338 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
339 .clkr.hw.init = &(struct clk_init_data){
340 .name = "gpll3_out_even",
341 .parent_names = (const char *[]){ "gpll3" },
343 .ops = &clk_alpha_pll_postdiv_ops,
347 static struct clk_alpha_pll_postdiv gpll3_out_main = {
349 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
350 .clkr.hw.init = &(struct clk_init_data){
351 .name = "gpll3_out_main",
352 .parent_names = (const char *[]){ "gpll3" },
354 .ops = &clk_alpha_pll_postdiv_ops,
358 static struct clk_alpha_pll_postdiv gpll3_out_odd = {
360 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
361 .clkr.hw.init = &(struct clk_init_data){
362 .name = "gpll3_out_odd",
363 .parent_names = (const char *[]){ "gpll3" },
365 .ops = &clk_alpha_pll_postdiv_ops,
369 static struct clk_alpha_pll_postdiv gpll3_out_test = {
371 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
372 .clkr.hw.init = &(struct clk_init_data){
373 .name = "gpll3_out_test",
374 .parent_names = (const char *[]){ "gpll3" },
376 .ops = &clk_alpha_pll_postdiv_ops,
380 static struct clk_alpha_pll gpll4 = {
382 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
383 .vco_table = fabia_vco,
384 .num_vco = ARRAY_SIZE(fabia_vco),
386 .enable_reg = 0x52000,
387 .enable_mask = BIT(4),
388 .hw.init = &(struct clk_init_data){
390 .parent_names = (const char *[]){ "xo" },
392 .ops = &clk_alpha_pll_ops,
397 static struct clk_alpha_pll_postdiv gpll4_out_even = {
399 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
400 .clkr.hw.init = &(struct clk_init_data){
401 .name = "gpll4_out_even",
402 .parent_names = (const char *[]){ "gpll4" },
404 .ops = &clk_alpha_pll_postdiv_ops,
408 static struct clk_alpha_pll_postdiv gpll4_out_main = {
410 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
411 .clkr.hw.init = &(struct clk_init_data){
412 .name = "gpll4_out_main",
413 .parent_names = (const char *[]){ "gpll4" },
415 .ops = &clk_alpha_pll_postdiv_ops,
419 static struct clk_alpha_pll_postdiv gpll4_out_odd = {
421 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
422 .clkr.hw.init = &(struct clk_init_data){
423 .name = "gpll4_out_odd",
424 .parent_names = (const char *[]){ "gpll4" },
426 .ops = &clk_alpha_pll_postdiv_ops,
430 static struct clk_alpha_pll_postdiv gpll4_out_test = {
432 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
433 .clkr.hw.init = &(struct clk_init_data){
434 .name = "gpll4_out_test",
435 .parent_names = (const char *[]){ "gpll4" },
437 .ops = &clk_alpha_pll_postdiv_ops,
441 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
442 F(19200000, P_XO, 1, 0, 0),
443 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
447 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
451 .parent_map = gcc_parent_map_1,
452 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
453 .clkr.hw.init = &(struct clk_init_data){
454 .name = "blsp1_qup1_i2c_apps_clk_src",
455 .parent_names = gcc_parent_names_1,
457 .ops = &clk_rcg2_ops,
461 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
462 F(960000, P_XO, 10, 1, 2),
463 F(4800000, P_XO, 4, 0, 0),
464 F(9600000, P_XO, 2, 0, 0),
465 F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
466 F(19200000, P_XO, 1, 0, 0),
467 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
468 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
472 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
476 .parent_map = gcc_parent_map_0,
477 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
478 .clkr.hw.init = &(struct clk_init_data){
479 .name = "blsp1_qup1_spi_apps_clk_src",
480 .parent_names = gcc_parent_names_0,
482 .ops = &clk_rcg2_ops,
486 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
490 .parent_map = gcc_parent_map_1,
491 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
492 .clkr.hw.init = &(struct clk_init_data){
493 .name = "blsp1_qup2_i2c_apps_clk_src",
494 .parent_names = gcc_parent_names_1,
496 .ops = &clk_rcg2_ops,
500 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
504 .parent_map = gcc_parent_map_0,
505 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
506 .clkr.hw.init = &(struct clk_init_data){
507 .name = "blsp1_qup2_spi_apps_clk_src",
508 .parent_names = gcc_parent_names_0,
510 .ops = &clk_rcg2_ops,
514 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
518 .parent_map = gcc_parent_map_1,
519 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
520 .clkr.hw.init = &(struct clk_init_data){
521 .name = "blsp1_qup3_i2c_apps_clk_src",
522 .parent_names = gcc_parent_names_1,
524 .ops = &clk_rcg2_ops,
528 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
532 .parent_map = gcc_parent_map_0,
533 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
534 .clkr.hw.init = &(struct clk_init_data){
535 .name = "blsp1_qup3_spi_apps_clk_src",
536 .parent_names = gcc_parent_names_0,
538 .ops = &clk_rcg2_ops,
542 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
546 .parent_map = gcc_parent_map_1,
547 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
548 .clkr.hw.init = &(struct clk_init_data){
549 .name = "blsp1_qup4_i2c_apps_clk_src",
550 .parent_names = gcc_parent_names_1,
552 .ops = &clk_rcg2_ops,
556 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
560 .parent_map = gcc_parent_map_0,
561 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
562 .clkr.hw.init = &(struct clk_init_data){
563 .name = "blsp1_qup4_spi_apps_clk_src",
564 .parent_names = gcc_parent_names_0,
566 .ops = &clk_rcg2_ops,
570 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
574 .parent_map = gcc_parent_map_1,
575 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
576 .clkr.hw.init = &(struct clk_init_data){
577 .name = "blsp1_qup5_i2c_apps_clk_src",
578 .parent_names = gcc_parent_names_1,
580 .ops = &clk_rcg2_ops,
584 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
588 .parent_map = gcc_parent_map_0,
589 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
590 .clkr.hw.init = &(struct clk_init_data){
591 .name = "blsp1_qup5_spi_apps_clk_src",
592 .parent_names = gcc_parent_names_0,
594 .ops = &clk_rcg2_ops,
598 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
602 .parent_map = gcc_parent_map_1,
603 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
604 .clkr.hw.init = &(struct clk_init_data){
605 .name = "blsp1_qup6_i2c_apps_clk_src",
606 .parent_names = gcc_parent_names_1,
608 .ops = &clk_rcg2_ops,
612 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
616 .parent_map = gcc_parent_map_0,
617 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
618 .clkr.hw.init = &(struct clk_init_data){
619 .name = "blsp1_qup6_spi_apps_clk_src",
620 .parent_names = gcc_parent_names_0,
622 .ops = &clk_rcg2_ops,
626 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
627 F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625),
628 F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625),
629 F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625),
630 F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15),
631 F(19200000, P_XO, 1, 0, 0),
632 F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
633 F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
634 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
635 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
636 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
637 F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
638 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
639 F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
640 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
641 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
645 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
649 .parent_map = gcc_parent_map_0,
650 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
651 .clkr.hw.init = &(struct clk_init_data){
652 .name = "blsp1_uart1_apps_clk_src",
653 .parent_names = gcc_parent_names_0,
655 .ops = &clk_rcg2_ops,
659 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
663 .parent_map = gcc_parent_map_0,
664 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
665 .clkr.hw.init = &(struct clk_init_data){
666 .name = "blsp1_uart2_apps_clk_src",
667 .parent_names = gcc_parent_names_0,
669 .ops = &clk_rcg2_ops,
673 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
677 .parent_map = gcc_parent_map_0,
678 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
679 .clkr.hw.init = &(struct clk_init_data){
680 .name = "blsp1_uart3_apps_clk_src",
681 .parent_names = gcc_parent_names_0,
683 .ops = &clk_rcg2_ops,
687 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
691 .parent_map = gcc_parent_map_1,
692 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
693 .clkr.hw.init = &(struct clk_init_data){
694 .name = "blsp2_qup1_i2c_apps_clk_src",
695 .parent_names = gcc_parent_names_1,
697 .ops = &clk_rcg2_ops,
701 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
705 .parent_map = gcc_parent_map_0,
706 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
707 .clkr.hw.init = &(struct clk_init_data){
708 .name = "blsp2_qup1_spi_apps_clk_src",
709 .parent_names = gcc_parent_names_0,
711 .ops = &clk_rcg2_ops,
715 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
719 .parent_map = gcc_parent_map_1,
720 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
721 .clkr.hw.init = &(struct clk_init_data){
722 .name = "blsp2_qup2_i2c_apps_clk_src",
723 .parent_names = gcc_parent_names_1,
725 .ops = &clk_rcg2_ops,
729 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
733 .parent_map = gcc_parent_map_0,
734 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
735 .clkr.hw.init = &(struct clk_init_data){
736 .name = "blsp2_qup2_spi_apps_clk_src",
737 .parent_names = gcc_parent_names_0,
739 .ops = &clk_rcg2_ops,
743 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
747 .parent_map = gcc_parent_map_1,
748 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
749 .clkr.hw.init = &(struct clk_init_data){
750 .name = "blsp2_qup3_i2c_apps_clk_src",
751 .parent_names = gcc_parent_names_1,
753 .ops = &clk_rcg2_ops,
757 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
761 .parent_map = gcc_parent_map_0,
762 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
763 .clkr.hw.init = &(struct clk_init_data){
764 .name = "blsp2_qup3_spi_apps_clk_src",
765 .parent_names = gcc_parent_names_0,
767 .ops = &clk_rcg2_ops,
771 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
775 .parent_map = gcc_parent_map_1,
776 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
777 .clkr.hw.init = &(struct clk_init_data){
778 .name = "blsp2_qup4_i2c_apps_clk_src",
779 .parent_names = gcc_parent_names_1,
781 .ops = &clk_rcg2_ops,
785 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
789 .parent_map = gcc_parent_map_0,
790 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
791 .clkr.hw.init = &(struct clk_init_data){
792 .name = "blsp2_qup4_spi_apps_clk_src",
793 .parent_names = gcc_parent_names_0,
795 .ops = &clk_rcg2_ops,
799 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
803 .parent_map = gcc_parent_map_1,
804 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
805 .clkr.hw.init = &(struct clk_init_data){
806 .name = "blsp2_qup5_i2c_apps_clk_src",
807 .parent_names = gcc_parent_names_1,
809 .ops = &clk_rcg2_ops,
813 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
817 .parent_map = gcc_parent_map_0,
818 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
819 .clkr.hw.init = &(struct clk_init_data){
820 .name = "blsp2_qup5_spi_apps_clk_src",
821 .parent_names = gcc_parent_names_0,
823 .ops = &clk_rcg2_ops,
827 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
831 .parent_map = gcc_parent_map_1,
832 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
833 .clkr.hw.init = &(struct clk_init_data){
834 .name = "blsp2_qup6_i2c_apps_clk_src",
835 .parent_names = gcc_parent_names_1,
837 .ops = &clk_rcg2_ops,
841 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
845 .parent_map = gcc_parent_map_0,
846 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
847 .clkr.hw.init = &(struct clk_init_data){
848 .name = "blsp2_qup6_spi_apps_clk_src",
849 .parent_names = gcc_parent_names_0,
851 .ops = &clk_rcg2_ops,
855 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
859 .parent_map = gcc_parent_map_0,
860 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
861 .clkr.hw.init = &(struct clk_init_data){
862 .name = "blsp2_uart1_apps_clk_src",
863 .parent_names = gcc_parent_names_0,
865 .ops = &clk_rcg2_ops,
869 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
873 .parent_map = gcc_parent_map_0,
874 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
875 .clkr.hw.init = &(struct clk_init_data){
876 .name = "blsp2_uart2_apps_clk_src",
877 .parent_names = gcc_parent_names_0,
879 .ops = &clk_rcg2_ops,
883 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
887 .parent_map = gcc_parent_map_0,
888 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
889 .clkr.hw.init = &(struct clk_init_data){
890 .name = "blsp2_uart3_apps_clk_src",
891 .parent_names = gcc_parent_names_0,
893 .ops = &clk_rcg2_ops,
897 static const struct freq_tbl ftbl_gp1_clk_src[] = {
898 F(19200000, P_XO, 1, 0, 0),
899 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
900 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
904 static struct clk_rcg2 gp1_clk_src = {
908 .parent_map = gcc_parent_map_2,
909 .freq_tbl = ftbl_gp1_clk_src,
910 .clkr.hw.init = &(struct clk_init_data){
911 .name = "gp1_clk_src",
912 .parent_names = gcc_parent_names_2,
914 .ops = &clk_rcg2_ops,
918 static struct clk_rcg2 gp2_clk_src = {
922 .parent_map = gcc_parent_map_2,
923 .freq_tbl = ftbl_gp1_clk_src,
924 .clkr.hw.init = &(struct clk_init_data){
925 .name = "gp2_clk_src",
926 .parent_names = gcc_parent_names_2,
928 .ops = &clk_rcg2_ops,
932 static struct clk_rcg2 gp3_clk_src = {
936 .parent_map = gcc_parent_map_2,
937 .freq_tbl = ftbl_gp1_clk_src,
938 .clkr.hw.init = &(struct clk_init_data){
939 .name = "gp3_clk_src",
940 .parent_names = gcc_parent_names_2,
942 .ops = &clk_rcg2_ops,
946 static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = {
947 F(19200000, P_XO, 1, 0, 0),
948 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
949 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
953 static struct clk_rcg2 hmss_ahb_clk_src = {
957 .parent_map = gcc_parent_map_1,
958 .freq_tbl = ftbl_hmss_ahb_clk_src,
959 .clkr.hw.init = &(struct clk_init_data){
960 .name = "hmss_ahb_clk_src",
961 .parent_names = gcc_parent_names_1,
963 .ops = &clk_rcg2_ops,
967 static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
968 F(19200000, P_XO, 1, 0, 0),
972 static struct clk_rcg2 hmss_rbcpr_clk_src = {
976 .parent_map = gcc_parent_map_1,
977 .freq_tbl = ftbl_hmss_rbcpr_clk_src,
978 .clkr.hw.init = &(struct clk_init_data){
979 .name = "hmss_rbcpr_clk_src",
980 .parent_names = gcc_parent_names_1,
982 .ops = &clk_rcg2_ops,
986 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
987 F(1010526, P_XO, 1, 1, 19),
991 static struct clk_rcg2 pcie_aux_clk_src = {
995 .parent_map = gcc_parent_map_3,
996 .freq_tbl = ftbl_pcie_aux_clk_src,
997 .clkr.hw.init = &(struct clk_init_data){
998 .name = "pcie_aux_clk_src",
999 .parent_names = gcc_parent_names_3,
1001 .ops = &clk_rcg2_ops,
1005 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1006 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1010 static struct clk_rcg2 pdm2_clk_src = {
1011 .cmd_rcgr = 0x33010,
1014 .parent_map = gcc_parent_map_1,
1015 .freq_tbl = ftbl_pdm2_clk_src,
1016 .clkr.hw.init = &(struct clk_init_data){
1017 .name = "pdm2_clk_src",
1018 .parent_names = gcc_parent_names_1,
1020 .ops = &clk_rcg2_ops,
1024 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1025 F(144000, P_XO, 16, 3, 25),
1026 F(400000, P_XO, 12, 1, 4),
1027 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
1028 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
1029 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1030 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1031 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1035 static struct clk_rcg2 sdcc2_apps_clk_src = {
1036 .cmd_rcgr = 0x14010,
1039 .parent_map = gcc_parent_map_4,
1040 .freq_tbl = ftbl_sdcc2_apps_clk_src,
1041 .clkr.hw.init = &(struct clk_init_data){
1042 .name = "sdcc2_apps_clk_src",
1043 .parent_names = gcc_parent_names_4,
1045 .ops = &clk_rcg2_ops,
1049 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
1050 F(144000, P_XO, 16, 3, 25),
1051 F(400000, P_XO, 12, 1, 4),
1052 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
1053 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
1054 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1055 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1059 static struct clk_rcg2 sdcc4_apps_clk_src = {
1060 .cmd_rcgr = 0x16010,
1063 .parent_map = gcc_parent_map_1,
1064 .freq_tbl = ftbl_sdcc4_apps_clk_src,
1065 .clkr.hw.init = &(struct clk_init_data){
1066 .name = "sdcc4_apps_clk_src",
1067 .parent_names = gcc_parent_names_1,
1069 .ops = &clk_rcg2_ops,
1073 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1074 F(105495, P_XO, 1, 1, 182),
1078 static struct clk_rcg2 tsif_ref_clk_src = {
1079 .cmd_rcgr = 0x36010,
1082 .parent_map = gcc_parent_map_5,
1083 .freq_tbl = ftbl_tsif_ref_clk_src,
1084 .clkr.hw.init = &(struct clk_init_data){
1085 .name = "tsif_ref_clk_src",
1086 .parent_names = gcc_parent_names_5,
1088 .ops = &clk_rcg2_ops,
1092 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1093 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1094 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1095 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1099 static struct clk_rcg2 ufs_axi_clk_src = {
1100 .cmd_rcgr = 0x75018,
1103 .parent_map = gcc_parent_map_0,
1104 .freq_tbl = ftbl_ufs_axi_clk_src,
1105 .clkr.hw.init = &(struct clk_init_data){
1106 .name = "ufs_axi_clk_src",
1107 .parent_names = gcc_parent_names_0,
1109 .ops = &clk_rcg2_ops,
1113 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1114 F(19200000, P_XO, 1, 0, 0),
1115 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1116 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1120 static struct clk_rcg2 usb30_master_clk_src = {
1124 .parent_map = gcc_parent_map_0,
1125 .freq_tbl = ftbl_usb30_master_clk_src,
1126 .clkr.hw.init = &(struct clk_init_data){
1127 .name = "usb30_master_clk_src",
1128 .parent_names = gcc_parent_names_0,
1130 .ops = &clk_rcg2_ops,
1134 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1138 .parent_map = gcc_parent_map_0,
1139 .freq_tbl = ftbl_hmss_rbcpr_clk_src,
1140 .clkr.hw.init = &(struct clk_init_data){
1141 .name = "usb30_mock_utmi_clk_src",
1142 .parent_names = gcc_parent_names_0,
1144 .ops = &clk_rcg2_ops,
1148 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1149 F(1200000, P_XO, 16, 0, 0),
1153 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1154 .cmd_rcgr = 0x5000c,
1157 .parent_map = gcc_parent_map_3,
1158 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1159 .clkr.hw.init = &(struct clk_init_data){
1160 .name = "usb3_phy_aux_clk_src",
1161 .parent_names = gcc_parent_names_3,
1163 .ops = &clk_rcg2_ops,
1167 static struct clk_branch gcc_aggre1_noc_xo_clk = {
1168 .halt_reg = 0x8202c,
1169 .halt_check = BRANCH_HALT,
1171 .enable_reg = 0x8202c,
1172 .enable_mask = BIT(0),
1173 .hw.init = &(struct clk_init_data){
1174 .name = "gcc_aggre1_noc_xo_clk",
1175 .ops = &clk_branch2_ops,
1180 static struct clk_branch gcc_aggre1_ufs_axi_clk = {
1181 .halt_reg = 0x82028,
1182 .halt_check = BRANCH_HALT,
1184 .enable_reg = 0x82028,
1185 .enable_mask = BIT(0),
1186 .hw.init = &(struct clk_init_data){
1187 .name = "gcc_aggre1_ufs_axi_clk",
1188 .parent_names = (const char *[]){
1192 .ops = &clk_branch2_ops,
1197 static struct clk_branch gcc_aggre1_usb3_axi_clk = {
1198 .halt_reg = 0x82024,
1199 .halt_check = BRANCH_HALT,
1201 .enable_reg = 0x82024,
1202 .enable_mask = BIT(0),
1203 .hw.init = &(struct clk_init_data){
1204 .name = "gcc_aggre1_usb3_axi_clk",
1205 .parent_names = (const char *[]){
1206 "usb30_master_clk_src",
1209 .ops = &clk_branch2_ops,
1214 static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = {
1215 .halt_reg = 0x48090,
1216 .halt_check = BRANCH_HALT,
1218 .enable_reg = 0x48090,
1219 .enable_mask = BIT(0),
1220 .hw.init = &(struct clk_init_data){
1221 .name = "gcc_apss_qdss_tsctr_div2_clk",
1222 .ops = &clk_branch2_ops,
1227 static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = {
1228 .halt_reg = 0x48094,
1229 .halt_check = BRANCH_HALT,
1231 .enable_reg = 0x48094,
1232 .enable_mask = BIT(0),
1233 .hw.init = &(struct clk_init_data){
1234 .name = "gcc_apss_qdss_tsctr_div8_clk",
1235 .ops = &clk_branch2_ops,
1240 static struct clk_branch gcc_bimc_hmss_axi_clk = {
1241 .halt_reg = 0x48004,
1242 .halt_check = BRANCH_HALT_VOTED,
1244 .enable_reg = 0x52004,
1245 .enable_mask = BIT(22),
1246 .hw.init = &(struct clk_init_data){
1247 .name = "gcc_bimc_hmss_axi_clk",
1248 .ops = &clk_branch2_ops,
1253 static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
1254 .halt_reg = 0x4401c,
1255 .halt_check = BRANCH_HALT,
1257 .enable_reg = 0x4401c,
1258 .enable_mask = BIT(0),
1259 .hw.init = &(struct clk_init_data){
1260 .name = "gcc_bimc_mss_q6_axi_clk",
1261 .ops = &clk_branch2_ops,
1266 static struct clk_branch gcc_blsp1_ahb_clk = {
1267 .halt_reg = 0x17004,
1268 .halt_check = BRANCH_HALT_VOTED,
1270 .enable_reg = 0x52004,
1271 .enable_mask = BIT(17),
1272 .hw.init = &(struct clk_init_data){
1273 .name = "gcc_blsp1_ahb_clk",
1274 .ops = &clk_branch2_ops,
1279 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1280 .halt_reg = 0x19008,
1281 .halt_check = BRANCH_HALT,
1283 .enable_reg = 0x19008,
1284 .enable_mask = BIT(0),
1285 .hw.init = &(struct clk_init_data){
1286 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1287 .parent_names = (const char *[]){
1288 "blsp1_qup1_i2c_apps_clk_src",
1291 .ops = &clk_branch2_ops,
1296 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1297 .halt_reg = 0x19004,
1298 .halt_check = BRANCH_HALT,
1300 .enable_reg = 0x19004,
1301 .enable_mask = BIT(0),
1302 .hw.init = &(struct clk_init_data){
1303 .name = "gcc_blsp1_qup1_spi_apps_clk",
1304 .parent_names = (const char *[]){
1305 "blsp1_qup1_spi_apps_clk_src",
1308 .ops = &clk_branch2_ops,
1313 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1314 .halt_reg = 0x1b008,
1315 .halt_check = BRANCH_HALT,
1317 .enable_reg = 0x1b008,
1318 .enable_mask = BIT(0),
1319 .hw.init = &(struct clk_init_data){
1320 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1321 .parent_names = (const char *[]){
1322 "blsp1_qup2_i2c_apps_clk_src",
1325 .ops = &clk_branch2_ops,
1330 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1331 .halt_reg = 0x1b004,
1332 .halt_check = BRANCH_HALT,
1334 .enable_reg = 0x1b004,
1335 .enable_mask = BIT(0),
1336 .hw.init = &(struct clk_init_data){
1337 .name = "gcc_blsp1_qup2_spi_apps_clk",
1338 .parent_names = (const char *[]){
1339 "blsp1_qup2_spi_apps_clk_src",
1342 .ops = &clk_branch2_ops,
1347 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1348 .halt_reg = 0x1d008,
1349 .halt_check = BRANCH_HALT,
1351 .enable_reg = 0x1d008,
1352 .enable_mask = BIT(0),
1353 .hw.init = &(struct clk_init_data){
1354 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1355 .parent_names = (const char *[]){
1356 "blsp1_qup3_i2c_apps_clk_src",
1359 .ops = &clk_branch2_ops,
1364 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1365 .halt_reg = 0x1d004,
1366 .halt_check = BRANCH_HALT,
1368 .enable_reg = 0x1d004,
1369 .enable_mask = BIT(0),
1370 .hw.init = &(struct clk_init_data){
1371 .name = "gcc_blsp1_qup3_spi_apps_clk",
1372 .parent_names = (const char *[]){
1373 "blsp1_qup3_spi_apps_clk_src",
1376 .ops = &clk_branch2_ops,
1381 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1382 .halt_reg = 0x1f008,
1383 .halt_check = BRANCH_HALT,
1385 .enable_reg = 0x1f008,
1386 .enable_mask = BIT(0),
1387 .hw.init = &(struct clk_init_data){
1388 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1389 .parent_names = (const char *[]){
1390 "blsp1_qup4_i2c_apps_clk_src",
1393 .ops = &clk_branch2_ops,
1398 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1399 .halt_reg = 0x1f004,
1400 .halt_check = BRANCH_HALT,
1402 .enable_reg = 0x1f004,
1403 .enable_mask = BIT(0),
1404 .hw.init = &(struct clk_init_data){
1405 .name = "gcc_blsp1_qup4_spi_apps_clk",
1406 .parent_names = (const char *[]){
1407 "blsp1_qup4_spi_apps_clk_src",
1410 .ops = &clk_branch2_ops,
1415 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1416 .halt_reg = 0x21008,
1417 .halt_check = BRANCH_HALT,
1419 .enable_reg = 0x21008,
1420 .enable_mask = BIT(0),
1421 .hw.init = &(struct clk_init_data){
1422 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1423 .parent_names = (const char *[]){
1424 "blsp1_qup5_i2c_apps_clk_src",
1427 .ops = &clk_branch2_ops,
1432 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1433 .halt_reg = 0x21004,
1434 .halt_check = BRANCH_HALT,
1436 .enable_reg = 0x21004,
1437 .enable_mask = BIT(0),
1438 .hw.init = &(struct clk_init_data){
1439 .name = "gcc_blsp1_qup5_spi_apps_clk",
1440 .parent_names = (const char *[]){
1441 "blsp1_qup5_spi_apps_clk_src",
1444 .ops = &clk_branch2_ops,
1449 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1450 .halt_reg = 0x23008,
1451 .halt_check = BRANCH_HALT,
1453 .enable_reg = 0x23008,
1454 .enable_mask = BIT(0),
1455 .hw.init = &(struct clk_init_data){
1456 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1457 .parent_names = (const char *[]){
1458 "blsp1_qup6_i2c_apps_clk_src",
1461 .ops = &clk_branch2_ops,
1466 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1467 .halt_reg = 0x23004,
1468 .halt_check = BRANCH_HALT,
1470 .enable_reg = 0x23004,
1471 .enable_mask = BIT(0),
1472 .hw.init = &(struct clk_init_data){
1473 .name = "gcc_blsp1_qup6_spi_apps_clk",
1474 .parent_names = (const char *[]){
1475 "blsp1_qup6_spi_apps_clk_src",
1478 .ops = &clk_branch2_ops,
1483 static struct clk_branch gcc_blsp1_sleep_clk = {
1484 .halt_reg = 0x17008,
1485 .halt_check = BRANCH_HALT_VOTED,
1487 .enable_reg = 0x52004,
1488 .enable_mask = BIT(16),
1489 .hw.init = &(struct clk_init_data){
1490 .name = "gcc_blsp1_sleep_clk",
1491 .ops = &clk_branch2_ops,
1496 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1497 .halt_reg = 0x1a004,
1498 .halt_check = BRANCH_HALT,
1500 .enable_reg = 0x1a004,
1501 .enable_mask = BIT(0),
1502 .hw.init = &(struct clk_init_data){
1503 .name = "gcc_blsp1_uart1_apps_clk",
1504 .parent_names = (const char *[]){
1505 "blsp1_uart1_apps_clk_src",
1508 .ops = &clk_branch2_ops,
1513 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1514 .halt_reg = 0x1c004,
1515 .halt_check = BRANCH_HALT,
1517 .enable_reg = 0x1c004,
1518 .enable_mask = BIT(0),
1519 .hw.init = &(struct clk_init_data){
1520 .name = "gcc_blsp1_uart2_apps_clk",
1521 .parent_names = (const char *[]){
1522 "blsp1_uart2_apps_clk_src",
1525 .ops = &clk_branch2_ops,
1530 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1531 .halt_reg = 0x1e004,
1532 .halt_check = BRANCH_HALT,
1534 .enable_reg = 0x1e004,
1535 .enable_mask = BIT(0),
1536 .hw.init = &(struct clk_init_data){
1537 .name = "gcc_blsp1_uart3_apps_clk",
1538 .parent_names = (const char *[]){
1539 "blsp1_uart3_apps_clk_src",
1542 .ops = &clk_branch2_ops,
1547 static struct clk_branch gcc_blsp2_ahb_clk = {
1548 .halt_reg = 0x25004,
1549 .halt_check = BRANCH_HALT_VOTED,
1551 .enable_reg = 0x52004,
1552 .enable_mask = BIT(15),
1553 .hw.init = &(struct clk_init_data){
1554 .name = "gcc_blsp2_ahb_clk",
1555 .ops = &clk_branch2_ops,
1560 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1561 .halt_reg = 0x26008,
1562 .halt_check = BRANCH_HALT,
1564 .enable_reg = 0x26008,
1565 .enable_mask = BIT(0),
1566 .hw.init = &(struct clk_init_data){
1567 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1568 .parent_names = (const char *[]){
1569 "blsp2_qup1_i2c_apps_clk_src",
1572 .ops = &clk_branch2_ops,
1577 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1578 .halt_reg = 0x26004,
1579 .halt_check = BRANCH_HALT,
1581 .enable_reg = 0x26004,
1582 .enable_mask = BIT(0),
1583 .hw.init = &(struct clk_init_data){
1584 .name = "gcc_blsp2_qup1_spi_apps_clk",
1585 .parent_names = (const char *[]){
1586 "blsp2_qup1_spi_apps_clk_src",
1589 .ops = &clk_branch2_ops,
1594 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1595 .halt_reg = 0x28008,
1596 .halt_check = BRANCH_HALT,
1598 .enable_reg = 0x28008,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1602 .parent_names = (const char *[]){
1603 "blsp2_qup2_i2c_apps_clk_src",
1606 .ops = &clk_branch2_ops,
1611 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1612 .halt_reg = 0x28004,
1613 .halt_check = BRANCH_HALT,
1615 .enable_reg = 0x28004,
1616 .enable_mask = BIT(0),
1617 .hw.init = &(struct clk_init_data){
1618 .name = "gcc_blsp2_qup2_spi_apps_clk",
1619 .parent_names = (const char *[]){
1620 "blsp2_qup2_spi_apps_clk_src",
1623 .ops = &clk_branch2_ops,
1628 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1629 .halt_reg = 0x2a008,
1630 .halt_check = BRANCH_HALT,
1632 .enable_reg = 0x2a008,
1633 .enable_mask = BIT(0),
1634 .hw.init = &(struct clk_init_data){
1635 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1636 .parent_names = (const char *[]){
1637 "blsp2_qup3_i2c_apps_clk_src",
1640 .ops = &clk_branch2_ops,
1645 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1646 .halt_reg = 0x2a004,
1647 .halt_check = BRANCH_HALT,
1649 .enable_reg = 0x2a004,
1650 .enable_mask = BIT(0),
1651 .hw.init = &(struct clk_init_data){
1652 .name = "gcc_blsp2_qup3_spi_apps_clk",
1653 .parent_names = (const char *[]){
1654 "blsp2_qup3_spi_apps_clk_src",
1657 .ops = &clk_branch2_ops,
1662 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1663 .halt_reg = 0x2c008,
1664 .halt_check = BRANCH_HALT,
1666 .enable_reg = 0x2c008,
1667 .enable_mask = BIT(0),
1668 .hw.init = &(struct clk_init_data){
1669 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1670 .parent_names = (const char *[]){
1671 "blsp2_qup4_i2c_apps_clk_src",
1674 .ops = &clk_branch2_ops,
1679 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1680 .halt_reg = 0x2c004,
1681 .halt_check = BRANCH_HALT,
1683 .enable_reg = 0x2c004,
1684 .enable_mask = BIT(0),
1685 .hw.init = &(struct clk_init_data){
1686 .name = "gcc_blsp2_qup4_spi_apps_clk",
1687 .parent_names = (const char *[]){
1688 "blsp2_qup4_spi_apps_clk_src",
1691 .ops = &clk_branch2_ops,
1696 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1697 .halt_reg = 0x2e008,
1698 .halt_check = BRANCH_HALT,
1700 .enable_reg = 0x2e008,
1701 .enable_mask = BIT(0),
1702 .hw.init = &(struct clk_init_data){
1703 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1704 .parent_names = (const char *[]){
1705 "blsp2_qup5_i2c_apps_clk_src",
1708 .ops = &clk_branch2_ops,
1713 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1714 .halt_reg = 0x2e004,
1715 .halt_check = BRANCH_HALT,
1717 .enable_reg = 0x2e004,
1718 .enable_mask = BIT(0),
1719 .hw.init = &(struct clk_init_data){
1720 .name = "gcc_blsp2_qup5_spi_apps_clk",
1721 .parent_names = (const char *[]){
1722 "blsp2_qup5_spi_apps_clk_src",
1725 .ops = &clk_branch2_ops,
1730 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1731 .halt_reg = 0x30008,
1732 .halt_check = BRANCH_HALT,
1734 .enable_reg = 0x30008,
1735 .enable_mask = BIT(0),
1736 .hw.init = &(struct clk_init_data){
1737 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1738 .parent_names = (const char *[]){
1739 "blsp2_qup6_i2c_apps_clk_src",
1742 .ops = &clk_branch2_ops,
1747 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1748 .halt_reg = 0x30004,
1749 .halt_check = BRANCH_HALT,
1751 .enable_reg = 0x30004,
1752 .enable_mask = BIT(0),
1753 .hw.init = &(struct clk_init_data){
1754 .name = "gcc_blsp2_qup6_spi_apps_clk",
1755 .parent_names = (const char *[]){
1756 "blsp2_qup6_spi_apps_clk_src",
1759 .ops = &clk_branch2_ops,
1764 static struct clk_branch gcc_blsp2_sleep_clk = {
1765 .halt_reg = 0x25008,
1766 .halt_check = BRANCH_HALT_VOTED,
1768 .enable_reg = 0x52004,
1769 .enable_mask = BIT(14),
1770 .hw.init = &(struct clk_init_data){
1771 .name = "gcc_blsp2_sleep_clk",
1772 .ops = &clk_branch2_ops,
1777 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1778 .halt_reg = 0x27004,
1779 .halt_check = BRANCH_HALT,
1781 .enable_reg = 0x27004,
1782 .enable_mask = BIT(0),
1783 .hw.init = &(struct clk_init_data){
1784 .name = "gcc_blsp2_uart1_apps_clk",
1785 .parent_names = (const char *[]){
1786 "blsp2_uart1_apps_clk_src",
1789 .ops = &clk_branch2_ops,
1794 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1795 .halt_reg = 0x29004,
1796 .halt_check = BRANCH_HALT,
1798 .enable_reg = 0x29004,
1799 .enable_mask = BIT(0),
1800 .hw.init = &(struct clk_init_data){
1801 .name = "gcc_blsp2_uart2_apps_clk",
1802 .parent_names = (const char *[]){
1803 "blsp2_uart2_apps_clk_src",
1806 .ops = &clk_branch2_ops,
1811 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1812 .halt_reg = 0x2b004,
1813 .halt_check = BRANCH_HALT,
1815 .enable_reg = 0x2b004,
1816 .enable_mask = BIT(0),
1817 .hw.init = &(struct clk_init_data){
1818 .name = "gcc_blsp2_uart3_apps_clk",
1819 .parent_names = (const char *[]){
1820 "blsp2_uart3_apps_clk_src",
1823 .ops = &clk_branch2_ops,
1828 static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
1830 .halt_check = BRANCH_HALT,
1832 .enable_reg = 0x5018,
1833 .enable_mask = BIT(0),
1834 .hw.init = &(struct clk_init_data){
1835 .name = "gcc_cfg_noc_usb3_axi_clk",
1836 .parent_names = (const char *[]){
1837 "usb30_master_clk_src",
1840 .ops = &clk_branch2_ops,
1845 static struct clk_branch gcc_gp1_clk = {
1846 .halt_reg = 0x64000,
1847 .halt_check = BRANCH_HALT,
1849 .enable_reg = 0x64000,
1850 .enable_mask = BIT(0),
1851 .hw.init = &(struct clk_init_data){
1852 .name = "gcc_gp1_clk",
1853 .parent_names = (const char *[]){
1857 .ops = &clk_branch2_ops,
1862 static struct clk_branch gcc_gp2_clk = {
1863 .halt_reg = 0x65000,
1864 .halt_check = BRANCH_HALT,
1866 .enable_reg = 0x65000,
1867 .enable_mask = BIT(0),
1868 .hw.init = &(struct clk_init_data){
1869 .name = "gcc_gp2_clk",
1870 .parent_names = (const char *[]){
1874 .ops = &clk_branch2_ops,
1879 static struct clk_branch gcc_gp3_clk = {
1880 .halt_reg = 0x66000,
1881 .halt_check = BRANCH_HALT,
1883 .enable_reg = 0x66000,
1884 .enable_mask = BIT(0),
1885 .hw.init = &(struct clk_init_data){
1886 .name = "gcc_gp3_clk",
1887 .parent_names = (const char *[]){
1891 .ops = &clk_branch2_ops,
1896 static struct clk_branch gcc_gpu_bimc_gfx_clk = {
1897 .halt_reg = 0x71010,
1898 .halt_check = BRANCH_HALT,
1900 .enable_reg = 0x71010,
1901 .enable_mask = BIT(0),
1902 .hw.init = &(struct clk_init_data){
1903 .name = "gcc_gpu_bimc_gfx_clk",
1904 .ops = &clk_branch2_ops,
1909 static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
1910 .halt_reg = 0x7100c,
1911 .halt_check = BRANCH_HALT,
1913 .enable_reg = 0x7100c,
1914 .enable_mask = BIT(0),
1915 .hw.init = &(struct clk_init_data){
1916 .name = "gcc_gpu_bimc_gfx_src_clk",
1917 .ops = &clk_branch2_ops,
1922 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1923 .halt_reg = 0x71004,
1924 .halt_check = BRANCH_HALT,
1926 .enable_reg = 0x71004,
1927 .enable_mask = BIT(0),
1928 .hw.init = &(struct clk_init_data){
1929 .name = "gcc_gpu_cfg_ahb_clk",
1930 .ops = &clk_branch2_ops,
1935 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1936 .halt_reg = 0x71018,
1937 .halt_check = BRANCH_HALT,
1939 .enable_reg = 0x71018,
1940 .enable_mask = BIT(0),
1941 .hw.init = &(struct clk_init_data){
1942 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1943 .ops = &clk_branch2_ops,
1948 static struct clk_branch gcc_hmss_ahb_clk = {
1949 .halt_reg = 0x48000,
1950 .halt_check = BRANCH_HALT_VOTED,
1952 .enable_reg = 0x52004,
1953 .enable_mask = BIT(21),
1954 .hw.init = &(struct clk_init_data){
1955 .name = "gcc_hmss_ahb_clk",
1956 .parent_names = (const char *[]){
1960 .ops = &clk_branch2_ops,
1965 static struct clk_branch gcc_hmss_at_clk = {
1966 .halt_reg = 0x48010,
1967 .halt_check = BRANCH_HALT,
1969 .enable_reg = 0x48010,
1970 .enable_mask = BIT(0),
1971 .hw.init = &(struct clk_init_data){
1972 .name = "gcc_hmss_at_clk",
1973 .ops = &clk_branch2_ops,
1978 static struct clk_branch gcc_hmss_rbcpr_clk = {
1979 .halt_reg = 0x48008,
1980 .halt_check = BRANCH_HALT,
1982 .enable_reg = 0x48008,
1983 .enable_mask = BIT(0),
1984 .hw.init = &(struct clk_init_data){
1985 .name = "gcc_hmss_rbcpr_clk",
1986 .parent_names = (const char *[]){
1987 "hmss_rbcpr_clk_src",
1990 .ops = &clk_branch2_ops,
1995 static struct clk_branch gcc_hmss_trig_clk = {
1996 .halt_reg = 0x4800c,
1997 .halt_check = BRANCH_HALT,
1999 .enable_reg = 0x4800c,
2000 .enable_mask = BIT(0),
2001 .hw.init = &(struct clk_init_data){
2002 .name = "gcc_hmss_trig_clk",
2003 .ops = &clk_branch2_ops,
2008 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
2010 .halt_check = BRANCH_HALT,
2012 .enable_reg = 0x9004,
2013 .enable_mask = BIT(0),
2014 .hw.init = &(struct clk_init_data){
2015 .name = "gcc_mmss_noc_cfg_ahb_clk",
2016 .ops = &clk_branch2_ops,
2018 * Any access to mmss depends on this clock.
2019 * Gating this clock has been shown to crash the system
2020 * when mmssnoc_axi_rpm_clk is inited in rpmcc.
2022 .flags = CLK_IS_CRITICAL,
2027 static struct clk_branch gcc_mmss_qm_ahb_clk = {
2029 .halt_check = BRANCH_HALT,
2031 .enable_reg = 0x9030,
2032 .enable_mask = BIT(0),
2033 .hw.init = &(struct clk_init_data){
2034 .name = "gcc_mmss_qm_ahb_clk",
2035 .ops = &clk_branch2_ops,
2040 static struct clk_branch gcc_mmss_qm_core_clk = {
2042 .halt_check = BRANCH_HALT,
2044 .enable_reg = 0x900c,
2045 .enable_mask = BIT(0),
2046 .hw.init = &(struct clk_init_data){
2047 .name = "gcc_mmss_qm_core_clk",
2048 .ops = &clk_branch2_ops,
2053 static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
2055 .halt_check = BRANCH_HALT,
2057 .enable_reg = 0x9000,
2058 .enable_mask = BIT(0),
2059 .hw.init = &(struct clk_init_data){
2060 .name = "gcc_mmss_sys_noc_axi_clk",
2061 .ops = &clk_branch2_ops,
2066 static struct clk_branch gcc_mss_at_clk = {
2067 .halt_reg = 0x8a00c,
2068 .halt_check = BRANCH_HALT,
2070 .enable_reg = 0x8a00c,
2071 .enable_mask = BIT(0),
2072 .hw.init = &(struct clk_init_data){
2073 .name = "gcc_mss_at_clk",
2074 .ops = &clk_branch2_ops,
2079 static struct clk_branch gcc_pcie_0_aux_clk = {
2080 .halt_reg = 0x6b014,
2081 .halt_check = BRANCH_HALT,
2083 .enable_reg = 0x6b014,
2084 .enable_mask = BIT(0),
2085 .hw.init = &(struct clk_init_data){
2086 .name = "gcc_pcie_0_aux_clk",
2087 .parent_names = (const char *[]){
2091 .ops = &clk_branch2_ops,
2096 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2097 .halt_reg = 0x6b010,
2098 .halt_check = BRANCH_HALT,
2100 .enable_reg = 0x6b010,
2101 .enable_mask = BIT(0),
2102 .hw.init = &(struct clk_init_data){
2103 .name = "gcc_pcie_0_cfg_ahb_clk",
2104 .ops = &clk_branch2_ops,
2109 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2110 .halt_reg = 0x6b00c,
2111 .halt_check = BRANCH_HALT,
2113 .enable_reg = 0x6b00c,
2114 .enable_mask = BIT(0),
2115 .hw.init = &(struct clk_init_data){
2116 .name = "gcc_pcie_0_mstr_axi_clk",
2117 .ops = &clk_branch2_ops,
2122 static struct clk_branch gcc_pcie_0_pipe_clk = {
2123 .halt_reg = 0x6b018,
2124 .halt_check = BRANCH_HALT,
2126 .enable_reg = 0x6b018,
2127 .enable_mask = BIT(0),
2128 .hw.init = &(struct clk_init_data){
2129 .name = "gcc_pcie_0_pipe_clk",
2130 .ops = &clk_branch2_ops,
2135 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2136 .halt_reg = 0x6b008,
2137 .halt_check = BRANCH_HALT,
2139 .enable_reg = 0x6b008,
2140 .enable_mask = BIT(0),
2141 .hw.init = &(struct clk_init_data){
2142 .name = "gcc_pcie_0_slv_axi_clk",
2143 .ops = &clk_branch2_ops,
2148 static struct clk_branch gcc_pcie_phy_aux_clk = {
2149 .halt_reg = 0x6f004,
2150 .halt_check = BRANCH_HALT,
2152 .enable_reg = 0x6f004,
2153 .enable_mask = BIT(0),
2154 .hw.init = &(struct clk_init_data){
2155 .name = "gcc_pcie_phy_aux_clk",
2156 .parent_names = (const char *[]){
2160 .ops = &clk_branch2_ops,
2165 static struct clk_branch gcc_pdm2_clk = {
2166 .halt_reg = 0x3300c,
2167 .halt_check = BRANCH_HALT,
2169 .enable_reg = 0x3300c,
2170 .enable_mask = BIT(0),
2171 .hw.init = &(struct clk_init_data){
2172 .name = "gcc_pdm2_clk",
2173 .parent_names = (const char *[]){
2177 .ops = &clk_branch2_ops,
2182 static struct clk_branch gcc_pdm_ahb_clk = {
2183 .halt_reg = 0x33004,
2184 .halt_check = BRANCH_HALT,
2186 .enable_reg = 0x33004,
2187 .enable_mask = BIT(0),
2188 .hw.init = &(struct clk_init_data){
2189 .name = "gcc_pdm_ahb_clk",
2190 .ops = &clk_branch2_ops,
2195 static struct clk_branch gcc_pdm_xo4_clk = {
2196 .halt_reg = 0x33008,
2197 .halt_check = BRANCH_HALT,
2199 .enable_reg = 0x33008,
2200 .enable_mask = BIT(0),
2201 .hw.init = &(struct clk_init_data){
2202 .name = "gcc_pdm_xo4_clk",
2203 .ops = &clk_branch2_ops,
2208 static struct clk_branch gcc_prng_ahb_clk = {
2209 .halt_reg = 0x34004,
2210 .halt_check = BRANCH_HALT_VOTED,
2212 .enable_reg = 0x52004,
2213 .enable_mask = BIT(13),
2214 .hw.init = &(struct clk_init_data){
2215 .name = "gcc_prng_ahb_clk",
2216 .ops = &clk_branch2_ops,
2221 static struct clk_branch gcc_sdcc2_ahb_clk = {
2222 .halt_reg = 0x14008,
2223 .halt_check = BRANCH_HALT,
2225 .enable_reg = 0x14008,
2226 .enable_mask = BIT(0),
2227 .hw.init = &(struct clk_init_data){
2228 .name = "gcc_sdcc2_ahb_clk",
2229 .ops = &clk_branch2_ops,
2234 static struct clk_branch gcc_sdcc2_apps_clk = {
2235 .halt_reg = 0x14004,
2236 .halt_check = BRANCH_HALT,
2238 .enable_reg = 0x14004,
2239 .enable_mask = BIT(0),
2240 .hw.init = &(struct clk_init_data){
2241 .name = "gcc_sdcc2_apps_clk",
2242 .parent_names = (const char *[]){
2243 "sdcc2_apps_clk_src",
2246 .ops = &clk_branch2_ops,
2251 static struct clk_branch gcc_sdcc4_ahb_clk = {
2252 .halt_reg = 0x16008,
2253 .halt_check = BRANCH_HALT,
2255 .enable_reg = 0x16008,
2256 .enable_mask = BIT(0),
2257 .hw.init = &(struct clk_init_data){
2258 .name = "gcc_sdcc4_ahb_clk",
2259 .ops = &clk_branch2_ops,
2264 static struct clk_branch gcc_sdcc4_apps_clk = {
2265 .halt_reg = 0x16004,
2266 .halt_check = BRANCH_HALT,
2268 .enable_reg = 0x16004,
2269 .enable_mask = BIT(0),
2270 .hw.init = &(struct clk_init_data){
2271 .name = "gcc_sdcc4_apps_clk",
2272 .parent_names = (const char *[]){
2273 "sdcc4_apps_clk_src",
2276 .ops = &clk_branch2_ops,
2281 static struct clk_branch gcc_tsif_ahb_clk = {
2282 .halt_reg = 0x36004,
2283 .halt_check = BRANCH_HALT,
2285 .enable_reg = 0x36004,
2286 .enable_mask = BIT(0),
2287 .hw.init = &(struct clk_init_data){
2288 .name = "gcc_tsif_ahb_clk",
2289 .ops = &clk_branch2_ops,
2294 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2295 .halt_reg = 0x3600c,
2296 .halt_check = BRANCH_HALT,
2298 .enable_reg = 0x3600c,
2299 .enable_mask = BIT(0),
2300 .hw.init = &(struct clk_init_data){
2301 .name = "gcc_tsif_inactivity_timers_clk",
2302 .ops = &clk_branch2_ops,
2307 static struct clk_branch gcc_tsif_ref_clk = {
2308 .halt_reg = 0x36008,
2309 .halt_check = BRANCH_HALT,
2311 .enable_reg = 0x36008,
2312 .enable_mask = BIT(0),
2313 .hw.init = &(struct clk_init_data){
2314 .name = "gcc_tsif_ref_clk",
2315 .parent_names = (const char *[]){
2319 .ops = &clk_branch2_ops,
2324 static struct clk_branch gcc_ufs_ahb_clk = {
2325 .halt_reg = 0x7500c,
2326 .halt_check = BRANCH_HALT,
2328 .enable_reg = 0x7500c,
2329 .enable_mask = BIT(0),
2330 .hw.init = &(struct clk_init_data){
2331 .name = "gcc_ufs_ahb_clk",
2332 .ops = &clk_branch2_ops,
2337 static struct clk_branch gcc_ufs_axi_clk = {
2338 .halt_reg = 0x75008,
2339 .halt_check = BRANCH_HALT,
2341 .enable_reg = 0x75008,
2342 .enable_mask = BIT(0),
2343 .hw.init = &(struct clk_init_data){
2344 .name = "gcc_ufs_axi_clk",
2345 .parent_names = (const char *[]){
2349 .ops = &clk_branch2_ops,
2354 static struct clk_branch gcc_ufs_ice_core_clk = {
2355 .halt_reg = 0x7600c,
2356 .halt_check = BRANCH_HALT,
2358 .enable_reg = 0x7600c,
2359 .enable_mask = BIT(0),
2360 .hw.init = &(struct clk_init_data){
2361 .name = "gcc_ufs_ice_core_clk",
2362 .ops = &clk_branch2_ops,
2367 static struct clk_branch gcc_ufs_phy_aux_clk = {
2368 .halt_reg = 0x76040,
2369 .halt_check = BRANCH_HALT,
2371 .enable_reg = 0x76040,
2372 .enable_mask = BIT(0),
2373 .hw.init = &(struct clk_init_data){
2374 .name = "gcc_ufs_phy_aux_clk",
2375 .ops = &clk_branch2_ops,
2380 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2381 .halt_reg = 0x75014,
2382 .halt_check = BRANCH_HALT_SKIP,
2384 .enable_reg = 0x75014,
2385 .enable_mask = BIT(0),
2386 .hw.init = &(struct clk_init_data){
2387 .name = "gcc_ufs_rx_symbol_0_clk",
2388 .ops = &clk_branch2_ops,
2393 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2394 .halt_reg = 0x7605c,
2395 .halt_check = BRANCH_HALT_SKIP,
2397 .enable_reg = 0x7605c,
2398 .enable_mask = BIT(0),
2399 .hw.init = &(struct clk_init_data){
2400 .name = "gcc_ufs_rx_symbol_1_clk",
2401 .ops = &clk_branch2_ops,
2406 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2407 .halt_reg = 0x75010,
2408 .halt_check = BRANCH_HALT_SKIP,
2410 .enable_reg = 0x75010,
2411 .enable_mask = BIT(0),
2412 .hw.init = &(struct clk_init_data){
2413 .name = "gcc_ufs_tx_symbol_0_clk",
2414 .ops = &clk_branch2_ops,
2419 static struct clk_branch gcc_ufs_unipro_core_clk = {
2420 .halt_reg = 0x76008,
2421 .halt_check = BRANCH_HALT,
2423 .enable_reg = 0x76008,
2424 .enable_mask = BIT(0),
2425 .hw.init = &(struct clk_init_data){
2426 .name = "gcc_ufs_unipro_core_clk",
2427 .ops = &clk_branch2_ops,
2432 static struct clk_branch gcc_usb30_master_clk = {
2434 .halt_check = BRANCH_HALT,
2436 .enable_reg = 0xf008,
2437 .enable_mask = BIT(0),
2438 .hw.init = &(struct clk_init_data){
2439 .name = "gcc_usb30_master_clk",
2440 .parent_names = (const char *[]){
2441 "usb30_master_clk_src",
2444 .ops = &clk_branch2_ops,
2449 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2451 .halt_check = BRANCH_HALT,
2453 .enable_reg = 0xf010,
2454 .enable_mask = BIT(0),
2455 .hw.init = &(struct clk_init_data){
2456 .name = "gcc_usb30_mock_utmi_clk",
2457 .parent_names = (const char *[]){
2458 "usb30_mock_utmi_clk_src",
2461 .ops = &clk_branch2_ops,
2466 static struct clk_branch gcc_usb30_sleep_clk = {
2468 .halt_check = BRANCH_HALT,
2470 .enable_reg = 0xf00c,
2471 .enable_mask = BIT(0),
2472 .hw.init = &(struct clk_init_data){
2473 .name = "gcc_usb30_sleep_clk",
2474 .ops = &clk_branch2_ops,
2479 static struct clk_branch gcc_usb3_phy_aux_clk = {
2480 .halt_reg = 0x50000,
2481 .halt_check = BRANCH_HALT,
2483 .enable_reg = 0x50000,
2484 .enable_mask = BIT(0),
2485 .hw.init = &(struct clk_init_data){
2486 .name = "gcc_usb3_phy_aux_clk",
2487 .parent_names = (const char *[]){
2488 "usb3_phy_aux_clk_src",
2491 .ops = &clk_branch2_ops,
2496 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2497 .halt_reg = 0x50004,
2498 .halt_check = BRANCH_HALT,
2500 .enable_reg = 0x50004,
2501 .enable_mask = BIT(0),
2502 .hw.init = &(struct clk_init_data){
2503 .name = "gcc_usb3_phy_pipe_clk",
2504 .ops = &clk_branch2_ops,
2509 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2510 .halt_reg = 0x6a004,
2511 .halt_check = BRANCH_HALT,
2513 .enable_reg = 0x6a004,
2514 .enable_mask = BIT(0),
2515 .hw.init = &(struct clk_init_data){
2516 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2517 .ops = &clk_branch2_ops,
2522 static struct clk_branch gcc_hdmi_clkref_clk = {
2523 .halt_reg = 0x88000,
2525 .enable_reg = 0x88000,
2526 .enable_mask = BIT(0),
2527 .hw.init = &(struct clk_init_data){
2528 .name = "gcc_hdmi_clkref_clk",
2529 .parent_names = (const char *[]){ "xo" },
2531 .ops = &clk_branch2_ops,
2536 static struct clk_branch gcc_ufs_clkref_clk = {
2537 .halt_reg = 0x88004,
2539 .enable_reg = 0x88004,
2540 .enable_mask = BIT(0),
2541 .hw.init = &(struct clk_init_data){
2542 .name = "gcc_ufs_clkref_clk",
2543 .parent_names = (const char *[]){ "xo" },
2545 .ops = &clk_branch2_ops,
2550 static struct clk_branch gcc_usb3_clkref_clk = {
2551 .halt_reg = 0x88008,
2553 .enable_reg = 0x88008,
2554 .enable_mask = BIT(0),
2555 .hw.init = &(struct clk_init_data){
2556 .name = "gcc_usb3_clkref_clk",
2557 .parent_names = (const char *[]){ "xo" },
2559 .ops = &clk_branch2_ops,
2564 static struct clk_branch gcc_pcie_clkref_clk = {
2565 .halt_reg = 0x8800c,
2567 .enable_reg = 0x8800c,
2568 .enable_mask = BIT(0),
2569 .hw.init = &(struct clk_init_data){
2570 .name = "gcc_pcie_clkref_clk",
2571 .parent_names = (const char *[]){ "xo" },
2573 .ops = &clk_branch2_ops,
2578 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
2579 .halt_reg = 0x88014,
2581 .enable_reg = 0x88014,
2582 .enable_mask = BIT(0),
2583 .hw.init = &(struct clk_init_data){
2584 .name = "gcc_rx1_usb2_clkref_clk",
2585 .parent_names = (const char *[]){ "xo" },
2587 .ops = &clk_branch2_ops,
2592 static struct gdsc pcie_0_gdsc = {
2596 .name = "pcie_0_gdsc",
2598 .pwrsts = PWRSTS_OFF_ON,
2602 static struct gdsc ufs_gdsc = {
2608 .pwrsts = PWRSTS_OFF_ON,
2612 static struct gdsc usb_30_gdsc = {
2616 .name = "usb_30_gdsc",
2618 .pwrsts = PWRSTS_OFF_ON,
2622 static struct clk_regmap *gcc_msm8998_clocks[] = {
2623 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2624 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2625 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2626 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2627 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2628 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2629 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2630 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2631 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2632 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2633 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2634 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2635 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2636 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2637 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2638 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2639 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2640 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2641 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2642 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2643 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2644 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2645 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2646 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2647 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2648 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2649 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2650 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2651 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2652 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2653 [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr,
2654 [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr,
2655 [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr,
2656 [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr,
2657 [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr,
2658 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
2659 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
2660 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2661 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2662 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2663 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2664 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2665 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2666 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2667 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2668 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2669 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2670 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2671 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2672 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2673 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
2674 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2675 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2676 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2677 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2678 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2679 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2680 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2681 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2682 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2683 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2684 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2685 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2686 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2687 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2688 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2689 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2690 [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
2691 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2692 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2693 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2694 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
2695 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2696 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2697 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2698 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
2699 [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
2700 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2701 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2702 [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
2703 [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
2704 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
2705 [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,
2706 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2707 [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,
2708 [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
2709 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
2710 [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr,
2711 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2712 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2713 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2714 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2715 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2716 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
2717 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2718 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2719 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2720 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2721 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2722 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2723 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2724 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2725 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2726 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
2727 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2728 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2729 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2730 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
2731 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
2732 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2733 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2734 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2735 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
2736 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2737 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2738 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2739 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2740 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2741 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2742 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2743 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2744 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2745 [GPLL0] = &gpll0.clkr,
2746 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2747 [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
2748 [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
2749 [GPLL0_OUT_TEST] = &gpll0_out_test.clkr,
2750 [GPLL1] = &gpll1.clkr,
2751 [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr,
2752 [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
2753 [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr,
2754 [GPLL1_OUT_TEST] = &gpll1_out_test.clkr,
2755 [GPLL2] = &gpll2.clkr,
2756 [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr,
2757 [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
2758 [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr,
2759 [GPLL2_OUT_TEST] = &gpll2_out_test.clkr,
2760 [GPLL3] = &gpll3.clkr,
2761 [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
2762 [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2763 [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr,
2764 [GPLL3_OUT_TEST] = &gpll3_out_test.clkr,
2765 [GPLL4] = &gpll4.clkr,
2766 [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
2767 [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
2768 [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr,
2769 [GPLL4_OUT_TEST] = &gpll4_out_test.clkr,
2770 [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr,
2771 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
2772 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
2773 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2774 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2775 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2776 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2777 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2778 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2779 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2780 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2781 [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
2782 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
2783 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
2784 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
2785 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
2788 static struct gdsc *gcc_msm8998_gdscs[] = {
2789 [PCIE_0_GDSC] = &pcie_0_gdsc,
2790 [UFS_GDSC] = &ufs_gdsc,
2791 [USB_30_GDSC] = &usb_30_gdsc,
2794 static const struct qcom_reset_map gcc_msm8998_resets[] = {
2795 [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
2796 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
2797 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
2798 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
2799 [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
2800 [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
2801 [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
2802 [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
2803 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
2804 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
2805 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
2806 [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
2807 [GCC_PCIE_0_BCR] = { 0x6b000 },
2808 [GCC_PDM_BCR] = { 0x33000 },
2809 [GCC_SDCC2_BCR] = { 0x14000 },
2810 [GCC_SDCC4_BCR] = { 0x16000 },
2811 [GCC_TSIF_BCR] = { 0x36000 },
2812 [GCC_UFS_BCR] = { 0x75000 },
2813 [GCC_USB_30_BCR] = { 0xf000 },
2814 [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
2815 [GCC_CONFIG_NOC_BCR] = { 0x5000 },
2816 [GCC_AHB2PHY_EAST_BCR] = { 0x7000 },
2817 [GCC_IMEM_BCR] = { 0x8000 },
2818 [GCC_PIMEM_BCR] = { 0xa000 },
2819 [GCC_MMSS_BCR] = { 0xb000 },
2820 [GCC_QDSS_BCR] = { 0xc000 },
2821 [GCC_WCSS_BCR] = { 0x11000 },
2822 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
2823 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
2824 [GCC_BLSP1_BCR] = { 0x17000 },
2825 [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
2826 [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
2827 [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
2828 [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 },
2829 [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 },
2830 [GCC_BLSP2_BCR] = { 0x25000 },
2831 [GCC_BLSP2_UART1_BCR] = { 0x27000 },
2832 [GCC_BLSP2_UART2_BCR] = { 0x29000 },
2833 [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
2834 [GCC_SRAM_SENSOR_BCR] = { 0x2d000 },
2835 [GCC_PRNG_BCR] = { 0x34000 },
2836 [GCC_TSIF_0_RESET] = { 0x36024 },
2837 [GCC_TSIF_1_RESET] = { 0x36028 },
2838 [GCC_TCSR_BCR] = { 0x37000 },
2839 [GCC_BOOT_ROM_BCR] = { 0x38000 },
2840 [GCC_MSG_RAM_BCR] = { 0x39000 },
2841 [GCC_TLMM_BCR] = { 0x3a000 },
2842 [GCC_MPM_BCR] = { 0x3b000 },
2843 [GCC_SEC_CTRL_BCR] = { 0x3d000 },
2844 [GCC_SPMI_BCR] = { 0x3f000 },
2845 [GCC_SPDM_BCR] = { 0x40000 },
2846 [GCC_CE1_BCR] = { 0x41000 },
2847 [GCC_BIMC_BCR] = { 0x44000 },
2848 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
2849 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 },
2850 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 },
2851 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 },
2852 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
2853 [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 },
2854 [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c },
2855 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
2856 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
2857 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
2858 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
2859 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
2860 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
2861 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
2862 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
2863 [GCC_APB2JTAG_BCR] = { 0x4c000 },
2864 [GCC_RBCPR_CX_BCR] = { 0x4e000 },
2865 [GCC_RBCPR_MX_BCR] = { 0x4f000 },
2866 [GCC_USB3_PHY_BCR] = { 0x50020 },
2867 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
2868 [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
2869 [GCC_SSC_BCR] = { 0x63000 },
2870 [GCC_SSC_RESET] = { 0x63020 },
2871 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2872 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
2873 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
2874 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
2875 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
2876 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c },
2877 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 },
2878 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
2879 [GCC_GPU_BCR] = { 0x71000 },
2880 [GCC_SPSS_BCR] = { 0x72000 },
2881 [GCC_OBT_ODT_BCR] = { 0x73000 },
2882 [GCC_VS_BCR] = { 0x7a000 },
2883 [GCC_MSS_VS_RESET] = { 0x7a100 },
2884 [GCC_GPU_VS_RESET] = { 0x7a104 },
2885 [GCC_APC0_VS_RESET] = { 0x7a108 },
2886 [GCC_APC1_VS_RESET] = { 0x7a10c },
2887 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
2888 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
2889 [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 },
2890 [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 },
2891 [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 },
2892 [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 },
2893 [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 },
2894 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 },
2895 [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
2896 [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
2897 [GCC_DCC_BCR] = { 0x84000 },
2898 [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 },
2899 [GCC_IPA_BCR] = { 0x89000 },
2900 [GCC_GLM_BCR] = { 0x8b000 },
2901 [GCC_SKL_BCR] = { 0x8c000 },
2902 [GCC_MSMPU_BCR] = { 0x8d000 },
2905 static const struct regmap_config gcc_msm8998_regmap_config = {
2909 .max_register = 0x8f000,
2913 static const struct qcom_cc_desc gcc_msm8998_desc = {
2914 .config = &gcc_msm8998_regmap_config,
2915 .clks = gcc_msm8998_clocks,
2916 .num_clks = ARRAY_SIZE(gcc_msm8998_clocks),
2917 .resets = gcc_msm8998_resets,
2918 .num_resets = ARRAY_SIZE(gcc_msm8998_resets),
2919 .gdscs = gcc_msm8998_gdscs,
2920 .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
2923 static int gcc_msm8998_probe(struct platform_device *pdev)
2925 struct regmap *regmap;
2928 regmap = qcom_cc_map(pdev, &gcc_msm8998_desc);
2930 return PTR_ERR(regmap);
2933 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
2934 * turned off by hardware during certain apps low power modes.
2936 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
2940 ret = devm_clk_hw_register(&pdev->dev, &xo.hw);
2944 return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
2947 static const struct of_device_id gcc_msm8998_match_table[] = {
2948 { .compatible = "qcom,gcc-msm8998" },
2951 MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table);
2953 static struct platform_driver gcc_msm8998_driver = {
2954 .probe = gcc_msm8998_probe,
2956 .name = "gcc-msm8998",
2957 .of_match_table = gcc_msm8998_match_table,
2961 static int __init gcc_msm8998_init(void)
2963 return platform_driver_register(&gcc_msm8998_driver);
2965 core_initcall(gcc_msm8998_init);
2967 static void __exit gcc_msm8998_exit(void)
2969 platform_driver_unregister(&gcc_msm8998_driver);
2971 module_exit(gcc_msm8998_exit);
2973 MODULE_DESCRIPTION("QCOM GCC msm8998 Driver");
2974 MODULE_LICENSE("GPL v2");
2975 MODULE_ALIAS("platform:gcc-msm8998");