1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
18 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
21 #include "clk-regmap.h"
24 #include "clk-branch.h"
25 #include "clk-hfpll.h"
28 static struct clk_pll pll3 = {
36 .clkr.hw.init = &(struct clk_init_data){
38 .parent_data = &(const struct clk_parent_data){
39 .fw_name = "pxo", .name = "pxo_board",
46 static struct clk_regmap pll4_vote = {
48 .enable_mask = BIT(4),
49 .hw.init = &(struct clk_init_data){
51 .parent_data = &(const struct clk_parent_data){
52 .fw_name = "pll4", .name = "pll4",
55 .ops = &clk_pll_vote_ops,
59 static struct clk_pll pll8 = {
67 .clkr.hw.init = &(struct clk_init_data){
69 .parent_data = &(const struct clk_parent_data){
70 .fw_name = "pxo", .name = "pxo_board",
77 static struct clk_regmap pll8_vote = {
79 .enable_mask = BIT(8),
80 .hw.init = &(struct clk_init_data){
82 .parent_hws = (const struct clk_hw*[]){
86 .ops = &clk_pll_vote_ops,
90 static struct hfpll_data hfpll0_data = {
97 .config_val = 0x7845c665,
99 .droop_val = 0x0108c000,
100 .min_rate = 600000000UL,
101 .max_rate = 1800000000UL,
104 static struct clk_hfpll hfpll0 = {
106 .clkr.hw.init = &(struct clk_init_data){
107 .parent_data = &(const struct clk_parent_data){
108 .fw_name = "pxo", .name = "pxo_board",
112 .ops = &clk_ops_hfpll,
113 .flags = CLK_IGNORE_UNUSED,
115 .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
118 static struct hfpll_data hfpll1_8064_data = {
123 .config_reg = 0x3244,
124 .status_reg = 0x325c,
125 .config_val = 0x7845c665,
127 .droop_val = 0x0108c000,
128 .min_rate = 600000000UL,
129 .max_rate = 1800000000UL,
132 static struct hfpll_data hfpll1_data = {
137 .config_reg = 0x3304,
138 .status_reg = 0x331c,
139 .config_val = 0x7845c665,
141 .droop_val = 0x0108c000,
142 .min_rate = 600000000UL,
143 .max_rate = 1800000000UL,
146 static struct clk_hfpll hfpll1 = {
148 .clkr.hw.init = &(struct clk_init_data){
149 .parent_data = &(const struct clk_parent_data){
150 .fw_name = "pxo", .name = "pxo_board",
154 .ops = &clk_ops_hfpll,
155 .flags = CLK_IGNORE_UNUSED,
157 .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
160 static struct hfpll_data hfpll2_data = {
165 .config_reg = 0x3284,
166 .status_reg = 0x329c,
167 .config_val = 0x7845c665,
169 .droop_val = 0x0108c000,
170 .min_rate = 600000000UL,
171 .max_rate = 1800000000UL,
174 static struct clk_hfpll hfpll2 = {
176 .clkr.hw.init = &(struct clk_init_data){
177 .parent_data = &(const struct clk_parent_data){
178 .fw_name = "pxo", .name = "pxo_board",
182 .ops = &clk_ops_hfpll,
183 .flags = CLK_IGNORE_UNUSED,
185 .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
188 static struct hfpll_data hfpll3_data = {
193 .config_reg = 0x32c4,
194 .status_reg = 0x32dc,
195 .config_val = 0x7845c665,
197 .droop_val = 0x0108c000,
198 .min_rate = 600000000UL,
199 .max_rate = 1800000000UL,
202 static struct clk_hfpll hfpll3 = {
204 .clkr.hw.init = &(struct clk_init_data){
205 .parent_data = &(const struct clk_parent_data){
206 .fw_name = "pxo", .name = "pxo_board",
210 .ops = &clk_ops_hfpll,
211 .flags = CLK_IGNORE_UNUSED,
213 .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
216 static struct hfpll_data hfpll_l2_8064_data = {
221 .config_reg = 0x3304,
222 .status_reg = 0x331c,
223 .config_val = 0x7845c665,
225 .droop_val = 0x0108c000,
226 .min_rate = 600000000UL,
227 .max_rate = 1800000000UL,
230 static struct hfpll_data hfpll_l2_data = {
235 .config_reg = 0x3404,
236 .status_reg = 0x341c,
237 .config_val = 0x7845c665,
239 .droop_val = 0x0108c000,
240 .min_rate = 600000000UL,
241 .max_rate = 1800000000UL,
244 static struct clk_hfpll hfpll_l2 = {
246 .clkr.hw.init = &(struct clk_init_data){
247 .parent_data = &(const struct clk_parent_data){
248 .fw_name = "pxo", .name = "pxo_board",
252 .ops = &clk_ops_hfpll,
253 .flags = CLK_IGNORE_UNUSED,
255 .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
258 static struct clk_pll pll14 = {
262 .config_reg = 0x31d4,
264 .status_reg = 0x31d8,
266 .clkr.hw.init = &(struct clk_init_data){
268 .parent_data = &(const struct clk_parent_data){
269 .fw_name = "pxo", .name = "pxo_board",
276 static struct clk_regmap pll14_vote = {
277 .enable_reg = 0x34c0,
278 .enable_mask = BIT(14),
279 .hw.init = &(struct clk_init_data){
280 .name = "pll14_vote",
281 .parent_hws = (const struct clk_hw*[]){
285 .ops = &clk_pll_vote_ops,
296 static const struct parent_map gcc_pxo_pll8_map[] = {
301 static const struct clk_parent_data gcc_pxo_pll8[] = {
302 { .fw_name = "pxo", .name = "pxo_board" },
303 { .hw = &pll8_vote.hw },
306 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
312 static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
313 { .fw_name = "pxo", .name = "pxo_board" },
314 { .hw = &pll8_vote.hw },
315 { .fw_name = "cxo", .name = "cxo_board" },
318 static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
324 static const struct clk_parent_data gcc_pxo_pll8_pll3[] = {
325 { .fw_name = "pxo", .name = "pxo_board" },
326 { .hw = &pll8_vote.hw },
327 { .hw = &pll3.clkr.hw },
330 static struct freq_tbl clk_tbl_gsbi_uart[] = {
331 { 1843200, P_PLL8, 2, 6, 625 },
332 { 3686400, P_PLL8, 2, 12, 625 },
333 { 7372800, P_PLL8, 2, 24, 625 },
334 { 14745600, P_PLL8, 2, 48, 625 },
335 { 16000000, P_PLL8, 4, 1, 6 },
336 { 24000000, P_PLL8, 4, 1, 4 },
337 { 32000000, P_PLL8, 4, 1, 3 },
338 { 40000000, P_PLL8, 1, 5, 48 },
339 { 46400000, P_PLL8, 1, 29, 240 },
340 { 48000000, P_PLL8, 4, 1, 2 },
341 { 51200000, P_PLL8, 1, 2, 15 },
342 { 56000000, P_PLL8, 1, 7, 48 },
343 { 58982400, P_PLL8, 1, 96, 625 },
344 { 64000000, P_PLL8, 2, 1, 3 },
348 static struct clk_rcg gsbi1_uart_src = {
353 .mnctr_reset_bit = 7,
354 .mnctr_mode_shift = 5,
365 .parent_map = gcc_pxo_pll8_map,
367 .freq_tbl = clk_tbl_gsbi_uart,
369 .enable_reg = 0x29d4,
370 .enable_mask = BIT(11),
371 .hw.init = &(struct clk_init_data){
372 .name = "gsbi1_uart_src",
373 .parent_data = gcc_pxo_pll8,
374 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
376 .flags = CLK_SET_PARENT_GATE,
381 static struct clk_branch gsbi1_uart_clk = {
385 .enable_reg = 0x29d4,
386 .enable_mask = BIT(9),
387 .hw.init = &(struct clk_init_data){
388 .name = "gsbi1_uart_clk",
389 .parent_hws = (const struct clk_hw*[]){
390 &gsbi1_uart_src.clkr.hw
393 .ops = &clk_branch_ops,
394 .flags = CLK_SET_RATE_PARENT,
399 static struct clk_rcg gsbi2_uart_src = {
404 .mnctr_reset_bit = 7,
405 .mnctr_mode_shift = 5,
416 .parent_map = gcc_pxo_pll8_map,
418 .freq_tbl = clk_tbl_gsbi_uart,
420 .enable_reg = 0x29f4,
421 .enable_mask = BIT(11),
422 .hw.init = &(struct clk_init_data){
423 .name = "gsbi2_uart_src",
424 .parent_data = gcc_pxo_pll8,
425 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
427 .flags = CLK_SET_PARENT_GATE,
432 static struct clk_branch gsbi2_uart_clk = {
436 .enable_reg = 0x29f4,
437 .enable_mask = BIT(9),
438 .hw.init = &(struct clk_init_data){
439 .name = "gsbi2_uart_clk",
440 .parent_hws = (const struct clk_hw*[]){
441 &gsbi2_uart_src.clkr.hw
444 .ops = &clk_branch_ops,
445 .flags = CLK_SET_RATE_PARENT,
450 static struct clk_rcg gsbi3_uart_src = {
455 .mnctr_reset_bit = 7,
456 .mnctr_mode_shift = 5,
467 .parent_map = gcc_pxo_pll8_map,
469 .freq_tbl = clk_tbl_gsbi_uart,
471 .enable_reg = 0x2a14,
472 .enable_mask = BIT(11),
473 .hw.init = &(struct clk_init_data){
474 .name = "gsbi3_uart_src",
475 .parent_data = gcc_pxo_pll8,
476 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
478 .flags = CLK_SET_PARENT_GATE,
483 static struct clk_branch gsbi3_uart_clk = {
487 .enable_reg = 0x2a14,
488 .enable_mask = BIT(9),
489 .hw.init = &(struct clk_init_data){
490 .name = "gsbi3_uart_clk",
491 .parent_hws = (const struct clk_hw*[]){
492 &gsbi3_uart_src.clkr.hw
495 .ops = &clk_branch_ops,
496 .flags = CLK_SET_RATE_PARENT,
501 static struct clk_rcg gsbi4_uart_src = {
506 .mnctr_reset_bit = 7,
507 .mnctr_mode_shift = 5,
518 .parent_map = gcc_pxo_pll8_map,
520 .freq_tbl = clk_tbl_gsbi_uart,
522 .enable_reg = 0x2a34,
523 .enable_mask = BIT(11),
524 .hw.init = &(struct clk_init_data){
525 .name = "gsbi4_uart_src",
526 .parent_data = gcc_pxo_pll8,
527 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
529 .flags = CLK_SET_PARENT_GATE,
534 static struct clk_branch gsbi4_uart_clk = {
538 .enable_reg = 0x2a34,
539 .enable_mask = BIT(9),
540 .hw.init = &(struct clk_init_data){
541 .name = "gsbi4_uart_clk",
542 .parent_hws = (const struct clk_hw*[]){
543 &gsbi4_uart_src.clkr.hw
546 .ops = &clk_branch_ops,
547 .flags = CLK_SET_RATE_PARENT,
552 static struct clk_rcg gsbi5_uart_src = {
557 .mnctr_reset_bit = 7,
558 .mnctr_mode_shift = 5,
569 .parent_map = gcc_pxo_pll8_map,
571 .freq_tbl = clk_tbl_gsbi_uart,
573 .enable_reg = 0x2a54,
574 .enable_mask = BIT(11),
575 .hw.init = &(struct clk_init_data){
576 .name = "gsbi5_uart_src",
577 .parent_data = gcc_pxo_pll8,
578 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
580 .flags = CLK_SET_PARENT_GATE,
585 static struct clk_branch gsbi5_uart_clk = {
589 .enable_reg = 0x2a54,
590 .enable_mask = BIT(9),
591 .hw.init = &(struct clk_init_data){
592 .name = "gsbi5_uart_clk",
593 .parent_hws = (const struct clk_hw*[]){
594 &gsbi5_uart_src.clkr.hw
597 .ops = &clk_branch_ops,
598 .flags = CLK_SET_RATE_PARENT,
603 static struct clk_rcg gsbi6_uart_src = {
608 .mnctr_reset_bit = 7,
609 .mnctr_mode_shift = 5,
620 .parent_map = gcc_pxo_pll8_map,
622 .freq_tbl = clk_tbl_gsbi_uart,
624 .enable_reg = 0x2a74,
625 .enable_mask = BIT(11),
626 .hw.init = &(struct clk_init_data){
627 .name = "gsbi6_uart_src",
628 .parent_data = gcc_pxo_pll8,
629 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
631 .flags = CLK_SET_PARENT_GATE,
636 static struct clk_branch gsbi6_uart_clk = {
640 .enable_reg = 0x2a74,
641 .enable_mask = BIT(9),
642 .hw.init = &(struct clk_init_data){
643 .name = "gsbi6_uart_clk",
644 .parent_hws = (const struct clk_hw*[]){
645 &gsbi6_uart_src.clkr.hw
648 .ops = &clk_branch_ops,
649 .flags = CLK_SET_RATE_PARENT,
654 static struct clk_rcg gsbi7_uart_src = {
659 .mnctr_reset_bit = 7,
660 .mnctr_mode_shift = 5,
671 .parent_map = gcc_pxo_pll8_map,
673 .freq_tbl = clk_tbl_gsbi_uart,
675 .enable_reg = 0x2a94,
676 .enable_mask = BIT(11),
677 .hw.init = &(struct clk_init_data){
678 .name = "gsbi7_uart_src",
679 .parent_data = gcc_pxo_pll8,
680 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
682 .flags = CLK_SET_PARENT_GATE,
687 static struct clk_branch gsbi7_uart_clk = {
691 .enable_reg = 0x2a94,
692 .enable_mask = BIT(9),
693 .hw.init = &(struct clk_init_data){
694 .name = "gsbi7_uart_clk",
695 .parent_hws = (const struct clk_hw*[]){
696 &gsbi7_uart_src.clkr.hw
699 .ops = &clk_branch_ops,
700 .flags = CLK_SET_RATE_PARENT,
705 static struct clk_rcg gsbi8_uart_src = {
710 .mnctr_reset_bit = 7,
711 .mnctr_mode_shift = 5,
722 .parent_map = gcc_pxo_pll8_map,
724 .freq_tbl = clk_tbl_gsbi_uart,
726 .enable_reg = 0x2ab4,
727 .enable_mask = BIT(11),
728 .hw.init = &(struct clk_init_data){
729 .name = "gsbi8_uart_src",
730 .parent_data = gcc_pxo_pll8,
731 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
733 .flags = CLK_SET_PARENT_GATE,
738 static struct clk_branch gsbi8_uart_clk = {
742 .enable_reg = 0x2ab4,
743 .enable_mask = BIT(9),
744 .hw.init = &(struct clk_init_data){
745 .name = "gsbi8_uart_clk",
746 .parent_hws = (const struct clk_hw*[]){
747 &gsbi8_uart_src.clkr.hw
750 .ops = &clk_branch_ops,
751 .flags = CLK_SET_RATE_PARENT,
756 static struct clk_rcg gsbi9_uart_src = {
761 .mnctr_reset_bit = 7,
762 .mnctr_mode_shift = 5,
773 .parent_map = gcc_pxo_pll8_map,
775 .freq_tbl = clk_tbl_gsbi_uart,
777 .enable_reg = 0x2ad4,
778 .enable_mask = BIT(11),
779 .hw.init = &(struct clk_init_data){
780 .name = "gsbi9_uart_src",
781 .parent_data = gcc_pxo_pll8,
782 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
784 .flags = CLK_SET_PARENT_GATE,
789 static struct clk_branch gsbi9_uart_clk = {
793 .enable_reg = 0x2ad4,
794 .enable_mask = BIT(9),
795 .hw.init = &(struct clk_init_data){
796 .name = "gsbi9_uart_clk",
797 .parent_hws = (const struct clk_hw*[]){
798 &gsbi9_uart_src.clkr.hw
801 .ops = &clk_branch_ops,
802 .flags = CLK_SET_RATE_PARENT,
807 static struct clk_rcg gsbi10_uart_src = {
812 .mnctr_reset_bit = 7,
813 .mnctr_mode_shift = 5,
824 .parent_map = gcc_pxo_pll8_map,
826 .freq_tbl = clk_tbl_gsbi_uart,
828 .enable_reg = 0x2af4,
829 .enable_mask = BIT(11),
830 .hw.init = &(struct clk_init_data){
831 .name = "gsbi10_uart_src",
832 .parent_data = gcc_pxo_pll8,
833 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
835 .flags = CLK_SET_PARENT_GATE,
840 static struct clk_branch gsbi10_uart_clk = {
844 .enable_reg = 0x2af4,
845 .enable_mask = BIT(9),
846 .hw.init = &(struct clk_init_data){
847 .name = "gsbi10_uart_clk",
848 .parent_hws = (const struct clk_hw*[]){
849 &gsbi10_uart_src.clkr.hw
852 .ops = &clk_branch_ops,
853 .flags = CLK_SET_RATE_PARENT,
858 static struct clk_rcg gsbi11_uart_src = {
863 .mnctr_reset_bit = 7,
864 .mnctr_mode_shift = 5,
875 .parent_map = gcc_pxo_pll8_map,
877 .freq_tbl = clk_tbl_gsbi_uart,
879 .enable_reg = 0x2b14,
880 .enable_mask = BIT(11),
881 .hw.init = &(struct clk_init_data){
882 .name = "gsbi11_uart_src",
883 .parent_data = gcc_pxo_pll8,
884 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
886 .flags = CLK_SET_PARENT_GATE,
891 static struct clk_branch gsbi11_uart_clk = {
895 .enable_reg = 0x2b14,
896 .enable_mask = BIT(9),
897 .hw.init = &(struct clk_init_data){
898 .name = "gsbi11_uart_clk",
899 .parent_hws = (const struct clk_hw*[]){
900 &gsbi11_uart_src.clkr.hw
903 .ops = &clk_branch_ops,
904 .flags = CLK_SET_RATE_PARENT,
909 static struct clk_rcg gsbi12_uart_src = {
914 .mnctr_reset_bit = 7,
915 .mnctr_mode_shift = 5,
926 .parent_map = gcc_pxo_pll8_map,
928 .freq_tbl = clk_tbl_gsbi_uart,
930 .enable_reg = 0x2b34,
931 .enable_mask = BIT(11),
932 .hw.init = &(struct clk_init_data){
933 .name = "gsbi12_uart_src",
934 .parent_data = gcc_pxo_pll8,
935 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
937 .flags = CLK_SET_PARENT_GATE,
942 static struct clk_branch gsbi12_uart_clk = {
946 .enable_reg = 0x2b34,
947 .enable_mask = BIT(9),
948 .hw.init = &(struct clk_init_data){
949 .name = "gsbi12_uart_clk",
950 .parent_hws = (const struct clk_hw*[]){
951 &gsbi12_uart_src.clkr.hw
954 .ops = &clk_branch_ops,
955 .flags = CLK_SET_RATE_PARENT,
960 static struct freq_tbl clk_tbl_gsbi_qup[] = {
961 { 1100000, P_PXO, 1, 2, 49 },
962 { 5400000, P_PXO, 1, 1, 5 },
963 { 10800000, P_PXO, 1, 2, 5 },
964 { 15060000, P_PLL8, 1, 2, 51 },
965 { 24000000, P_PLL8, 4, 1, 4 },
966 { 25600000, P_PLL8, 1, 1, 15 },
967 { 27000000, P_PXO, 1, 0, 0 },
968 { 48000000, P_PLL8, 4, 1, 2 },
969 { 51200000, P_PLL8, 1, 2, 15 },
973 static struct clk_rcg gsbi1_qup_src = {
978 .mnctr_reset_bit = 7,
979 .mnctr_mode_shift = 5,
990 .parent_map = gcc_pxo_pll8_map,
992 .freq_tbl = clk_tbl_gsbi_qup,
994 .enable_reg = 0x29cc,
995 .enable_mask = BIT(11),
996 .hw.init = &(struct clk_init_data){
997 .name = "gsbi1_qup_src",
998 .parent_data = gcc_pxo_pll8,
999 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1000 .ops = &clk_rcg_ops,
1001 .flags = CLK_SET_PARENT_GATE,
1006 static struct clk_branch gsbi1_qup_clk = {
1010 .enable_reg = 0x29cc,
1011 .enable_mask = BIT(9),
1012 .hw.init = &(struct clk_init_data){
1013 .name = "gsbi1_qup_clk",
1014 .parent_hws = (const struct clk_hw*[]){
1015 &gsbi1_qup_src.clkr.hw
1018 .ops = &clk_branch_ops,
1019 .flags = CLK_SET_RATE_PARENT,
1024 static struct clk_rcg gsbi2_qup_src = {
1029 .mnctr_reset_bit = 7,
1030 .mnctr_mode_shift = 5,
1041 .parent_map = gcc_pxo_pll8_map,
1043 .freq_tbl = clk_tbl_gsbi_qup,
1045 .enable_reg = 0x29ec,
1046 .enable_mask = BIT(11),
1047 .hw.init = &(struct clk_init_data){
1048 .name = "gsbi2_qup_src",
1049 .parent_data = gcc_pxo_pll8,
1050 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1051 .ops = &clk_rcg_ops,
1052 .flags = CLK_SET_PARENT_GATE,
1057 static struct clk_branch gsbi2_qup_clk = {
1061 .enable_reg = 0x29ec,
1062 .enable_mask = BIT(9),
1063 .hw.init = &(struct clk_init_data){
1064 .name = "gsbi2_qup_clk",
1065 .parent_hws = (const struct clk_hw*[]){
1066 &gsbi2_qup_src.clkr.hw
1069 .ops = &clk_branch_ops,
1070 .flags = CLK_SET_RATE_PARENT,
1075 static struct clk_rcg gsbi3_qup_src = {
1080 .mnctr_reset_bit = 7,
1081 .mnctr_mode_shift = 5,
1092 .parent_map = gcc_pxo_pll8_map,
1094 .freq_tbl = clk_tbl_gsbi_qup,
1096 .enable_reg = 0x2a0c,
1097 .enable_mask = BIT(11),
1098 .hw.init = &(struct clk_init_data){
1099 .name = "gsbi3_qup_src",
1100 .parent_data = gcc_pxo_pll8,
1101 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1102 .ops = &clk_rcg_ops,
1103 .flags = CLK_SET_PARENT_GATE,
1108 static struct clk_branch gsbi3_qup_clk = {
1112 .enable_reg = 0x2a0c,
1113 .enable_mask = BIT(9),
1114 .hw.init = &(struct clk_init_data){
1115 .name = "gsbi3_qup_clk",
1116 .parent_hws = (const struct clk_hw*[]){
1117 &gsbi3_qup_src.clkr.hw
1120 .ops = &clk_branch_ops,
1121 .flags = CLK_SET_RATE_PARENT,
1126 static struct clk_rcg gsbi4_qup_src = {
1131 .mnctr_reset_bit = 7,
1132 .mnctr_mode_shift = 5,
1143 .parent_map = gcc_pxo_pll8_map,
1145 .freq_tbl = clk_tbl_gsbi_qup,
1147 .enable_reg = 0x2a2c,
1148 .enable_mask = BIT(11),
1149 .hw.init = &(struct clk_init_data){
1150 .name = "gsbi4_qup_src",
1151 .parent_data = gcc_pxo_pll8,
1152 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1153 .ops = &clk_rcg_ops,
1154 .flags = CLK_SET_PARENT_GATE,
1159 static struct clk_branch gsbi4_qup_clk = {
1163 .enable_reg = 0x2a2c,
1164 .enable_mask = BIT(9),
1165 .hw.init = &(struct clk_init_data){
1166 .name = "gsbi4_qup_clk",
1167 .parent_hws = (const struct clk_hw*[]){
1168 &gsbi4_qup_src.clkr.hw
1171 .ops = &clk_branch_ops,
1172 .flags = CLK_SET_RATE_PARENT,
1177 static struct clk_rcg gsbi5_qup_src = {
1182 .mnctr_reset_bit = 7,
1183 .mnctr_mode_shift = 5,
1194 .parent_map = gcc_pxo_pll8_map,
1196 .freq_tbl = clk_tbl_gsbi_qup,
1198 .enable_reg = 0x2a4c,
1199 .enable_mask = BIT(11),
1200 .hw.init = &(struct clk_init_data){
1201 .name = "gsbi5_qup_src",
1202 .parent_data = gcc_pxo_pll8,
1203 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1204 .ops = &clk_rcg_ops,
1205 .flags = CLK_SET_PARENT_GATE,
1210 static struct clk_branch gsbi5_qup_clk = {
1214 .enable_reg = 0x2a4c,
1215 .enable_mask = BIT(9),
1216 .hw.init = &(struct clk_init_data){
1217 .name = "gsbi5_qup_clk",
1218 .parent_hws = (const struct clk_hw*[]){
1219 &gsbi5_qup_src.clkr.hw
1222 .ops = &clk_branch_ops,
1223 .flags = CLK_SET_RATE_PARENT,
1228 static struct clk_rcg gsbi6_qup_src = {
1233 .mnctr_reset_bit = 7,
1234 .mnctr_mode_shift = 5,
1245 .parent_map = gcc_pxo_pll8_map,
1247 .freq_tbl = clk_tbl_gsbi_qup,
1249 .enable_reg = 0x2a6c,
1250 .enable_mask = BIT(11),
1251 .hw.init = &(struct clk_init_data){
1252 .name = "gsbi6_qup_src",
1253 .parent_data = gcc_pxo_pll8,
1254 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1255 .ops = &clk_rcg_ops,
1256 .flags = CLK_SET_PARENT_GATE,
1261 static struct clk_branch gsbi6_qup_clk = {
1265 .enable_reg = 0x2a6c,
1266 .enable_mask = BIT(9),
1267 .hw.init = &(struct clk_init_data){
1268 .name = "gsbi6_qup_clk",
1269 .parent_hws = (const struct clk_hw*[]){
1270 &gsbi6_qup_src.clkr.hw
1273 .ops = &clk_branch_ops,
1274 .flags = CLK_SET_RATE_PARENT,
1279 static struct clk_rcg gsbi7_qup_src = {
1284 .mnctr_reset_bit = 7,
1285 .mnctr_mode_shift = 5,
1296 .parent_map = gcc_pxo_pll8_map,
1298 .freq_tbl = clk_tbl_gsbi_qup,
1300 .enable_reg = 0x2a8c,
1301 .enable_mask = BIT(11),
1302 .hw.init = &(struct clk_init_data){
1303 .name = "gsbi7_qup_src",
1304 .parent_data = gcc_pxo_pll8,
1305 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1306 .ops = &clk_rcg_ops,
1307 .flags = CLK_SET_PARENT_GATE,
1312 static struct clk_branch gsbi7_qup_clk = {
1316 .enable_reg = 0x2a8c,
1317 .enable_mask = BIT(9),
1318 .hw.init = &(struct clk_init_data){
1319 .name = "gsbi7_qup_clk",
1320 .parent_hws = (const struct clk_hw*[]){
1321 &gsbi7_qup_src.clkr.hw
1324 .ops = &clk_branch_ops,
1325 .flags = CLK_SET_RATE_PARENT,
1330 static struct clk_rcg gsbi8_qup_src = {
1335 .mnctr_reset_bit = 7,
1336 .mnctr_mode_shift = 5,
1347 .parent_map = gcc_pxo_pll8_map,
1349 .freq_tbl = clk_tbl_gsbi_qup,
1351 .enable_reg = 0x2aac,
1352 .enable_mask = BIT(11),
1353 .hw.init = &(struct clk_init_data){
1354 .name = "gsbi8_qup_src",
1355 .parent_data = gcc_pxo_pll8,
1356 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1357 .ops = &clk_rcg_ops,
1358 .flags = CLK_SET_PARENT_GATE,
1363 static struct clk_branch gsbi8_qup_clk = {
1367 .enable_reg = 0x2aac,
1368 .enable_mask = BIT(9),
1369 .hw.init = &(struct clk_init_data){
1370 .name = "gsbi8_qup_clk",
1371 .parent_hws = (const struct clk_hw*[]){
1372 &gsbi8_qup_src.clkr.hw
1375 .ops = &clk_branch_ops,
1376 .flags = CLK_SET_RATE_PARENT,
1381 static struct clk_rcg gsbi9_qup_src = {
1386 .mnctr_reset_bit = 7,
1387 .mnctr_mode_shift = 5,
1398 .parent_map = gcc_pxo_pll8_map,
1400 .freq_tbl = clk_tbl_gsbi_qup,
1402 .enable_reg = 0x2acc,
1403 .enable_mask = BIT(11),
1404 .hw.init = &(struct clk_init_data){
1405 .name = "gsbi9_qup_src",
1406 .parent_data = gcc_pxo_pll8,
1407 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1408 .ops = &clk_rcg_ops,
1409 .flags = CLK_SET_PARENT_GATE,
1414 static struct clk_branch gsbi9_qup_clk = {
1418 .enable_reg = 0x2acc,
1419 .enable_mask = BIT(9),
1420 .hw.init = &(struct clk_init_data){
1421 .name = "gsbi9_qup_clk",
1422 .parent_hws = (const struct clk_hw*[]){
1423 &gsbi9_qup_src.clkr.hw
1426 .ops = &clk_branch_ops,
1427 .flags = CLK_SET_RATE_PARENT,
1432 static struct clk_rcg gsbi10_qup_src = {
1437 .mnctr_reset_bit = 7,
1438 .mnctr_mode_shift = 5,
1449 .parent_map = gcc_pxo_pll8_map,
1451 .freq_tbl = clk_tbl_gsbi_qup,
1453 .enable_reg = 0x2aec,
1454 .enable_mask = BIT(11),
1455 .hw.init = &(struct clk_init_data){
1456 .name = "gsbi10_qup_src",
1457 .parent_data = gcc_pxo_pll8,
1458 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1459 .ops = &clk_rcg_ops,
1460 .flags = CLK_SET_PARENT_GATE,
1465 static struct clk_branch gsbi10_qup_clk = {
1469 .enable_reg = 0x2aec,
1470 .enable_mask = BIT(9),
1471 .hw.init = &(struct clk_init_data){
1472 .name = "gsbi10_qup_clk",
1473 .parent_hws = (const struct clk_hw*[]){
1474 &gsbi10_qup_src.clkr.hw
1477 .ops = &clk_branch_ops,
1478 .flags = CLK_SET_RATE_PARENT,
1483 static struct clk_rcg gsbi11_qup_src = {
1488 .mnctr_reset_bit = 7,
1489 .mnctr_mode_shift = 5,
1500 .parent_map = gcc_pxo_pll8_map,
1502 .freq_tbl = clk_tbl_gsbi_qup,
1504 .enable_reg = 0x2b0c,
1505 .enable_mask = BIT(11),
1506 .hw.init = &(struct clk_init_data){
1507 .name = "gsbi11_qup_src",
1508 .parent_data = gcc_pxo_pll8,
1509 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1510 .ops = &clk_rcg_ops,
1511 .flags = CLK_SET_PARENT_GATE,
1516 static struct clk_branch gsbi11_qup_clk = {
1520 .enable_reg = 0x2b0c,
1521 .enable_mask = BIT(9),
1522 .hw.init = &(struct clk_init_data){
1523 .name = "gsbi11_qup_clk",
1524 .parent_hws = (const struct clk_hw*[]){
1525 &gsbi11_qup_src.clkr.hw
1528 .ops = &clk_branch_ops,
1529 .flags = CLK_SET_RATE_PARENT,
1534 static struct clk_rcg gsbi12_qup_src = {
1539 .mnctr_reset_bit = 7,
1540 .mnctr_mode_shift = 5,
1551 .parent_map = gcc_pxo_pll8_map,
1553 .freq_tbl = clk_tbl_gsbi_qup,
1555 .enable_reg = 0x2b2c,
1556 .enable_mask = BIT(11),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "gsbi12_qup_src",
1559 .parent_data = gcc_pxo_pll8,
1560 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1561 .ops = &clk_rcg_ops,
1562 .flags = CLK_SET_PARENT_GATE,
1567 static struct clk_branch gsbi12_qup_clk = {
1571 .enable_reg = 0x2b2c,
1572 .enable_mask = BIT(9),
1573 .hw.init = &(struct clk_init_data){
1574 .name = "gsbi12_qup_clk",
1575 .parent_hws = (const struct clk_hw*[]){
1576 &gsbi12_qup_src.clkr.hw
1579 .ops = &clk_branch_ops,
1580 .flags = CLK_SET_RATE_PARENT,
1585 static const struct freq_tbl clk_tbl_gp[] = {
1586 { 9600000, P_CXO, 2, 0, 0 },
1587 { 13500000, P_PXO, 2, 0, 0 },
1588 { 19200000, P_CXO, 1, 0, 0 },
1589 { 27000000, P_PXO, 1, 0, 0 },
1590 { 64000000, P_PLL8, 2, 1, 3 },
1591 { 76800000, P_PLL8, 1, 1, 5 },
1592 { 96000000, P_PLL8, 4, 0, 0 },
1593 { 128000000, P_PLL8, 3, 0, 0 },
1594 { 192000000, P_PLL8, 2, 0, 0 },
1598 static struct clk_rcg gp0_src = {
1603 .mnctr_reset_bit = 7,
1604 .mnctr_mode_shift = 5,
1615 .parent_map = gcc_pxo_pll8_cxo_map,
1617 .freq_tbl = clk_tbl_gp,
1619 .enable_reg = 0x2d24,
1620 .enable_mask = BIT(11),
1621 .hw.init = &(struct clk_init_data){
1623 .parent_data = gcc_pxo_pll8_cxo,
1624 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1625 .ops = &clk_rcg_ops,
1626 .flags = CLK_SET_PARENT_GATE,
1631 static struct clk_branch gp0_clk = {
1635 .enable_reg = 0x2d24,
1636 .enable_mask = BIT(9),
1637 .hw.init = &(struct clk_init_data){
1639 .parent_hws = (const struct clk_hw*[]){
1643 .ops = &clk_branch_ops,
1644 .flags = CLK_SET_RATE_PARENT,
1649 static struct clk_rcg gp1_src = {
1654 .mnctr_reset_bit = 7,
1655 .mnctr_mode_shift = 5,
1666 .parent_map = gcc_pxo_pll8_cxo_map,
1668 .freq_tbl = clk_tbl_gp,
1670 .enable_reg = 0x2d44,
1671 .enable_mask = BIT(11),
1672 .hw.init = &(struct clk_init_data){
1674 .parent_data = gcc_pxo_pll8_cxo,
1675 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1676 .ops = &clk_rcg_ops,
1677 .flags = CLK_SET_RATE_GATE,
1682 static struct clk_branch gp1_clk = {
1686 .enable_reg = 0x2d44,
1687 .enable_mask = BIT(9),
1688 .hw.init = &(struct clk_init_data){
1690 .parent_hws = (const struct clk_hw*[]){
1694 .ops = &clk_branch_ops,
1695 .flags = CLK_SET_RATE_PARENT,
1700 static struct clk_rcg gp2_src = {
1705 .mnctr_reset_bit = 7,
1706 .mnctr_mode_shift = 5,
1717 .parent_map = gcc_pxo_pll8_cxo_map,
1719 .freq_tbl = clk_tbl_gp,
1721 .enable_reg = 0x2d64,
1722 .enable_mask = BIT(11),
1723 .hw.init = &(struct clk_init_data){
1725 .parent_data = gcc_pxo_pll8_cxo,
1726 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1727 .ops = &clk_rcg_ops,
1728 .flags = CLK_SET_RATE_GATE,
1733 static struct clk_branch gp2_clk = {
1737 .enable_reg = 0x2d64,
1738 .enable_mask = BIT(9),
1739 .hw.init = &(struct clk_init_data){
1741 .parent_hws = (const struct clk_hw*[]){
1745 .ops = &clk_branch_ops,
1746 .flags = CLK_SET_RATE_PARENT,
1751 static struct clk_branch pmem_clk = {
1757 .enable_reg = 0x25a0,
1758 .enable_mask = BIT(4),
1759 .hw.init = &(struct clk_init_data){
1761 .ops = &clk_branch_ops,
1766 static struct clk_rcg prng_src = {
1774 .parent_map = gcc_pxo_pll8_map,
1777 .hw.init = &(struct clk_init_data){
1779 .parent_data = gcc_pxo_pll8,
1780 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1781 .ops = &clk_rcg_ops,
1786 static struct clk_branch prng_clk = {
1788 .halt_check = BRANCH_HALT_VOTED,
1791 .enable_reg = 0x3080,
1792 .enable_mask = BIT(10),
1793 .hw.init = &(struct clk_init_data){
1795 .parent_hws = (const struct clk_hw*[]){
1799 .ops = &clk_branch_ops,
1804 static const struct freq_tbl clk_tbl_sdc[] = {
1805 { 144000, P_PXO, 3, 2, 125 },
1806 { 400000, P_PLL8, 4, 1, 240 },
1807 { 16000000, P_PLL8, 4, 1, 6 },
1808 { 17070000, P_PLL8, 1, 2, 45 },
1809 { 20210000, P_PLL8, 1, 1, 19 },
1810 { 24000000, P_PLL8, 4, 1, 4 },
1811 { 48000000, P_PLL8, 4, 1, 2 },
1812 { 64000000, P_PLL8, 3, 1, 2 },
1813 { 96000000, P_PLL8, 4, 0, 0 },
1814 { 192000000, P_PLL8, 2, 0, 0 },
1818 static struct clk_rcg sdc1_src = {
1823 .mnctr_reset_bit = 7,
1824 .mnctr_mode_shift = 5,
1835 .parent_map = gcc_pxo_pll8_map,
1837 .freq_tbl = clk_tbl_sdc,
1839 .enable_reg = 0x282c,
1840 .enable_mask = BIT(11),
1841 .hw.init = &(struct clk_init_data){
1843 .parent_data = gcc_pxo_pll8,
1844 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1845 .ops = &clk_rcg_ops,
1850 static struct clk_branch sdc1_clk = {
1854 .enable_reg = 0x282c,
1855 .enable_mask = BIT(9),
1856 .hw.init = &(struct clk_init_data){
1858 .parent_hws = (const struct clk_hw*[]){
1862 .ops = &clk_branch_ops,
1863 .flags = CLK_SET_RATE_PARENT,
1868 static struct clk_rcg sdc2_src = {
1873 .mnctr_reset_bit = 7,
1874 .mnctr_mode_shift = 5,
1885 .parent_map = gcc_pxo_pll8_map,
1887 .freq_tbl = clk_tbl_sdc,
1889 .enable_reg = 0x284c,
1890 .enable_mask = BIT(11),
1891 .hw.init = &(struct clk_init_data){
1893 .parent_data = gcc_pxo_pll8,
1894 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1895 .ops = &clk_rcg_ops,
1900 static struct clk_branch sdc2_clk = {
1904 .enable_reg = 0x284c,
1905 .enable_mask = BIT(9),
1906 .hw.init = &(struct clk_init_data){
1908 .parent_hws = (const struct clk_hw*[]){
1912 .ops = &clk_branch_ops,
1913 .flags = CLK_SET_RATE_PARENT,
1918 static struct clk_rcg sdc3_src = {
1923 .mnctr_reset_bit = 7,
1924 .mnctr_mode_shift = 5,
1935 .parent_map = gcc_pxo_pll8_map,
1937 .freq_tbl = clk_tbl_sdc,
1939 .enable_reg = 0x286c,
1940 .enable_mask = BIT(11),
1941 .hw.init = &(struct clk_init_data){
1943 .parent_data = gcc_pxo_pll8,
1944 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1945 .ops = &clk_rcg_ops,
1950 static struct clk_branch sdc3_clk = {
1954 .enable_reg = 0x286c,
1955 .enable_mask = BIT(9),
1956 .hw.init = &(struct clk_init_data){
1958 .parent_hws = (const struct clk_hw*[]){
1962 .ops = &clk_branch_ops,
1963 .flags = CLK_SET_RATE_PARENT,
1968 static struct clk_rcg sdc4_src = {
1973 .mnctr_reset_bit = 7,
1974 .mnctr_mode_shift = 5,
1985 .parent_map = gcc_pxo_pll8_map,
1987 .freq_tbl = clk_tbl_sdc,
1989 .enable_reg = 0x288c,
1990 .enable_mask = BIT(11),
1991 .hw.init = &(struct clk_init_data){
1993 .parent_data = gcc_pxo_pll8,
1994 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1995 .ops = &clk_rcg_ops,
2000 static struct clk_branch sdc4_clk = {
2004 .enable_reg = 0x288c,
2005 .enable_mask = BIT(9),
2006 .hw.init = &(struct clk_init_data){
2008 .parent_hws = (const struct clk_hw*[]){
2012 .ops = &clk_branch_ops,
2013 .flags = CLK_SET_RATE_PARENT,
2018 static struct clk_rcg sdc5_src = {
2023 .mnctr_reset_bit = 7,
2024 .mnctr_mode_shift = 5,
2035 .parent_map = gcc_pxo_pll8_map,
2037 .freq_tbl = clk_tbl_sdc,
2039 .enable_reg = 0x28ac,
2040 .enable_mask = BIT(11),
2041 .hw.init = &(struct clk_init_data){
2043 .parent_data = gcc_pxo_pll8,
2044 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2045 .ops = &clk_rcg_ops,
2050 static struct clk_branch sdc5_clk = {
2054 .enable_reg = 0x28ac,
2055 .enable_mask = BIT(9),
2056 .hw.init = &(struct clk_init_data){
2058 .parent_hws = (const struct clk_hw*[]){
2062 .ops = &clk_branch_ops,
2063 .flags = CLK_SET_RATE_PARENT,
2068 static const struct freq_tbl clk_tbl_tsif_ref[] = {
2069 { 105000, P_PXO, 1, 1, 256 },
2073 static struct clk_rcg tsif_ref_src = {
2078 .mnctr_reset_bit = 7,
2079 .mnctr_mode_shift = 5,
2090 .parent_map = gcc_pxo_pll8_map,
2092 .freq_tbl = clk_tbl_tsif_ref,
2094 .enable_reg = 0x2710,
2095 .enable_mask = BIT(11),
2096 .hw.init = &(struct clk_init_data){
2097 .name = "tsif_ref_src",
2098 .parent_data = gcc_pxo_pll8,
2099 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2100 .ops = &clk_rcg_ops,
2101 .flags = CLK_SET_RATE_GATE,
2106 static struct clk_branch tsif_ref_clk = {
2110 .enable_reg = 0x2710,
2111 .enable_mask = BIT(9),
2112 .hw.init = &(struct clk_init_data){
2113 .name = "tsif_ref_clk",
2114 .parent_hws = (const struct clk_hw*[]){
2115 &tsif_ref_src.clkr.hw
2118 .ops = &clk_branch_ops,
2119 .flags = CLK_SET_RATE_PARENT,
2124 static const struct freq_tbl clk_tbl_usb[] = {
2125 { 60000000, P_PLL8, 1, 5, 32 },
2129 static struct clk_rcg usb_hs1_xcvr_src = {
2134 .mnctr_reset_bit = 7,
2135 .mnctr_mode_shift = 5,
2146 .parent_map = gcc_pxo_pll8_map,
2148 .freq_tbl = clk_tbl_usb,
2150 .enable_reg = 0x290c,
2151 .enable_mask = BIT(11),
2152 .hw.init = &(struct clk_init_data){
2153 .name = "usb_hs1_xcvr_src",
2154 .parent_data = gcc_pxo_pll8,
2155 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2156 .ops = &clk_rcg_ops,
2157 .flags = CLK_SET_RATE_GATE,
2162 static struct clk_branch usb_hs1_xcvr_clk = {
2166 .enable_reg = 0x290c,
2167 .enable_mask = BIT(9),
2168 .hw.init = &(struct clk_init_data){
2169 .name = "usb_hs1_xcvr_clk",
2170 .parent_hws = (const struct clk_hw*[]){
2171 &usb_hs1_xcvr_src.clkr.hw
2174 .ops = &clk_branch_ops,
2175 .flags = CLK_SET_RATE_PARENT,
2180 static struct clk_rcg usb_hs3_xcvr_src = {
2185 .mnctr_reset_bit = 7,
2186 .mnctr_mode_shift = 5,
2197 .parent_map = gcc_pxo_pll8_map,
2199 .freq_tbl = clk_tbl_usb,
2201 .enable_reg = 0x370c,
2202 .enable_mask = BIT(11),
2203 .hw.init = &(struct clk_init_data){
2204 .name = "usb_hs3_xcvr_src",
2205 .parent_data = gcc_pxo_pll8,
2206 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2207 .ops = &clk_rcg_ops,
2208 .flags = CLK_SET_RATE_GATE,
2213 static struct clk_branch usb_hs3_xcvr_clk = {
2217 .enable_reg = 0x370c,
2218 .enable_mask = BIT(9),
2219 .hw.init = &(struct clk_init_data){
2220 .name = "usb_hs3_xcvr_clk",
2221 .parent_hws = (const struct clk_hw*[]){
2222 &usb_hs3_xcvr_src.clkr.hw
2225 .ops = &clk_branch_ops,
2226 .flags = CLK_SET_RATE_PARENT,
2231 static struct clk_rcg usb_hs4_xcvr_src = {
2236 .mnctr_reset_bit = 7,
2237 .mnctr_mode_shift = 5,
2248 .parent_map = gcc_pxo_pll8_map,
2250 .freq_tbl = clk_tbl_usb,
2252 .enable_reg = 0x372c,
2253 .enable_mask = BIT(11),
2254 .hw.init = &(struct clk_init_data){
2255 .name = "usb_hs4_xcvr_src",
2256 .parent_data = gcc_pxo_pll8,
2257 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2258 .ops = &clk_rcg_ops,
2259 .flags = CLK_SET_RATE_GATE,
2264 static struct clk_branch usb_hs4_xcvr_clk = {
2268 .enable_reg = 0x372c,
2269 .enable_mask = BIT(9),
2270 .hw.init = &(struct clk_init_data){
2271 .name = "usb_hs4_xcvr_clk",
2272 .parent_hws = (const struct clk_hw*[]){
2273 &usb_hs4_xcvr_src.clkr.hw
2276 .ops = &clk_branch_ops,
2277 .flags = CLK_SET_RATE_PARENT,
2282 static struct clk_rcg usb_hsic_xcvr_fs_src = {
2287 .mnctr_reset_bit = 7,
2288 .mnctr_mode_shift = 5,
2299 .parent_map = gcc_pxo_pll8_map,
2301 .freq_tbl = clk_tbl_usb,
2303 .enable_reg = 0x2928,
2304 .enable_mask = BIT(11),
2305 .hw.init = &(struct clk_init_data){
2306 .name = "usb_hsic_xcvr_fs_src",
2307 .parent_data = gcc_pxo_pll8,
2308 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2309 .ops = &clk_rcg_ops,
2310 .flags = CLK_SET_RATE_GATE,
2315 static struct clk_branch usb_hsic_xcvr_fs_clk = {
2319 .enable_reg = 0x2928,
2320 .enable_mask = BIT(9),
2321 .hw.init = &(struct clk_init_data){
2322 .name = "usb_hsic_xcvr_fs_clk",
2323 .parent_hws = (const struct clk_hw*[]){
2324 &usb_hsic_xcvr_fs_src.clkr.hw,
2327 .ops = &clk_branch_ops,
2328 .flags = CLK_SET_RATE_PARENT,
2333 static struct clk_branch usb_hsic_system_clk = {
2337 .enable_reg = 0x292c,
2338 .enable_mask = BIT(4),
2339 .hw.init = &(struct clk_init_data){
2340 .parent_hws = (const struct clk_hw*[]){
2341 &usb_hsic_xcvr_fs_src.clkr.hw,
2344 .name = "usb_hsic_system_clk",
2345 .ops = &clk_branch_ops,
2346 .flags = CLK_SET_RATE_PARENT,
2351 static struct clk_branch usb_hsic_hsic_clk = {
2355 .enable_reg = 0x2b44,
2356 .enable_mask = BIT(0),
2357 .hw.init = &(struct clk_init_data){
2358 .parent_hws = (const struct clk_hw*[]){
2362 .name = "usb_hsic_hsic_clk",
2363 .ops = &clk_branch_ops,
2368 static struct clk_branch usb_hsic_hsio_cal_clk = {
2372 .enable_reg = 0x2b48,
2373 .enable_mask = BIT(0),
2374 .hw.init = &(struct clk_init_data){
2375 .name = "usb_hsic_hsio_cal_clk",
2376 .ops = &clk_branch_ops,
2381 static struct clk_rcg usb_fs1_xcvr_fs_src = {
2386 .mnctr_reset_bit = 7,
2387 .mnctr_mode_shift = 5,
2398 .parent_map = gcc_pxo_pll8_map,
2400 .freq_tbl = clk_tbl_usb,
2402 .enable_reg = 0x2968,
2403 .enable_mask = BIT(11),
2404 .hw.init = &(struct clk_init_data){
2405 .name = "usb_fs1_xcvr_fs_src",
2406 .parent_data = gcc_pxo_pll8,
2407 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2408 .ops = &clk_rcg_ops,
2409 .flags = CLK_SET_RATE_GATE,
2414 static struct clk_branch usb_fs1_xcvr_fs_clk = {
2418 .enable_reg = 0x2968,
2419 .enable_mask = BIT(9),
2420 .hw.init = &(struct clk_init_data){
2421 .name = "usb_fs1_xcvr_fs_clk",
2422 .parent_hws = (const struct clk_hw*[]){
2423 &usb_fs1_xcvr_fs_src.clkr.hw,
2426 .ops = &clk_branch_ops,
2427 .flags = CLK_SET_RATE_PARENT,
2432 static struct clk_branch usb_fs1_system_clk = {
2436 .enable_reg = 0x296c,
2437 .enable_mask = BIT(4),
2438 .hw.init = &(struct clk_init_data){
2439 .parent_hws = (const struct clk_hw*[]){
2440 &usb_fs1_xcvr_fs_src.clkr.hw,
2443 .name = "usb_fs1_system_clk",
2444 .ops = &clk_branch_ops,
2445 .flags = CLK_SET_RATE_PARENT,
2450 static struct clk_rcg usb_fs2_xcvr_fs_src = {
2455 .mnctr_reset_bit = 7,
2456 .mnctr_mode_shift = 5,
2467 .parent_map = gcc_pxo_pll8_map,
2469 .freq_tbl = clk_tbl_usb,
2471 .enable_reg = 0x2988,
2472 .enable_mask = BIT(11),
2473 .hw.init = &(struct clk_init_data){
2474 .name = "usb_fs2_xcvr_fs_src",
2475 .parent_data = gcc_pxo_pll8,
2476 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2477 .ops = &clk_rcg_ops,
2478 .flags = CLK_SET_RATE_GATE,
2483 static struct clk_branch usb_fs2_xcvr_fs_clk = {
2487 .enable_reg = 0x2988,
2488 .enable_mask = BIT(9),
2489 .hw.init = &(struct clk_init_data){
2490 .name = "usb_fs2_xcvr_fs_clk",
2491 .parent_hws = (const struct clk_hw*[]){
2492 &usb_fs2_xcvr_fs_src.clkr.hw,
2495 .ops = &clk_branch_ops,
2496 .flags = CLK_SET_RATE_PARENT,
2501 static struct clk_branch usb_fs2_system_clk = {
2505 .enable_reg = 0x298c,
2506 .enable_mask = BIT(4),
2507 .hw.init = &(struct clk_init_data){
2508 .name = "usb_fs2_system_clk",
2509 .parent_hws = (const struct clk_hw*[]){
2510 &usb_fs2_xcvr_fs_src.clkr.hw,
2513 .ops = &clk_branch_ops,
2514 .flags = CLK_SET_RATE_PARENT,
2519 static struct clk_branch ce1_core_clk = {
2525 .enable_reg = 0x2724,
2526 .enable_mask = BIT(4),
2527 .hw.init = &(struct clk_init_data){
2528 .name = "ce1_core_clk",
2529 .ops = &clk_branch_ops,
2534 static struct clk_branch ce1_h_clk = {
2538 .enable_reg = 0x2720,
2539 .enable_mask = BIT(4),
2540 .hw.init = &(struct clk_init_data){
2541 .name = "ce1_h_clk",
2542 .ops = &clk_branch_ops,
2547 static struct clk_branch dma_bam_h_clk = {
2553 .enable_reg = 0x25c0,
2554 .enable_mask = BIT(4),
2555 .hw.init = &(struct clk_init_data){
2556 .name = "dma_bam_h_clk",
2557 .ops = &clk_branch_ops,
2562 static struct clk_branch gsbi1_h_clk = {
2568 .enable_reg = 0x29c0,
2569 .enable_mask = BIT(4),
2570 .hw.init = &(struct clk_init_data){
2571 .name = "gsbi1_h_clk",
2572 .ops = &clk_branch_ops,
2577 static struct clk_branch gsbi2_h_clk = {
2583 .enable_reg = 0x29e0,
2584 .enable_mask = BIT(4),
2585 .hw.init = &(struct clk_init_data){
2586 .name = "gsbi2_h_clk",
2587 .ops = &clk_branch_ops,
2592 static struct clk_branch gsbi3_h_clk = {
2598 .enable_reg = 0x2a00,
2599 .enable_mask = BIT(4),
2600 .hw.init = &(struct clk_init_data){
2601 .name = "gsbi3_h_clk",
2602 .ops = &clk_branch_ops,
2607 static struct clk_branch gsbi4_h_clk = {
2613 .enable_reg = 0x2a20,
2614 .enable_mask = BIT(4),
2615 .hw.init = &(struct clk_init_data){
2616 .name = "gsbi4_h_clk",
2617 .ops = &clk_branch_ops,
2622 static struct clk_branch gsbi5_h_clk = {
2628 .enable_reg = 0x2a40,
2629 .enable_mask = BIT(4),
2630 .hw.init = &(struct clk_init_data){
2631 .name = "gsbi5_h_clk",
2632 .ops = &clk_branch_ops,
2637 static struct clk_branch gsbi6_h_clk = {
2643 .enable_reg = 0x2a60,
2644 .enable_mask = BIT(4),
2645 .hw.init = &(struct clk_init_data){
2646 .name = "gsbi6_h_clk",
2647 .ops = &clk_branch_ops,
2652 static struct clk_branch gsbi7_h_clk = {
2658 .enable_reg = 0x2a80,
2659 .enable_mask = BIT(4),
2660 .hw.init = &(struct clk_init_data){
2661 .name = "gsbi7_h_clk",
2662 .ops = &clk_branch_ops,
2667 static struct clk_branch gsbi8_h_clk = {
2673 .enable_reg = 0x2aa0,
2674 .enable_mask = BIT(4),
2675 .hw.init = &(struct clk_init_data){
2676 .name = "gsbi8_h_clk",
2677 .ops = &clk_branch_ops,
2682 static struct clk_branch gsbi9_h_clk = {
2688 .enable_reg = 0x2ac0,
2689 .enable_mask = BIT(4),
2690 .hw.init = &(struct clk_init_data){
2691 .name = "gsbi9_h_clk",
2692 .ops = &clk_branch_ops,
2697 static struct clk_branch gsbi10_h_clk = {
2703 .enable_reg = 0x2ae0,
2704 .enable_mask = BIT(4),
2705 .hw.init = &(struct clk_init_data){
2706 .name = "gsbi10_h_clk",
2707 .ops = &clk_branch_ops,
2712 static struct clk_branch gsbi11_h_clk = {
2718 .enable_reg = 0x2b00,
2719 .enable_mask = BIT(4),
2720 .hw.init = &(struct clk_init_data){
2721 .name = "gsbi11_h_clk",
2722 .ops = &clk_branch_ops,
2727 static struct clk_branch gsbi12_h_clk = {
2733 .enable_reg = 0x2b20,
2734 .enable_mask = BIT(4),
2735 .hw.init = &(struct clk_init_data){
2736 .name = "gsbi12_h_clk",
2737 .ops = &clk_branch_ops,
2742 static struct clk_branch tsif_h_clk = {
2748 .enable_reg = 0x2700,
2749 .enable_mask = BIT(4),
2750 .hw.init = &(struct clk_init_data){
2751 .name = "tsif_h_clk",
2752 .ops = &clk_branch_ops,
2757 static struct clk_branch usb_fs1_h_clk = {
2761 .enable_reg = 0x2960,
2762 .enable_mask = BIT(4),
2763 .hw.init = &(struct clk_init_data){
2764 .name = "usb_fs1_h_clk",
2765 .ops = &clk_branch_ops,
2770 static struct clk_branch usb_fs2_h_clk = {
2774 .enable_reg = 0x2980,
2775 .enable_mask = BIT(4),
2776 .hw.init = &(struct clk_init_data){
2777 .name = "usb_fs2_h_clk",
2778 .ops = &clk_branch_ops,
2783 static struct clk_branch usb_hs1_h_clk = {
2789 .enable_reg = 0x2900,
2790 .enable_mask = BIT(4),
2791 .hw.init = &(struct clk_init_data){
2792 .name = "usb_hs1_h_clk",
2793 .ops = &clk_branch_ops,
2798 static struct clk_branch usb_hs3_h_clk = {
2802 .enable_reg = 0x3700,
2803 .enable_mask = BIT(4),
2804 .hw.init = &(struct clk_init_data){
2805 .name = "usb_hs3_h_clk",
2806 .ops = &clk_branch_ops,
2811 static struct clk_branch usb_hs4_h_clk = {
2815 .enable_reg = 0x3720,
2816 .enable_mask = BIT(4),
2817 .hw.init = &(struct clk_init_data){
2818 .name = "usb_hs4_h_clk",
2819 .ops = &clk_branch_ops,
2824 static struct clk_branch usb_hsic_h_clk = {
2828 .enable_reg = 0x2920,
2829 .enable_mask = BIT(4),
2830 .hw.init = &(struct clk_init_data){
2831 .name = "usb_hsic_h_clk",
2832 .ops = &clk_branch_ops,
2837 static struct clk_branch sdc1_h_clk = {
2843 .enable_reg = 0x2820,
2844 .enable_mask = BIT(4),
2845 .hw.init = &(struct clk_init_data){
2846 .name = "sdc1_h_clk",
2847 .ops = &clk_branch_ops,
2852 static struct clk_branch sdc2_h_clk = {
2858 .enable_reg = 0x2840,
2859 .enable_mask = BIT(4),
2860 .hw.init = &(struct clk_init_data){
2861 .name = "sdc2_h_clk",
2862 .ops = &clk_branch_ops,
2867 static struct clk_branch sdc3_h_clk = {
2873 .enable_reg = 0x2860,
2874 .enable_mask = BIT(4),
2875 .hw.init = &(struct clk_init_data){
2876 .name = "sdc3_h_clk",
2877 .ops = &clk_branch_ops,
2882 static struct clk_branch sdc4_h_clk = {
2888 .enable_reg = 0x2880,
2889 .enable_mask = BIT(4),
2890 .hw.init = &(struct clk_init_data){
2891 .name = "sdc4_h_clk",
2892 .ops = &clk_branch_ops,
2897 static struct clk_branch sdc5_h_clk = {
2903 .enable_reg = 0x28a0,
2904 .enable_mask = BIT(4),
2905 .hw.init = &(struct clk_init_data){
2906 .name = "sdc5_h_clk",
2907 .ops = &clk_branch_ops,
2912 static struct clk_branch adm0_clk = {
2914 .halt_check = BRANCH_HALT_VOTED,
2917 .enable_reg = 0x3080,
2918 .enable_mask = BIT(2),
2919 .hw.init = &(struct clk_init_data){
2921 .ops = &clk_branch_ops,
2926 static struct clk_branch adm0_pbus_clk = {
2930 .halt_check = BRANCH_HALT_VOTED,
2933 .enable_reg = 0x3080,
2934 .enable_mask = BIT(3),
2935 .hw.init = &(struct clk_init_data){
2936 .name = "adm0_pbus_clk",
2937 .ops = &clk_branch_ops,
2942 static struct freq_tbl clk_tbl_ce3[] = {
2943 { 48000000, P_PLL8, 8 },
2944 { 100000000, P_PLL3, 12 },
2945 { 120000000, P_PLL3, 10 },
2949 static struct clk_rcg ce3_src = {
2957 .parent_map = gcc_pxo_pll8_pll3_map,
2959 .freq_tbl = clk_tbl_ce3,
2961 .enable_reg = 0x36c0,
2962 .enable_mask = BIT(7),
2963 .hw.init = &(struct clk_init_data){
2965 .parent_data = gcc_pxo_pll8_pll3,
2966 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3),
2967 .ops = &clk_rcg_ops,
2968 .flags = CLK_SET_RATE_GATE,
2973 static struct clk_branch ce3_core_clk = {
2977 .enable_reg = 0x36cc,
2978 .enable_mask = BIT(4),
2979 .hw.init = &(struct clk_init_data){
2980 .name = "ce3_core_clk",
2981 .parent_hws = (const struct clk_hw*[]){
2985 .ops = &clk_branch_ops,
2986 .flags = CLK_SET_RATE_PARENT,
2991 static struct clk_branch ce3_h_clk = {
2995 .enable_reg = 0x36c4,
2996 .enable_mask = BIT(4),
2997 .hw.init = &(struct clk_init_data){
2998 .name = "ce3_h_clk",
2999 .parent_hws = (const struct clk_hw*[]){
3003 .ops = &clk_branch_ops,
3004 .flags = CLK_SET_RATE_PARENT,
3009 static const struct freq_tbl clk_tbl_sata_ref[] = {
3010 { 48000000, P_PLL8, 8, 0, 0 },
3011 { 100000000, P_PLL3, 12, 0, 0 },
3015 static struct clk_rcg sata_clk_src = {
3023 .parent_map = gcc_pxo_pll8_pll3_map,
3025 .freq_tbl = clk_tbl_sata_ref,
3027 .enable_reg = 0x2c08,
3028 .enable_mask = BIT(7),
3029 .hw.init = &(struct clk_init_data){
3030 .name = "sata_clk_src",
3031 .parent_data = gcc_pxo_pll8_pll3,
3032 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3),
3033 .ops = &clk_rcg_ops,
3034 .flags = CLK_SET_RATE_GATE,
3039 static struct clk_branch sata_rxoob_clk = {
3043 .enable_reg = 0x2c0c,
3044 .enable_mask = BIT(4),
3045 .hw.init = &(struct clk_init_data){
3046 .name = "sata_rxoob_clk",
3047 .parent_hws = (const struct clk_hw*[]){
3048 &sata_clk_src.clkr.hw,
3051 .ops = &clk_branch_ops,
3052 .flags = CLK_SET_RATE_PARENT,
3057 static struct clk_branch sata_pmalive_clk = {
3061 .enable_reg = 0x2c10,
3062 .enable_mask = BIT(4),
3063 .hw.init = &(struct clk_init_data){
3064 .name = "sata_pmalive_clk",
3065 .parent_hws = (const struct clk_hw*[]){
3066 &sata_clk_src.clkr.hw,
3069 .ops = &clk_branch_ops,
3070 .flags = CLK_SET_RATE_PARENT,
3075 static struct clk_branch sata_phy_ref_clk = {
3079 .enable_reg = 0x2c14,
3080 .enable_mask = BIT(4),
3081 .hw.init = &(struct clk_init_data){
3082 .name = "sata_phy_ref_clk",
3083 .parent_data = &(const struct clk_parent_data){
3084 .fw_name = "pxo", .name = "pxo_board",
3087 .ops = &clk_branch_ops,
3092 static struct clk_branch sata_a_clk = {
3096 .enable_reg = 0x2c20,
3097 .enable_mask = BIT(4),
3098 .hw.init = &(struct clk_init_data){
3099 .name = "sata_a_clk",
3100 .ops = &clk_branch_ops,
3105 static struct clk_branch sata_h_clk = {
3109 .enable_reg = 0x2c00,
3110 .enable_mask = BIT(4),
3111 .hw.init = &(struct clk_init_data){
3112 .name = "sata_h_clk",
3113 .ops = &clk_branch_ops,
3118 static struct clk_branch sfab_sata_s_h_clk = {
3122 .enable_reg = 0x2480,
3123 .enable_mask = BIT(4),
3124 .hw.init = &(struct clk_init_data){
3125 .name = "sfab_sata_s_h_clk",
3126 .ops = &clk_branch_ops,
3131 static struct clk_branch sata_phy_cfg_clk = {
3135 .enable_reg = 0x2c40,
3136 .enable_mask = BIT(4),
3137 .hw.init = &(struct clk_init_data){
3138 .name = "sata_phy_cfg_clk",
3139 .ops = &clk_branch_ops,
3144 static struct clk_branch pcie_phy_ref_clk = {
3148 .enable_reg = 0x22d0,
3149 .enable_mask = BIT(4),
3150 .hw.init = &(struct clk_init_data){
3151 .name = "pcie_phy_ref_clk",
3152 .ops = &clk_branch_ops,
3157 static struct clk_branch pcie_h_clk = {
3161 .enable_reg = 0x22cc,
3162 .enable_mask = BIT(4),
3163 .hw.init = &(struct clk_init_data){
3164 .name = "pcie_h_clk",
3165 .ops = &clk_branch_ops,
3170 static struct clk_branch pcie_a_clk = {
3174 .enable_reg = 0x22c0,
3175 .enable_mask = BIT(4),
3176 .hw.init = &(struct clk_init_data){
3177 .name = "pcie_a_clk",
3178 .ops = &clk_branch_ops,
3183 static struct clk_branch pmic_arb0_h_clk = {
3185 .halt_check = BRANCH_HALT_VOTED,
3188 .enable_reg = 0x3080,
3189 .enable_mask = BIT(8),
3190 .hw.init = &(struct clk_init_data){
3191 .name = "pmic_arb0_h_clk",
3192 .ops = &clk_branch_ops,
3197 static struct clk_branch pmic_arb1_h_clk = {
3199 .halt_check = BRANCH_HALT_VOTED,
3202 .enable_reg = 0x3080,
3203 .enable_mask = BIT(9),
3204 .hw.init = &(struct clk_init_data){
3205 .name = "pmic_arb1_h_clk",
3206 .ops = &clk_branch_ops,
3211 static struct clk_branch pmic_ssbi2_clk = {
3213 .halt_check = BRANCH_HALT_VOTED,
3216 .enable_reg = 0x3080,
3217 .enable_mask = BIT(7),
3218 .hw.init = &(struct clk_init_data){
3219 .name = "pmic_ssbi2_clk",
3220 .ops = &clk_branch_ops,
3225 static struct clk_branch rpm_msg_ram_h_clk = {
3229 .halt_check = BRANCH_HALT_VOTED,
3232 .enable_reg = 0x3080,
3233 .enable_mask = BIT(6),
3234 .hw.init = &(struct clk_init_data){
3235 .name = "rpm_msg_ram_h_clk",
3236 .ops = &clk_branch_ops,
3241 static struct clk_regmap *gcc_msm8960_clks[] = {
3242 [PLL3] = &pll3.clkr,
3243 [PLL4_VOTE] = &pll4_vote,
3244 [PLL8] = &pll8.clkr,
3245 [PLL8_VOTE] = &pll8_vote,
3246 [PLL14] = &pll14.clkr,
3247 [PLL14_VOTE] = &pll14_vote,
3248 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3249 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3250 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3251 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3252 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3253 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3254 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3255 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3256 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3257 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3258 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3259 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3260 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3261 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3262 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
3263 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
3264 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
3265 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
3266 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
3267 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
3268 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
3269 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
3270 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
3271 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
3272 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3273 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3274 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3275 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3276 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3277 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3278 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3279 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3280 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3281 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3282 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3283 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3284 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3285 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3286 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
3287 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
3288 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
3289 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
3290 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
3291 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
3292 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
3293 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
3294 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
3295 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
3296 [GP0_SRC] = &gp0_src.clkr,
3297 [GP0_CLK] = &gp0_clk.clkr,
3298 [GP1_SRC] = &gp1_src.clkr,
3299 [GP1_CLK] = &gp1_clk.clkr,
3300 [GP2_SRC] = &gp2_src.clkr,
3301 [GP2_CLK] = &gp2_clk.clkr,
3302 [PMEM_A_CLK] = &pmem_clk.clkr,
3303 [PRNG_SRC] = &prng_src.clkr,
3304 [PRNG_CLK] = &prng_clk.clkr,
3305 [SDC1_SRC] = &sdc1_src.clkr,
3306 [SDC1_CLK] = &sdc1_clk.clkr,
3307 [SDC2_SRC] = &sdc2_src.clkr,
3308 [SDC2_CLK] = &sdc2_clk.clkr,
3309 [SDC3_SRC] = &sdc3_src.clkr,
3310 [SDC3_CLK] = &sdc3_clk.clkr,
3311 [SDC4_SRC] = &sdc4_src.clkr,
3312 [SDC4_CLK] = &sdc4_clk.clkr,
3313 [SDC5_SRC] = &sdc5_src.clkr,
3314 [SDC5_CLK] = &sdc5_clk.clkr,
3315 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3316 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3317 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3318 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3319 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3320 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3321 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3322 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3323 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3324 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3325 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3326 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3327 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
3328 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
3329 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
3330 [CE1_CORE_CLK] = &ce1_core_clk.clkr,
3331 [CE1_H_CLK] = &ce1_h_clk.clkr,
3332 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3333 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3334 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3335 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3336 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3337 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3338 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3339 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3340 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
3341 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
3342 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
3343 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
3344 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
3345 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3346 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3347 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
3348 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3349 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3350 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3351 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3352 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3353 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3354 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
3355 [ADM0_CLK] = &adm0_clk.clkr,
3356 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3357 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3358 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3359 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3360 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3361 [PLL9] = &hfpll0.clkr,
3362 [PLL10] = &hfpll1.clkr,
3363 [PLL12] = &hfpll_l2.clkr,
3366 static const struct qcom_reset_map gcc_msm8960_resets[] = {
3367 [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
3368 [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
3369 [QDSS_STM_RESET] = { 0x2060, 6 },
3370 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3371 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3372 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3373 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3374 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3375 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3376 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3377 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3378 [ADM0_C2_RESET] = { 0x220c, 4},
3379 [ADM0_C1_RESET] = { 0x220c, 3},
3380 [ADM0_C0_RESET] = { 0x220c, 2},
3381 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3382 [ADM0_RESET] = { 0x220c },
3383 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3384 [QDSS_POR_RESET] = { 0x2260, 4 },
3385 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3386 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3387 [QDSS_AXI_RESET] = { 0x2260, 1 },
3388 [QDSS_DBG_RESET] = { 0x2260 },
3389 [PCIE_A_RESET] = { 0x22c0, 7 },
3390 [PCIE_AUX_RESET] = { 0x22c8, 7 },
3391 [PCIE_H_RESET] = { 0x22d0, 7 },
3392 [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
3393 [SFAB_PCIE_S_RESET] = { 0x22d4 },
3394 [SFAB_MSS_M_RESET] = { 0x2340, 7 },
3395 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3396 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3397 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3398 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3399 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3400 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3401 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3402 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3403 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3404 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3405 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3406 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3407 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3408 [PPSS_PROC_RESET] = { 0x2594, 1 },
3409 [PPSS_RESET] = { 0x2594},
3410 [DMA_BAM_RESET] = { 0x25c0, 7 },
3411 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3412 [SLIMBUS_H_RESET] = { 0x2620, 7 },
3413 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3414 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3415 [TSIF_H_RESET] = { 0x2700, 7 },
3416 [CE1_H_RESET] = { 0x2720, 7 },
3417 [CE1_CORE_RESET] = { 0x2724, 7 },
3418 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3419 [CE2_H_RESET] = { 0x2740, 7 },
3420 [CE2_CORE_RESET] = { 0x2744, 7 },
3421 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3422 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3423 [RPM_PROC_RESET] = { 0x27c0, 7 },
3424 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3425 [SDC1_RESET] = { 0x2830 },
3426 [SDC2_RESET] = { 0x2850 },
3427 [SDC3_RESET] = { 0x2870 },
3428 [SDC4_RESET] = { 0x2890 },
3429 [SDC5_RESET] = { 0x28b0 },
3430 [DFAB_A2_RESET] = { 0x28c0, 7 },
3431 [USB_HS1_RESET] = { 0x2910 },
3432 [USB_HSIC_RESET] = { 0x2934 },
3433 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3434 [USB_FS1_RESET] = { 0x2974 },
3435 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
3436 [USB_FS2_RESET] = { 0x2994 },
3437 [GSBI1_RESET] = { 0x29dc },
3438 [GSBI2_RESET] = { 0x29fc },
3439 [GSBI3_RESET] = { 0x2a1c },
3440 [GSBI4_RESET] = { 0x2a3c },
3441 [GSBI5_RESET] = { 0x2a5c },
3442 [GSBI6_RESET] = { 0x2a7c },
3443 [GSBI7_RESET] = { 0x2a9c },
3444 [GSBI8_RESET] = { 0x2abc },
3445 [GSBI9_RESET] = { 0x2adc },
3446 [GSBI10_RESET] = { 0x2afc },
3447 [GSBI11_RESET] = { 0x2b1c },
3448 [GSBI12_RESET] = { 0x2b3c },
3449 [SPDM_RESET] = { 0x2b6c },
3450 [TLMM_H_RESET] = { 0x2ba0, 7 },
3451 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
3452 [MSS_SLP_RESET] = { 0x2c60, 7 },
3453 [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
3454 [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
3455 [MSS_RESET] = { 0x2c64 },
3456 [SATA_H_RESET] = { 0x2c80, 7 },
3457 [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
3458 [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
3459 [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
3460 [TSSC_RESET] = { 0x2ca0, 7 },
3461 [PDM_RESET] = { 0x2cc0, 12 },
3462 [MPM_H_RESET] = { 0x2da0, 7 },
3463 [MPM_RESET] = { 0x2da4 },
3464 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3465 [PRNG_RESET] = { 0x2e80, 12 },
3466 [RIVA_RESET] = { 0x35e0 },
3469 static struct clk_regmap *gcc_apq8064_clks[] = {
3470 [PLL3] = &pll3.clkr,
3471 [PLL4_VOTE] = &pll4_vote,
3472 [PLL8] = &pll8.clkr,
3473 [PLL8_VOTE] = &pll8_vote,
3474 [PLL14] = &pll14.clkr,
3475 [PLL14_VOTE] = &pll14_vote,
3476 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3477 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3478 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3479 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3480 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3481 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3482 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3483 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3484 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3485 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3486 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3487 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3488 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3489 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3490 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3491 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3492 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3493 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3494 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3495 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3496 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3497 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3498 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3499 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3500 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3501 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3502 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3503 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3504 [GP0_SRC] = &gp0_src.clkr,
3505 [GP0_CLK] = &gp0_clk.clkr,
3506 [GP1_SRC] = &gp1_src.clkr,
3507 [GP1_CLK] = &gp1_clk.clkr,
3508 [GP2_SRC] = &gp2_src.clkr,
3509 [GP2_CLK] = &gp2_clk.clkr,
3510 [PMEM_A_CLK] = &pmem_clk.clkr,
3511 [PRNG_SRC] = &prng_src.clkr,
3512 [PRNG_CLK] = &prng_clk.clkr,
3513 [SDC1_SRC] = &sdc1_src.clkr,
3514 [SDC1_CLK] = &sdc1_clk.clkr,
3515 [SDC2_SRC] = &sdc2_src.clkr,
3516 [SDC2_CLK] = &sdc2_clk.clkr,
3517 [SDC3_SRC] = &sdc3_src.clkr,
3518 [SDC3_CLK] = &sdc3_clk.clkr,
3519 [SDC4_SRC] = &sdc4_src.clkr,
3520 [SDC4_CLK] = &sdc4_clk.clkr,
3521 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3522 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3523 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3524 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3525 [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3526 [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3527 [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3528 [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3529 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3530 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3531 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3532 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3533 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3534 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3535 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3536 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3537 [SATA_H_CLK] = &sata_h_clk.clkr,
3538 [SATA_CLK_SRC] = &sata_clk_src.clkr,
3539 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3540 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3541 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3542 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3543 [SATA_A_CLK] = &sata_a_clk.clkr,
3544 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3545 [CE3_SRC] = &ce3_src.clkr,
3546 [CE3_CORE_CLK] = &ce3_core_clk.clkr,
3547 [CE3_H_CLK] = &ce3_h_clk.clkr,
3548 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3549 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3550 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3551 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3552 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3553 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3554 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3555 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3556 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3557 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3558 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3559 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3560 [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3561 [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
3562 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3563 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3564 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3565 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3566 [ADM0_CLK] = &adm0_clk.clkr,
3567 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3568 [PCIE_A_CLK] = &pcie_a_clk.clkr,
3569 [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3570 [PCIE_H_CLK] = &pcie_h_clk.clkr,
3571 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3572 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3573 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3574 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3575 [PLL9] = &hfpll0.clkr,
3576 [PLL10] = &hfpll1.clkr,
3577 [PLL12] = &hfpll_l2.clkr,
3578 [PLL16] = &hfpll2.clkr,
3579 [PLL17] = &hfpll3.clkr,
3582 static const struct qcom_reset_map gcc_apq8064_resets[] = {
3583 [QDSS_STM_RESET] = { 0x2060, 6 },
3584 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3585 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3586 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3587 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3588 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3589 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3590 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3591 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3592 [ADM0_C2_RESET] = { 0x220c, 4},
3593 [ADM0_C1_RESET] = { 0x220c, 3},
3594 [ADM0_C0_RESET] = { 0x220c, 2},
3595 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3596 [ADM0_RESET] = { 0x220c },
3597 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3598 [QDSS_POR_RESET] = { 0x2260, 4 },
3599 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3600 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3601 [QDSS_AXI_RESET] = { 0x2260, 1 },
3602 [QDSS_DBG_RESET] = { 0x2260 },
3603 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3604 [SFAB_PCIE_S_RESET] = { 0x22d8 },
3605 [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3606 [PCIE_PHY_RESET] = { 0x22dc, 5 },
3607 [PCIE_PCI_RESET] = { 0x22dc, 4 },
3608 [PCIE_POR_RESET] = { 0x22dc, 3 },
3609 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3610 [PCIE_ACLK_RESET] = { 0x22dc },
3611 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3612 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3613 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3614 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3615 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3616 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3617 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3618 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3619 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3620 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3621 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3622 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3623 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3624 [PPSS_PROC_RESET] = { 0x2594, 1 },
3625 [PPSS_RESET] = { 0x2594},
3626 [DMA_BAM_RESET] = { 0x25c0, 7 },
3627 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3628 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3629 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3630 [TSIF_H_RESET] = { 0x2700, 7 },
3631 [CE1_H_RESET] = { 0x2720, 7 },
3632 [CE1_CORE_RESET] = { 0x2724, 7 },
3633 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3634 [CE2_H_RESET] = { 0x2740, 7 },
3635 [CE2_CORE_RESET] = { 0x2744, 7 },
3636 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3637 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3638 [RPM_PROC_RESET] = { 0x27c0, 7 },
3639 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3640 [SDC1_RESET] = { 0x2830 },
3641 [SDC2_RESET] = { 0x2850 },
3642 [SDC3_RESET] = { 0x2870 },
3643 [SDC4_RESET] = { 0x2890 },
3644 [USB_HS1_RESET] = { 0x2910 },
3645 [USB_HSIC_RESET] = { 0x2934 },
3646 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3647 [USB_FS1_RESET] = { 0x2974 },
3648 [GSBI1_RESET] = { 0x29dc },
3649 [GSBI2_RESET] = { 0x29fc },
3650 [GSBI3_RESET] = { 0x2a1c },
3651 [GSBI4_RESET] = { 0x2a3c },
3652 [GSBI5_RESET] = { 0x2a5c },
3653 [GSBI6_RESET] = { 0x2a7c },
3654 [GSBI7_RESET] = { 0x2a9c },
3655 [SPDM_RESET] = { 0x2b6c },
3656 [TLMM_H_RESET] = { 0x2ba0, 7 },
3657 [SATA_SFAB_M_RESET] = { 0x2c18 },
3658 [SATA_RESET] = { 0x2c1c },
3659 [GSS_SLP_RESET] = { 0x2c60, 7 },
3660 [GSS_RESET] = { 0x2c64 },
3661 [TSSC_RESET] = { 0x2ca0, 7 },
3662 [PDM_RESET] = { 0x2cc0, 12 },
3663 [MPM_H_RESET] = { 0x2da0, 7 },
3664 [MPM_RESET] = { 0x2da4 },
3665 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3666 [PRNG_RESET] = { 0x2e80, 12 },
3667 [RIVA_RESET] = { 0x35e0 },
3668 [CE3_H_RESET] = { 0x36c4, 7 },
3669 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3670 [SFAB_CE3_S_RESET] = { 0x36c8 },
3671 [CE3_RESET] = { 0x36cc, 7 },
3672 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3673 [USB_HS3_RESET] = { 0x3710 },
3674 [USB_HS4_RESET] = { 0x3730 },
3677 static const struct regmap_config gcc_msm8960_regmap_config = {
3681 .max_register = 0x3660,
3685 static const struct regmap_config gcc_apq8064_regmap_config = {
3689 .max_register = 0x3880,
3693 static const struct qcom_cc_desc gcc_msm8960_desc = {
3694 .config = &gcc_msm8960_regmap_config,
3695 .clks = gcc_msm8960_clks,
3696 .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
3697 .resets = gcc_msm8960_resets,
3698 .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
3701 static const struct qcom_cc_desc gcc_apq8064_desc = {
3702 .config = &gcc_apq8064_regmap_config,
3703 .clks = gcc_apq8064_clks,
3704 .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
3705 .resets = gcc_apq8064_resets,
3706 .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
3709 static const struct of_device_id gcc_msm8960_match_table[] = {
3710 { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
3711 { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
3714 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
3716 static int gcc_msm8960_probe(struct platform_device *pdev)
3718 struct device *dev = &pdev->dev;
3719 const struct of_device_id *match;
3720 struct platform_device *tsens;
3723 match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
3727 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
3731 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
3735 ret = qcom_cc_probe(pdev, match->data);
3739 if (match->data == &gcc_apq8064_desc) {
3740 hfpll1.d = &hfpll1_8064_data;
3741 hfpll_l2.d = &hfpll_l2_8064_data;
3744 if (of_get_available_child_count(pdev->dev.of_node) != 0)
3745 return devm_of_platform_populate(&pdev->dev);
3747 tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
3750 return PTR_ERR(tsens);
3752 platform_set_drvdata(pdev, tsens);
3757 static int gcc_msm8960_remove(struct platform_device *pdev)
3759 struct platform_device *tsens = platform_get_drvdata(pdev);
3762 platform_device_unregister(tsens);
3767 static struct platform_driver gcc_msm8960_driver = {
3768 .probe = gcc_msm8960_probe,
3769 .remove = gcc_msm8960_remove,
3771 .name = "gcc-msm8960",
3772 .of_match_table = gcc_msm8960_match_table,
3776 static int __init gcc_msm8960_init(void)
3778 return platform_driver_register(&gcc_msm8960_driver);
3780 core_initcall(gcc_msm8960_init);
3782 static void __exit gcc_msm8960_exit(void)
3784 platform_driver_unregister(&gcc_msm8960_driver);
3786 module_exit(gcc_msm8960_exit);
3788 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
3789 MODULE_LICENSE("GPL v2");
3790 MODULE_ALIAS("platform:gcc-msm8960");