drivers/clk/qcom/gcc-msm8917.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2023 Otto Pflüger
   4  *
   5  * Based on gcc-msm8953.c:
   6  *   Copyright 2021, The Linux Foundation. All rights reserved.
   7  * with parts taken from gcc-qcs404.c:
   8  *   Copyright 2018, The Linux Foundation. All rights reserved.
   9  * and gcc-msm8939.c:
  10  *   Copyright 2020 Linaro Limited
  11  * adapted with data from clock-gcc-8952.c in Qualcomm's msm-4.9 release:
  12  *   Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  13  */
  14
  15 #include <linux/bitops.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/err.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regmap.h>
  24 #include <linux/reset-controller.h>
  25
  26 #include <dt-bindings/clock/qcom,gcc-msm8917.h>
  27
  28 #include "clk-alpha-pll.h"
  29 #include "clk-branch.h"
  30 #include "clk-pll.h"
  31 #include "clk-rcg.h"
  32 #include "common.h"
  33 #include "gdsc.h"
  34 #include "reset.h"
  35
  36 enum {
  37         DT_XO,
  38         DT_SLEEP_CLK,
  39         DT_DSI0PLL,
  40         DT_DSI0PLL_BYTE,
  41 };
  42
  43 enum {
  44         P_XO,
  45         P_SLEEP_CLK,
  46         P_GPLL0,
  47         P_GPLL3,
  48         P_GPLL4,
  49         P_GPLL6,
  50         P_DSI0PLL,
  51         P_DSI0PLL_BYTE,
  52 };
  53
  54 static struct clk_alpha_pll gpll0_sleep_clk_src = {
  55         .offset = 0x21000,
  56         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  57         .clkr = {
  58                 .enable_reg = 0x45008,
  59                 .enable_mask = BIT(23),
  60                 .enable_is_inverted = true,
  61                 .hw.init = &(struct clk_init_data){
  62                         .name = "gpll0_sleep_clk_src",
  63                         .parent_data = &(const struct clk_parent_data) {
  64                                 .index = DT_XO,
  65                         },
  66                         .num_parents = 1,
  67                         .ops = &clk_alpha_pll_ops,
  68                 },
  69         },
  70 };
  71
  72 static struct clk_alpha_pll gpll0_early = {
  73         .offset = 0x21000,
  74         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  75         .clkr = {
  76                 .enable_reg = 0x45000,
  77                 .enable_mask = BIT(0),
  78                 .hw.init = &(struct clk_init_data) {
  79                         .name = "gpll0_early",
  80                         .parent_hws = (const struct clk_hw*[]){
  81                                 &gpll0_sleep_clk_src.clkr.hw,
  82                         },
  83                         .num_parents = 1,
  84                         .ops = &clk_alpha_pll_fixed_ops,
  85                 },
  86         },
  87 };
  88
  89 static struct clk_alpha_pll_postdiv gpll0 = {
  90         .offset = 0x21000,
  91         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  92         .clkr.hw.init = &(struct clk_init_data){
  93                 .name = "gpll0",
  94                 .parent_hws = (const struct clk_hw*[]){
  95                         &gpll0_early.clkr.hw,
  96                 },
  97                 .num_parents = 1,
  98                 .ops = &clk_alpha_pll_postdiv_ro_ops,
  99         },
 100 };
 101
 102 static const struct pll_vco gpll3_p_vco[] = {
 103         { 700000000, 1400000000, 0 },
 104 };
 105
 106 static const struct alpha_pll_config gpll3_early_config = {
 107         .l = 63,
 108         .config_ctl_val = 0x4001055b,
 109         .early_output_mask = 0,
 110         .post_div_mask = GENMASK(11, 8),
 111         .post_div_val = BIT(8),
 112 };
 113
 114 static struct clk_alpha_pll gpll3_early = {
 115         .offset = 0x22000,
 116         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 117         .vco_table = gpll3_p_vco,
 118         .num_vco = ARRAY_SIZE(gpll3_p_vco),
 119         .flags = SUPPORTS_DYNAMIC_UPDATE,
 120         .clkr = {
 121                 .hw.init = &(struct clk_init_data){
 122                         .name = "gpll3_early",
 123                         .parent_data = &(const struct clk_parent_data) {
 124                                 .index = DT_XO,
 125                         },
 126                         .num_parents = 1,
 127                         .ops = &clk_alpha_pll_ops,
 128                 },
 129         },
 130 };
 131
 132 static struct clk_alpha_pll_postdiv gpll3 = {
 133         .offset = 0x22000,
 134         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 135         .clkr.hw.init = &(struct clk_init_data){
 136                 .name = "gpll3",
 137                 .parent_hws = (const struct clk_hw*[]){
 138                         &gpll3_early.clkr.hw,
 139                 },
 140                 .num_parents = 1,
 141                 .ops = &clk_alpha_pll_postdiv_ops,
 142                 .flags = CLK_SET_RATE_PARENT,
 143         },
 144 };
 145
 146 static struct clk_alpha_pll gpll4_early = {
 147         .offset = 0x24000,
 148         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 149         .clkr = {
 150                 .enable_reg = 0x45000,
 151                 .enable_mask = BIT(5),
 152                 .hw.init = &(struct clk_init_data){
 153                         .name = "gpll4_early",
 154                         .parent_data = &(const struct clk_parent_data) {
 155                                 .index = DT_XO,
 156                         },
 157                         .num_parents = 1,
 158                         .ops = &clk_alpha_pll_fixed_ops,
 159                 },
 160         },
 161 };
 162
 163 static struct clk_alpha_pll_postdiv gpll4 = {
 164         .offset = 0x24000,
 165         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 166         .clkr.hw.init = &(struct clk_init_data){
 167                 .name = "gpll4",
 168                 .parent_hws = (const struct clk_hw*[]){
 169                         &gpll4_early.clkr.hw,
 170                 },
 171                 .num_parents = 1,
 172                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 173         },
 174 };
 175
 176 static struct clk_pll gpll6_early = {
 177         .l_reg = 0x37004,
 178         .m_reg = 0x37008,
 179         .n_reg = 0x3700c,
 180         .config_reg = 0x37014,
 181         .mode_reg = 0x37000,
 182         .status_reg = 0x3701c,
 183         .status_bit = 17,
 184         .clkr.hw.init = &(struct clk_init_data){
 185                 .name = "gpll6_early",
 186                 .parent_data = &(const struct clk_parent_data) {
 187                         .index = DT_XO,
 188                 },
 189                 .num_parents = 1,
 190                 .ops = &clk_pll_ops,
 191         },
 192 };
 193
 194 static struct clk_regmap gpll6 = {
 195         .enable_reg = 0x45000,
 196         .enable_mask = BIT(7),
 197         .hw.init = &(struct clk_init_data){
 198                 .name = "gpll6",
 199                 .parent_hws = (const struct clk_hw*[]){
 200                         &gpll6_early.clkr.hw,
 201                 },
 202                 .num_parents = 1,
 203                 .ops = &clk_pll_vote_ops,
 204         },
 205 };
 206
 207 static const struct parent_map gcc_xo_gpll0_map[] = {
 208         { P_XO, 0 },
 209         { P_GPLL0, 1 },
 210 };
 211
 212 static const struct parent_map gcc_xo_gpll0_out_aux_map[] = {
 213         { P_XO, 0 },
 214         { P_GPLL0, 2 },
 215 };
 216
 217 static const struct clk_parent_data gcc_xo_gpll0_data[] = {
 218         { .index = DT_XO },
 219         { .hw = &gpll0.clkr.hw },
 220 };
 221
 222 static const struct parent_map gcc_xo_gpll0_gpll6_sleep_map[] = {
 223         { P_XO, 0 },
 224         { P_GPLL0, 1 },
 225         { P_GPLL6, 2 },
 226         { P_SLEEP_CLK, 6 },
 227 };
 228
 229 static const struct clk_parent_data gcc_xo_gpll0_gpll6_sleep_data[] = {
 230         { .index = DT_XO },
 231         { .hw = &gpll0.clkr.hw },
 232         { .hw = &gpll6.hw },
 233         { .index = DT_SLEEP_CLK },
 234 };
 235
 236 static const struct parent_map gcc_xo_gpll0_gpll6_gpll4_map[] = {
 237         { P_XO, 0 },
 238         { P_GPLL0, 1 },
 239         { P_GPLL6, 2 },
 240         { P_GPLL4, 3 },
 241 };
 242
 243 static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll4_data[] = {
 244         { .index = DT_XO },
 245         { .hw = &gpll0.clkr.hw },
 246         { .hw = &gpll6.hw },
 247         { .hw = &gpll4.clkr.hw },
 248 };
 249
 250 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
 251         F(19200000, P_XO, 1, 0, 0),
 252         F(50000000, P_GPLL0, 16, 0, 0),
 253         F(100000000, P_GPLL0, 8, 0, 0),
 254         F(133330000, P_GPLL0, 6, 0, 0),
 255         { }
 256 };
 257
 258 static struct clk_rcg2 apss_ahb_clk_src = {
 259         .cmd_rcgr = 0x46000,
 260         .hid_width = 5,
 261         .freq_tbl = ftbl_apss_ahb_clk_src,
 262         .parent_map = gcc_xo_gpll0_map,
 263         .clkr.hw.init = &(struct clk_init_data) {
 264                 .name = "apss_ahb_clk_src",
 265                 .parent_data = gcc_xo_gpll0_data,
 266                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 267                 .ops = &clk_rcg2_ops,
 268         }
 269 };
 270
 271 static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
 272         F(19200000, P_XO, 1, 0, 0),
 273         F(50000000, P_GPLL0, 16, 0, 0),
 274         { }
 275 };
 276
 277 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 278         .cmd_rcgr = 0x03000,
 279         .hid_width = 5,
 280         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 281         .parent_map = gcc_xo_gpll0_map,
 282         .clkr.hw.init = &(struct clk_init_data) {
 283                 .name = "blsp1_qup2_i2c_apps_clk_src",
 284                 .parent_data = gcc_xo_gpll0_data,
 285                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 286                 .ops = &clk_rcg2_ops,
 287         }
 288 };
 289
 290 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 291         .cmd_rcgr = 0x04000,
 292         .hid_width = 5,
 293         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 294         .parent_map = gcc_xo_gpll0_map,
 295         .clkr.hw.init = &(struct clk_init_data) {
 296                 .name = "blsp1_qup3_i2c_apps_clk_src",
 297                 .parent_data = gcc_xo_gpll0_data,
 298                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 299                 .ops = &clk_rcg2_ops,
 300         }
 301 };
 302
 303 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 304         .cmd_rcgr = 0x05000,
 305         .hid_width = 5,
 306         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 307         .parent_map = gcc_xo_gpll0_map,
 308         .clkr.hw.init = &(struct clk_init_data) {
 309                 .name = "blsp1_qup4_i2c_apps_clk_src",
 310                 .parent_data = gcc_xo_gpll0_data,
 311                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 312                 .ops = &clk_rcg2_ops,
 313         }
 314 };
 315
 316 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 317         .cmd_rcgr = 0x0c00c,
 318         .hid_width = 5,
 319         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 320         .parent_map = gcc_xo_gpll0_map,
 321         .clkr.hw.init = &(struct clk_init_data) {
 322                 .name = "blsp2_qup1_i2c_apps_clk_src",
 323                 .parent_data = gcc_xo_gpll0_data,
 324                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 325                 .ops = &clk_rcg2_ops,
 326         }
 327 };
 328
 329 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 330         .cmd_rcgr = 0x0d000,
 331         .hid_width = 5,
 332         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 333         .parent_map = gcc_xo_gpll0_map,
 334         .clkr.hw.init = &(struct clk_init_data) {
 335                 .name = "blsp2_qup2_i2c_apps_clk_src",
 336                 .parent_data = gcc_xo_gpll0_data,
 337                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 338                 .ops = &clk_rcg2_ops,
 339         }
 340 };
 341
 342 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 343         .cmd_rcgr = 0x0f000,
 344         .hid_width = 5,
 345         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 346         .parent_map = gcc_xo_gpll0_map,
 347         .clkr.hw.init = &(struct clk_init_data) {
 348                 .name = "blsp2_qup3_i2c_apps_clk_src",
 349                 .parent_data = gcc_xo_gpll0_data,
 350                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 351                 .ops = &clk_rcg2_ops,
 352         }
 353 };
 354
 355 static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
 356         F(960000, P_XO, 10, 1, 2),
 357         F(4800000, P_XO, 4, 0, 0),
 358         F(9600000, P_XO, 2, 0, 0),
 359         F(16000000, P_GPLL0, 10, 1, 5),
 360         F(19200000, P_XO, 1, 0, 0),
 361         F(25000000, P_GPLL0, 16, 1, 2),
 362         F(50000000, P_GPLL0, 16, 0, 0),
 363         { }
 364 };
 365
 366 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 367         .cmd_rcgr = 0x03014,
 368         .hid_width = 5,
 369         .mnd_width = 8,
 370         .freq_tbl = ftbl_blsp_spi_apps_clk_src,
 371         .parent_map = gcc_xo_gpll0_map,
 372         .clkr.hw.init = &(struct clk_init_data) {
 373                 .name = "blsp1_qup2_spi_apps_clk_src",
 374                 .parent_data = gcc_xo_gpll0_data,
 375                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 376                 .ops = &clk_rcg2_ops,
 377         }
 378 };
 379
 380 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 381         .cmd_rcgr = 0x04024,
 382         .hid_width = 5,
 383         .mnd_width = 8,
 384         .freq_tbl = ftbl_blsp_spi_apps_clk_src,
 385         .parent_map = gcc_xo_gpll0_map,
 386         .clkr.hw.init = &(struct clk_init_data) {
 387                 .name = "blsp1_qup3_spi_apps_clk_src",
 388                 .parent_data = gcc_xo_gpll0_data,
 389                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 390                 .ops = &clk_rcg2_ops,
 391         }
 392 };
 393
 394 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 395         .cmd_rcgr = 0x05024,
 396         .hid_width = 5,
 397         .mnd_width = 8,
 398         .freq_tbl = ftbl_blsp_spi_apps_clk_src,
 399         .parent_map = gcc_xo_gpll0_map,
 400         .clkr.hw.init = &(struct clk_init_data) {
 401                 .name = "blsp1_qup4_spi_apps_clk_src",
 402                 .parent_data = gcc_xo_gpll0_data,
 403                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 404                 .ops = &clk_rcg2_ops,
 405         }
 406 };
 407
 408 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 409         .cmd_rcgr = 0x0c024,
 410         .hid_width = 5,
 411         .mnd_width = 8,
 412         .freq_tbl = ftbl_blsp_spi_apps_clk_src,
 413         .parent_map = gcc_xo_gpll0_map,
 414         .clkr.hw.init = &(struct clk_init_data) {
 415                 .name = "blsp2_qup1_spi_apps_clk_src",
 416                 .parent_data = gcc_xo_gpll0_data,
 417                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 418                 .ops = &clk_rcg2_ops,
 419         }
 420 };
 421
 422 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 423         .cmd_rcgr = 0x0d014,
 424         .hid_width = 5,
 425         .mnd_width = 8,
 426         .freq_tbl = ftbl_blsp_spi_apps_clk_src,
 427         .parent_map = gcc_xo_gpll0_map,
 428         .clkr.hw.init = &(struct clk_init_data) {
 429                 .name = "blsp2_qup2_spi_apps_clk_src",
 430                 .parent_data = gcc_xo_gpll0_data,
 431                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 432                 .ops = &clk_rcg2_ops,
 433         }
 434 };
 435
 436 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 437         .cmd_rcgr = 0x0f024,
 438         .hid_width = 5,
 439         .mnd_width = 8,
 440         .freq_tbl = ftbl_blsp_spi_apps_clk_src,
 441         .parent_map = gcc_xo_gpll0_map,
 442         .clkr.hw.init = &(struct clk_init_data) {
 443                 .name = "blsp2_qup3_spi_apps_clk_src",
 444                 .parent_data = gcc_xo_gpll0_data,
 445                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 446                 .ops = &clk_rcg2_ops,
 447         }
 448 };
 449
 450 static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
 451         F(3686400, P_GPLL0, 1, 72, 15625),
 452         F(7372800, P_GPLL0, 1, 144, 15625),
 453         F(14745600, P_GPLL0, 1, 288, 15625),
 454         F(16000000, P_GPLL0, 10, 1, 5),
 455         F(19200000, P_XO, 1, 0, 0),
 456         F(24000000, P_GPLL0, 1, 3, 100),
 457         F(25000000, P_GPLL0, 16, 1, 2),
 458         F(32000000, P_GPLL0, 1, 1, 25),
 459         F(40000000, P_GPLL0, 1, 1, 20),
 460         F(46400000, P_GPLL0, 1, 29, 500),
 461         F(48000000, P_GPLL0, 1, 3, 50),
 462         F(51200000, P_GPLL0, 1, 8, 125),
 463         F(56000000, P_GPLL0, 1, 7, 100),
 464         F(58982400, P_GPLL0, 1, 1152, 15625),
 465         F(60000000, P_GPLL0, 1, 3, 40),
 466         F(64000000, P_GPLL0, 1, 2, 25),
 467         { }
 468 };
 469
 470 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 471         .cmd_rcgr = 0x02044,
 472         .hid_width = 5,
 473         .mnd_width = 16,
 474         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 475         .parent_map = gcc_xo_gpll0_map,
 476         .clkr.hw.init = &(struct clk_init_data) {
 477                 .name = "blsp1_uart1_apps_clk_src",
 478                 .parent_data = gcc_xo_gpll0_data,
 479                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 480                 .ops = &clk_rcg2_ops,
 481         }
 482 };
 483
 484 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 485         .cmd_rcgr = 0x03034,
 486         .hid_width = 5,
 487         .mnd_width = 16,
 488         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 489         .parent_map = gcc_xo_gpll0_map,
 490         .clkr.hw.init = &(struct clk_init_data) {
 491                 .name = "blsp1_uart2_apps_clk_src",
 492                 .parent_data = gcc_xo_gpll0_data,
 493                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 494                 .ops = &clk_rcg2_ops,
 495         }
 496 };
 497
 498 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 499         .cmd_rcgr = 0x0c044,
 500         .hid_width = 5,
 501         .mnd_width = 16,
 502         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 503         .parent_map = gcc_xo_gpll0_map,
 504         .clkr.hw.init = &(struct clk_init_data) {
 505                 .name = "blsp2_uart1_apps_clk_src",
 506                 .parent_data = gcc_xo_gpll0_data,
 507                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 508                 .ops = &clk_rcg2_ops,
 509         }
 510 };
 511
 512 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 513         .cmd_rcgr = 0x0d034,
 514         .hid_width = 5,
 515         .mnd_width = 16,
 516         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 517         .parent_map = gcc_xo_gpll0_map,
 518         .clkr.hw.init = &(struct clk_init_data) {
 519                 .name = "blsp2_uart2_apps_clk_src",
 520                 .parent_data = gcc_xo_gpll0_data,
 521                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 522                 .ops = &clk_rcg2_ops,
 523         }
 524 };
 525
 526 static const struct parent_map gcc_byte0_map[] = {
 527         { P_XO, 0 },
 528         { P_DSI0PLL_BYTE, 1 },
 529 };
 530
 531 static const struct clk_parent_data gcc_byte_data[] = {
 532         { .index = DT_XO },
 533         { .index = DT_DSI0PLL_BYTE },
 534 };
 535
 536 static struct clk_rcg2 byte0_clk_src = {
 537         .cmd_rcgr = 0x4d044,
 538         .hid_width = 5,
 539         .parent_map = gcc_byte0_map,
 540         .clkr.hw.init = &(struct clk_init_data) {
 541                 .name = "byte0_clk_src",
 542                 .parent_data = gcc_byte_data,
 543                 .num_parents = ARRAY_SIZE(gcc_byte_data),
 544                 .ops = &clk_byte2_ops,
 545                 .flags = CLK_SET_RATE_PARENT,
 546         }
 547 };
 548
 549 static const struct freq_tbl ftbl_camss_gp_clk_src[] = {
 550         F(100000000, P_GPLL0, 8, 0, 0),
 551         F(160000000, P_GPLL0, 5, 0, 0),
 552         F(200000000, P_GPLL0, 4, 0, 0),
 553         { }
 554 };
 555
 556 static struct clk_rcg2 camss_gp0_clk_src = {
 557         .cmd_rcgr = 0x54000,
 558         .hid_width = 5,
 559         .mnd_width = 8,
 560         .freq_tbl = ftbl_camss_gp_clk_src,
 561         .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
 562         .clkr.hw.init = &(struct clk_init_data) {
 563                 .name = "camss_gp0_clk_src",
 564                 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
 565                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
 566                 .ops = &clk_rcg2_ops,
 567         }
 568 };
 569
 570 static struct clk_rcg2 camss_gp1_clk_src = {
 571         .cmd_rcgr = 0x55000,
 572         .hid_width = 5,
 573         .mnd_width = 8,
 574         .freq_tbl = ftbl_camss_gp_clk_src,
 575         .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
 576         .clkr.hw.init = &(struct clk_init_data) {
 577                 .name = "camss_gp1_clk_src",
 578                 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
 579                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
 580                 .ops = &clk_rcg2_ops,
 581         }
 582 };
 583
 584 static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = {
 585         F(40000000, P_GPLL0, 10, 1, 2),
 586         F(61540000, P_GPLL0, 13, 0, 0),
 587         F(80000000, P_GPLL0, 10, 0, 0),
 588         { }
 589 };
 590
 591 static struct clk_rcg2 camss_top_ahb_clk_src = {
 592         .cmd_rcgr = 0x5a000,
 593         .hid_width = 5,
 594         .freq_tbl = ftbl_camss_top_ahb_clk_src,
 595         .parent_map = gcc_xo_gpll0_map,
 596         .clkr.hw.init = &(struct clk_init_data) {
 597                 .name = "camss_top_ahb_clk_src",
 598                 .parent_data = gcc_xo_gpll0_data,
 599                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 600                 .ops = &clk_rcg2_ops,
 601         }
 602 };
 603
 604 static const struct freq_tbl ftbl_cci_clk_src[] = {
 605         F(19200000, P_XO, 1, 0, 0),
 606         F(37500000, P_GPLL0, 1, 3, 64),
 607         { }
 608 };
 609
 610 static struct clk_rcg2 cci_clk_src = {
 611         .cmd_rcgr = 0x51000,
 612         .hid_width = 5,
 613         .mnd_width = 8,
 614         .freq_tbl = ftbl_cci_clk_src,
 615         .parent_map = gcc_xo_gpll0_out_aux_map,
 616         .clkr.hw.init = &(struct clk_init_data) {
 617                 .name = "cci_clk_src",
 618                 .parent_data = gcc_xo_gpll0_data,
 619                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 620                 .ops = &clk_rcg2_ops,
 621         }
 622 };
 623
 624 static const struct parent_map gcc_cpp_map[] = {
 625         { P_XO, 0 },
 626         { P_GPLL0, 1 },
 627         { P_GPLL6, 3 },
 628 };
 629
 630 static const struct clk_parent_data gcc_cpp_data[] = {
 631         { .index = DT_XO },
 632         { .hw = &gpll0.clkr.hw },
 633         { .hw = &gpll6.hw },
 634 };
 635
 636 static const struct freq_tbl ftbl_cpp_clk_src[] = {
 637         F(133330000, P_GPLL0, 6, 0, 0),
 638         F(160000000, P_GPLL0, 5, 0, 0),
 639         F(266670000, P_GPLL0, 3, 0, 0),
 640         F(308570000, P_GPLL0, 3.5, 0, 0),
 641         F(320000000, P_GPLL0, 2.5, 0, 0),
 642         F(360000000, P_GPLL6, 3, 0, 0),
 643         { }
 644 };
 645
 646 static struct clk_rcg2 cpp_clk_src = {
 647         .cmd_rcgr = 0x58018,
 648         .hid_width = 5,
 649         .freq_tbl = ftbl_cpp_clk_src,
 650         .parent_map = gcc_cpp_map,
 651         .clkr.hw.init = &(struct clk_init_data) {
 652                 .name = "cpp_clk_src",
 653                 .parent_data = gcc_cpp_data,
 654                 .num_parents = ARRAY_SIZE(gcc_cpp_data),
 655                 .ops = &clk_rcg2_ops,
 656         }
 657 };
 658
 659 static const struct freq_tbl ftbl_crypto_clk_src[] = {
 660         F(50000000, P_GPLL0, 16, 0, 0),
 661         F(80000000, P_GPLL0, 10, 0, 0),
 662         F(100000000, P_GPLL0, 8, 0, 0),
 663         F(160000000, P_GPLL0, 5, 0, 0),
 664         { }
 665 };
 666
 667 static struct clk_rcg2 crypto_clk_src = {
 668         .cmd_rcgr = 0x16004,
 669         .hid_width = 5,
 670         .freq_tbl = ftbl_crypto_clk_src,
 671         .parent_map = gcc_xo_gpll0_map,
 672         .clkr.hw.init = &(struct clk_init_data) {
 673                 .name = "crypto_clk_src",
 674                 .parent_data = gcc_xo_gpll0_data,
 675                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 676                 .ops = &clk_rcg2_ops,
 677         }
 678 };
 679
 680 static const struct freq_tbl ftbl_csi_clk_src[] = {
 681         F(100000000, P_GPLL0, 8, 0, 0),
 682         F(160000000, P_GPLL0, 5, 0, 0),
 683         F(200000000, P_GPLL0, 4, 0, 0),
 684         { }
 685 };
 686
 687 static struct clk_rcg2 csi0_clk_src = {
 688         .cmd_rcgr = 0x4e020,
 689         .hid_width = 5,
 690         .freq_tbl = ftbl_csi_clk_src,
 691         .parent_map = gcc_xo_gpll0_map,
 692         .clkr.hw.init = &(struct clk_init_data) {
 693                 .name = "csi0_clk_src",
 694                 .parent_data = gcc_xo_gpll0_data,
 695                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 696                 .ops = &clk_rcg2_ops,
 697         }
 698 };
 699
 700 static struct clk_rcg2 csi1_clk_src = {
 701         .cmd_rcgr = 0x4f020,
 702         .hid_width = 5,
 703         .freq_tbl = ftbl_csi_clk_src,
 704         .parent_map = gcc_xo_gpll0_map,
 705         .clkr.hw.init = &(struct clk_init_data) {
 706                 .name = "csi1_clk_src",
 707                 .parent_data = gcc_xo_gpll0_data,
 708                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 709                 .ops = &clk_rcg2_ops,
 710         }
 711 };
 712
 713 static struct clk_rcg2 csi2_clk_src = {
 714         .cmd_rcgr = 0x3c020,
 715         .hid_width = 5,
 716         .freq_tbl = ftbl_csi_clk_src,
 717         .parent_map = gcc_xo_gpll0_map,
 718         .clkr.hw.init = &(struct clk_init_data) {
 719                 .name = "csi2_clk_src",
 720                 .parent_data = gcc_xo_gpll0_data,
 721                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 722                 .ops = &clk_rcg2_ops,
 723         }
 724 };
 725
 726 static const struct freq_tbl ftbl_csi_phytimer_clk_src[] = {
 727         F(100000000, P_GPLL0, 8, 0, 0),
 728         F(160000000, P_GPLL0, 5, 0, 0),
 729         F(200000000, P_GPLL0, 4, 0, 0),
 730         F(266670000, P_GPLL0, 3, 0, 0),
 731         { }
 732 };
 733
 734 static struct clk_rcg2 csi0phytimer_clk_src = {
 735         .cmd_rcgr = 0x4e000,
 736         .hid_width = 5,
 737         .freq_tbl = ftbl_csi_phytimer_clk_src,
 738         .parent_map = gcc_xo_gpll0_map,
 739         .clkr.hw.init = &(struct clk_init_data) {
 740                 .name = "csi0phytimer_clk_src",
 741                 .parent_data = gcc_xo_gpll0_data,
 742                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 743                 .ops = &clk_rcg2_ops,
 744         }
 745 };
 746
 747 static struct clk_rcg2 csi1phytimer_clk_src = {
 748         .cmd_rcgr = 0x4f000,
 749         .hid_width = 5,
 750         .freq_tbl = ftbl_csi_phytimer_clk_src,
 751         .parent_map = gcc_xo_gpll0_map,
 752         .clkr.hw.init = &(struct clk_init_data) {
 753                 .name = "csi1phytimer_clk_src",
 754                 .parent_data = gcc_xo_gpll0_data,
 755                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 756                 .ops = &clk_rcg2_ops,
 757         }
 758 };
 759
 760 static const struct freq_tbl ftbl_esc0_1_clk_src[] = {
 761         F(19200000, P_XO, 1, 0, 0),
 762         { }
 763 };
 764
 765 static struct clk_rcg2 esc0_clk_src = {
 766         .cmd_rcgr = 0x4d05c,
 767         .hid_width = 5,
 768         .freq_tbl = ftbl_esc0_1_clk_src,
 769         .parent_map = gcc_xo_gpll0_out_aux_map,
 770         .clkr.hw.init = &(struct clk_init_data) {
 771                 .name = "esc0_clk_src",
 772                 .parent_data = gcc_xo_gpll0_data,
 773                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 774                 .ops = &clk_rcg2_ops,
 775         }
 776 };
 777
 778 static const struct parent_map gcc_gfx3d_map[] = {
 779         { P_XO, 0 },
 780         { P_GPLL0, 1 },
 781         { P_GPLL3, 2 },
 782         { P_GPLL6, 3 },
 783 };
 784
 785 static const struct parent_map gcc_gfx3d_map_qm215[] = {
 786         { P_XO, 0 },
 787         { P_GPLL0, 5 },
 788         { P_GPLL3, 2 },
 789         { P_GPLL6, 6 },
 790 };
 791
 792 static const struct clk_parent_data gcc_gfx3d_data[] = {
 793         { .index = DT_XO },
 794         { .hw = &gpll0.clkr.hw },
 795         { .hw = &gpll3.clkr.hw },
 796         { .hw = &gpll6.hw },
 797 };
 798
 799 static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
 800         F(19200000, P_XO, 1, 0, 0),
 801         F(50000000, P_GPLL0, 16, 0, 0),
 802         F(80000000, P_GPLL0, 10, 0, 0),
 803         F(100000000, P_GPLL0, 8, 0, 0),
 804         F(160000000, P_GPLL0, 5, 0, 0),
 805         F(200000000, P_GPLL0, 4, 0, 0),
 806         F(228570000, P_GPLL0, 3.5, 0, 0),
 807         F(240000000, P_GPLL6, 4.5, 0, 0),
 808         F(266670000, P_GPLL0, 3, 0, 0),
 809         F(270000000, P_GPLL6, 4, 0, 0),
 810         F(320000000, P_GPLL0, 2.5, 0, 0),
 811         F(400000000, P_GPLL0, 2, 0, 0),
 812         F(465000000, P_GPLL3, 1, 0, 0),
 813         F(484800000, P_GPLL3, 1, 0, 0),
 814         F(500000000, P_GPLL3, 1, 0, 0),
 815         F(523200000, P_GPLL3, 1, 0, 0),
 816         F(550000000, P_GPLL3, 1, 0, 0),
 817         F(598000000, P_GPLL3, 1, 0, 0),
 818         { }
 819 };
 820
 821 static struct clk_rcg2 gfx3d_clk_src = {
 822         .cmd_rcgr = 0x59000,
 823         .hid_width = 5,
 824         .freq_tbl = ftbl_gfx3d_clk_src,
 825         .parent_map = gcc_gfx3d_map,
 826         .clkr.hw.init = &(struct clk_init_data) {
 827                 .name = "gfx3d_clk_src",
 828                 .parent_data = gcc_gfx3d_data,
 829                 .num_parents = ARRAY_SIZE(gcc_gfx3d_data),
 830                 .ops = &clk_rcg2_ops,
 831                 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 832         }
 833 };
 834
 835 static const struct freq_tbl ftbl_gp_clk_src[] = {
 836         F(19200000, P_XO, 1, 0, 0),
 837         { }
 838 };
 839
 840 static struct clk_rcg2 gp1_clk_src = {
 841         .cmd_rcgr = 0x08004,
 842         .hid_width = 5,
 843         .mnd_width = 8,
 844         .freq_tbl = ftbl_gp_clk_src,
 845         .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
 846         .clkr.hw.init = &(struct clk_init_data) {
 847                 .name = "gp1_clk_src",
 848                 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
 849                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
 850                 .ops = &clk_rcg2_ops,
 851         }
 852 };
 853
 854 static struct clk_rcg2 gp2_clk_src = {
 855         .cmd_rcgr = 0x09004,
 856         .hid_width = 5,
 857         .mnd_width = 8,
 858         .freq_tbl = ftbl_gp_clk_src,
 859         .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
 860         .clkr.hw.init = &(struct clk_init_data) {
 861                 .name = "gp2_clk_src",
 862                 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
 863                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
 864                 .ops = &clk_rcg2_ops,
 865         }
 866 };
 867
 868 static struct clk_rcg2 gp3_clk_src = {
 869         .cmd_rcgr = 0x0a004,
 870         .hid_width = 5,
 871         .mnd_width = 8,
 872         .freq_tbl = ftbl_gp_clk_src,
 873         .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
 874         .clkr.hw.init = &(struct clk_init_data) {
 875                 .name = "gp3_clk_src",
 876                 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
 877                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
 878                 .ops = &clk_rcg2_ops,
 879         }
 880 };
 881
 882 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
 883         F(133330000, P_GPLL0, 6, 0, 0),
 884         F(266670000, P_GPLL0, 3, 0, 0),
 885         F(320000000, P_GPLL0, 2.5, 0, 0),
 886         { }
 887 };
 888
 889 static struct clk_rcg2 jpeg0_clk_src = {
 890         .cmd_rcgr = 0x57000,
 891         .hid_width = 5,
 892         .freq_tbl = ftbl_jpeg0_clk_src,
 893         .parent_map = gcc_xo_gpll0_map,
 894         .clkr.hw.init = &(struct clk_init_data) {
 895                 .name = "jpeg0_clk_src",
 896                 .parent_data = gcc_xo_gpll0_data,
 897                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 898                 .ops = &clk_rcg2_ops,
 899         }
 900 };
 901
 902 static const struct freq_tbl ftbl_mclk_clk_src[] = {
 903         F(19200000, P_XO, 1, 0, 0),
 904         F(24000000, P_GPLL6, 1, 1, 45),
 905         F(66667000, P_GPLL0, 12, 0, 0),
 906         { }
 907 };
 908
 909 static struct clk_rcg2 mclk0_clk_src = {
 910         .cmd_rcgr = 0x52000,
 911         .hid_width = 5,
 912         .mnd_width = 8,
 913         .freq_tbl = ftbl_mclk_clk_src,
 914         .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
 915         .clkr.hw.init = &(struct clk_init_data) {
 916                 .name = "mclk0_clk_src",
 917                 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
 918                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
 919                 .ops = &clk_rcg2_ops,
 920         }
 921 };
 922
 923 static struct clk_rcg2 mclk1_clk_src = {
 924         .cmd_rcgr = 0x53000,
 925         .hid_width = 5,
 926         .mnd_width = 8,
 927         .freq_tbl = ftbl_mclk_clk_src,
 928         .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
 929         .clkr.hw.init = &(struct clk_init_data) {
 930                 .name = "mclk1_clk_src",
 931                 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
 932                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
 933                 .ops = &clk_rcg2_ops,
 934         }
 935 };
 936
 937 static struct clk_rcg2 mclk2_clk_src = {
 938         .cmd_rcgr = 0x5c000,
 939         .hid_width = 5,
 940         .mnd_width = 8,
 941         .freq_tbl = ftbl_mclk_clk_src,
 942         .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
 943         .clkr.hw.init = &(struct clk_init_data) {
 944                 .name = "mclk2_clk_src",
 945                 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
 946                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
 947                 .ops = &clk_rcg2_ops,
 948         }
 949 };
 950
 951 static const struct freq_tbl ftbl_mdp_clk_src[] = {
 952         F(50000000, P_GPLL0, 16, 0, 0),
 953         F(80000000, P_GPLL0, 10, 0, 0),
 954         F(100000000, P_GPLL0, 8, 0, 0),
 955         F(145450000, P_GPLL0, 5.5, 0, 0),
 956         F(160000000, P_GPLL0, 5, 0, 0),
 957         F(177780000, P_GPLL0, 4.5, 0, 0),
 958         F(200000000, P_GPLL0, 4, 0, 0),
 959         F(266670000, P_GPLL0, 3, 0, 0),
 960         F(320000000, P_GPLL0, 2.5, 0, 0),
 961         { }
 962 };
 963
 964 static struct clk_rcg2 mdp_clk_src = {
 965         .cmd_rcgr = 0x4d014,
 966         .hid_width = 5,
 967         .freq_tbl = ftbl_mdp_clk_src,
 968         .parent_map = gcc_xo_gpll0_map,
 969         .clkr.hw.init = &(struct clk_init_data) {
 970                 .name = "mdp_clk_src",
 971                 .parent_data = gcc_xo_gpll0_data,
 972                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
 973                 .ops = &clk_rcg2_ops,
 974         }
 975 };
 976
 977 static const struct parent_map gcc_pclk_map[] = {
 978         { P_XO, 0 },
 979         { P_DSI0PLL, 1 },
 980 };
 981
 982 static const struct clk_parent_data gcc_pclk_data[] = {
 983         { .index = DT_XO },
 984         { .index = DT_DSI0PLL },
 985 };
 986
 987 static struct clk_rcg2 pclk0_clk_src = {
 988         .cmd_rcgr = 0x4d000,
 989         .hid_width = 5,
 990         .mnd_width = 8,
 991         .parent_map = gcc_pclk_map,
 992         .clkr.hw.init = &(struct clk_init_data) {
 993                 .name = "pclk0_clk_src",
 994                 .parent_data = gcc_pclk_data,
 995                 .num_parents = ARRAY_SIZE(gcc_pclk_data),
 996                 .ops = &clk_pixel_ops,
 997                 .flags = CLK_SET_RATE_PARENT,
 998         }
 999 };
1000
1001 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1002         F(64000000, P_GPLL0, 12.5, 0, 0),
1003         { }
1004 };
1005
1006 static struct clk_rcg2 pdm2_clk_src = {
1007         .cmd_rcgr = 0x44010,
1008         .hid_width = 5,
1009         .freq_tbl = ftbl_pdm2_clk_src,
1010         .parent_map = gcc_xo_gpll0_map,
1011         .clkr.hw.init = &(struct clk_init_data) {
1012                 .name = "pdm2_clk_src",
1013                 .parent_data = gcc_xo_gpll0_data,
1014                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1015                 .ops = &clk_rcg2_ops,
1016         }
1017 };
1018
1019 static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
1020         F(100000000, P_GPLL0, 8, 0, 0),
1021         F(200000000, P_GPLL0, 4, 0, 0),
1022         { }
1023 };
1024
1025 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1026         .cmd_rcgr = 0x5d000,
1027         .hid_width = 5,
1028         .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
1029         .parent_map = gcc_xo_gpll0_map,
1030         .clkr.hw.init = &(struct clk_init_data) {
1031                 .name = "sdcc1_ice_core_clk_src",
1032                 .parent_data = gcc_xo_gpll0_data,
1033                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1034                 .ops = &clk_rcg2_ops,
1035         }
1036 };
1037
1038 static const struct parent_map gcc_sdcc1_apps_map[] = {
1039         { P_XO, 0 },
1040         { P_GPLL0, 1 },
1041         { P_GPLL4, 2 },
1042 };
1043
1044 static const struct clk_parent_data gcc_sdcc1_apss_data[] = {
1045         { .index = DT_XO },
1046         { .hw = &gpll0.clkr.hw },
1047         { .hw = &gpll4.clkr.hw },
1048 };
1049
1050 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1051         F(144000, P_XO, 16, 3, 25),
1052         F(400000, P_XO, 12, 1, 4),
1053         F(20000000, P_GPLL0, 10, 1, 4),
1054         F(25000000, P_GPLL0, 16, 1, 2),
1055         F(50000000, P_GPLL0, 16, 0, 0),
1056         F(100000000, P_GPLL0, 8, 0, 0),
1057         F(177770000, P_GPLL0, 4.5, 0, 0),
1058         F(192000000, P_GPLL4, 6, 0, 0),
1059         F(200000000, P_GPLL0, 4, 0, 0),
1060         F(384000000, P_GPLL4, 3, 0, 0),
1061         { }
1062 };
1063
1064 static struct clk_rcg2 sdcc1_apps_clk_src = {
1065         .cmd_rcgr = 0x42004,
1066         .hid_width = 5,
1067         .mnd_width = 8,
1068         .freq_tbl = ftbl_sdcc1_apps_clk_src,
1069         .parent_map = gcc_sdcc1_apps_map,
1070         .clkr.hw.init = &(struct clk_init_data) {
1071                 .name = "sdcc1_apps_clk_src",
1072                 .parent_data = gcc_sdcc1_apss_data,
1073                 .num_parents = ARRAY_SIZE(gcc_sdcc1_apss_data),
1074                 .ops = &clk_rcg2_floor_ops,
1075         }
1076 };
1077
1078 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1079         F(144000, P_XO, 16, 3, 25),
1080         F(400000, P_XO, 12, 1, 4),
1081         F(20000000, P_GPLL0, 10, 1, 4),
1082         F(25000000, P_GPLL0, 16, 1, 2),
1083         F(50000000, P_GPLL0, 16, 0, 0),
1084         F(100000000, P_GPLL0, 8, 0, 0),
1085         F(177770000, P_GPLL0, 4.5, 0, 0),
1086         F(200000000, P_GPLL0, 4, 0, 0),
1087         { }
1088 };
1089
1090 static struct clk_rcg2 sdcc2_apps_clk_src = {
1091         .cmd_rcgr = 0x43004,
1092         .hid_width = 5,
1093         .mnd_width = 8,
1094         .freq_tbl = ftbl_sdcc2_apps_clk_src,
1095         .parent_map = gcc_xo_gpll0_map,
1096         .clkr.hw.init = &(struct clk_init_data) {
1097                 .name = "sdcc2_apps_clk_src",
1098                 .parent_data = gcc_xo_gpll0_data,
1099                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1100                 .ops = &clk_rcg2_floor_ops,
1101         }
1102 };
1103
1104 static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1105         F(80000000, P_GPLL0, 10, 0, 0),
1106         F(100000000, P_GPLL0, 8, 0, 0),
1107         F(133330000, P_GPLL0, 6, 0, 0),
1108         F(177780000, P_GPLL0, 4.5, 0, 0),
1109         { }
1110 };
1111
1112 static struct clk_rcg2 usb_hs_system_clk_src = {
1113         .cmd_rcgr = 0x41010,
1114         .hid_width = 5,
1115         .parent_map = gcc_xo_gpll0_map,
1116         .freq_tbl = ftbl_usb_hs_system_clk_src,
1117         .clkr.hw.init = &(struct clk_init_data){
1118                 .name = "usb_hs_system_clk_src",
1119                 .parent_data = gcc_xo_gpll0_data,
1120                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1121                 .ops = &clk_rcg2_ops,
1122         },
1123 };
1124
1125 static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
1126         F(133330000, P_GPLL0, 6, 0, 0),
1127         F(180000000, P_GPLL6, 6, 0, 0),
1128         F(228570000, P_GPLL0, 3.5, 0, 0),
1129         F(266670000, P_GPLL0, 3, 0, 0),
1130         F(308570000, P_GPLL6, 3.5, 0, 0),
1131         F(329140000, P_GPLL4, 3.5, 0, 0),
1132         F(360000000, P_GPLL6, 3, 0, 0),
1133         { }
1134 };
1135
1136 static struct clk_rcg2 vcodec0_clk_src = {
1137         .cmd_rcgr = 0x4c000,
1138         .hid_width = 5,
1139         .freq_tbl = ftbl_vcodec0_clk_src,
1140         .parent_map = gcc_xo_gpll0_gpll6_gpll4_map,
1141         .clkr.hw.init = &(struct clk_init_data) {
1142                 .name = "vcodec0_clk_src",
1143                 .parent_data = gcc_xo_gpll0_gpll6_gpll4_data,
1144                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll4_data),
1145                 .ops = &clk_rcg2_ops,
1146         }
1147 };
1148
1149 static const struct freq_tbl ftbl_vfe_clk_src[] = {
1150         F(50000000, P_GPLL0, 16, 0, 0),
1151         F(80000000, P_GPLL0, 10, 0, 0),
1152         F(100000000, P_GPLL0, 8, 0, 0),
1153         F(133330000, P_GPLL0, 6, 0, 0),
1154         F(160000000, P_GPLL0, 5, 0, 0),
1155         F(200000000, P_GPLL0, 4, 0, 0),
1156         F(266670000, P_GPLL0, 3, 0, 0),
1157         F(308570000, P_GPLL6, 3.5, 0, 0),
1158         F(320000000, P_GPLL0, 2.5, 0, 0),
1159         F(329140000, P_GPLL4, 3.5, 0, 0),
1160         F(360000000, P_GPLL6, 3, 0, 0),
1161         { }
1162 };
1163
1164 static struct clk_rcg2 vfe0_clk_src = {
1165         .cmd_rcgr = 0x58000,
1166         .hid_width = 5,
1167         .freq_tbl = ftbl_vfe_clk_src,
1168         .parent_map = gcc_xo_gpll0_gpll6_gpll4_map,
1169         .clkr.hw.init = &(struct clk_init_data) {
1170                 .name = "vfe0_clk_src",
1171                 .parent_data = gcc_xo_gpll0_gpll6_gpll4_data,
1172                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll4_data),
1173                 .ops = &clk_rcg2_ops,
1174         }
1175 };
1176
1177 static struct clk_rcg2 vfe1_clk_src = {
1178         .cmd_rcgr = 0x58054,
1179         .hid_width = 5,
1180         .freq_tbl = ftbl_vfe_clk_src,
1181         .parent_map = gcc_xo_gpll0_gpll6_gpll4_map,
1182         .clkr.hw.init = &(struct clk_init_data) {
1183                 .name = "vfe1_clk_src",
1184                 .parent_data = gcc_xo_gpll0_gpll6_gpll4_data,
1185                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll4_data),
1186                 .ops = &clk_rcg2_ops,
1187         }
1188 };
1189
1190 static const struct freq_tbl ftbl_vsync_clk_src[] = {
1191         F(19200000, P_XO, 1, 0, 0),
1192         { }
1193 };
1194
1195 static struct clk_rcg2 vsync_clk_src = {
1196         .cmd_rcgr = 0x4d02c,
1197         .hid_width = 5,
1198         .freq_tbl = ftbl_vsync_clk_src,
1199         .parent_map = gcc_xo_gpll0_out_aux_map,
1200         .clkr.hw.init = &(struct clk_init_data) {
1201                 .name = "vsync_clk_src",
1202                 .parent_data = gcc_xo_gpll0_data,
1203                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1204                 .ops = &clk_rcg2_ops,
1205         }
1206 };
1207
1208 static struct clk_branch gcc_apss_tcu_clk = {
1209         .halt_reg = 0x12018,
1210         .halt_check = BRANCH_HALT_VOTED,
1211         .clkr = {
1212                 .enable_reg = 0x4500c,
1213                 .enable_mask = BIT(1),
1214                 .hw.init = &(struct clk_init_data) {
1215                         .name = "gcc_apss_tcu_clk",
1216                         .ops = &clk_branch2_ops,
1217                 }
1218         }
1219 };
1220
1221 static struct clk_branch gcc_bimc_gfx_clk = {
1222         .halt_reg = 0x59034,
1223         .halt_check = BRANCH_HALT,
1224         .clkr = {
1225                 .enable_reg = 0x59034,
1226                 .enable_mask = BIT(0),
1227                 .hw.init = &(struct clk_init_data) {
1228                         .name = "gcc_bimc_gfx_clk",
1229                         .ops = &clk_branch2_ops,
1230                 }
1231         }
1232 };
1233
1234 static struct clk_branch gcc_bimc_gpu_clk = {
1235         .halt_reg = 0x59030,
1236         .halt_check = BRANCH_HALT,
1237         .clkr = {
1238                 .enable_reg = 0x59030,
1239                 .enable_mask = BIT(0),
1240                 .hw.init = &(struct clk_init_data) {
1241                         .name = "gcc_bimc_gpu_clk",
1242                         .ops = &clk_branch2_ops,
1243                 }
1244         }
1245 };
1246
1247 static struct clk_branch gcc_blsp1_ahb_clk = {
1248         .halt_reg = 0x01008,
1249         .halt_check = BRANCH_HALT_VOTED,
1250         .clkr = {
1251                 .enable_reg = 0x45004,
1252                 .enable_mask = BIT(10),
1253                 .hw.init = &(struct clk_init_data) {
1254                         .name = "gcc_blsp1_ahb_clk",
1255                         .ops = &clk_branch2_ops,
1256                 }
1257         }
1258 };
1259
1260 static struct clk_branch gcc_blsp2_ahb_clk = {
1261         .halt_reg = 0x0b008,
1262         .halt_check = BRANCH_HALT_VOTED,
1263         .clkr = {
1264                 .enable_reg = 0x45004,
1265                 .enable_mask = BIT(20),
1266                 .hw.init = &(struct clk_init_data) {
1267                         .name = "gcc_blsp2_ahb_clk",
1268                         .ops = &clk_branch2_ops,
1269                 }
1270         }
1271 };
1272
1273 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1274         .halt_reg = 0x03010,
1275         .halt_check = BRANCH_HALT,
1276         .clkr = {
1277                 .enable_reg = 0x03010,
1278                 .enable_mask = BIT(0),
1279                 .hw.init = &(struct clk_init_data) {
1280                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1281                         .parent_hws = (const struct clk_hw*[]){
1282                                 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1283                         },
1284                         .num_parents = 1,
1285                         .ops = &clk_branch2_ops,
1286                         .flags = CLK_SET_RATE_PARENT,
1287                 }
1288         }
1289 };
1290
1291 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1292         .halt_reg = 0x04020,
1293         .halt_check = BRANCH_HALT,
1294         .clkr = {
1295                 .enable_reg = 0x04020,
1296                 .enable_mask = BIT(0),
1297                 .hw.init = &(struct clk_init_data) {
1298                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1299                         .parent_hws = (const struct clk_hw*[]){
1300                                 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1301                         },
1302                         .num_parents = 1,
1303                         .ops = &clk_branch2_ops,
1304                         .flags = CLK_SET_RATE_PARENT,
1305                 }
1306         }
1307 };
1308
1309 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1310         .halt_reg = 0x05020,
1311         .halt_check = BRANCH_HALT,
1312         .clkr = {
1313                 .enable_reg = 0x05020,
1314                 .enable_mask = BIT(0),
1315                 .hw.init = &(struct clk_init_data) {
1316                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1317                         .parent_hws = (const struct clk_hw*[]){
1318                                 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1319                         },
1320                         .num_parents = 1,
1321                         .ops = &clk_branch2_ops,
1322                         .flags = CLK_SET_RATE_PARENT,
1323                 }
1324         }
1325 };
1326
1327 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1328         .halt_reg = 0x0c008,
1329         .halt_check = BRANCH_HALT,
1330         .clkr = {
1331                 .enable_reg = 0x0c008,
1332                 .enable_mask = BIT(0),
1333                 .hw.init = &(struct clk_init_data) {
1334                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1335                         .parent_hws = (const struct clk_hw*[]){
1336                                 &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
1337                         },
1338                         .num_parents = 1,
1339                         .ops = &clk_branch2_ops,
1340                         .flags = CLK_SET_RATE_PARENT,
1341                 }
1342         }
1343 };
1344
1345 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1346         .halt_reg = 0x0d010,
1347         .halt_check = BRANCH_HALT,
1348         .clkr = {
1349                 .enable_reg = 0x0d010,
1350                 .enable_mask = BIT(0),
1351                 .hw.init = &(struct clk_init_data) {
1352                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1353                         .parent_hws = (const struct clk_hw*[]){
1354                                 &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
1355                         },
1356                         .num_parents = 1,
1357                         .ops = &clk_branch2_ops,
1358                         .flags = CLK_SET_RATE_PARENT,
1359                 }
1360         }
1361 };
1362
1363 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1364         .halt_reg = 0x0f020,
1365         .halt_check = BRANCH_HALT,
1366         .clkr = {
1367                 .enable_reg = 0x0f020,
1368                 .enable_mask = BIT(0),
1369                 .hw.init = &(struct clk_init_data) {
1370                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
1371                         .parent_hws = (const struct clk_hw*[]){
1372                                 &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
1373                         },
1374                         .num_parents = 1,
1375                         .ops = &clk_branch2_ops,
1376                         .flags = CLK_SET_RATE_PARENT,
1377                 }
1378         }
1379 };
1380
1381 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1382         .halt_reg = 0x0300c,
1383         .halt_check = BRANCH_HALT,
1384         .clkr = {
1385                 .enable_reg = 0x0300c,
1386                 .enable_mask = BIT(0),
1387                 .hw.init = &(struct clk_init_data) {
1388                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1389                         .parent_hws = (const struct clk_hw*[]){
1390                                 &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1391                         },
1392                         .num_parents = 1,
1393                         .ops = &clk_branch2_ops,
1394                         .flags = CLK_SET_RATE_PARENT,
1395                 }
1396         }
1397 };
1398
1399 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1400         .halt_reg = 0x0401c,
1401         .halt_check = BRANCH_HALT,
1402         .clkr = {
1403                 .enable_reg = 0x0401c,
1404                 .enable_mask = BIT(0),
1405                 .hw.init = &(struct clk_init_data) {
1406                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1407                         .parent_hws = (const struct clk_hw*[]){
1408                                 &blsp1_qup3_spi_apps_clk_src.clkr.hw,
1409                         },
1410                         .num_parents = 1,
1411                         .ops = &clk_branch2_ops,
1412                         .flags = CLK_SET_RATE_PARENT,
1413                 }
1414         }
1415 };
1416
1417 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1418         .halt_reg = 0x0501c,
1419         .halt_check = BRANCH_HALT,
1420         .clkr = {
1421                 .enable_reg = 0x0501c,
1422                 .enable_mask = BIT(0),
1423                 .hw.init = &(struct clk_init_data) {
1424                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1425                         .parent_hws = (const struct clk_hw*[]){
1426                                 &blsp1_qup4_spi_apps_clk_src.clkr.hw,
1427                         },
1428                         .num_parents = 1,
1429                         .ops = &clk_branch2_ops,
1430                         .flags = CLK_SET_RATE_PARENT,
1431                 }
1432         }
1433 };
1434
1435 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1436         .halt_reg = 0x0c004,
1437         .halt_check = BRANCH_HALT,
1438         .clkr = {
1439                 .enable_reg = 0x0c004,
1440                 .enable_mask = BIT(0),
1441                 .hw.init = &(struct clk_init_data) {
1442                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1443                         .parent_hws = (const struct clk_hw*[]){
1444                                 &blsp2_qup1_spi_apps_clk_src.clkr.hw,
1445                         },
1446                         .num_parents = 1,
1447                         .ops = &clk_branch2_ops,
1448                         .flags = CLK_SET_RATE_PARENT,
1449                 }
1450         }
1451 };
1452
1453 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1454         .halt_reg = 0x0d00c,
1455         .halt_check = BRANCH_HALT,
1456         .clkr = {
1457                 .enable_reg = 0x0d00c,
1458                 .enable_mask = BIT(0),
1459                 .hw.init = &(struct clk_init_data) {
1460                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1461                         .parent_hws = (const struct clk_hw*[]){
1462                                 &blsp2_qup2_spi_apps_clk_src.clkr.hw,
1463                         },
1464                         .num_parents = 1,
1465                         .ops = &clk_branch2_ops,
1466                         .flags = CLK_SET_RATE_PARENT,
1467                 }
1468         }
1469 };
1470
1471 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1472         .halt_reg = 0x0f01c,
1473         .halt_check = BRANCH_HALT,
1474         .clkr = {
1475                 .enable_reg = 0x0f01c,
1476                 .enable_mask = BIT(0),
1477                 .hw.init = &(struct clk_init_data) {
1478                         .name = "gcc_blsp2_qup3_spi_apps_clk",
1479                         .parent_hws = (const struct clk_hw*[]){
1480                                 &blsp2_qup3_spi_apps_clk_src.clkr.hw,
1481                         },
1482                         .num_parents = 1,
1483                         .ops = &clk_branch2_ops,
1484                         .flags = CLK_SET_RATE_PARENT,
1485                 }
1486         }
1487 };
1488
1489 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1490         .halt_reg = 0x0203c,
1491         .halt_check = BRANCH_HALT,
1492         .clkr = {
1493                 .enable_reg = 0x0203c,
1494                 .enable_mask = BIT(0),
1495                 .hw.init = &(struct clk_init_data) {
1496                         .name = "gcc_blsp1_uart1_apps_clk",
1497                         .parent_hws = (const struct clk_hw*[]){
1498                                 &blsp1_uart1_apps_clk_src.clkr.hw,
1499                         },
1500                         .num_parents = 1,
1501                         .ops = &clk_branch2_ops,
1502                         .flags = CLK_SET_RATE_PARENT,
1503                 }
1504         }
1505 };
1506
1507 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1508         .halt_reg = 0x0302c,
1509         .halt_check = BRANCH_HALT,
1510         .clkr = {
1511                 .enable_reg = 0x0302c,
1512                 .enable_mask = BIT(0),
1513                 .hw.init = &(struct clk_init_data) {
1514                         .name = "gcc_blsp1_uart2_apps_clk",
1515                         .parent_hws = (const struct clk_hw*[]){
1516                                 &blsp1_uart2_apps_clk_src.clkr.hw,
1517                         },
1518                         .num_parents = 1,
1519                         .ops = &clk_branch2_ops,
1520                         .flags = CLK_SET_RATE_PARENT,
1521                 }
1522         }
1523 };
1524
1525 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1526         .halt_reg = 0x0c03c,
1527         .halt_check = BRANCH_HALT,
1528         .clkr = {
1529                 .enable_reg = 0x0c03c,
1530                 .enable_mask = BIT(0),
1531                 .hw.init = &(struct clk_init_data) {
1532                         .name = "gcc_blsp2_uart1_apps_clk",
1533                         .parent_hws = (const struct clk_hw*[]){
1534                                 &blsp2_uart1_apps_clk_src.clkr.hw,
1535                         },
1536                         .num_parents = 1,
1537                         .ops = &clk_branch2_ops,
1538                         .flags = CLK_SET_RATE_PARENT,
1539                 }
1540         }
1541 };
1542
1543 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1544         .halt_reg = 0x0d02c,
1545         .halt_check = BRANCH_HALT,
1546         .clkr = {
1547                 .enable_reg = 0x0d02c,
1548                 .enable_mask = BIT(0),
1549                 .hw.init = &(struct clk_init_data) {
1550                         .name = "gcc_blsp2_uart2_apps_clk",
1551                         .parent_hws = (const struct clk_hw*[]){
1552                                 &blsp2_uart2_apps_clk_src.clkr.hw,
1553                         },
1554                         .num_parents = 1,
1555                         .ops = &clk_branch2_ops,
1556                         .flags = CLK_SET_RATE_PARENT,
1557                 }
1558         }
1559 };
1560
1561 static struct clk_branch gcc_boot_rom_ahb_clk = {
1562         .halt_reg = 0x1300c,
1563         .halt_check = BRANCH_HALT_VOTED,
1564         .clkr = {
1565                 .enable_reg = 0x45004,
1566                 .enable_mask = BIT(7),
1567                 .hw.init = &(struct clk_init_data) {
1568                         .name = "gcc_boot_rom_ahb_clk",
1569                         .ops = &clk_branch2_ops,
1570                 }
1571         }
1572 };
1573
1574 static struct clk_branch gcc_camss_ahb_clk = {
1575         .halt_reg = 0x56004,
1576         .halt_check = BRANCH_HALT,
1577         .clkr = {
1578                 .enable_reg = 0x56004,
1579                 .enable_mask = BIT(0),
1580                 .hw.init = &(struct clk_init_data) {
1581                         .name = "gcc_camss_ahb_clk",
1582                         .ops = &clk_branch2_ops,
1583                 }
1584         }
1585 };
1586
1587 static struct clk_branch gcc_camss_cci_ahb_clk = {
1588         .halt_reg = 0x5101c,
1589         .halt_check = BRANCH_HALT,
1590         .clkr = {
1591                 .enable_reg = 0x5101c,
1592                 .enable_mask = BIT(0),
1593                 .hw.init = &(struct clk_init_data) {
1594                         .name = "gcc_camss_cci_ahb_clk",
1595                         .parent_hws = (const struct clk_hw*[]){
1596                                 &camss_top_ahb_clk_src.clkr.hw,
1597                         },
1598                         .num_parents = 1,
1599                         .ops = &clk_branch2_ops,
1600                         .flags = CLK_SET_RATE_PARENT,
1601                 }
1602         }
1603 };
1604
1605 static struct clk_branch gcc_camss_cci_clk = {
1606         .halt_reg = 0x51018,
1607         .halt_check = BRANCH_HALT,
1608         .clkr = {
1609                 .enable_reg = 0x51018,
1610                 .enable_mask = BIT(0),
1611                 .hw.init = &(struct clk_init_data) {
1612                         .name = "gcc_camss_cci_clk",
1613                         .parent_hws = (const struct clk_hw*[]){
1614                                 &cci_clk_src.clkr.hw,
1615                         },
1616                         .num_parents = 1,
1617                         .ops = &clk_branch2_ops,
1618                         .flags = CLK_SET_RATE_PARENT,
1619                 }
1620         }
1621 };
1622
1623 static struct clk_branch gcc_camss_cpp_ahb_clk = {
1624         .halt_reg = 0x58040,
1625         .halt_check = BRANCH_HALT,
1626         .clkr = {
1627                 .enable_reg = 0x58040,
1628                 .enable_mask = BIT(0),
1629                 .hw.init = &(struct clk_init_data) {
1630                         .name = "gcc_camss_cpp_ahb_clk",
1631                         .parent_hws = (const struct clk_hw*[]){
1632                                 &camss_top_ahb_clk_src.clkr.hw,
1633                         },
1634                         .num_parents = 1,
1635                         .ops = &clk_branch2_ops,
1636                         .flags = CLK_SET_RATE_PARENT,
1637                 }
1638         }
1639 };
1640
1641 static struct clk_branch gcc_camss_cpp_clk = {
1642         .halt_reg = 0x5803c,
1643         .halt_check = BRANCH_HALT,
1644         .clkr = {
1645                 .enable_reg = 0x5803c,
1646                 .enable_mask = BIT(0),
1647                 .hw.init = &(struct clk_init_data) {
1648                         .name = "gcc_camss_cpp_clk",
1649                         .parent_hws = (const struct clk_hw*[]){
1650                                 &cpp_clk_src.clkr.hw,
1651                         },
1652                         .num_parents = 1,
1653                         .ops = &clk_branch2_ops,
1654                         .flags = CLK_SET_RATE_PARENT,
1655                 }
1656         }
1657 };
1658
1659 static struct clk_branch gcc_camss_csi0_ahb_clk = {
1660         .halt_reg = 0x4e040,
1661         .halt_check = BRANCH_HALT,
1662         .clkr = {
1663                 .enable_reg = 0x4e040,
1664                 .enable_mask = BIT(0),
1665                 .hw.init = &(struct clk_init_data) {
1666                         .name = "gcc_camss_csi0_ahb_clk",
1667                         .parent_hws = (const struct clk_hw*[]){
1668                                 &camss_top_ahb_clk_src.clkr.hw,
1669                         },
1670                         .num_parents = 1,
1671                         .ops = &clk_branch2_ops,
1672                         .flags = CLK_SET_RATE_PARENT,
1673                 }
1674         }
1675 };
1676
1677 static struct clk_branch gcc_camss_csi1_ahb_clk = {
1678         .halt_reg = 0x4f040,
1679         .halt_check = BRANCH_HALT,
1680         .clkr = {
1681                 .enable_reg = 0x4f040,
1682                 .enable_mask = BIT(0),
1683                 .hw.init = &(struct clk_init_data) {
1684                         .name = "gcc_camss_csi1_ahb_clk",
1685                         .parent_hws = (const struct clk_hw*[]){
1686                                 &camss_top_ahb_clk_src.clkr.hw,
1687                         },
1688                         .num_parents = 1,
1689                         .ops = &clk_branch2_ops,
1690                         .flags = CLK_SET_RATE_PARENT,
1691                 }
1692         }
1693 };
1694
1695 static struct clk_branch gcc_camss_csi2_ahb_clk = {
1696         .halt_reg = 0x3c040,
1697         .halt_check = BRANCH_HALT,
1698         .clkr = {
1699                 .enable_reg = 0x3c040,
1700                 .enable_mask = BIT(0),
1701                 .hw.init = &(struct clk_init_data) {
1702                         .name = "gcc_camss_csi2_ahb_clk",
1703                         .parent_hws = (const struct clk_hw*[]){
1704                                 &camss_top_ahb_clk_src.clkr.hw,
1705                         },
1706                         .num_parents = 1,
1707                         .ops = &clk_branch2_ops,
1708                         .flags = CLK_SET_RATE_PARENT,
1709                 }
1710         }
1711 };
1712
1713 static struct clk_branch gcc_camss_csi0_clk = {
1714         .halt_reg = 0x4e03c,
1715         .halt_check = BRANCH_HALT,
1716         .clkr = {
1717                 .enable_reg = 0x4e03c,
1718                 .enable_mask = BIT(0),
1719                 .hw.init = &(struct clk_init_data) {
1720                         .name = "gcc_camss_csi0_clk",
1721                         .parent_hws = (const struct clk_hw*[]){
1722                                 &csi0_clk_src.clkr.hw,
1723                         },
1724                         .num_parents = 1,
1725                         .ops = &clk_branch2_ops,
1726                         .flags = CLK_SET_RATE_PARENT,
1727                 }
1728         }
1729 };
1730
1731 static struct clk_branch gcc_camss_csi1_clk = {
1732         .halt_reg = 0x4f03c,
1733         .halt_check = BRANCH_HALT,
1734         .clkr = {
1735                 .enable_reg = 0x4f03c,
1736                 .enable_mask = BIT(0),
1737                 .hw.init = &(struct clk_init_data) {
1738                         .name = "gcc_camss_csi1_clk",
1739                         .parent_hws = (const struct clk_hw*[]){
1740                                 &csi1_clk_src.clkr.hw,
1741                         },
1742                         .num_parents = 1,
1743                         .ops = &clk_branch2_ops,
1744                         .flags = CLK_SET_RATE_PARENT,
1745                 }
1746         }
1747 };
1748
1749 static struct clk_branch gcc_camss_csi2_clk = {
1750         .halt_reg = 0x3c03c,
1751         .halt_check = BRANCH_HALT,
1752         .clkr = {
1753                 .enable_reg = 0x3c03c,
1754                 .enable_mask = BIT(0),
1755                 .hw.init = &(struct clk_init_data) {
1756                         .name = "gcc_camss_csi2_clk",
1757                         .parent_hws = (const struct clk_hw*[]){
1758                                 &csi2_clk_src.clkr.hw,
1759                         },
1760                         .num_parents = 1,
1761                         .ops = &clk_branch2_ops,
1762                         .flags = CLK_SET_RATE_PARENT,
1763                 }
1764         }
1765 };
1766
1767 static struct clk_branch gcc_camss_csi0phy_clk = {
1768         .halt_reg = 0x4e048,
1769         .halt_check = BRANCH_HALT,
1770         .clkr = {
1771                 .enable_reg = 0x4e048,
1772                 .enable_mask = BIT(0),
1773                 .hw.init = &(struct clk_init_data) {
1774                         .name = "gcc_camss_csi0phy_clk",
1775                         .parent_hws = (const struct clk_hw*[]){
1776                                 &csi0_clk_src.clkr.hw,
1777                         },
1778                         .num_parents = 1,
1779                         .ops = &clk_branch2_ops,
1780                         .flags = CLK_SET_RATE_PARENT,
1781                 }
1782         }
1783 };
1784
1785 static struct clk_branch gcc_camss_csi1phy_clk = {
1786         .halt_reg = 0x4f048,
1787         .halt_check = BRANCH_HALT,
1788         .clkr = {
1789                 .enable_reg = 0x4f048,
1790                 .enable_mask = BIT(0),
1791                 .hw.init = &(struct clk_init_data) {
1792                         .name = "gcc_camss_csi1phy_clk",
1793                         .parent_hws = (const struct clk_hw*[]){
1794                                 &csi1_clk_src.clkr.hw,
1795                         },
1796                         .num_parents = 1,
1797                         .ops = &clk_branch2_ops,
1798                         .flags = CLK_SET_RATE_PARENT,
1799                 }
1800         }
1801 };
1802
1803 static struct clk_branch gcc_camss_csi2phy_clk = {
1804         .halt_reg = 0x3c048,
1805         .halt_check = BRANCH_HALT,
1806         .clkr = {
1807                 .enable_reg = 0x3c048,
1808                 .enable_mask = BIT(0),
1809                 .hw.init = &(struct clk_init_data) {
1810                         .name = "gcc_camss_csi2phy_clk",
1811                         .parent_hws = (const struct clk_hw*[]){
1812                                 &csi2_clk_src.clkr.hw,
1813                         },
1814                         .num_parents = 1,
1815                         .ops = &clk_branch2_ops,
1816                         .flags = CLK_SET_RATE_PARENT,
1817                 }
1818         }
1819 };
1820
1821 static struct clk_branch gcc_camss_csi0phytimer_clk = {
1822         .halt_reg = 0x4e01c,
1823         .halt_check = BRANCH_HALT,
1824         .clkr = {
1825                 .enable_reg = 0x4e01c,
1826                 .enable_mask = BIT(0),
1827                 .hw.init = &(struct clk_init_data) {
1828                         .name = "gcc_camss_csi0phytimer_clk",
1829                         .parent_hws = (const struct clk_hw*[]){
1830                                 &csi0phytimer_clk_src.clkr.hw,
1831                         },
1832                         .num_parents = 1,
1833                         .ops = &clk_branch2_ops,
1834                         .flags = CLK_SET_RATE_PARENT,
1835                 }
1836         }
1837 };
1838
1839 static struct clk_branch gcc_camss_csi1phytimer_clk = {
1840         .halt_reg = 0x4f01c,
1841         .halt_check = BRANCH_HALT,
1842         .clkr = {
1843                 .enable_reg = 0x4f01c,
1844                 .enable_mask = BIT(0),
1845                 .hw.init = &(struct clk_init_data) {
1846                         .name = "gcc_camss_csi1phytimer_clk",
1847                         .parent_hws = (const struct clk_hw*[]){
1848                                 &csi1phytimer_clk_src.clkr.hw,
1849                         },
1850                         .num_parents = 1,
1851                         .ops = &clk_branch2_ops,
1852                         .flags = CLK_SET_RATE_PARENT,
1853                 }
1854         }
1855 };
1856
1857 static struct clk_branch gcc_camss_csi0pix_clk = {
1858         .halt_reg = 0x4e058,
1859         .halt_check = BRANCH_HALT,
1860         .clkr = {
1861                 .enable_reg = 0x4e058,
1862                 .enable_mask = BIT(0),
1863                 .hw.init = &(struct clk_init_data) {
1864                         .name = "gcc_camss_csi0pix_clk",
1865                         .parent_hws = (const struct clk_hw*[]){
1866                                 &csi0_clk_src.clkr.hw,
1867                         },
1868                         .num_parents = 1,
1869                         .ops = &clk_branch2_ops,
1870                         .flags = CLK_SET_RATE_PARENT,
1871                 }
1872         }
1873 };
1874
1875 static struct clk_branch gcc_camss_csi1pix_clk = {
1876         .halt_reg = 0x4f058,
1877         .halt_check = BRANCH_HALT,
1878         .clkr = {
1879                 .enable_reg = 0x4f058,
1880                 .enable_mask = BIT(0),
1881                 .hw.init = &(struct clk_init_data) {
1882                         .name = "gcc_camss_csi1pix_clk",
1883                         .parent_hws = (const struct clk_hw*[]){
1884                                 &csi1_clk_src.clkr.hw,
1885                         },
1886                         .num_parents = 1,
1887                         .ops = &clk_branch2_ops,
1888                         .flags = CLK_SET_RATE_PARENT,
1889                 }
1890         }
1891 };
1892
1893 static struct clk_branch gcc_camss_csi2pix_clk = {
1894         .halt_reg = 0x3c058,
1895         .halt_check = BRANCH_HALT,
1896         .clkr = {
1897                 .enable_reg = 0x3c058,
1898                 .enable_mask = BIT(0),
1899                 .hw.init = &(struct clk_init_data) {
1900                         .name = "gcc_camss_csi2pix_clk",
1901                         .parent_hws = (const struct clk_hw*[]){
1902                                 &csi2_clk_src.clkr.hw,
1903                         },
1904                         .num_parents = 1,
1905                         .ops = &clk_branch2_ops,
1906                         .flags = CLK_SET_RATE_PARENT,
1907                 }
1908         }
1909 };
1910
1911 static struct clk_branch gcc_camss_csi0rdi_clk = {
1912         .halt_reg = 0x4e050,
1913         .halt_check = BRANCH_HALT,
1914         .clkr = {
1915                 .enable_reg = 0x4e050,
1916                 .enable_mask = BIT(0),
1917                 .hw.init = &(struct clk_init_data) {
1918                         .name = "gcc_camss_csi0rdi_clk",
1919                         .parent_hws = (const struct clk_hw*[]){
1920                                 &csi0_clk_src.clkr.hw,
1921                         },
1922                         .num_parents = 1,
1923                         .ops = &clk_branch2_ops,
1924                         .flags = CLK_SET_RATE_PARENT,
1925                 }
1926         }
1927 };
1928
1929 static struct clk_branch gcc_camss_csi1rdi_clk = {
1930         .halt_reg = 0x4f050,
1931         .halt_check = BRANCH_HALT,
1932         .clkr = {
1933                 .enable_reg = 0x4f050,
1934                 .enable_mask = BIT(0),
1935                 .hw.init = &(struct clk_init_data) {
1936                         .name = "gcc_camss_csi1rdi_clk",
1937                         .parent_hws = (const struct clk_hw*[]){
1938                                 &csi1_clk_src.clkr.hw,
1939                         },
1940                         .num_parents = 1,
1941                         .ops = &clk_branch2_ops,
1942                         .flags = CLK_SET_RATE_PARENT,
1943                 }
1944         }
1945 };
1946
1947 static struct clk_branch gcc_camss_csi2rdi_clk = {
1948         .halt_reg = 0x3c050,
1949         .halt_check = BRANCH_HALT,
1950         .clkr = {
1951                 .enable_reg = 0x3c050,
1952                 .enable_mask = BIT(0),
1953                 .hw.init = &(struct clk_init_data) {
1954                         .name = "gcc_camss_csi2rdi_clk",
1955                         .parent_hws = (const struct clk_hw*[]){
1956                                 &csi2_clk_src.clkr.hw,
1957                         },
1958                         .num_parents = 1,
1959                         .ops = &clk_branch2_ops,
1960                         .flags = CLK_SET_RATE_PARENT,
1961                 }
1962         }
1963 };
1964
1965 static struct clk_branch gcc_camss_csi_vfe0_clk = {
1966         .halt_reg = 0x58050,
1967         .halt_check = BRANCH_HALT,
1968         .clkr = {
1969                 .enable_reg = 0x58050,
1970                 .enable_mask = BIT(0),
1971                 .hw.init = &(struct clk_init_data) {
1972                         .name = "gcc_camss_csi_vfe0_clk",
1973                         .parent_hws = (const struct clk_hw*[]){
1974                                 &vfe0_clk_src.clkr.hw,
1975                         },
1976                         .num_parents = 1,
1977                         .ops = &clk_branch2_ops,
1978                         .flags = CLK_SET_RATE_PARENT,
1979                 }
1980         }
1981 };
1982
1983 static struct clk_branch gcc_camss_csi_vfe1_clk = {
1984         .halt_reg = 0x58074,
1985         .halt_check = BRANCH_HALT,
1986         .clkr = {
1987                 .enable_reg = 0x58074,
1988                 .enable_mask = BIT(0),
1989                 .hw.init = &(struct clk_init_data) {
1990                         .name = "gcc_camss_csi_vfe1_clk",
1991                         .parent_hws = (const struct clk_hw*[]){
1992                                 &vfe1_clk_src.clkr.hw,
1993                         },
1994                         .num_parents = 1,
1995                         .ops = &clk_branch2_ops,
1996                         .flags = CLK_SET_RATE_PARENT,
1997                 }
1998         }
1999 };
2000
2001 static struct clk_branch gcc_camss_gp0_clk = {
2002         .halt_reg = 0x54018,
2003         .halt_check = BRANCH_HALT,
2004         .clkr = {
2005                 .enable_reg = 0x54018,
2006                 .enable_mask = BIT(0),
2007                 .hw.init = &(struct clk_init_data) {
2008                         .name = "gcc_camss_gp0_clk",
2009                         .parent_hws = (const struct clk_hw*[]){
2010                                 &camss_gp0_clk_src.clkr.hw,
2011                         },
2012                         .num_parents = 1,
2013                         .ops = &clk_branch2_ops,
2014                         .flags = CLK_SET_RATE_PARENT,
2015                 }
2016         }
2017 };
2018
2019 static struct clk_branch gcc_camss_gp1_clk = {
2020         .halt_reg = 0x55018,
2021         .halt_check = BRANCH_HALT,
2022         .clkr = {
2023                 .enable_reg = 0x55018,
2024                 .enable_mask = BIT(0),
2025                 .hw.init = &(struct clk_init_data) {
2026                         .name = "gcc_camss_gp1_clk",
2027                         .parent_hws = (const struct clk_hw*[]){
2028                                 &camss_gp1_clk_src.clkr.hw,
2029                         },
2030                         .num_parents = 1,
2031                         .ops = &clk_branch2_ops,
2032                         .flags = CLK_SET_RATE_PARENT,
2033                 }
2034         }
2035 };
2036
2037 static struct clk_branch gcc_camss_ispif_ahb_clk = {
2038         .halt_reg = 0x50004,
2039         .halt_check = BRANCH_HALT,
2040         .clkr = {
2041                 .enable_reg = 0x50004,
2042                 .enable_mask = BIT(0),
2043                 .hw.init = &(struct clk_init_data) {
2044                         .name = "gcc_camss_ispif_ahb_clk",
2045                         .parent_hws = (const struct clk_hw*[]){
2046                                 &camss_top_ahb_clk_src.clkr.hw,
2047                         },
2048                         .num_parents = 1,
2049                         .ops = &clk_branch2_ops,
2050                         .flags = CLK_SET_RATE_PARENT,
2051                 }
2052         }
2053 };
2054
2055 static struct clk_branch gcc_camss_jpeg0_clk = {
2056         .halt_reg = 0x57020,
2057         .halt_check = BRANCH_HALT,
2058         .clkr = {
2059                 .enable_reg = 0x57020,
2060                 .enable_mask = BIT(0),
2061                 .hw.init = &(struct clk_init_data) {
2062                         .name = "gcc_camss_jpeg0_clk",
2063                         .parent_hws = (const struct clk_hw*[]){
2064                                 &jpeg0_clk_src.clkr.hw,
2065                         },
2066                         .num_parents = 1,
2067                         .ops = &clk_branch2_ops,
2068                         .flags = CLK_SET_RATE_PARENT,
2069                 }
2070         }
2071 };
2072
2073 static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2074         .halt_reg = 0x57024,
2075         .halt_check = BRANCH_HALT,
2076         .clkr = {
2077                 .enable_reg = 0x57024,
2078                 .enable_mask = BIT(0),
2079                 .hw.init = &(struct clk_init_data) {
2080                         .name = "gcc_camss_jpeg_ahb_clk",
2081                         .parent_hws = (const struct clk_hw*[]){
2082                                 &camss_top_ahb_clk_src.clkr.hw,
2083                         },
2084                         .num_parents = 1,
2085                         .ops = &clk_branch2_ops,
2086                         .flags = CLK_SET_RATE_PARENT,
2087                 }
2088         }
2089 };
2090
2091 static struct clk_branch gcc_camss_jpeg_axi_clk = {
2092         .halt_reg = 0x57028,
2093         .halt_check = BRANCH_HALT,
2094         .clkr = {
2095                 .enable_reg = 0x57028,
2096                 .enable_mask = BIT(0),
2097                 .hw.init = &(struct clk_init_data) {
2098                         .name = "gcc_camss_jpeg_axi_clk",
2099                         .ops = &clk_branch2_ops,
2100                 }
2101         }
2102 };
2103
2104 static struct clk_branch gcc_camss_mclk0_clk = {
2105         .halt_reg = 0x52018,
2106         .halt_check = BRANCH_HALT,
2107         .clkr = {
2108                 .enable_reg = 0x52018,
2109                 .enable_mask = BIT(0),
2110                 .hw.init = &(struct clk_init_data) {
2111                         .name = "gcc_camss_mclk0_clk",
2112                         .parent_hws = (const struct clk_hw*[]){
2113                                 &mclk0_clk_src.clkr.hw,
2114                         },
2115                         .num_parents = 1,
2116                         .ops = &clk_branch2_ops,
2117                         .flags = CLK_SET_RATE_PARENT,
2118                 }
2119         }
2120 };
2121
2122 static struct clk_branch gcc_camss_mclk1_clk = {
2123         .halt_reg = 0x53018,
2124         .halt_check = BRANCH_HALT,
2125         .clkr = {
2126                 .enable_reg = 0x53018,
2127                 .enable_mask = BIT(0),
2128                 .hw.init = &(struct clk_init_data) {
2129                         .name = "gcc_camss_mclk1_clk",
2130                         .parent_hws = (const struct clk_hw*[]){
2131                                 &mclk1_clk_src.clkr.hw,
2132                         },
2133                         .num_parents = 1,
2134                         .ops = &clk_branch2_ops,
2135                         .flags = CLK_SET_RATE_PARENT,
2136                 }
2137         }
2138 };
2139
2140 static struct clk_branch gcc_camss_mclk2_clk = {
2141         .halt_reg = 0x5c018,
2142         .halt_check = BRANCH_HALT,
2143         .clkr = {
2144                 .enable_reg = 0x5c018,
2145                 .enable_mask = BIT(0),
2146                 .hw.init = &(struct clk_init_data) {
2147                         .name = "gcc_camss_mclk2_clk",
2148                         .parent_hws = (const struct clk_hw*[]){
2149                                 &mclk2_clk_src.clkr.hw,
2150                         },
2151                         .num_parents = 1,
2152                         .ops = &clk_branch2_ops,
2153                         .flags = CLK_SET_RATE_PARENT,
2154                 }
2155         }
2156 };
2157
2158 static struct clk_branch gcc_camss_micro_ahb_clk = {
2159         .halt_reg = 0x5600c,
2160         .halt_check = BRANCH_HALT,
2161         .clkr = {
2162                 .enable_reg = 0x5600c,
2163                 .enable_mask = BIT(0),
2164                 .hw.init = &(struct clk_init_data) {
2165                         .name = "gcc_camss_micro_ahb_clk",
2166                         .parent_hws = (const struct clk_hw*[]){
2167                                 &camss_top_ahb_clk_src.clkr.hw,
2168                         },
2169                         .num_parents = 1,
2170                         .ops = &clk_branch2_ops,
2171                         .flags = CLK_SET_RATE_PARENT,
2172                 }
2173         }
2174 };
2175
2176 static struct clk_branch gcc_camss_top_ahb_clk = {
2177         .halt_reg = 0x5a014,
2178         .halt_check = BRANCH_HALT,
2179         .clkr = {
2180                 .enable_reg = 0x5a014,
2181                 .enable_mask = BIT(0),
2182                 .hw.init = &(struct clk_init_data) {
2183                         .name = "gcc_camss_top_ahb_clk",
2184                         .parent_hws = (const struct clk_hw*[]){
2185                                 &camss_top_ahb_clk_src.clkr.hw,
2186                         },
2187                         .num_parents = 1,
2188                         .ops = &clk_branch2_ops,
2189                         .flags = CLK_SET_RATE_PARENT,
2190                 }
2191         }
2192 };
2193
2194 static struct clk_branch gcc_camss_vfe0_ahb_clk = {
2195         .halt_reg = 0x58044,
2196         .halt_check = BRANCH_HALT,
2197         .clkr = {
2198                 .enable_reg = 0x58044,
2199                 .enable_mask = BIT(0),
2200                 .hw.init = &(struct clk_init_data) {
2201                         .name = "gcc_camss_vfe0_ahb_clk",
2202                         .parent_hws = (const struct clk_hw*[]){
2203                                 &camss_top_ahb_clk_src.clkr.hw,
2204                         },
2205                         .num_parents = 1,
2206                         .ops = &clk_branch2_ops,
2207                         .flags = CLK_SET_RATE_PARENT,
2208                 }
2209         }
2210 };
2211
2212 static struct clk_branch gcc_camss_vfe0_axi_clk = {
2213         .halt_reg = 0x58048,
2214         .halt_check = BRANCH_HALT,
2215         .clkr = {
2216                 .enable_reg = 0x58048,
2217                 .enable_mask = BIT(0),
2218                 .hw.init = &(struct clk_init_data) {
2219                         .name = "gcc_camss_vfe0_axi_clk",
2220                         .ops = &clk_branch2_ops,
2221                 }
2222         }
2223 };
2224
2225 static struct clk_branch gcc_camss_vfe0_clk = {
2226         .halt_reg = 0x58038,
2227         .halt_check = BRANCH_HALT,
2228         .clkr = {
2229                 .enable_reg = 0x58038,
2230                 .enable_mask = BIT(0),
2231                 .hw.init = &(struct clk_init_data) {
2232                         .name = "gcc_camss_vfe0_clk",
2233                         .parent_hws = (const struct clk_hw*[]){
2234                                 &vfe0_clk_src.clkr.hw,
2235                         },
2236                         .num_parents = 1,
2237                         .ops = &clk_branch2_ops,
2238                         .flags = CLK_SET_RATE_PARENT,
2239                 }
2240         }
2241 };
2242
2243 static struct clk_branch gcc_camss_vfe1_ahb_clk = {
2244         .halt_reg = 0x58060,
2245         .halt_check = BRANCH_HALT,
2246         .clkr = {
2247                 .enable_reg = 0x58060,
2248                 .enable_mask = BIT(0),
2249                 .hw.init = &(struct clk_init_data) {
2250                         .name = "gcc_camss_vfe1_ahb_clk",
2251                         .parent_hws = (const struct clk_hw*[]){
2252                                 &camss_top_ahb_clk_src.clkr.hw,
2253                         },
2254                         .num_parents = 1,
2255                         .ops = &clk_branch2_ops,
2256                         .flags = CLK_SET_RATE_PARENT,
2257                 }
2258         }
2259 };
2260
2261 static struct clk_branch gcc_camss_vfe1_axi_clk = {
2262         .halt_reg = 0x58068,
2263         .halt_check = BRANCH_HALT,
2264         .clkr = {
2265                 .enable_reg = 0x58068,
2266                 .enable_mask = BIT(0),
2267                 .hw.init = &(struct clk_init_data) {
2268                         .name = "gcc_camss_vfe1_axi_clk",
2269                         .ops = &clk_branch2_ops,
2270                 }
2271         }
2272 };
2273
2274 static struct clk_branch gcc_camss_vfe1_clk = {
2275         .halt_reg = 0x5805c,
2276         .halt_check = BRANCH_HALT,
2277         .clkr = {
2278                 .enable_reg = 0x5805c,
2279                 .enable_mask = BIT(0),
2280                 .hw.init = &(struct clk_init_data) {
2281                         .name = "gcc_camss_vfe1_clk",
2282                         .parent_hws = (const struct clk_hw*[]){
2283                                 &vfe1_clk_src.clkr.hw,
2284                         },
2285                         .num_parents = 1,
2286                         .ops = &clk_branch2_ops,
2287                         .flags = CLK_SET_RATE_PARENT,
2288                 }
2289         }
2290 };
2291
2292 static struct clk_branch gcc_cpp_tbu_clk = {
2293         .halt_reg = 0x12040,
2294         .halt_check = BRANCH_HALT_VOTED,
2295         .clkr = {
2296                 .enable_reg = 0x4500c,
2297                 .enable_mask = BIT(14),
2298                 .hw.init = &(struct clk_init_data) {
2299                         .name = "gcc_cpp_tbu_clk",
2300                         .ops = &clk_branch2_ops,
2301                 }
2302         }
2303 };
2304
2305 static struct clk_branch gcc_crypto_ahb_clk = {
2306         .halt_reg = 0x16024,
2307         .halt_check = BRANCH_HALT_VOTED,
2308         .clkr = {
2309                 .enable_reg = 0x45004,
2310                 .enable_mask = BIT(0),
2311                 .hw.init = &(struct clk_init_data) {
2312                         .name = "gcc_crypto_ahb_clk",
2313                         .ops = &clk_branch2_ops,
2314                 }
2315         }
2316 };
2317
2318 static struct clk_branch gcc_crypto_axi_clk = {
2319         .halt_reg = 0x16020,
2320         .halt_check = BRANCH_HALT_VOTED,
2321         .clkr = {
2322                 .enable_reg = 0x45004,
2323                 .enable_mask = BIT(1),
2324                 .hw.init = &(struct clk_init_data) {
2325                         .name = "gcc_crypto_axi_clk",
2326                         .ops = &clk_branch2_ops,
2327                 }
2328         }
2329 };
2330
2331 static struct clk_branch gcc_crypto_clk = {
2332         .halt_reg = 0x1601c,
2333         .halt_check = BRANCH_HALT_VOTED,
2334         .clkr = {
2335                 .enable_reg = 0x45004,
2336                 .enable_mask = BIT(2),
2337                 .hw.init = &(struct clk_init_data) {
2338                         .name = "gcc_crypto_clk",
2339                         .parent_hws = (const struct clk_hw*[]){
2340                                 &crypto_clk_src.clkr.hw,
2341                         },
2342                         .num_parents = 1,
2343                         .ops = &clk_branch2_ops,
2344                         .flags = CLK_SET_RATE_PARENT,
2345                 }
2346         }
2347 };
2348
2349 static struct clk_branch gcc_dcc_clk = {
2350         .halt_reg = 0x77004,
2351         .halt_check = BRANCH_HALT,
2352         .clkr = {
2353                 .enable_reg = 0x77004,
2354                 .enable_mask = BIT(0),
2355                 .hw.init = &(struct clk_init_data) {
2356                         .name = "gcc_dcc_clk",
2357                         .ops = &clk_branch2_ops,
2358                 }
2359         }
2360 };
2361
2362 static struct clk_branch gcc_gfx_tbu_clk = {
2363         .halt_reg = 0x12010,
2364         .halt_check = BRANCH_HALT_VOTED,
2365         .clkr = {
2366                 .enable_reg = 0x4500c,
2367                 .enable_mask = BIT(3),
2368                 .hw.init = &(struct clk_init_data){
2369                         .name = "gcc_gfx_tbu_clk",
2370                         .ops = &clk_branch2_ops,
2371                 },
2372         },
2373 };
2374
2375 static struct clk_branch gcc_gfx_tcu_clk = {
2376         .halt_reg = 0x12020,
2377         .halt_check = BRANCH_HALT_VOTED,
2378         .clkr = {
2379                 .enable_reg = 0x4500c,
2380                 .enable_mask = BIT(2),
2381                 .hw.init = &(struct clk_init_data){
2382                         .name = "gcc_gfx_tcu_clk",
2383                         .ops = &clk_branch2_ops,
2384                 },
2385         },
2386 };
2387
2388 static struct clk_branch gcc_gtcu_ahb_clk = {
2389         .halt_reg = 0x12044,
2390         .halt_check = BRANCH_HALT_VOTED,
2391         .clkr = {
2392                 .enable_reg = 0x4500c,
2393                 .enable_mask = BIT(13),
2394                 .hw.init = &(struct clk_init_data){
2395                         .name = "gcc_gtcu_ahb_clk",
2396                         .ops = &clk_branch2_ops,
2397                 },
2398         },
2399 };
2400
2401 static struct clk_branch gcc_gp1_clk = {
2402         .halt_reg = 0x08000,
2403         .halt_check = BRANCH_HALT,
2404         .clkr = {
2405                 .enable_reg = 0x08000,
2406                 .enable_mask = BIT(0),
2407                 .hw.init = &(struct clk_init_data) {
2408                         .name = "gcc_gp1_clk",
2409                         .parent_hws = (const struct clk_hw*[]){
2410                                 &gp1_clk_src.clkr.hw,
2411                         },
2412                         .num_parents = 1,
2413                         .ops = &clk_branch2_ops,
2414                         .flags = CLK_SET_RATE_PARENT,
2415                 }
2416         }
2417 };
2418
2419 static struct clk_branch gcc_gp2_clk = {
2420         .halt_reg = 0x09000,
2421         .halt_check = BRANCH_HALT,
2422         .clkr = {
2423                 .enable_reg = 0x09000,
2424                 .enable_mask = BIT(0),
2425                 .hw.init = &(struct clk_init_data) {
2426                         .name = "gcc_gp2_clk",
2427                         .parent_hws = (const struct clk_hw*[]){
2428                                 &gp2_clk_src.clkr.hw,
2429                         },
2430                         .num_parents = 1,
2431                         .ops = &clk_branch2_ops,
2432                         .flags = CLK_SET_RATE_PARENT,
2433                 }
2434         }
2435 };
2436
2437 static struct clk_branch gcc_gp3_clk = {
2438         .halt_reg = 0x0a000,
2439         .halt_check = BRANCH_HALT,
2440         .clkr = {
2441                 .enable_reg = 0x0a000,
2442                 .enable_mask = BIT(0),
2443                 .hw.init = &(struct clk_init_data) {
2444                         .name = "gcc_gp3_clk",
2445                         .parent_hws = (const struct clk_hw*[]){
2446                                 &gp3_clk_src.clkr.hw,
2447                         },
2448                         .num_parents = 1,
2449                         .ops = &clk_branch2_ops,
2450                         .flags = CLK_SET_RATE_PARENT,
2451                 }
2452         }
2453 };
2454
2455 static struct clk_branch gcc_jpeg_tbu_clk = {
2456         .halt_reg = 0x12034,
2457         .halt_check = BRANCH_HALT_VOTED,
2458         .clkr = {
2459                 .enable_reg = 0x4500c,
2460                 .enable_mask = BIT(10),
2461                 .hw.init = &(struct clk_init_data) {
2462                         .name = "gcc_jpeg_tbu_clk",
2463                         .ops = &clk_branch2_ops,
2464                 }
2465         }
2466 };
2467
2468 static struct clk_branch gcc_mdp_tbu_clk = {
2469         .halt_reg = 0x1201c,
2470         .halt_check = BRANCH_HALT_VOTED,
2471         .clkr = {
2472                 .enable_reg = 0x4500c,
2473                 .enable_mask = BIT(4),
2474                 .hw.init = &(struct clk_init_data) {
2475                         .name = "gcc_mdp_tbu_clk",
2476                         .ops = &clk_branch2_ops,
2477                 }
2478         }
2479 };
2480
2481 static struct clk_branch gcc_mdss_ahb_clk = {
2482         .halt_reg = 0x4d07c,
2483         .halt_check = BRANCH_HALT,
2484         .clkr = {
2485                 .enable_reg = 0x4d07c,
2486                 .enable_mask = BIT(0),
2487                 .hw.init = &(struct clk_init_data) {
2488                         .name = "gcc_mdss_ahb_clk",
2489                         .ops = &clk_branch2_ops,
2490                 }
2491         }
2492 };
2493
2494 static struct clk_branch gcc_mdss_axi_clk = {
2495         .halt_reg = 0x4d080,
2496         .halt_check = BRANCH_HALT,
2497         .clkr = {
2498                 .enable_reg = 0x4d080,
2499                 .enable_mask = BIT(0),
2500                 .hw.init = &(struct clk_init_data) {
2501                         .name = "gcc_mdss_axi_clk",
2502                         .ops = &clk_branch2_ops,
2503                 }
2504         }
2505 };
2506
2507 static struct clk_branch gcc_mdss_byte0_clk = {
2508         .halt_reg = 0x4d094,
2509         .halt_check = BRANCH_HALT,
2510         .clkr = {
2511                 .enable_reg = 0x4d094,
2512                 .enable_mask = BIT(0),
2513                 .hw.init = &(struct clk_init_data) {
2514                         .name = "gcc_mdss_byte0_clk",
2515                         .parent_hws = (const struct clk_hw*[]){
2516                                 &byte0_clk_src.clkr.hw,
2517                         },
2518                         .num_parents = 1,
2519                         .ops = &clk_branch2_ops,
2520                         .flags = CLK_SET_RATE_PARENT,
2521                 }
2522         }
2523 };
2524
2525 static struct clk_branch gcc_mdss_esc0_clk = {
2526         .halt_reg = 0x4d098,
2527         .halt_check = BRANCH_HALT,
2528         .clkr = {
2529                 .enable_reg = 0x4d098,
2530                 .enable_mask = BIT(0),
2531                 .hw.init = &(struct clk_init_data) {
2532                         .name = "gcc_mdss_esc0_clk",
2533                         .parent_hws = (const struct clk_hw*[]){
2534                                 &esc0_clk_src.clkr.hw,
2535                         },
2536                         .num_parents = 1,
2537                         .ops = &clk_branch2_ops,
2538                         .flags = CLK_SET_RATE_PARENT,
2539                 }
2540         }
2541 };
2542
2543 static struct clk_branch gcc_mdss_mdp_clk = {
2544         .halt_reg = 0x4d088,
2545         .halt_check = BRANCH_HALT,
2546         .clkr = {
2547                 .enable_reg = 0x4d088,
2548                 .enable_mask = BIT(0),
2549                 .hw.init = &(struct clk_init_data) {
2550                         .name = "gcc_mdss_mdp_clk",
2551                         .parent_hws = (const struct clk_hw*[]){
2552                                 &mdp_clk_src.clkr.hw,
2553                         },
2554                         .num_parents = 1,
2555                         .ops = &clk_branch2_ops,
2556                         .flags = CLK_SET_RATE_PARENT,
2557                 }
2558         }
2559 };
2560
2561 static struct clk_branch gcc_mdss_pclk0_clk = {
2562         .halt_reg = 0x4d084,
2563         .halt_check = BRANCH_HALT,
2564         .clkr = {
2565                 .enable_reg = 0x4d084,
2566                 .enable_mask = BIT(0),
2567                 .hw.init = &(struct clk_init_data) {
2568                         .name = "gcc_mdss_pclk0_clk",
2569                         .parent_hws = (const struct clk_hw*[]){
2570                                 &pclk0_clk_src.clkr.hw,
2571                         },
2572                         .num_parents = 1,
2573                         .ops = &clk_branch2_ops,
2574                         .flags = CLK_SET_RATE_PARENT,
2575                 }
2576         }
2577 };
2578
2579 static struct clk_branch gcc_mdss_vsync_clk = {
2580         .halt_reg = 0x4d090,
2581         .halt_check = BRANCH_HALT,
2582         .clkr = {
2583                 .enable_reg = 0x4d090,
2584                 .enable_mask = BIT(0),
2585                 .hw.init = &(struct clk_init_data) {
2586                         .name = "gcc_mdss_vsync_clk",
2587                         .parent_hws = (const struct clk_hw*[]){
2588                                 &vsync_clk_src.clkr.hw,
2589                         },
2590                         .num_parents = 1,
2591                         .ops = &clk_branch2_ops,
2592                         .flags = CLK_SET_RATE_PARENT,
2593                 }
2594         }
2595 };
2596
2597 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2598         .halt_reg = 0x49000,
2599         .halt_check = BRANCH_HALT,
2600         .clkr = {
2601                 .enable_reg = 0x49000,
2602                 .enable_mask = BIT(0),
2603                 .hw.init = &(struct clk_init_data) {
2604                         .name = "gcc_mss_cfg_ahb_clk",
2605                         .ops = &clk_branch2_ops,
2606                 }
2607         }
2608 };
2609
2610 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
2611         .halt_reg = 0x49004,
2612         .halt_check = BRANCH_HALT,
2613         .clkr = {
2614                 .enable_reg = 0x49004,
2615                 .enable_mask = BIT(0),
2616                 .hw.init = &(struct clk_init_data) {
2617                         .name = "gcc_mss_q6_bimc_axi_clk",
2618                         .ops = &clk_branch2_ops,
2619                 }
2620         }
2621 };
2622
2623 static struct clk_branch gcc_oxili_ahb_clk = {
2624         .halt_reg = 0x59028,
2625         .halt_check = BRANCH_HALT,
2626         .clkr = {
2627                 .enable_reg = 0x59028,
2628                 .enable_mask = BIT(0),
2629                 .hw.init = &(struct clk_init_data) {
2630                         .name = "gcc_oxili_ahb_clk",
2631                         .ops = &clk_branch2_ops,
2632                 }
2633         }
2634 };
2635
2636 static struct clk_branch gcc_oxili_gfx3d_clk = {
2637         .halt_reg = 0x59020,
2638         .halt_check = BRANCH_HALT,
2639         .clkr = {
2640                 .enable_reg = 0x59020,
2641                 .enable_mask = BIT(0),
2642                 .hw.init = &(struct clk_init_data) {
2643                         .name = "gcc_oxili_gfx3d_clk",
2644                         .parent_hws = (const struct clk_hw*[]){
2645                                 &gfx3d_clk_src.clkr.hw,
2646                         },
2647                         .num_parents = 1,
2648                         .ops = &clk_branch2_ops,
2649                         .flags = CLK_SET_RATE_PARENT,
2650                 }
2651         }
2652 };
2653
2654 static struct clk_branch gcc_pdm2_clk = {
2655         .halt_reg = 0x4400c,
2656         .halt_check = BRANCH_HALT,
2657         .clkr = {
2658                 .enable_reg = 0x4400c,
2659                 .enable_mask = BIT(0),
2660                 .hw.init = &(struct clk_init_data) {
2661                         .name = "gcc_pdm2_clk",
2662                         .parent_hws = (const struct clk_hw*[]){
2663                                 &pdm2_clk_src.clkr.hw,
2664                         },
2665                         .num_parents = 1,
2666                         .ops = &clk_branch2_ops,
2667                         .flags = CLK_SET_RATE_PARENT,
2668                 }
2669         }
2670 };
2671
2672 static struct clk_branch gcc_pdm_ahb_clk = {
2673         .halt_reg = 0x44004,
2674         .halt_check = BRANCH_HALT,
2675         .clkr = {
2676                 .enable_reg = 0x44004,
2677                 .enable_mask = BIT(0),
2678                 .hw.init = &(struct clk_init_data) {
2679                         .name = "gcc_pdm_ahb_clk",
2680                         .ops = &clk_branch2_ops,
2681                 }
2682         }
2683 };
2684
2685 static struct clk_branch gcc_prng_ahb_clk = {
2686         .halt_reg = 0x13004,
2687         .halt_check = BRANCH_HALT_VOTED,
2688         .clkr = {
2689                 .enable_reg = 0x45004,
2690                 .enable_mask = BIT(8),
2691                 .hw.init = &(struct clk_init_data) {
2692                         .name = "gcc_prng_ahb_clk",
2693                         .ops = &clk_branch2_ops,
2694                 }
2695         }
2696 };
2697
2698 static struct clk_branch gcc_qdss_dap_clk = {
2699         .halt_reg = 0x29084,
2700         .halt_check = BRANCH_HALT_VOTED,
2701         .clkr = {
2702                 .enable_reg = 0x45004,
2703                 .enable_mask = BIT(11),
2704                 .hw.init = &(struct clk_init_data) {
2705                         .name = "gcc_qdss_dap_clk",
2706                         .ops = &clk_branch2_ops,
2707                 }
2708         }
2709 };
2710
2711 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2712         .halt_reg = 0x5d014,
2713         .halt_check = BRANCH_HALT,
2714         .clkr = {
2715                 .enable_reg = 0x5d014,
2716                 .enable_mask = BIT(0),
2717                 .hw.init = &(struct clk_init_data) {
2718                         .name = "gcc_sdcc1_ice_core_clk",
2719                         .parent_hws = (const struct clk_hw*[]){
2720                                 &sdcc1_ice_core_clk_src.clkr.hw,
2721                         },
2722                         .num_parents = 1,
2723                         .ops = &clk_branch2_ops,
2724                         .flags = CLK_SET_RATE_PARENT,
2725                 }
2726         }
2727 };
2728
2729 static struct clk_branch gcc_sdcc1_ahb_clk = {
2730         .halt_reg = 0x4201c,
2731         .halt_check = BRANCH_HALT,
2732         .clkr = {
2733                 .enable_reg = 0x4201c,
2734                 .enable_mask = BIT(0),
2735                 .hw.init = &(struct clk_init_data) {
2736                         .name = "gcc_sdcc1_ahb_clk",
2737                         .ops = &clk_branch2_ops,
2738                 }
2739         }
2740 };
2741
2742 static struct clk_branch gcc_sdcc2_ahb_clk = {
2743         .halt_reg = 0x4301c,
2744         .halt_check = BRANCH_HALT,
2745         .clkr = {
2746                 .enable_reg = 0x4301c,
2747                 .enable_mask = BIT(0),
2748                 .hw.init = &(struct clk_init_data) {
2749                         .name = "gcc_sdcc2_ahb_clk",
2750                         .ops = &clk_branch2_ops,
2751                 }
2752         }
2753 };
2754
2755 static struct clk_branch gcc_sdcc1_apps_clk = {
2756         .halt_reg = 0x42018,
2757         .halt_check = BRANCH_HALT,
2758         .clkr = {
2759                 .enable_reg = 0x42018,
2760                 .enable_mask = BIT(0),
2761                 .hw.init = &(struct clk_init_data) {
2762                         .name = "gcc_sdcc1_apps_clk",
2763                         .parent_hws = (const struct clk_hw*[]){
2764                                 &sdcc1_apps_clk_src.clkr.hw,
2765                         },
2766                         .num_parents = 1,
2767                         .ops = &clk_branch2_ops,
2768                         .flags = CLK_SET_RATE_PARENT,
2769                 }
2770         }
2771 };
2772
2773 static struct clk_branch gcc_sdcc2_apps_clk = {
2774         .halt_reg = 0x43018,
2775         .halt_check = BRANCH_HALT,
2776         .clkr = {
2777                 .enable_reg = 0x43018,
2778                 .enable_mask = BIT(0),
2779                 .hw.init = &(struct clk_init_data) {
2780                         .name = "gcc_sdcc2_apps_clk",
2781                         .parent_hws = (const struct clk_hw*[]){
2782                                 &sdcc2_apps_clk_src.clkr.hw,
2783                         },
2784                         .num_parents = 1,
2785                         .ops = &clk_branch2_ops,
2786                         .flags = CLK_SET_RATE_PARENT,
2787                 }
2788         }
2789 };
2790
2791 static struct clk_branch gcc_smmu_cfg_clk = {
2792         .halt_reg = 0x12038,
2793         .halt_check = BRANCH_HALT_VOTED,
2794         .clkr = {
2795                 .enable_reg = 0x4500c,
2796                 .enable_mask = BIT(12),
2797                 .hw.init = &(struct clk_init_data) {
2798                         .name = "gcc_smmu_cfg_clk",
2799                         .ops = &clk_branch2_ops,
2800                 }
2801         }
2802 };
2803
2804 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2805         .halt_reg = 0x4102c,
2806         .clkr = {
2807                 .enable_reg = 0x4102c,
2808                 .enable_mask = BIT(0),
2809                 .hw.init = &(struct clk_init_data){
2810                         .name = "gcc_usb2a_phy_sleep_clk",
2811                         .ops = &clk_branch2_ops,
2812                 },
2813         },
2814 };
2815
2816 static struct clk_branch gcc_usb_hs_ahb_clk = {
2817         .halt_reg = 0x41008,
2818         .clkr = {
2819                 .enable_reg = 0x41008,
2820                 .enable_mask = BIT(0),
2821                 .hw.init = &(struct clk_init_data){
2822                         .name = "gcc_usb_hs_ahb_clk",
2823                         .ops = &clk_branch2_ops,
2824                 },
2825         },
2826 };
2827
2828 static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
2829         .halt_reg = 0x41030,
2830         .clkr = {
2831                 .enable_reg = 0x41030,
2832                 .enable_mask = BIT(0),
2833                 .hw.init = &(struct clk_init_data){
2834                         .name = "gcc_usb_hs_phy_cfg_ahb_clk",
2835                         .ops = &clk_branch2_ops,
2836                 },
2837         },
2838 };
2839
2840 static struct clk_branch gcc_usb_hs_system_clk = {
2841         .halt_reg = 0x41004,
2842         .clkr = {
2843                 .enable_reg = 0x41004,
2844                 .enable_mask = BIT(0),
2845                 .hw.init = &(struct clk_init_data){
2846                         .name = "gcc_usb_hs_system_clk",
2847                         .parent_hws = (const struct clk_hw*[]){
2848                                 &usb_hs_system_clk_src.clkr.hw,
2849                         },
2850                         .num_parents = 1,
2851                         .flags = CLK_SET_RATE_PARENT,
2852                         .ops = &clk_branch2_ops,
2853                 },
2854         },
2855 };
2856
2857 static struct clk_branch gcc_venus0_ahb_clk = {
2858         .halt_reg = 0x4c020,
2859         .halt_check = BRANCH_HALT,
2860         .clkr = {
2861                 .enable_reg = 0x4c020,
2862                 .enable_mask = BIT(0),
2863                 .hw.init = &(struct clk_init_data) {
2864                         .name = "gcc_venus0_ahb_clk",
2865                         .ops = &clk_branch2_ops,
2866                 }
2867         }
2868 };
2869
2870 static struct clk_branch gcc_venus0_axi_clk = {
2871         .halt_reg = 0x4c024,
2872         .halt_check = BRANCH_HALT,
2873         .clkr = {
2874                 .enable_reg = 0x4c024,
2875                 .enable_mask = BIT(0),
2876                 .hw.init = &(struct clk_init_data) {
2877                         .name = "gcc_venus0_axi_clk",
2878                         .ops = &clk_branch2_ops,
2879                 }
2880         }
2881 };
2882
2883 static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
2884         .halt_reg = 0x4c02c,
2885         .halt_check = BRANCH_HALT,
2886         .clkr = {
2887                 .enable_reg = 0x4c02c,
2888                 .enable_mask = BIT(0),
2889                 .hw.init = &(struct clk_init_data) {
2890                         .name = "gcc_venus0_core0_vcodec0_clk",
2891                         .parent_hws = (const struct clk_hw*[]){
2892                                 &vcodec0_clk_src.clkr.hw,
2893                         },
2894                         .num_parents = 1,
2895                         .ops = &clk_branch2_ops,
2896                         .flags = CLK_SET_RATE_PARENT,
2897                 }
2898         }
2899 };
2900
2901 static struct clk_branch gcc_venus0_vcodec0_clk = {
2902         .halt_reg = 0x4c01c,
2903         .halt_check = BRANCH_HALT,
2904         .clkr = {
2905                 .enable_reg = 0x4c01c,
2906                 .enable_mask = BIT(0),
2907                 .hw.init = &(struct clk_init_data) {
2908                         .name = "gcc_venus0_vcodec0_clk",
2909                         .parent_hws = (const struct clk_hw*[]){
2910                                 &vcodec0_clk_src.clkr.hw,
2911                         },
2912                         .num_parents = 1,
2913                         .ops = &clk_branch2_ops,
2914                         .flags = CLK_SET_RATE_PARENT,
2915                 }
2916         }
2917 };
2918
2919 static struct clk_branch gcc_venus_tbu_clk = {
2920         .halt_reg = 0x12014,
2921         .halt_check = BRANCH_HALT_VOTED,
2922         .clkr = {
2923                 .enable_reg = 0x4500c,
2924                 .enable_mask = BIT(5),
2925                 .hw.init = &(struct clk_init_data) {
2926                         .name = "gcc_venus_tbu_clk",
2927                         .ops = &clk_branch2_ops,
2928                 }
2929         }
2930 };
2931
2932 static struct clk_branch gcc_vfe1_tbu_clk = {
2933         .halt_reg = 0x12090,
2934         .halt_check = BRANCH_HALT_VOTED,
2935         .clkr = {
2936                 .enable_reg = 0x4500c,
2937                 .enable_mask = BIT(17),
2938                 .hw.init = &(struct clk_init_data) {
2939                         .name = "gcc_vfe1_tbu_clk",
2940                         .ops = &clk_branch2_ops,
2941                 }
2942         }
2943 };
2944
2945 static struct clk_branch gcc_vfe_tbu_clk = {
2946         .halt_reg = 0x1203c,
2947         .halt_check = BRANCH_HALT_VOTED,
2948         .clkr = {
2949                 .enable_reg = 0x4500c,
2950                 .enable_mask = BIT(9),
2951                 .hw.init = &(struct clk_init_data) {
2952                         .name = "gcc_vfe_tbu_clk",
2953                         .ops = &clk_branch2_ops,
2954                 }
2955         }
2956 };
2957
2958 static struct gdsc venus_gdsc = {
2959         .gdscr = 0x4c018,
2960         .cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
2961         .cxc_count = 2,
2962         .pd = {
2963                 .name = "venus_gdsc",
2964         },
2965         .pwrsts = PWRSTS_OFF_ON,
2966 };
2967
2968 static struct gdsc venus_core0_gdsc = {
2969         .gdscr = 0x4c028,
2970         .cxcs = (unsigned int []){ 0x4c02c },
2971         .cxc_count = 1,
2972         .pd = {
2973                 .name = "venus_core0",
2974         },
2975         .flags = HW_CTRL,
2976         .pwrsts = PWRSTS_OFF_ON,
2977 };
2978
2979 static struct gdsc mdss_gdsc = {
2980         .gdscr = 0x4d078,
2981         .cxcs = (unsigned int []){ 0x4d080, 0x4d088 },
2982         .cxc_count = 2,
2983         .pd = {
2984                 .name = "mdss_gdsc",
2985         },
2986         .pwrsts = PWRSTS_OFF_ON,
2987 };
2988
2989 static struct gdsc jpeg_gdsc = {
2990         .gdscr = 0x5701c,
2991         .cxcs = (unsigned int []){ 0x57020, 0x57028 },
2992         .cxc_count = 2,
2993         .pd = {
2994                 .name = "jpeg_gdsc",
2995         },
2996         .pwrsts = PWRSTS_OFF_ON,
2997 };
2998
2999 static struct gdsc vfe0_gdsc = {
3000         .gdscr = 0x58034,
3001         .cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },
3002         .cxc_count = 4,
3003         .pd = {
3004                 .name = "vfe0_gdsc",
3005         },
3006         .pwrsts = PWRSTS_OFF_ON,
3007 };
3008
3009 static struct gdsc vfe1_gdsc = {
3010         .gdscr = 0x5806c,
3011         .cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },
3012         .cxc_count = 4,
3013         .pd = {
3014                 .name = "vfe1_gdsc",
3015         },
3016         .pwrsts = PWRSTS_OFF_ON,
3017 };
3018
3019 static struct gdsc oxili_gx_gdsc = {
3020         .gdscr = 0x5901c,
3021         .clamp_io_ctrl = 0x5b00c,
3022         .cxcs = (unsigned int []){ 0x59000, 0x59020 },
3023         .cxc_count = 2,
3024         .pd = {
3025                 .name = "oxili_gx_gdsc",
3026         },
3027         .pwrsts = PWRSTS_OFF_ON,
3028         .flags = CLAMP_IO,
3029 };
3030
3031 static struct gdsc cpp_gdsc = {
3032         .gdscr = 0x58078,
3033         .cxcs = (unsigned int []){ 0x5803c, 0x58064 },
3034         .cxc_count = 2,
3035         .pd = {
3036                 .name = "cpp_gdsc",
3037         },
3038         .flags = ALWAYS_ON,
3039         .pwrsts = PWRSTS_OFF_ON,
3040 };
3041
3042 static struct clk_regmap *gcc_msm8917_clocks[] = {
3043         [GPLL0] = &gpll0.clkr,
3044         [GPLL0_EARLY] = &gpll0_early.clkr,
3045         [GPLL3] = &gpll3.clkr,
3046         [GPLL3_EARLY] = &gpll3_early.clkr,
3047         [GPLL4] = &gpll4.clkr,
3048         [GPLL4_EARLY] = &gpll4_early.clkr,
3049         [GPLL6] = &gpll6,
3050         [GPLL6_EARLY] = &gpll6_early.clkr,
3051         [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3052         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3053         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3054         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3055         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3056         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3057         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3058         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3059         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3060         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3061         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3062         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3063         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3064         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3065         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3066         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3067         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3068         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3069         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3070         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3071         [CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
3072         [CCI_CLK_SRC] = &cci_clk_src.clkr,
3073         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3074         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3075         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3076         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3077         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3078         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3079         [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3080         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3081         [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3082         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3083         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3084         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3085         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3086         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3087         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3088         [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3089         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3090         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3091         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3092         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3093         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3094         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3095         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3096         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3097         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3098         [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3099         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3100         [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3101         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3102         [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3103         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3104         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3105         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3106         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3107         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3108         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3109         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3110         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3111         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3112         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3113         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3114         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3115         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3116         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3117         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3118         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3119         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3120         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3121         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3122         [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3123         [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3124         [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3125         [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3126         [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3127         [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3128         [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3129         [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3130         [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3131         [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3132         [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3133         [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3134         [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3135         [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3136         [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3137         [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3138         [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3139         [GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
3140         [GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
3141         [GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
3142         [GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
3143         [GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
3144         [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3145         [GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
3146         [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3147         [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3148         [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3149         [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3150         [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3151         [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3152         [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3153         [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3154         [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
3155         [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3156         [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3157         [GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
3158         [GCC_CAMSS_VFE0_AXI_CLK] = &gcc_camss_vfe0_axi_clk.clkr,
3159         [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3160         [GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
3161         [GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,
3162         [GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
3163         [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
3164         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3165         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3166         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3167         [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
3168         [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
3169         [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3170         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3171         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3172         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3173         [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3174         [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3175         [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3176         [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3177         [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3178         [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3179         [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3180         [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3181         [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3182         [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3183         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3184         [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3185         [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3186         [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3187         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3188         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3189         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3190         [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3191         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3192         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3193         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3194         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3195         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3196         [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3197         [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3198         [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3199         [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
3200         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3201         [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3202         [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3203         [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
3204         [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3205         [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3206         [GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,
3207         [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3208 };
3209
3210 static const struct qcom_reset_map gcc_msm8917_resets[] = {
3211         [GCC_CAMSS_MICRO_BCR]           = { 0x56008 },
3212         [GCC_MSS_BCR]                   = { 0x71000 },
3213         [GCC_QUSB2_PHY_BCR]             = { 0x4103c },
3214         [GCC_USB_HS_BCR]                = { 0x41000 },
3215         [GCC_USB2_HS_PHY_ONLY_BCR]      = { 0x41034 },
3216 };
3217
3218 static const struct regmap_config gcc_msm8917_regmap_config = {
3219         .reg_bits       = 32,
3220         .reg_stride     = 4,
3221         .val_bits       = 32,
3222         .max_register   = 0x80000,
3223         .fast_io        = true,
3224 };
3225
3226 static struct gdsc *gcc_msm8917_gdscs[] = {
3227         [CPP_GDSC] = &cpp_gdsc,
3228         [JPEG_GDSC] = &jpeg_gdsc,
3229         [MDSS_GDSC] = &mdss_gdsc,
3230         [OXILI_GX_GDSC] = &oxili_gx_gdsc,
3231         [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3232         [VENUS_GDSC] = &venus_gdsc,
3233         [VFE0_GDSC] = &vfe0_gdsc,
3234         [VFE1_GDSC] = &vfe1_gdsc,
3235 };
3236
3237 static const struct qcom_cc_desc gcc_msm8917_desc = {
3238         .config = &gcc_msm8917_regmap_config,
3239         .clks = gcc_msm8917_clocks,
3240         .num_clks = ARRAY_SIZE(gcc_msm8917_clocks),
3241         .resets = gcc_msm8917_resets,
3242         .num_resets = ARRAY_SIZE(gcc_msm8917_resets),
3243         .gdscs = gcc_msm8917_gdscs,
3244         .num_gdscs = ARRAY_SIZE(gcc_msm8917_gdscs),
3245 };
3246
3247 static const struct qcom_cc_desc gcc_qm215_desc = {
3248         .config = &gcc_msm8917_regmap_config,
3249         .clks = gcc_msm8917_clocks,
3250         .num_clks = ARRAY_SIZE(gcc_msm8917_clocks),
3251         .resets = gcc_msm8917_resets,
3252         .num_resets = ARRAY_SIZE(gcc_msm8917_resets),
3253         .gdscs = gcc_msm8917_gdscs,
3254         .num_gdscs = ARRAY_SIZE(gcc_msm8917_gdscs),
3255 };
3256
3257 static int gcc_msm8917_probe(struct platform_device *pdev)
3258 {
3259         struct regmap *regmap;
3260         const struct qcom_cc_desc *gcc_desc;
3261
3262         gcc_desc = of_device_get_match_data(&pdev->dev);
3263
3264         if (gcc_desc == &gcc_qm215_desc)
3265                 gfx3d_clk_src.parent_map = gcc_gfx3d_map_qm215;
3266
3267         regmap = qcom_cc_map(pdev, gcc_desc);
3268         if (IS_ERR(regmap))
3269                 return PTR_ERR(regmap);
3270
3271         clk_alpha_pll_configure(&gpll3_early, regmap, &gpll3_early_config);
3272
3273         return qcom_cc_really_probe(pdev, gcc_desc, regmap);
3274 }
3275
3276 static const struct of_device_id gcc_msm8917_match_table[] = {
3277         { .compatible = "qcom,gcc-msm8917", .data = &gcc_msm8917_desc },
3278         { .compatible = "qcom,gcc-qm215", .data = &gcc_qm215_desc },
3279         {},
3280 };
3281
3282 static struct platform_driver gcc_msm8917_driver = {
3283         .probe = gcc_msm8917_probe,
3284         .driver = {
3285                 .name = "gcc-msm8917",
3286                 .of_match_table = gcc_msm8917_match_table,
3287         },
3288 };
3289
3290 static int __init gcc_msm8917_init(void)
3291 {
3292         return platform_driver_register(&gcc_msm8917_driver);
3293 }
3294 core_initcall(gcc_msm8917_init);
3295
3296 static void __exit gcc_msm8917_exit(void)
3297 {
3298         platform_driver_unregister(&gcc_msm8917_driver);
3299 }
3300 module_exit(gcc_msm8917_exit);
3301
3302 MODULE_DESCRIPTION("Qualcomm GCC MSM8917 Driver");
3303 MODULE_LICENSE("GPL");