drivers/clk/qcom/gcc-ipq8074.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/err.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/regmap.h>
  14
  15 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
  16
  17 #include "common.h"
  18 #include "clk-regmap.h"
  19 #include "clk-pll.h"
  20 #include "clk-rcg.h"
  21 #include "clk-branch.h"
  22 #include "clk-alpha-pll.h"
  23 #include "clk-regmap-divider.h"
  24 #include "clk-regmap-mux.h"
  25 #include "gdsc.h"
  26 #include "reset.h"
  27
  28 enum {
  29         P_XO,
  30         P_GPLL0,
  31         P_GPLL0_DIV2,
  32         P_GPLL2,
  33         P_GPLL4,
  34         P_GPLL6,
  35         P_SLEEP_CLK,
  36         P_PCIE20_PHY0_PIPE,
  37         P_PCIE20_PHY1_PIPE,
  38         P_USB3PHY_0_PIPE,
  39         P_USB3PHY_1_PIPE,
  40         P_UBI32_PLL,
  41         P_NSS_CRYPTO_PLL,
  42         P_BIAS_PLL,
  43         P_BIAS_PLL_NSS_NOC,
  44         P_UNIPHY0_RX,
  45         P_UNIPHY0_TX,
  46         P_UNIPHY1_RX,
  47         P_UNIPHY1_TX,
  48         P_UNIPHY2_RX,
  49         P_UNIPHY2_TX,
  50 };
  51
  52 static struct clk_alpha_pll gpll0_main = {
  53         .offset = 0x21000,
  54         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  55         .clkr = {
  56                 .enable_reg = 0x0b000,
  57                 .enable_mask = BIT(0),
  58                 .hw.init = &(struct clk_init_data){
  59                         .name = "gpll0_main",
  60                         .parent_data = &(const struct clk_parent_data){
  61                                 .fw_name = "xo",
  62                                 .name = "xo",
  63                         },
  64                         .num_parents = 1,
  65                         .ops = &clk_alpha_pll_ops,
  66                 },
  67         },
  68 };
  69
  70 static struct clk_fixed_factor gpll0_out_main_div2 = {
  71         .mult = 1,
  72         .div = 2,
  73         .hw.init = &(struct clk_init_data){
  74                 .name = "gpll0_out_main_div2",
  75                 .parent_hws = (const struct clk_hw *[]){
  76                                 &gpll0_main.clkr.hw },
  77                 .num_parents = 1,
  78                 .ops = &clk_fixed_factor_ops,
  79                 .flags = CLK_SET_RATE_PARENT,
  80         },
  81 };
  82
  83 static struct clk_alpha_pll_postdiv gpll0 = {
  84         .offset = 0x21000,
  85         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  86         .width = 4,
  87         .clkr.hw.init = &(struct clk_init_data){
  88                 .name = "gpll0",
  89                 .parent_hws = (const struct clk_hw *[]){
  90                                 &gpll0_main.clkr.hw },
  91                 .num_parents = 1,
  92                 .ops = &clk_alpha_pll_postdiv_ro_ops,
  93         },
  94 };
  95
  96 static struct clk_alpha_pll gpll2_main = {
  97         .offset = 0x4a000,
  98         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  99         .clkr = {
 100                 .enable_reg = 0x0b000,
 101                 .enable_mask = BIT(2),
 102                 .hw.init = &(struct clk_init_data){
 103                         .name = "gpll2_main",
 104                         .parent_data = &(const struct clk_parent_data){
 105                                 .fw_name = "xo",
 106                                 .name = "xo",
 107                         },
 108                         .num_parents = 1,
 109                         .ops = &clk_alpha_pll_ops,
 110                         .flags = CLK_IS_CRITICAL,
 111                 },
 112         },
 113 };
 114
 115 static struct clk_alpha_pll_postdiv gpll2 = {
 116         .offset = 0x4a000,
 117         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 118         .width = 4,
 119         .clkr.hw.init = &(struct clk_init_data){
 120                 .name = "gpll2",
 121                 .parent_hws = (const struct clk_hw *[]){
 122                                 &gpll2_main.clkr.hw },
 123                 .num_parents = 1,
 124                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 125                 .flags = CLK_SET_RATE_PARENT,
 126         },
 127 };
 128
 129 static struct clk_alpha_pll gpll4_main = {
 130         .offset = 0x24000,
 131         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 132         .clkr = {
 133                 .enable_reg = 0x0b000,
 134                 .enable_mask = BIT(5),
 135                 .hw.init = &(struct clk_init_data){
 136                         .name = "gpll4_main",
 137                         .parent_data = &(const struct clk_parent_data){
 138                                 .fw_name = "xo",
 139                                 .name = "xo",
 140                         },
 141                         .num_parents = 1,
 142                         .ops = &clk_alpha_pll_ops,
 143                         .flags = CLK_IS_CRITICAL,
 144                 },
 145         },
 146 };
 147
 148 static struct clk_alpha_pll_postdiv gpll4 = {
 149         .offset = 0x24000,
 150         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 151         .width = 4,
 152         .clkr.hw.init = &(struct clk_init_data){
 153                 .name = "gpll4",
 154                 .parent_hws = (const struct clk_hw *[]){
 155                                 &gpll4_main.clkr.hw },
 156                 .num_parents = 1,
 157                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 158                 .flags = CLK_SET_RATE_PARENT,
 159         },
 160 };
 161
 162 static struct clk_alpha_pll gpll6_main = {
 163         .offset = 0x37000,
 164         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 165         .flags = SUPPORTS_DYNAMIC_UPDATE,
 166         .clkr = {
 167                 .enable_reg = 0x0b000,
 168                 .enable_mask = BIT(7),
 169                 .hw.init = &(struct clk_init_data){
 170                         .name = "gpll6_main",
 171                         .parent_data = &(const struct clk_parent_data){
 172                                 .fw_name = "xo",
 173                                 .name = "xo",
 174                         },
 175                         .num_parents = 1,
 176                         .ops = &clk_alpha_pll_ops,
 177                         .flags = CLK_IS_CRITICAL,
 178                 },
 179         },
 180 };
 181
 182 static struct clk_alpha_pll_postdiv gpll6 = {
 183         .offset = 0x37000,
 184         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 185         .width = 2,
 186         .clkr.hw.init = &(struct clk_init_data){
 187                 .name = "gpll6",
 188                 .parent_hws = (const struct clk_hw *[]){
 189                                 &gpll6_main.clkr.hw },
 190                 .num_parents = 1,
 191                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 192                 .flags = CLK_SET_RATE_PARENT,
 193         },
 194 };
 195
 196 static struct clk_fixed_factor gpll6_out_main_div2 = {
 197         .mult = 1,
 198         .div = 2,
 199         .hw.init = &(struct clk_init_data){
 200                 .name = "gpll6_out_main_div2",
 201                 .parent_hws = (const struct clk_hw *[]){
 202                                 &gpll6_main.clkr.hw },
 203                 .num_parents = 1,
 204                 .ops = &clk_fixed_factor_ops,
 205                 .flags = CLK_SET_RATE_PARENT,
 206         },
 207 };
 208
 209 static struct clk_alpha_pll ubi32_pll_main = {
 210         .offset = 0x25000,
 211         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 212         .flags = SUPPORTS_DYNAMIC_UPDATE,
 213         .clkr = {
 214                 .enable_reg = 0x0b000,
 215                 .enable_mask = BIT(6),
 216                 .hw.init = &(struct clk_init_data){
 217                         .name = "ubi32_pll_main",
 218                         .parent_data = &(const struct clk_parent_data){
 219                                 .fw_name = "xo",
 220                                 .name = "xo",
 221                         },
 222                         .num_parents = 1,
 223                         .ops = &clk_alpha_pll_huayra_ops,
 224                 },
 225         },
 226 };
 227
 228 static struct clk_alpha_pll_postdiv ubi32_pll = {
 229         .offset = 0x25000,
 230         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 231         .width = 2,
 232         .clkr.hw.init = &(struct clk_init_data){
 233                 .name = "ubi32_pll",
 234                 .parent_hws = (const struct clk_hw *[]){
 235                                 &ubi32_pll_main.clkr.hw },
 236                 .num_parents = 1,
 237                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 238                 .flags = CLK_SET_RATE_PARENT,
 239         },
 240 };
 241
 242 static struct clk_alpha_pll nss_crypto_pll_main = {
 243         .offset = 0x22000,
 244         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 245         .clkr = {
 246                 .enable_reg = 0x0b000,
 247                 .enable_mask = BIT(4),
 248                 .hw.init = &(struct clk_init_data){
 249                         .name = "nss_crypto_pll_main",
 250                         .parent_data = &(const struct clk_parent_data){
 251                                 .fw_name = "xo",
 252                                 .name = "xo",
 253                         },
 254                         .num_parents = 1,
 255                         .ops = &clk_alpha_pll_ops,
 256                 },
 257         },
 258 };
 259
 260 static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 261         .offset = 0x22000,
 262         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 263         .width = 4,
 264         .clkr.hw.init = &(struct clk_init_data){
 265                 .name = "nss_crypto_pll",
 266                 .parent_hws = (const struct clk_hw *[]){
 267                                 &nss_crypto_pll_main.clkr.hw },
 268                 .num_parents = 1,
 269                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 270                 .flags = CLK_SET_RATE_PARENT,
 271         },
 272 };
 273
 274 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 275         F(19200000, P_XO, 1, 0, 0),
 276         F(50000000, P_GPLL0, 16, 0, 0),
 277         F(100000000, P_GPLL0, 8, 0, 0),
 278         { }
 279 };
 280
 281 static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
 282         { .fw_name = "xo", .name = "xo" },
 283         { .hw = &gpll0.clkr.hw},
 284         { .hw = &gpll0_out_main_div2.hw},
 285 };
 286
 287 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
 288         { P_XO, 0 },
 289         { P_GPLL0, 1 },
 290         { P_GPLL0_DIV2, 4 },
 291 };
 292
 293 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 294         .cmd_rcgr = 0x27000,
 295         .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 296         .hid_width = 5,
 297         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 298         .clkr.hw.init = &(struct clk_init_data){
 299                 .name = "pcnoc_bfdcd_clk_src",
 300                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 301                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 302                 .ops = &clk_rcg2_ops,
 303                 .flags = CLK_IS_CRITICAL,
 304         },
 305 };
 306
 307 static struct clk_fixed_factor pcnoc_clk_src = {
 308         .mult = 1,
 309         .div = 1,
 310         .hw.init = &(struct clk_init_data){
 311                 .name = "pcnoc_clk_src",
 312                 .parent_hws = (const struct clk_hw *[]){
 313                                 &pcnoc_bfdcd_clk_src.clkr.hw },
 314                 .num_parents = 1,
 315                 .ops = &clk_fixed_factor_ops,
 316                 .flags = CLK_SET_RATE_PARENT,
 317         },
 318 };
 319
 320 static struct clk_branch gcc_sleep_clk_src = {
 321         .halt_reg = 0x30000,
 322         .clkr = {
 323                 .enable_reg = 0x30000,
 324                 .enable_mask = BIT(1),
 325                 .hw.init = &(struct clk_init_data){
 326                         .name = "gcc_sleep_clk_src",
 327                         .parent_data = &(const struct clk_parent_data){
 328                                 .fw_name = "sleep_clk",
 329                                 .name = "sleep_clk",
 330                         },
 331                         .num_parents = 1,
 332                         .ops = &clk_branch2_ops,
 333                         .flags = CLK_IS_CRITICAL,
 334                 },
 335         },
 336 };
 337
 338 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
 339         F(19200000, P_XO, 1, 0, 0),
 340         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 341         F(50000000, P_GPLL0, 16, 0, 0),
 342         { }
 343 };
 344
 345 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 346         .cmd_rcgr = 0x0200c,
 347         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 348         .hid_width = 5,
 349         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 350         .clkr.hw.init = &(struct clk_init_data){
 351                 .name = "blsp1_qup1_i2c_apps_clk_src",
 352                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 353                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 354                 .ops = &clk_rcg2_ops,
 355         },
 356 };
 357
 358 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
 359         F(960000, P_XO, 10, 1, 2),
 360         F(4800000, P_XO, 4, 0, 0),
 361         F(9600000, P_XO, 2, 0, 0),
 362         F(12500000, P_GPLL0_DIV2, 16, 1, 2),
 363         F(16000000, P_GPLL0, 10, 1, 5),
 364         F(19200000, P_XO, 1, 0, 0),
 365         F(25000000, P_GPLL0, 16, 1, 2),
 366         F(50000000, P_GPLL0, 16, 0, 0),
 367         { }
 368 };
 369
 370 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 371         .cmd_rcgr = 0x02024,
 372         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 373         .mnd_width = 8,
 374         .hid_width = 5,
 375         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 376         .clkr.hw.init = &(struct clk_init_data){
 377                 .name = "blsp1_qup1_spi_apps_clk_src",
 378                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 379                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 380                 .ops = &clk_rcg2_ops,
 381         },
 382 };
 383
 384 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 385         .cmd_rcgr = 0x03000,
 386         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 387         .hid_width = 5,
 388         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 389         .clkr.hw.init = &(struct clk_init_data){
 390                 .name = "blsp1_qup2_i2c_apps_clk_src",
 391                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 392                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 393                 .ops = &clk_rcg2_ops,
 394         },
 395 };
 396
 397 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 398         .cmd_rcgr = 0x03014,
 399         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 400         .mnd_width = 8,
 401         .hid_width = 5,
 402         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 403         .clkr.hw.init = &(struct clk_init_data){
 404                 .name = "blsp1_qup2_spi_apps_clk_src",
 405                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 406                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 407                 .ops = &clk_rcg2_ops,
 408         },
 409 };
 410
 411 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 412         .cmd_rcgr = 0x04000,
 413         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 414         .hid_width = 5,
 415         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 416         .clkr.hw.init = &(struct clk_init_data){
 417                 .name = "blsp1_qup3_i2c_apps_clk_src",
 418                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 419                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 420                 .ops = &clk_rcg2_ops,
 421         },
 422 };
 423
 424 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 425         .cmd_rcgr = 0x04014,
 426         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 427         .mnd_width = 8,
 428         .hid_width = 5,
 429         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 430         .clkr.hw.init = &(struct clk_init_data){
 431                 .name = "blsp1_qup3_spi_apps_clk_src",
 432                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 433                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 434                 .ops = &clk_rcg2_ops,
 435         },
 436 };
 437
 438 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 439         .cmd_rcgr = 0x05000,
 440         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 441         .hid_width = 5,
 442         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 443         .clkr.hw.init = &(struct clk_init_data){
 444                 .name = "blsp1_qup4_i2c_apps_clk_src",
 445                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 446                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 447                 .ops = &clk_rcg2_ops,
 448         },
 449 };
 450
 451 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 452         .cmd_rcgr = 0x05014,
 453         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 454         .mnd_width = 8,
 455         .hid_width = 5,
 456         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 457         .clkr.hw.init = &(struct clk_init_data){
 458                 .name = "blsp1_qup4_spi_apps_clk_src",
 459                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 460                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 461                 .ops = &clk_rcg2_ops,
 462         },
 463 };
 464
 465 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 466         .cmd_rcgr = 0x06000,
 467         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 468         .hid_width = 5,
 469         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 470         .clkr.hw.init = &(struct clk_init_data){
 471                 .name = "blsp1_qup5_i2c_apps_clk_src",
 472                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 473                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 474                 .ops = &clk_rcg2_ops,
 475         },
 476 };
 477
 478 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 479         .cmd_rcgr = 0x06014,
 480         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 481         .mnd_width = 8,
 482         .hid_width = 5,
 483         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 484         .clkr.hw.init = &(struct clk_init_data){
 485                 .name = "blsp1_qup5_spi_apps_clk_src",
 486                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 487                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 488                 .ops = &clk_rcg2_ops,
 489         },
 490 };
 491
 492 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 493         .cmd_rcgr = 0x07000,
 494         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 495         .hid_width = 5,
 496         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 497         .clkr.hw.init = &(struct clk_init_data){
 498                 .name = "blsp1_qup6_i2c_apps_clk_src",
 499                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 500                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 501                 .ops = &clk_rcg2_ops,
 502         },
 503 };
 504
 505 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 506         .cmd_rcgr = 0x07014,
 507         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 508         .mnd_width = 8,
 509         .hid_width = 5,
 510         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 511         .clkr.hw.init = &(struct clk_init_data){
 512                 .name = "blsp1_qup6_spi_apps_clk_src",
 513                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 514                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 515                 .ops = &clk_rcg2_ops,
 516         },
 517 };
 518
 519 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
 520         F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 521         F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 522         F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 523         F(16000000, P_GPLL0_DIV2, 5, 1, 5),
 524         F(19200000, P_XO, 1, 0, 0),
 525         F(24000000, P_GPLL0, 1, 3, 100),
 526         F(25000000, P_GPLL0, 16, 1, 2),
 527         F(32000000, P_GPLL0, 1, 1, 25),
 528         F(40000000, P_GPLL0, 1, 1, 20),
 529         F(46400000, P_GPLL0, 1, 29, 500),
 530         F(48000000, P_GPLL0, 1, 3, 50),
 531         F(51200000, P_GPLL0, 1, 8, 125),
 532         F(56000000, P_GPLL0, 1, 7, 100),
 533         F(58982400, P_GPLL0, 1, 1152, 15625),
 534         F(60000000, P_GPLL0, 1, 3, 40),
 535         F(64000000, P_GPLL0, 12.5, 1, 1),
 536         { }
 537 };
 538
 539 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 540         .cmd_rcgr = 0x02044,
 541         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 542         .mnd_width = 16,
 543         .hid_width = 5,
 544         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 545         .clkr.hw.init = &(struct clk_init_data){
 546                 .name = "blsp1_uart1_apps_clk_src",
 547                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 548                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 549                 .ops = &clk_rcg2_ops,
 550         },
 551 };
 552
 553 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 554         .cmd_rcgr = 0x03034,
 555         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 556         .mnd_width = 16,
 557         .hid_width = 5,
 558         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 559         .clkr.hw.init = &(struct clk_init_data){
 560                 .name = "blsp1_uart2_apps_clk_src",
 561                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 562                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 563                 .ops = &clk_rcg2_ops,
 564         },
 565 };
 566
 567 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 568         .cmd_rcgr = 0x04034,
 569         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 570         .mnd_width = 16,
 571         .hid_width = 5,
 572         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 573         .clkr.hw.init = &(struct clk_init_data){
 574                 .name = "blsp1_uart3_apps_clk_src",
 575                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 576                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 577                 .ops = &clk_rcg2_ops,
 578         },
 579 };
 580
 581 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 582         .cmd_rcgr = 0x05034,
 583         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 584         .mnd_width = 16,
 585         .hid_width = 5,
 586         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 587         .clkr.hw.init = &(struct clk_init_data){
 588                 .name = "blsp1_uart4_apps_clk_src",
 589                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 590                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 591                 .ops = &clk_rcg2_ops,
 592         },
 593 };
 594
 595 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 596         .cmd_rcgr = 0x06034,
 597         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 598         .mnd_width = 16,
 599         .hid_width = 5,
 600         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 601         .clkr.hw.init = &(struct clk_init_data){
 602                 .name = "blsp1_uart5_apps_clk_src",
 603                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 604                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 605                 .ops = &clk_rcg2_ops,
 606         },
 607 };
 608
 609 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 610         .cmd_rcgr = 0x07034,
 611         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 612         .mnd_width = 16,
 613         .hid_width = 5,
 614         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 615         .clkr.hw.init = &(struct clk_init_data){
 616                 .name = "blsp1_uart6_apps_clk_src",
 617                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 618                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 619                 .ops = &clk_rcg2_ops,
 620         },
 621 };
 622
 623 static const struct clk_parent_data gcc_xo_gpll0[] = {
 624         { .fw_name = "xo" },
 625         { .hw = &gpll0.clkr.hw },
 626 };
 627
 628 static const struct parent_map gcc_xo_gpll0_map[] = {
 629         { P_XO, 0 },
 630         { P_GPLL0, 1 },
 631 };
 632
 633 static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
 634         F(19200000, P_XO, 1, 0, 0),
 635         F(200000000, P_GPLL0, 4, 0, 0),
 636         { }
 637 };
 638
 639 static struct clk_rcg2 pcie0_axi_clk_src = {
 640         .cmd_rcgr = 0x75054,
 641         .freq_tbl = ftbl_pcie_axi_clk_src,
 642         .hid_width = 5,
 643         .parent_map = gcc_xo_gpll0_map,
 644         .clkr.hw.init = &(struct clk_init_data){
 645                 .name = "pcie0_axi_clk_src",
 646                 .parent_data = gcc_xo_gpll0,
 647                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 648                 .ops = &clk_rcg2_ops,
 649         },
 650 };
 651
 652 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
 653         F(19200000, P_XO, 1, 0, 0),
 654 };
 655
 656 static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = {
 657         { .fw_name = "xo", .name = "xo" },
 658         { .hw = &gpll0.clkr.hw },
 659         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 660 };
 661
 662 static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
 663         { P_XO, 0 },
 664         { P_GPLL0, 2 },
 665         { P_SLEEP_CLK, 6 },
 666 };
 667
 668 static struct clk_rcg2 pcie0_aux_clk_src = {
 669         .cmd_rcgr = 0x75024,
 670         .freq_tbl = ftbl_pcie_aux_clk_src,
 671         .mnd_width = 16,
 672         .hid_width = 5,
 673         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 674         .clkr.hw.init = &(struct clk_init_data){
 675                 .name = "pcie0_aux_clk_src",
 676                 .parent_data = gcc_xo_gpll0_sleep_clk,
 677                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
 678                 .ops = &clk_rcg2_ops,
 679         },
 680 };
 681
 682 static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
 683         { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
 684         { .fw_name = "xo", .name = "xo" },
 685 };
 686
 687 static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
 688         { P_PCIE20_PHY0_PIPE, 0 },
 689         { P_XO, 2 },
 690 };
 691
 692 static struct clk_regmap_mux pcie0_pipe_clk_src = {
 693         .reg = 0x7501c,
 694         .shift = 8,
 695         .width = 2,
 696         .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
 697         .clkr = {
 698                 .hw.init = &(struct clk_init_data){
 699                         .name = "pcie0_pipe_clk_src",
 700                         .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
 701                         .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
 702                         .ops = &clk_regmap_mux_closest_ops,
 703                         .flags = CLK_SET_RATE_PARENT,
 704                 },
 705         },
 706 };
 707
 708 static struct clk_rcg2 pcie1_axi_clk_src = {
 709         .cmd_rcgr = 0x76054,
 710         .freq_tbl = ftbl_pcie_axi_clk_src,
 711         .hid_width = 5,
 712         .parent_map = gcc_xo_gpll0_map,
 713         .clkr.hw.init = &(struct clk_init_data){
 714                 .name = "pcie1_axi_clk_src",
 715                 .parent_data = gcc_xo_gpll0,
 716                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 717                 .ops = &clk_rcg2_ops,
 718         },
 719 };
 720
 721 static struct clk_rcg2 pcie1_aux_clk_src = {
 722         .cmd_rcgr = 0x76024,
 723         .freq_tbl = ftbl_pcie_aux_clk_src,
 724         .mnd_width = 16,
 725         .hid_width = 5,
 726         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 727         .clkr.hw.init = &(struct clk_init_data){
 728                 .name = "pcie1_aux_clk_src",
 729                 .parent_data = gcc_xo_gpll0_sleep_clk,
 730                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
 731                 .ops = &clk_rcg2_ops,
 732         },
 733 };
 734
 735 static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
 736         { .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
 737         { .fw_name = "xo", .name = "xo" },
 738 };
 739
 740 static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
 741         { P_PCIE20_PHY1_PIPE, 0 },
 742         { P_XO, 2 },
 743 };
 744
 745 static struct clk_regmap_mux pcie1_pipe_clk_src = {
 746         .reg = 0x7601c,
 747         .shift = 8,
 748         .width = 2,
 749         .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map,
 750         .clkr = {
 751                 .hw.init = &(struct clk_init_data){
 752                         .name = "pcie1_pipe_clk_src",
 753                         .parent_data = gcc_pcie20_phy1_pipe_clk_xo,
 754                         .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
 755                         .ops = &clk_regmap_mux_closest_ops,
 756                         .flags = CLK_SET_RATE_PARENT,
 757                 },
 758         },
 759 };
 760
 761 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
 762         F(144000, P_XO, 16, 3, 25),
 763         F(400000, P_XO, 12, 1, 4),
 764         F(24000000, P_GPLL2, 12, 1, 4),
 765         F(48000000, P_GPLL2, 12, 1, 2),
 766         F(96000000, P_GPLL2, 12, 0, 0),
 767         F(177777778, P_GPLL0, 4.5, 0, 0),
 768         F(192000000, P_GPLL2, 6, 0, 0),
 769         F(384000000, P_GPLL2, 3, 0, 0),
 770         { }
 771 };
 772
 773 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
 774         { .fw_name = "xo", .name = "xo" },
 775         { .hw = &gpll0.clkr.hw },
 776         { .hw = &gpll2.clkr.hw },
 777         { .hw = &gpll0_out_main_div2.hw },
 778 };
 779
 780 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
 781         { P_XO, 0 },
 782         { P_GPLL0, 1 },
 783         { P_GPLL2, 2 },
 784         { P_GPLL0_DIV2, 4 },
 785 };
 786
 787 static struct clk_rcg2 sdcc1_apps_clk_src = {
 788         .cmd_rcgr = 0x42004,
 789         .freq_tbl = ftbl_sdcc_apps_clk_src,
 790         .mnd_width = 8,
 791         .hid_width = 5,
 792         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
 793         .clkr.hw.init = &(struct clk_init_data){
 794                 .name = "sdcc1_apps_clk_src",
 795                 .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
 796                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
 797                 .ops = &clk_rcg2_floor_ops,
 798         },
 799 };
 800
 801 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
 802         F(19200000, P_XO, 1, 0, 0),
 803         F(160000000, P_GPLL0, 5, 0, 0),
 804         F(308570000, P_GPLL6, 3.5, 0, 0),
 805 };
 806
 807 static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
 808         { .fw_name = "xo", .name = "xo" },
 809         { .hw = &gpll0.clkr.hw },
 810         { .hw = &gpll6.clkr.hw },
 811         { .hw = &gpll0_out_main_div2.hw },
 812 };
 813
 814 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
 815         { P_XO, 0 },
 816         { P_GPLL0, 1 },
 817         { P_GPLL6, 2 },
 818         { P_GPLL0_DIV2, 4 },
 819 };
 820
 821 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 822         .cmd_rcgr = 0x5d000,
 823         .freq_tbl = ftbl_sdcc_ice_core_clk_src,
 824         .mnd_width = 8,
 825         .hid_width = 5,
 826         .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
 827         .clkr.hw.init = &(struct clk_init_data){
 828                 .name = "sdcc1_ice_core_clk_src",
 829                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
 830                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_div2),
 831                 .ops = &clk_rcg2_ops,
 832         },
 833 };
 834
 835 static struct clk_rcg2 sdcc2_apps_clk_src = {
 836         .cmd_rcgr = 0x43004,
 837         .freq_tbl = ftbl_sdcc_apps_clk_src,
 838         .mnd_width = 8,
 839         .hid_width = 5,
 840         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
 841         .clkr.hw.init = &(struct clk_init_data){
 842                 .name = "sdcc2_apps_clk_src",
 843                 .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
 844                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
 845                 .ops = &clk_rcg2_floor_ops,
 846         },
 847 };
 848
 849 static const struct freq_tbl ftbl_usb_master_clk_src[] = {
 850         F(80000000, P_GPLL0_DIV2, 5, 0, 0),
 851         F(100000000, P_GPLL0, 8, 0, 0),
 852         F(133330000, P_GPLL0, 6, 0, 0),
 853         { }
 854 };
 855
 856 static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
 857         { .fw_name = "xo", .name = "xo" },
 858         { .hw = &gpll0_out_main_div2.hw },
 859         { .hw = &gpll0.clkr.hw },
 860 };
 861
 862 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 863         { P_XO, 0 },
 864         { P_GPLL0_DIV2, 2 },
 865         { P_GPLL0, 1 },
 866 };
 867
 868 static struct clk_rcg2 usb0_master_clk_src = {
 869         .cmd_rcgr = 0x3e00c,
 870         .freq_tbl = ftbl_usb_master_clk_src,
 871         .mnd_width = 8,
 872         .hid_width = 5,
 873         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
 874         .clkr.hw.init = &(struct clk_init_data){
 875                 .name = "usb0_master_clk_src",
 876                 .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
 877                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
 878                 .ops = &clk_rcg2_ops,
 879         },
 880 };
 881
 882 static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
 883         F(19200000, P_XO, 1, 0, 0),
 884         { }
 885 };
 886
 887 static struct clk_rcg2 usb0_aux_clk_src = {
 888         .cmd_rcgr = 0x3e05c,
 889         .freq_tbl = ftbl_usb_aux_clk_src,
 890         .mnd_width = 16,
 891         .hid_width = 5,
 892         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 893         .clkr.hw.init = &(struct clk_init_data){
 894                 .name = "usb0_aux_clk_src",
 895                 .parent_data = gcc_xo_gpll0_sleep_clk,
 896                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
 897                 .ops = &clk_rcg2_ops,
 898         },
 899 };
 900
 901 static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
 902         F(19200000, P_XO, 1, 0, 0),
 903         F(20000000, P_GPLL6, 6, 1, 9),
 904         F(60000000, P_GPLL6, 6, 1, 3),
 905         { }
 906 };
 907
 908 static const struct clk_parent_data gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
 909         { .fw_name = "xo", .name = "xo" },
 910         { .hw = &gpll6.clkr.hw },
 911         { .hw = &gpll0.clkr.hw },
 912         { .hw = &gpll0_out_main_div2.hw },
 913 };
 914
 915 static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
 916         { P_XO, 0 },
 917         { P_GPLL6, 1 },
 918         { P_GPLL0, 3 },
 919         { P_GPLL0_DIV2, 4 },
 920 };
 921
 922 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
 923         .cmd_rcgr = 0x3e020,
 924         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
 925         .mnd_width = 8,
 926         .hid_width = 5,
 927         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
 928         .clkr.hw.init = &(struct clk_init_data){
 929                 .name = "usb0_mock_utmi_clk_src",
 930                 .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
 931                 .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
 932                 .ops = &clk_rcg2_ops,
 933         },
 934 };
 935
 936 static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
 937         { .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
 938         { .fw_name = "xo", .name = "xo" },
 939 };
 940
 941 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
 942         { P_USB3PHY_0_PIPE, 0 },
 943         { P_XO, 2 },
 944 };
 945
 946 static struct clk_regmap_mux usb0_pipe_clk_src = {
 947         .reg = 0x3e048,
 948         .shift = 8,
 949         .width = 2,
 950         .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
 951         .clkr = {
 952                 .hw.init = &(struct clk_init_data){
 953                         .name = "usb0_pipe_clk_src",
 954                         .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
 955                         .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
 956                         .ops = &clk_regmap_mux_closest_ops,
 957                         .flags = CLK_SET_RATE_PARENT,
 958                 },
 959         },
 960 };
 961
 962 static struct clk_rcg2 usb1_master_clk_src = {
 963         .cmd_rcgr = 0x3f00c,
 964         .freq_tbl = ftbl_usb_master_clk_src,
 965         .mnd_width = 8,
 966         .hid_width = 5,
 967         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
 968         .clkr.hw.init = &(struct clk_init_data){
 969                 .name = "usb1_master_clk_src",
 970                 .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
 971                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
 972                 .ops = &clk_rcg2_ops,
 973         },
 974 };
 975
 976 static struct clk_rcg2 usb1_aux_clk_src = {
 977         .cmd_rcgr = 0x3f05c,
 978         .freq_tbl = ftbl_usb_aux_clk_src,
 979         .mnd_width = 16,
 980         .hid_width = 5,
 981         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 982         .clkr.hw.init = &(struct clk_init_data){
 983                 .name = "usb1_aux_clk_src",
 984                 .parent_data = gcc_xo_gpll0_sleep_clk,
 985                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
 986                 .ops = &clk_rcg2_ops,
 987         },
 988 };
 989
 990 static struct clk_rcg2 usb1_mock_utmi_clk_src = {
 991         .cmd_rcgr = 0x3f020,
 992         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
 993         .mnd_width = 8,
 994         .hid_width = 5,
 995         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
 996         .clkr.hw.init = &(struct clk_init_data){
 997                 .name = "usb1_mock_utmi_clk_src",
 998                 .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
 999                 .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
1000                 .ops = &clk_rcg2_ops,
1001         },
1002 };
1003
1004 static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
1005         { .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
1006         { .fw_name = "xo", .name = "xo" },
1007 };
1008
1009 static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
1010         { P_USB3PHY_1_PIPE, 0 },
1011         { P_XO, 2 },
1012 };
1013
1014 static struct clk_regmap_mux usb1_pipe_clk_src = {
1015         .reg = 0x3f048,
1016         .shift = 8,
1017         .width = 2,
1018         .parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map,
1019         .clkr = {
1020                 .hw.init = &(struct clk_init_data){
1021                         .name = "usb1_pipe_clk_src",
1022                         .parent_data = gcc_usb3phy_1_cc_pipe_clk_xo,
1023                         .num_parents = ARRAY_SIZE(gcc_usb3phy_1_cc_pipe_clk_xo),
1024                         .ops = &clk_regmap_mux_closest_ops,
1025                         .flags = CLK_SET_RATE_PARENT,
1026                 },
1027         },
1028 };
1029
1030 static struct clk_branch gcc_xo_clk_src = {
1031         .halt_reg = 0x30018,
1032         .clkr = {
1033                 .enable_reg = 0x30018,
1034                 .enable_mask = BIT(1),
1035                 .hw.init = &(struct clk_init_data){
1036                         .name = "gcc_xo_clk_src",
1037                         .parent_data = &(const struct clk_parent_data){
1038                                 .fw_name = "xo",
1039                                 .name = "xo",
1040                         },
1041                         .num_parents = 1,
1042                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1043                         .ops = &clk_branch2_ops,
1044                 },
1045         },
1046 };
1047
1048 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
1049         .mult = 1,
1050         .div = 4,
1051         .hw.init = &(struct clk_init_data){
1052                 .name = "gcc_xo_div4_clk_src",
1053                 .parent_hws = (const struct clk_hw *[]){
1054                                 &gcc_xo_clk_src.clkr.hw },
1055                 .num_parents = 1,
1056                 .ops = &clk_fixed_factor_ops,
1057                 .flags = CLK_SET_RATE_PARENT,
1058         },
1059 };
1060
1061 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1062         F(19200000, P_XO, 1, 0, 0),
1063         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1064         F(100000000, P_GPLL0, 8, 0, 0),
1065         F(133333333, P_GPLL0, 6, 0, 0),
1066         F(160000000, P_GPLL0, 5, 0, 0),
1067         F(200000000, P_GPLL0, 4, 0, 0),
1068         F(266666667, P_GPLL0, 3, 0, 0),
1069         { }
1070 };
1071
1072 static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
1073         { .fw_name = "xo", .name = "xo" },
1074         { .hw = &gpll0.clkr.hw },
1075         { .hw = &gpll6.clkr.hw },
1076         { .hw = &gpll0_out_main_div2.hw },
1077 };
1078
1079 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
1080         { P_XO, 0 },
1081         { P_GPLL0, 1 },
1082         { P_GPLL6, 2 },
1083         { P_GPLL0_DIV2, 3 },
1084 };
1085
1086 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1087         .cmd_rcgr = 0x26004,
1088         .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1089         .hid_width = 5,
1090         .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1091         .clkr.hw.init = &(struct clk_init_data){
1092                 .name = "system_noc_bfdcd_clk_src",
1093                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1094                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_out_main_div2),
1095                 .ops = &clk_rcg2_ops,
1096                 .flags = CLK_IS_CRITICAL,
1097         },
1098 };
1099
1100 static struct clk_fixed_factor system_noc_clk_src = {
1101         .mult = 1,
1102         .div = 1,
1103         .hw.init = &(struct clk_init_data){
1104                 .name = "system_noc_clk_src",
1105                 .parent_hws = (const struct clk_hw *[]){
1106                                 &system_noc_bfdcd_clk_src.clkr.hw },
1107                 .num_parents = 1,
1108                 .ops = &clk_fixed_factor_ops,
1109                 .flags = CLK_SET_RATE_PARENT,
1110         },
1111 };
1112
1113 static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
1114         F(19200000, P_XO, 1, 0, 0),
1115         F(200000000, P_GPLL0, 4, 0, 0),
1116         { }
1117 };
1118
1119 static struct clk_rcg2 nss_ce_clk_src = {
1120         .cmd_rcgr = 0x68098,
1121         .freq_tbl = ftbl_nss_ce_clk_src,
1122         .hid_width = 5,
1123         .parent_map = gcc_xo_gpll0_map,
1124         .clkr.hw.init = &(struct clk_init_data){
1125                 .name = "nss_ce_clk_src",
1126                 .parent_data = gcc_xo_gpll0,
1127                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1128                 .ops = &clk_rcg2_ops,
1129         },
1130 };
1131
1132 static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
1133         F(19200000, P_XO, 1, 0, 0),
1134         F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1135         { }
1136 };
1137
1138 static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
1139         { .fw_name = "xo", .name = "xo" },
1140         { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
1141         { .hw = &gpll0.clkr.hw },
1142         { .hw = &gpll2.clkr.hw },
1143 };
1144
1145 static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
1146         { P_XO, 0 },
1147         { P_BIAS_PLL_NSS_NOC, 1 },
1148         { P_GPLL0, 2 },
1149         { P_GPLL2, 3 },
1150 };
1151
1152 static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
1153         .cmd_rcgr = 0x68088,
1154         .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
1155         .hid_width = 5,
1156         .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
1157         .clkr.hw.init = &(struct clk_init_data){
1158                 .name = "nss_noc_bfdcd_clk_src",
1159                 .parent_data = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
1160                 .num_parents = ARRAY_SIZE(gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2),
1161                 .ops = &clk_rcg2_ops,
1162         },
1163 };
1164
1165 static struct clk_fixed_factor nss_noc_clk_src = {
1166         .mult = 1,
1167         .div = 1,
1168         .hw.init = &(struct clk_init_data){
1169                 .name = "nss_noc_clk_src",
1170                 .parent_hws = (const struct clk_hw *[]){
1171                                 &nss_noc_bfdcd_clk_src.clkr.hw },
1172                 .num_parents = 1,
1173                 .ops = &clk_fixed_factor_ops,
1174                 .flags = CLK_SET_RATE_PARENT,
1175         },
1176 };
1177
1178 static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
1179         F(19200000, P_XO, 1, 0, 0),
1180         F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1181         { }
1182 };
1183
1184 static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
1185         { .fw_name = "xo", .name = "xo" },
1186         { .hw = &nss_crypto_pll.clkr.hw },
1187         { .hw = &gpll0.clkr.hw },
1188 };
1189
1190 static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
1191         { P_XO, 0 },
1192         { P_NSS_CRYPTO_PLL, 1 },
1193         { P_GPLL0, 2 },
1194 };
1195
1196 static struct clk_rcg2 nss_crypto_clk_src = {
1197         .cmd_rcgr = 0x68144,
1198         .freq_tbl = ftbl_nss_crypto_clk_src,
1199         .mnd_width = 16,
1200         .hid_width = 5,
1201         .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
1202         .clkr.hw.init = &(struct clk_init_data){
1203                 .name = "nss_crypto_clk_src",
1204                 .parent_data = gcc_xo_nss_crypto_pll_gpll0,
1205                 .num_parents = ARRAY_SIZE(gcc_xo_nss_crypto_pll_gpll0),
1206                 .ops = &clk_rcg2_ops,
1207         },
1208 };
1209
1210 static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1211         F(19200000, P_XO, 1, 0, 0),
1212         F(187200000, P_UBI32_PLL, 8, 0, 0),
1213         F(748800000, P_UBI32_PLL, 2, 0, 0),
1214         F(1497600000, P_UBI32_PLL, 1, 0, 0),
1215         F(1689600000, P_UBI32_PLL, 1, 0, 0),
1216         { }
1217 };
1218
1219 static const struct clk_parent_data gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
1220         { .fw_name = "xo", .name = "xo" },
1221         { .hw = &ubi32_pll.clkr.hw },
1222         { .hw = &gpll0.clkr.hw },
1223         { .hw = &gpll2.clkr.hw },
1224         { .hw = &gpll4.clkr.hw },
1225         { .hw = &gpll6.clkr.hw },
1226 };
1227
1228 static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
1229         { P_XO, 0 },
1230         { P_UBI32_PLL, 1 },
1231         { P_GPLL0, 2 },
1232         { P_GPLL2, 3 },
1233         { P_GPLL4, 4 },
1234         { P_GPLL6, 5 },
1235 };
1236
1237 static struct clk_rcg2 nss_ubi0_clk_src = {
1238         .cmd_rcgr = 0x68104,
1239         .freq_tbl = ftbl_nss_ubi_clk_src,
1240         .hid_width = 5,
1241         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1242         .clkr.hw.init = &(struct clk_init_data){
1243                 .name = "nss_ubi0_clk_src",
1244                 .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1245                 .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
1246                 .ops = &clk_rcg2_ops,
1247                 .flags = CLK_SET_RATE_PARENT,
1248         },
1249 };
1250
1251 static struct clk_regmap_div nss_ubi0_div_clk_src = {
1252         .reg = 0x68118,
1253         .shift = 0,
1254         .width = 4,
1255         .clkr = {
1256                 .hw.init = &(struct clk_init_data){
1257                         .name = "nss_ubi0_div_clk_src",
1258                         .parent_hws = (const struct clk_hw *[]){
1259                                 &nss_ubi0_clk_src.clkr.hw },
1260                         .num_parents = 1,
1261                         .ops = &clk_regmap_div_ro_ops,
1262                         .flags = CLK_SET_RATE_PARENT,
1263                 },
1264         },
1265 };
1266
1267 static struct clk_rcg2 nss_ubi1_clk_src = {
1268         .cmd_rcgr = 0x68124,
1269         .freq_tbl = ftbl_nss_ubi_clk_src,
1270         .hid_width = 5,
1271         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1272         .clkr.hw.init = &(struct clk_init_data){
1273                 .name = "nss_ubi1_clk_src",
1274                 .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1275                 .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
1276                 .ops = &clk_rcg2_ops,
1277                 .flags = CLK_SET_RATE_PARENT,
1278         },
1279 };
1280
1281 static struct clk_regmap_div nss_ubi1_div_clk_src = {
1282         .reg = 0x68138,
1283         .shift = 0,
1284         .width = 4,
1285         .clkr = {
1286                 .hw.init = &(struct clk_init_data){
1287                         .name = "nss_ubi1_div_clk_src",
1288                         .parent_hws = (const struct clk_hw *[]){
1289                                 &nss_ubi1_clk_src.clkr.hw },
1290                         .num_parents = 1,
1291                         .ops = &clk_regmap_div_ro_ops,
1292                         .flags = CLK_SET_RATE_PARENT,
1293                 },
1294         },
1295 };
1296
1297 static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = {
1298         F(19200000, P_XO, 1, 0, 0),
1299         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1300         { }
1301 };
1302
1303 static const struct clk_parent_data gcc_xo_gpll0_out_main_div2[] = {
1304         { .fw_name = "xo", .name = "xo" },
1305         { .hw = &gpll0_out_main_div2.hw },
1306 };
1307
1308 static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
1309         { P_XO, 0 },
1310         { P_GPLL0_DIV2, 1 },
1311 };
1312
1313 static struct clk_rcg2 ubi_mpt_clk_src = {
1314         .cmd_rcgr = 0x68090,
1315         .freq_tbl = ftbl_ubi_mpt_clk_src,
1316         .hid_width = 5,
1317         .parent_map = gcc_xo_gpll0_out_main_div2_map,
1318         .clkr.hw.init = &(struct clk_init_data){
1319                 .name = "ubi_mpt_clk_src",
1320                 .parent_data = gcc_xo_gpll0_out_main_div2,
1321                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2),
1322                 .ops = &clk_rcg2_ops,
1323         },
1324 };
1325
1326 static const struct freq_tbl ftbl_nss_imem_clk_src[] = {
1327         F(19200000, P_XO, 1, 0, 0),
1328         F(400000000, P_GPLL0, 2, 0, 0),
1329         { }
1330 };
1331
1332 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
1333         { .fw_name = "xo", .name = "xo" },
1334         { .hw = &gpll0.clkr.hw },
1335         { .hw = &gpll4.clkr.hw },
1336 };
1337
1338 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
1339         { P_XO, 0 },
1340         { P_GPLL0, 1 },
1341         { P_GPLL4, 2 },
1342 };
1343
1344 static struct clk_rcg2 nss_imem_clk_src = {
1345         .cmd_rcgr = 0x68158,
1346         .freq_tbl = ftbl_nss_imem_clk_src,
1347         .hid_width = 5,
1348         .parent_map = gcc_xo_gpll0_gpll4_map,
1349         .clkr.hw.init = &(struct clk_init_data){
1350                 .name = "nss_imem_clk_src",
1351                 .parent_data = gcc_xo_gpll0_gpll4,
1352                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1353                 .ops = &clk_rcg2_ops,
1354         },
1355 };
1356
1357 static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
1358         F(19200000, P_XO, 1, 0, 0),
1359         F(300000000, P_BIAS_PLL, 1, 0, 0),
1360         { }
1361 };
1362
1363 static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
1364         { .fw_name = "xo", .name = "xo" },
1365         { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1366         { .hw = &gpll0.clkr.hw },
1367         { .hw = &gpll4.clkr.hw },
1368         { .hw = &nss_crypto_pll.clkr.hw },
1369         { .hw = &ubi32_pll.clkr.hw },
1370 };
1371
1372 static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
1373         { P_XO, 0 },
1374         { P_BIAS_PLL, 1 },
1375         { P_GPLL0, 2 },
1376         { P_GPLL4, 3 },
1377         { P_NSS_CRYPTO_PLL, 4 },
1378         { P_UBI32_PLL, 5 },
1379 };
1380
1381 static struct clk_rcg2 nss_ppe_clk_src = {
1382         .cmd_rcgr = 0x68080,
1383         .freq_tbl = ftbl_nss_ppe_clk_src,
1384         .hid_width = 5,
1385         .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
1386         .clkr.hw.init = &(struct clk_init_data){
1387                 .name = "nss_ppe_clk_src",
1388                 .parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
1389                 .num_parents = ARRAY_SIZE(gcc_xo_bias_gpll0_gpll4_nss_ubi32),
1390                 .ops = &clk_rcg2_ops,
1391         },
1392 };
1393
1394 static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1395         .mult = 1,
1396         .div = 4,
1397         .hw.init = &(struct clk_init_data){
1398                 .name = "nss_ppe_cdiv_clk_src",
1399                 .parent_hws = (const struct clk_hw *[]){
1400                                 &nss_ppe_clk_src.clkr.hw },
1401                 .num_parents = 1,
1402                 .ops = &clk_fixed_factor_ops,
1403                 .flags = CLK_SET_RATE_PARENT,
1404         },
1405 };
1406
1407 static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
1408         F(19200000, P_XO, 1, 0, 0),
1409         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1410         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1411         { }
1412 };
1413
1414 static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
1415         { .fw_name = "xo", .name = "xo" },
1416         { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1417         { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1418         { .hw = &ubi32_pll.clkr.hw },
1419         { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1420 };
1421
1422 static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
1423         { P_XO, 0 },
1424         { P_UNIPHY0_RX, 1 },
1425         { P_UNIPHY0_TX, 2 },
1426         { P_UBI32_PLL, 5 },
1427         { P_BIAS_PLL, 6 },
1428 };
1429
1430 static struct clk_rcg2 nss_port1_rx_clk_src = {
1431         .cmd_rcgr = 0x68020,
1432         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1433         .hid_width = 5,
1434         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1435         .clkr.hw.init = &(struct clk_init_data){
1436                 .name = "nss_port1_rx_clk_src",
1437                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1438                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1439                 .ops = &clk_rcg2_ops,
1440         },
1441 };
1442
1443 static struct clk_regmap_div nss_port1_rx_div_clk_src = {
1444         .reg = 0x68400,
1445         .shift = 0,
1446         .width = 4,
1447         .clkr = {
1448                 .hw.init = &(struct clk_init_data){
1449                         .name = "nss_port1_rx_div_clk_src",
1450                         .parent_hws = (const struct clk_hw *[]){
1451                                 &nss_port1_rx_clk_src.clkr.hw },
1452                         .num_parents = 1,
1453                         .ops = &clk_regmap_div_ops,
1454                         .flags = CLK_SET_RATE_PARENT,
1455                 },
1456         },
1457 };
1458
1459 static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
1460         F(19200000, P_XO, 1, 0, 0),
1461         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1462         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1463         { }
1464 };
1465
1466 static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
1467         { .fw_name = "xo", .name = "xo" },
1468         { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1469         { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1470         { .hw = &ubi32_pll.clkr.hw },
1471         { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1472 };
1473
1474 static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
1475         { P_XO, 0 },
1476         { P_UNIPHY0_TX, 1 },
1477         { P_UNIPHY0_RX, 2 },
1478         { P_UBI32_PLL, 5 },
1479         { P_BIAS_PLL, 6 },
1480 };
1481
1482 static struct clk_rcg2 nss_port1_tx_clk_src = {
1483         .cmd_rcgr = 0x68028,
1484         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1485         .hid_width = 5,
1486         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1487         .clkr.hw.init = &(struct clk_init_data){
1488                 .name = "nss_port1_tx_clk_src",
1489                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1490                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1491                 .ops = &clk_rcg2_ops,
1492         },
1493 };
1494
1495 static struct clk_regmap_div nss_port1_tx_div_clk_src = {
1496         .reg = 0x68404,
1497         .shift = 0,
1498         .width = 4,
1499         .clkr = {
1500                 .hw.init = &(struct clk_init_data){
1501                         .name = "nss_port1_tx_div_clk_src",
1502                         .parent_hws = (const struct clk_hw *[]){
1503                                 &nss_port1_tx_clk_src.clkr.hw },
1504                         .num_parents = 1,
1505                         .ops = &clk_regmap_div_ops,
1506                         .flags = CLK_SET_RATE_PARENT,
1507                 },
1508         },
1509 };
1510
1511 static struct clk_rcg2 nss_port2_rx_clk_src = {
1512         .cmd_rcgr = 0x68030,
1513         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1514         .hid_width = 5,
1515         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1516         .clkr.hw.init = &(struct clk_init_data){
1517                 .name = "nss_port2_rx_clk_src",
1518                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1519                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1520                 .ops = &clk_rcg2_ops,
1521         },
1522 };
1523
1524 static struct clk_regmap_div nss_port2_rx_div_clk_src = {
1525         .reg = 0x68410,
1526         .shift = 0,
1527         .width = 4,
1528         .clkr = {
1529                 .hw.init = &(struct clk_init_data){
1530                         .name = "nss_port2_rx_div_clk_src",
1531                         .parent_hws = (const struct clk_hw *[]){
1532                                 &nss_port2_rx_clk_src.clkr.hw },
1533                         .num_parents = 1,
1534                         .ops = &clk_regmap_div_ops,
1535                         .flags = CLK_SET_RATE_PARENT,
1536                 },
1537         },
1538 };
1539
1540 static struct clk_rcg2 nss_port2_tx_clk_src = {
1541         .cmd_rcgr = 0x68038,
1542         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1543         .hid_width = 5,
1544         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1545         .clkr.hw.init = &(struct clk_init_data){
1546                 .name = "nss_port2_tx_clk_src",
1547                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1548                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1549                 .ops = &clk_rcg2_ops,
1550         },
1551 };
1552
1553 static struct clk_regmap_div nss_port2_tx_div_clk_src = {
1554         .reg = 0x68414,
1555         .shift = 0,
1556         .width = 4,
1557         .clkr = {
1558                 .hw.init = &(struct clk_init_data){
1559                         .name = "nss_port2_tx_div_clk_src",
1560                         .parent_hws = (const struct clk_hw *[]){
1561                                 &nss_port2_tx_clk_src.clkr.hw },
1562                         .num_parents = 1,
1563                         .ops = &clk_regmap_div_ops,
1564                         .flags = CLK_SET_RATE_PARENT,
1565                 },
1566         },
1567 };
1568
1569 static struct clk_rcg2 nss_port3_rx_clk_src = {
1570         .cmd_rcgr = 0x68040,
1571         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1572         .hid_width = 5,
1573         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1574         .clkr.hw.init = &(struct clk_init_data){
1575                 .name = "nss_port3_rx_clk_src",
1576                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1577                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1578                 .ops = &clk_rcg2_ops,
1579         },
1580 };
1581
1582 static struct clk_regmap_div nss_port3_rx_div_clk_src = {
1583         .reg = 0x68420,
1584         .shift = 0,
1585         .width = 4,
1586         .clkr = {
1587                 .hw.init = &(struct clk_init_data){
1588                         .name = "nss_port3_rx_div_clk_src",
1589                         .parent_hws = (const struct clk_hw *[]){
1590                                 &nss_port3_rx_clk_src.clkr.hw },
1591                         .num_parents = 1,
1592                         .ops = &clk_regmap_div_ops,
1593                         .flags = CLK_SET_RATE_PARENT,
1594                 },
1595         },
1596 };
1597
1598 static struct clk_rcg2 nss_port3_tx_clk_src = {
1599         .cmd_rcgr = 0x68048,
1600         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1601         .hid_width = 5,
1602         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1603         .clkr.hw.init = &(struct clk_init_data){
1604                 .name = "nss_port3_tx_clk_src",
1605                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1606                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1607                 .ops = &clk_rcg2_ops,
1608         },
1609 };
1610
1611 static struct clk_regmap_div nss_port3_tx_div_clk_src = {
1612         .reg = 0x68424,
1613         .shift = 0,
1614         .width = 4,
1615         .clkr = {
1616                 .hw.init = &(struct clk_init_data){
1617                         .name = "nss_port3_tx_div_clk_src",
1618                         .parent_hws = (const struct clk_hw *[]){
1619                                 &nss_port3_tx_clk_src.clkr.hw },
1620                         .num_parents = 1,
1621                         .ops = &clk_regmap_div_ops,
1622                         .flags = CLK_SET_RATE_PARENT,
1623                 },
1624         },
1625 };
1626
1627 static struct clk_rcg2 nss_port4_rx_clk_src = {
1628         .cmd_rcgr = 0x68050,
1629         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1630         .hid_width = 5,
1631         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1632         .clkr.hw.init = &(struct clk_init_data){
1633                 .name = "nss_port4_rx_clk_src",
1634                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1635                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1636                 .ops = &clk_rcg2_ops,
1637         },
1638 };
1639
1640 static struct clk_regmap_div nss_port4_rx_div_clk_src = {
1641         .reg = 0x68430,
1642         .shift = 0,
1643         .width = 4,
1644         .clkr = {
1645                 .hw.init = &(struct clk_init_data){
1646                         .name = "nss_port4_rx_div_clk_src",
1647                         .parent_hws = (const struct clk_hw *[]){
1648                                 &nss_port4_rx_clk_src.clkr.hw },
1649                         .num_parents = 1,
1650                         .ops = &clk_regmap_div_ops,
1651                         .flags = CLK_SET_RATE_PARENT,
1652                 },
1653         },
1654 };
1655
1656 static struct clk_rcg2 nss_port4_tx_clk_src = {
1657         .cmd_rcgr = 0x68058,
1658         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1659         .hid_width = 5,
1660         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1661         .clkr.hw.init = &(struct clk_init_data){
1662                 .name = "nss_port4_tx_clk_src",
1663                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1664                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1665                 .ops = &clk_rcg2_ops,
1666         },
1667 };
1668
1669 static struct clk_regmap_div nss_port4_tx_div_clk_src = {
1670         .reg = 0x68434,
1671         .shift = 0,
1672         .width = 4,
1673         .clkr = {
1674                 .hw.init = &(struct clk_init_data){
1675                         .name = "nss_port4_tx_div_clk_src",
1676                         .parent_hws = (const struct clk_hw *[]){
1677                                 &nss_port4_tx_clk_src.clkr.hw },
1678                         .num_parents = 1,
1679                         .ops = &clk_regmap_div_ops,
1680                         .flags = CLK_SET_RATE_PARENT,
1681                 },
1682         },
1683 };
1684
1685 static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
1686         F(19200000, P_XO, 1, 0, 0),
1687         F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1688         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1689         F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1690         F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1691         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1692         F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1693         F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1694         { }
1695 };
1696
1697 static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
1698         { .fw_name = "xo", .name = "xo" },
1699         { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1700         { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1701         { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
1702         { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
1703         { .hw = &ubi32_pll.clkr.hw },
1704         { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1705 };
1706
1707 static const struct parent_map
1708 gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
1709         { P_XO, 0 },
1710         { P_UNIPHY0_RX, 1 },
1711         { P_UNIPHY0_TX, 2 },
1712         { P_UNIPHY1_RX, 3 },
1713         { P_UNIPHY1_TX, 4 },
1714         { P_UBI32_PLL, 5 },
1715         { P_BIAS_PLL, 6 },
1716 };
1717
1718 static struct clk_rcg2 nss_port5_rx_clk_src = {
1719         .cmd_rcgr = 0x68060,
1720         .freq_tbl = ftbl_nss_port5_rx_clk_src,
1721         .hid_width = 5,
1722         .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
1723         .clkr.hw.init = &(struct clk_init_data){
1724                 .name = "nss_port5_rx_clk_src",
1725                 .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
1726                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
1727                 .ops = &clk_rcg2_ops,
1728         },
1729 };
1730
1731 static struct clk_regmap_div nss_port5_rx_div_clk_src = {
1732         .reg = 0x68440,
1733         .shift = 0,
1734         .width = 4,
1735         .clkr = {
1736                 .hw.init = &(struct clk_init_data){
1737                         .name = "nss_port5_rx_div_clk_src",
1738                         .parent_hws = (const struct clk_hw *[]){
1739                                 &nss_port5_rx_clk_src.clkr.hw },
1740                         .num_parents = 1,
1741                         .ops = &clk_regmap_div_ops,
1742                         .flags = CLK_SET_RATE_PARENT,
1743                 },
1744         },
1745 };
1746
1747 static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
1748         F(19200000, P_XO, 1, 0, 0),
1749         F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1750         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1751         F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1752         F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1753         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1754         F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1755         F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1756         { }
1757 };
1758
1759 static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
1760         { .fw_name = "xo", .name = "xo" },
1761         { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1762         { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1763         { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
1764         { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
1765         { .hw = &ubi32_pll.clkr.hw },
1766         { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1767 };
1768
1769 static const struct parent_map
1770 gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
1771         { P_XO, 0 },
1772         { P_UNIPHY0_TX, 1 },
1773         { P_UNIPHY0_RX, 2 },
1774         { P_UNIPHY1_TX, 3 },
1775         { P_UNIPHY1_RX, 4 },
1776         { P_UBI32_PLL, 5 },
1777         { P_BIAS_PLL, 6 },
1778 };
1779
1780 static struct clk_rcg2 nss_port5_tx_clk_src = {
1781         .cmd_rcgr = 0x68068,
1782         .freq_tbl = ftbl_nss_port5_tx_clk_src,
1783         .hid_width = 5,
1784         .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
1785         .clkr.hw.init = &(struct clk_init_data){
1786                 .name = "nss_port5_tx_clk_src",
1787                 .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
1788                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
1789                 .ops = &clk_rcg2_ops,
1790         },
1791 };
1792
1793 static struct clk_regmap_div nss_port5_tx_div_clk_src = {
1794         .reg = 0x68444,
1795         .shift = 0,
1796         .width = 4,
1797         .clkr = {
1798                 .hw.init = &(struct clk_init_data){
1799                         .name = "nss_port5_tx_div_clk_src",
1800                         .parent_hws = (const struct clk_hw *[]){
1801                                 &nss_port5_tx_clk_src.clkr.hw },
1802                         .num_parents = 1,
1803                         .ops = &clk_regmap_div_ops,
1804                         .flags = CLK_SET_RATE_PARENT,
1805                 },
1806         },
1807 };
1808
1809 static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
1810         F(19200000, P_XO, 1, 0, 0),
1811         F(25000000, P_UNIPHY2_RX, 5, 0, 0),
1812         F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1813         F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1814         F(125000000, P_UNIPHY2_RX, 1, 0, 0),
1815         F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1816         F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1817         F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1818         { }
1819 };
1820
1821 static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
1822         { .fw_name = "xo", .name = "xo" },
1823         { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
1824         { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
1825         { .hw = &ubi32_pll.clkr.hw },
1826         { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1827 };
1828
1829 static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
1830         { P_XO, 0 },
1831         { P_UNIPHY2_RX, 1 },
1832         { P_UNIPHY2_TX, 2 },
1833         { P_UBI32_PLL, 5 },
1834         { P_BIAS_PLL, 6 },
1835 };
1836
1837 static struct clk_rcg2 nss_port6_rx_clk_src = {
1838         .cmd_rcgr = 0x68070,
1839         .freq_tbl = ftbl_nss_port6_rx_clk_src,
1840         .hid_width = 5,
1841         .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
1842         .clkr.hw.init = &(struct clk_init_data){
1843                 .name = "nss_port6_rx_clk_src",
1844                 .parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
1845                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
1846                 .ops = &clk_rcg2_ops,
1847         },
1848 };
1849
1850 static struct clk_regmap_div nss_port6_rx_div_clk_src = {
1851         .reg = 0x68450,
1852         .shift = 0,
1853         .width = 4,
1854         .clkr = {
1855                 .hw.init = &(struct clk_init_data){
1856                         .name = "nss_port6_rx_div_clk_src",
1857                         .parent_hws = (const struct clk_hw *[]){
1858                                 &nss_port6_rx_clk_src.clkr.hw },
1859                         .num_parents = 1,
1860                         .ops = &clk_regmap_div_ops,
1861                         .flags = CLK_SET_RATE_PARENT,
1862                 },
1863         },
1864 };
1865
1866 static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
1867         F(19200000, P_XO, 1, 0, 0),
1868         F(25000000, P_UNIPHY2_TX, 5, 0, 0),
1869         F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1870         F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1871         F(125000000, P_UNIPHY2_TX, 1, 0, 0),
1872         F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1873         F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1874         F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1875         { }
1876 };
1877
1878 static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
1879         { .fw_name = "xo", .name = "xo" },
1880         { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
1881         { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
1882         { .hw = &ubi32_pll.clkr.hw },
1883         { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1884 };
1885
1886 static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
1887         { P_XO, 0 },
1888         { P_UNIPHY2_TX, 1 },
1889         { P_UNIPHY2_RX, 2 },
1890         { P_UBI32_PLL, 5 },
1891         { P_BIAS_PLL, 6 },
1892 };
1893
1894 static struct clk_rcg2 nss_port6_tx_clk_src = {
1895         .cmd_rcgr = 0x68078,
1896         .freq_tbl = ftbl_nss_port6_tx_clk_src,
1897         .hid_width = 5,
1898         .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
1899         .clkr.hw.init = &(struct clk_init_data){
1900                 .name = "nss_port6_tx_clk_src",
1901                 .parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
1902                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
1903                 .ops = &clk_rcg2_ops,
1904         },
1905 };
1906
1907 static struct clk_regmap_div nss_port6_tx_div_clk_src = {
1908         .reg = 0x68454,
1909         .shift = 0,
1910         .width = 4,
1911         .clkr = {
1912                 .hw.init = &(struct clk_init_data){
1913                         .name = "nss_port6_tx_div_clk_src",
1914                         .parent_hws = (const struct clk_hw *[]){
1915                                 &nss_port6_tx_clk_src.clkr.hw },
1916                         .num_parents = 1,
1917                         .ops = &clk_regmap_div_ops,
1918                         .flags = CLK_SET_RATE_PARENT,
1919                 },
1920         },
1921 };
1922
1923 static struct freq_tbl ftbl_crypto_clk_src[] = {
1924         F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1925         F(80000000, P_GPLL0, 10, 0, 0),
1926         F(100000000, P_GPLL0, 8, 0, 0),
1927         F(160000000, P_GPLL0, 5, 0, 0),
1928         { }
1929 };
1930
1931 static struct clk_rcg2 crypto_clk_src = {
1932         .cmd_rcgr = 0x16004,
1933         .freq_tbl = ftbl_crypto_clk_src,
1934         .hid_width = 5,
1935         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1936         .clkr.hw.init = &(struct clk_init_data){
1937                 .name = "crypto_clk_src",
1938                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1939                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
1940                 .ops = &clk_rcg2_ops,
1941         },
1942 };
1943
1944 static struct freq_tbl ftbl_gp_clk_src[] = {
1945         F(19200000, P_XO, 1, 0, 0),
1946         { }
1947 };
1948
1949 static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
1950         { .fw_name = "xo", .name = "xo" },
1951         { .hw = &gpll0.clkr.hw },
1952         { .hw = &gpll6.clkr.hw },
1953         { .hw = &gpll0_out_main_div2.hw },
1954         { .fw_name = "sleep_clk", .name = "sleep_clk" },
1955 };
1956
1957 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
1958         { P_XO, 0 },
1959         { P_GPLL0, 1 },
1960         { P_GPLL6, 2 },
1961         { P_GPLL0_DIV2, 4 },
1962         { P_SLEEP_CLK, 6 },
1963 };
1964
1965 static struct clk_rcg2 gp1_clk_src = {
1966         .cmd_rcgr = 0x08004,
1967         .freq_tbl = ftbl_gp_clk_src,
1968         .mnd_width = 8,
1969         .hid_width = 5,
1970         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1971         .clkr.hw.init = &(struct clk_init_data){
1972                 .name = "gp1_clk_src",
1973                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1974                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
1975                 .ops = &clk_rcg2_ops,
1976         },
1977 };
1978
1979 static struct clk_rcg2 gp2_clk_src = {
1980         .cmd_rcgr = 0x09004,
1981         .freq_tbl = ftbl_gp_clk_src,
1982         .mnd_width = 8,
1983         .hid_width = 5,
1984         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1985         .clkr.hw.init = &(struct clk_init_data){
1986                 .name = "gp2_clk_src",
1987                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1988                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
1989                 .ops = &clk_rcg2_ops,
1990         },
1991 };
1992
1993 static struct clk_rcg2 gp3_clk_src = {
1994         .cmd_rcgr = 0x0a004,
1995         .freq_tbl = ftbl_gp_clk_src,
1996         .mnd_width = 8,
1997         .hid_width = 5,
1998         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1999         .clkr.hw.init = &(struct clk_init_data){
2000                 .name = "gp3_clk_src",
2001                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2002                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
2003                 .ops = &clk_rcg2_ops,
2004         },
2005 };
2006
2007 static struct clk_branch gcc_blsp1_ahb_clk = {
2008         .halt_reg = 0x01008,
2009         .clkr = {
2010                 .enable_reg = 0x01008,
2011                 .enable_mask = BIT(0),
2012                 .hw.init = &(struct clk_init_data){
2013                         .name = "gcc_blsp1_ahb_clk",
2014                         .parent_hws = (const struct clk_hw *[]){
2015                                 &pcnoc_clk_src.hw },
2016                         .num_parents = 1,
2017                         .flags = CLK_SET_RATE_PARENT,
2018                         .ops = &clk_branch2_ops,
2019                 },
2020         },
2021 };
2022
2023 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
2024         .halt_reg = 0x02008,
2025         .clkr = {
2026                 .enable_reg = 0x02008,
2027                 .enable_mask = BIT(0),
2028                 .hw.init = &(struct clk_init_data){
2029                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
2030                         .parent_hws = (const struct clk_hw *[]){
2031                                 &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
2032                         .num_parents = 1,
2033                         .flags = CLK_SET_RATE_PARENT,
2034                         .ops = &clk_branch2_ops,
2035                 },
2036         },
2037 };
2038
2039 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
2040         .halt_reg = 0x02004,
2041         .clkr = {
2042                 .enable_reg = 0x02004,
2043                 .enable_mask = BIT(0),
2044                 .hw.init = &(struct clk_init_data){
2045                         .name = "gcc_blsp1_qup1_spi_apps_clk",
2046                         .parent_hws = (const struct clk_hw *[]){
2047                                 &blsp1_qup1_spi_apps_clk_src.clkr.hw },
2048                         .num_parents = 1,
2049                         .flags = CLK_SET_RATE_PARENT,
2050                         .ops = &clk_branch2_ops,
2051                 },
2052         },
2053 };
2054
2055 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
2056         .halt_reg = 0x03010,
2057         .clkr = {
2058                 .enable_reg = 0x03010,
2059                 .enable_mask = BIT(0),
2060                 .hw.init = &(struct clk_init_data){
2061                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
2062                         .parent_hws = (const struct clk_hw *[]){
2063                                 &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
2064                         .num_parents = 1,
2065                         .flags = CLK_SET_RATE_PARENT,
2066                         .ops = &clk_branch2_ops,
2067                 },
2068         },
2069 };
2070
2071 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2072         .halt_reg = 0x0300c,
2073         .clkr = {
2074                 .enable_reg = 0x0300c,
2075                 .enable_mask = BIT(0),
2076                 .hw.init = &(struct clk_init_data){
2077                         .name = "gcc_blsp1_qup2_spi_apps_clk",
2078                         .parent_hws = (const struct clk_hw *[]){
2079                                 &blsp1_qup2_spi_apps_clk_src.clkr.hw },
2080                         .num_parents = 1,
2081                         .flags = CLK_SET_RATE_PARENT,
2082                         .ops = &clk_branch2_ops,
2083                 },
2084         },
2085 };
2086
2087 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
2088         .halt_reg = 0x04010,
2089         .clkr = {
2090                 .enable_reg = 0x04010,
2091                 .enable_mask = BIT(0),
2092                 .hw.init = &(struct clk_init_data){
2093                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
2094                         .parent_hws = (const struct clk_hw *[]){
2095                                 &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
2096                         .num_parents = 1,
2097                         .flags = CLK_SET_RATE_PARENT,
2098                         .ops = &clk_branch2_ops,
2099                 },
2100         },
2101 };
2102
2103 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2104         .halt_reg = 0x0400c,
2105         .clkr = {
2106                 .enable_reg = 0x0400c,
2107                 .enable_mask = BIT(0),
2108                 .hw.init = &(struct clk_init_data){
2109                         .name = "gcc_blsp1_qup3_spi_apps_clk",
2110                         .parent_hws = (const struct clk_hw *[]){
2111                                 &blsp1_qup3_spi_apps_clk_src.clkr.hw },
2112                         .num_parents = 1,
2113                         .flags = CLK_SET_RATE_PARENT,
2114                         .ops = &clk_branch2_ops,
2115                 },
2116         },
2117 };
2118
2119 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2120         .halt_reg = 0x05010,
2121         .clkr = {
2122                 .enable_reg = 0x05010,
2123                 .enable_mask = BIT(0),
2124                 .hw.init = &(struct clk_init_data){
2125                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
2126                         .parent_hws = (const struct clk_hw *[]){
2127                                 &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
2128                         .num_parents = 1,
2129                         .flags = CLK_SET_RATE_PARENT,
2130                         .ops = &clk_branch2_ops,
2131                 },
2132         },
2133 };
2134
2135 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2136         .halt_reg = 0x0500c,
2137         .clkr = {
2138                 .enable_reg = 0x0500c,
2139                 .enable_mask = BIT(0),
2140                 .hw.init = &(struct clk_init_data){
2141                         .name = "gcc_blsp1_qup4_spi_apps_clk",
2142                         .parent_hws = (const struct clk_hw *[]){
2143                                 &blsp1_qup4_spi_apps_clk_src.clkr.hw },
2144                         .num_parents = 1,
2145                         .flags = CLK_SET_RATE_PARENT,
2146                         .ops = &clk_branch2_ops,
2147                 },
2148         },
2149 };
2150
2151 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2152         .halt_reg = 0x06010,
2153         .clkr = {
2154                 .enable_reg = 0x06010,
2155                 .enable_mask = BIT(0),
2156                 .hw.init = &(struct clk_init_data){
2157                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
2158                         .parent_hws = (const struct clk_hw *[]){
2159                                 &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
2160                         .num_parents = 1,
2161                         .flags = CLK_SET_RATE_PARENT,
2162                         .ops = &clk_branch2_ops,
2163                 },
2164         },
2165 };
2166
2167 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2168         .halt_reg = 0x0600c,
2169         .clkr = {
2170                 .enable_reg = 0x0600c,
2171                 .enable_mask = BIT(0),
2172                 .hw.init = &(struct clk_init_data){
2173                         .name = "gcc_blsp1_qup5_spi_apps_clk",
2174                         .parent_hws = (const struct clk_hw *[]){
2175                                 &blsp1_qup5_spi_apps_clk_src.clkr.hw },
2176                         .num_parents = 1,
2177                         .flags = CLK_SET_RATE_PARENT,
2178                         .ops = &clk_branch2_ops,
2179                 },
2180         },
2181 };
2182
2183 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2184         .halt_reg = 0x07010,
2185         .clkr = {
2186                 .enable_reg = 0x07010,
2187                 .enable_mask = BIT(0),
2188                 .hw.init = &(struct clk_init_data){
2189                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
2190                         .parent_hws = (const struct clk_hw *[]){
2191                                 &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
2192                         .num_parents = 1,
2193                         .flags = CLK_SET_RATE_PARENT,
2194                         .ops = &clk_branch2_ops,
2195                 },
2196         },
2197 };
2198
2199 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2200         .halt_reg = 0x0700c,
2201         .clkr = {
2202                 .enable_reg = 0x0700c,
2203                 .enable_mask = BIT(0),
2204                 .hw.init = &(struct clk_init_data){
2205                         .name = "gcc_blsp1_qup6_spi_apps_clk",
2206                         .parent_hws = (const struct clk_hw *[]){
2207                                 &blsp1_qup6_spi_apps_clk_src.clkr.hw },
2208                         .num_parents = 1,
2209                         .flags = CLK_SET_RATE_PARENT,
2210                         .ops = &clk_branch2_ops,
2211                 },
2212         },
2213 };
2214
2215 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2216         .halt_reg = 0x0203c,
2217         .clkr = {
2218                 .enable_reg = 0x0203c,
2219                 .enable_mask = BIT(0),
2220                 .hw.init = &(struct clk_init_data){
2221                         .name = "gcc_blsp1_uart1_apps_clk",
2222                         .parent_hws = (const struct clk_hw *[]){
2223                                 &blsp1_uart1_apps_clk_src.clkr.hw },
2224                         .num_parents = 1,
2225                         .flags = CLK_SET_RATE_PARENT,
2226                         .ops = &clk_branch2_ops,
2227                 },
2228         },
2229 };
2230
2231 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2232         .halt_reg = 0x0302c,
2233         .clkr = {
2234                 .enable_reg = 0x0302c,
2235                 .enable_mask = BIT(0),
2236                 .hw.init = &(struct clk_init_data){
2237                         .name = "gcc_blsp1_uart2_apps_clk",
2238                         .parent_hws = (const struct clk_hw *[]){
2239                                 &blsp1_uart2_apps_clk_src.clkr.hw },
2240                         .num_parents = 1,
2241                         .flags = CLK_SET_RATE_PARENT,
2242                         .ops = &clk_branch2_ops,
2243                 },
2244         },
2245 };
2246
2247 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
2248         .halt_reg = 0x0402c,
2249         .clkr = {
2250                 .enable_reg = 0x0402c,
2251                 .enable_mask = BIT(0),
2252                 .hw.init = &(struct clk_init_data){
2253                         .name = "gcc_blsp1_uart3_apps_clk",
2254                         .parent_hws = (const struct clk_hw *[]){
2255                                 &blsp1_uart3_apps_clk_src.clkr.hw },
2256                         .num_parents = 1,
2257                         .flags = CLK_SET_RATE_PARENT,
2258                         .ops = &clk_branch2_ops,
2259                 },
2260         },
2261 };
2262
2263 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
2264         .halt_reg = 0x0502c,
2265         .clkr = {
2266                 .enable_reg = 0x0502c,
2267                 .enable_mask = BIT(0),
2268                 .hw.init = &(struct clk_init_data){
2269                         .name = "gcc_blsp1_uart4_apps_clk",
2270                         .parent_hws = (const struct clk_hw *[]){
2271                                 &blsp1_uart4_apps_clk_src.clkr.hw },
2272                         .num_parents = 1,
2273                         .flags = CLK_SET_RATE_PARENT,
2274                         .ops = &clk_branch2_ops,
2275                 },
2276         },
2277 };
2278
2279 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
2280         .halt_reg = 0x0602c,
2281         .clkr = {
2282                 .enable_reg = 0x0602c,
2283                 .enable_mask = BIT(0),
2284                 .hw.init = &(struct clk_init_data){
2285                         .name = "gcc_blsp1_uart5_apps_clk",
2286                         .parent_hws = (const struct clk_hw *[]){
2287                                 &blsp1_uart5_apps_clk_src.clkr.hw },
2288                         .num_parents = 1,
2289                         .flags = CLK_SET_RATE_PARENT,
2290                         .ops = &clk_branch2_ops,
2291                 },
2292         },
2293 };
2294
2295 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
2296         .halt_reg = 0x0702c,
2297         .clkr = {
2298                 .enable_reg = 0x0702c,
2299                 .enable_mask = BIT(0),
2300                 .hw.init = &(struct clk_init_data){
2301                         .name = "gcc_blsp1_uart6_apps_clk",
2302                         .parent_hws = (const struct clk_hw *[]){
2303                                 &blsp1_uart6_apps_clk_src.clkr.hw },
2304                         .num_parents = 1,
2305                         .flags = CLK_SET_RATE_PARENT,
2306                         .ops = &clk_branch2_ops,
2307                 },
2308         },
2309 };
2310
2311 static struct clk_branch gcc_prng_ahb_clk = {
2312         .halt_reg = 0x13004,
2313         .halt_check = BRANCH_HALT_VOTED,
2314         .clkr = {
2315                 .enable_reg = 0x0b004,
2316                 .enable_mask = BIT(8),
2317                 .hw.init = &(struct clk_init_data){
2318                         .name = "gcc_prng_ahb_clk",
2319                         .parent_hws = (const struct clk_hw *[]){
2320                                 &pcnoc_clk_src.hw },
2321                         .num_parents = 1,
2322                         .flags = CLK_SET_RATE_PARENT,
2323                         .ops = &clk_branch2_ops,
2324                 },
2325         },
2326 };
2327
2328 static struct clk_branch gcc_qpic_ahb_clk = {
2329         .halt_reg = 0x57024,
2330         .clkr = {
2331                 .enable_reg = 0x57024,
2332                 .enable_mask = BIT(0),
2333                 .hw.init = &(struct clk_init_data){
2334                         .name = "gcc_qpic_ahb_clk",
2335                         .parent_hws = (const struct clk_hw *[]){
2336                                 &pcnoc_clk_src.hw },
2337                         .num_parents = 1,
2338                         .flags = CLK_SET_RATE_PARENT,
2339                         .ops = &clk_branch2_ops,
2340                 },
2341         },
2342 };
2343
2344 static struct clk_branch gcc_qpic_clk = {
2345         .halt_reg = 0x57020,
2346         .clkr = {
2347                 .enable_reg = 0x57020,
2348                 .enable_mask = BIT(0),
2349                 .hw.init = &(struct clk_init_data){
2350                         .name = "gcc_qpic_clk",
2351                         .parent_hws = (const struct clk_hw *[]){
2352                                 &pcnoc_clk_src.hw },
2353                         .num_parents = 1,
2354                         .flags = CLK_SET_RATE_PARENT,
2355                         .ops = &clk_branch2_ops,
2356                 },
2357         },
2358 };
2359
2360 static struct clk_branch gcc_pcie0_ahb_clk = {
2361         .halt_reg = 0x75010,
2362         .clkr = {
2363                 .enable_reg = 0x75010,
2364                 .enable_mask = BIT(0),
2365                 .hw.init = &(struct clk_init_data){
2366                         .name = "gcc_pcie0_ahb_clk",
2367                         .parent_hws = (const struct clk_hw *[]){
2368                                 &pcnoc_clk_src.hw },
2369                         .num_parents = 1,
2370                         .flags = CLK_SET_RATE_PARENT,
2371                         .ops = &clk_branch2_ops,
2372                 },
2373         },
2374 };
2375
2376 static struct clk_branch gcc_pcie0_aux_clk = {
2377         .halt_reg = 0x75014,
2378         .clkr = {
2379                 .enable_reg = 0x75014,
2380                 .enable_mask = BIT(0),
2381                 .hw.init = &(struct clk_init_data){
2382                         .name = "gcc_pcie0_aux_clk",
2383                         .parent_hws = (const struct clk_hw *[]){
2384                                 &pcie0_aux_clk_src.clkr.hw },
2385                         .num_parents = 1,
2386                         .flags = CLK_SET_RATE_PARENT,
2387                         .ops = &clk_branch2_ops,
2388                 },
2389         },
2390 };
2391
2392 static struct clk_branch gcc_pcie0_axi_m_clk = {
2393         .halt_reg = 0x75008,
2394         .clkr = {
2395                 .enable_reg = 0x75008,
2396                 .enable_mask = BIT(0),
2397                 .hw.init = &(struct clk_init_data){
2398                         .name = "gcc_pcie0_axi_m_clk",
2399                         .parent_hws = (const struct clk_hw *[]){
2400                                 &pcie0_axi_clk_src.clkr.hw },
2401                         .num_parents = 1,
2402                         .flags = CLK_SET_RATE_PARENT,
2403                         .ops = &clk_branch2_ops,
2404                 },
2405         },
2406 };
2407
2408 static struct clk_branch gcc_pcie0_axi_s_clk = {
2409         .halt_reg = 0x7500c,
2410         .clkr = {
2411                 .enable_reg = 0x7500c,
2412                 .enable_mask = BIT(0),
2413                 .hw.init = &(struct clk_init_data){
2414                         .name = "gcc_pcie0_axi_s_clk",
2415                         .parent_hws = (const struct clk_hw *[]){
2416                                 &pcie0_axi_clk_src.clkr.hw },
2417                         .num_parents = 1,
2418                         .flags = CLK_SET_RATE_PARENT,
2419                         .ops = &clk_branch2_ops,
2420                 },
2421         },
2422 };
2423
2424 static struct clk_branch gcc_pcie0_pipe_clk = {
2425         .halt_reg = 0x75018,
2426         .halt_check = BRANCH_HALT_DELAY,
2427         .clkr = {
2428                 .enable_reg = 0x75018,
2429                 .enable_mask = BIT(0),
2430                 .hw.init = &(struct clk_init_data){
2431                         .name = "gcc_pcie0_pipe_clk",
2432                         .parent_hws = (const struct clk_hw *[]){
2433                                 &pcie0_pipe_clk_src.clkr.hw },
2434                         .num_parents = 1,
2435                         .flags = CLK_SET_RATE_PARENT,
2436                         .ops = &clk_branch2_ops,
2437                 },
2438         },
2439 };
2440
2441 static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
2442         .halt_reg = 0x26048,
2443         .clkr = {
2444                 .enable_reg = 0x26048,
2445                 .enable_mask = BIT(0),
2446                 .hw.init = &(struct clk_init_data){
2447                         .name = "gcc_sys_noc_pcie0_axi_clk",
2448                         .parent_hws = (const struct clk_hw *[]){
2449                                 &pcie0_axi_clk_src.clkr.hw },
2450                         .num_parents = 1,
2451                         .flags = CLK_SET_RATE_PARENT,
2452                         .ops = &clk_branch2_ops,
2453                 },
2454         },
2455 };
2456
2457 static struct clk_branch gcc_pcie1_ahb_clk = {
2458         .halt_reg = 0x76010,
2459         .clkr = {
2460                 .enable_reg = 0x76010,
2461                 .enable_mask = BIT(0),
2462                 .hw.init = &(struct clk_init_data){
2463                         .name = "gcc_pcie1_ahb_clk",
2464                         .parent_hws = (const struct clk_hw *[]){
2465                                 &pcnoc_clk_src.hw },
2466                         .num_parents = 1,
2467                         .flags = CLK_SET_RATE_PARENT,
2468                         .ops = &clk_branch2_ops,
2469                 },
2470         },
2471 };
2472
2473 static struct clk_branch gcc_pcie1_aux_clk = {
2474         .halt_reg = 0x76014,
2475         .clkr = {
2476                 .enable_reg = 0x76014,
2477                 .enable_mask = BIT(0),
2478                 .hw.init = &(struct clk_init_data){
2479                         .name = "gcc_pcie1_aux_clk",
2480                         .parent_hws = (const struct clk_hw *[]){
2481                                 &pcie1_aux_clk_src.clkr.hw },
2482                         .num_parents = 1,
2483                         .flags = CLK_SET_RATE_PARENT,
2484                         .ops = &clk_branch2_ops,
2485                 },
2486         },
2487 };
2488
2489 static struct clk_branch gcc_pcie1_axi_m_clk = {
2490         .halt_reg = 0x76008,
2491         .clkr = {
2492                 .enable_reg = 0x76008,
2493                 .enable_mask = BIT(0),
2494                 .hw.init = &(struct clk_init_data){
2495                         .name = "gcc_pcie1_axi_m_clk",
2496                         .parent_hws = (const struct clk_hw *[]){
2497                                 &pcie1_axi_clk_src.clkr.hw },
2498                         .num_parents = 1,
2499                         .flags = CLK_SET_RATE_PARENT,
2500                         .ops = &clk_branch2_ops,
2501                 },
2502         },
2503 };
2504
2505 static struct clk_branch gcc_pcie1_axi_s_clk = {
2506         .halt_reg = 0x7600c,
2507         .clkr = {
2508                 .enable_reg = 0x7600c,
2509                 .enable_mask = BIT(0),
2510                 .hw.init = &(struct clk_init_data){
2511                         .name = "gcc_pcie1_axi_s_clk",
2512                         .parent_hws = (const struct clk_hw *[]){
2513                                 &pcie1_axi_clk_src.clkr.hw },
2514                         .num_parents = 1,
2515                         .flags = CLK_SET_RATE_PARENT,
2516                         .ops = &clk_branch2_ops,
2517                 },
2518         },
2519 };
2520
2521 static struct clk_branch gcc_pcie1_pipe_clk = {
2522         .halt_reg = 0x76018,
2523         .halt_check = BRANCH_HALT_DELAY,
2524         .clkr = {
2525                 .enable_reg = 0x76018,
2526                 .enable_mask = BIT(0),
2527                 .hw.init = &(struct clk_init_data){
2528                         .name = "gcc_pcie1_pipe_clk",
2529                         .parent_hws = (const struct clk_hw *[]){
2530                                 &pcie1_pipe_clk_src.clkr.hw },
2531                         .num_parents = 1,
2532                         .flags = CLK_SET_RATE_PARENT,
2533                         .ops = &clk_branch2_ops,
2534                 },
2535         },
2536 };
2537
2538 static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
2539         .halt_reg = 0x2604c,
2540         .clkr = {
2541                 .enable_reg = 0x2604c,
2542                 .enable_mask = BIT(0),
2543                 .hw.init = &(struct clk_init_data){
2544                         .name = "gcc_sys_noc_pcie1_axi_clk",
2545                         .parent_hws = (const struct clk_hw *[]){
2546                                 &pcie1_axi_clk_src.clkr.hw },
2547                         .num_parents = 1,
2548                         .flags = CLK_SET_RATE_PARENT,
2549                         .ops = &clk_branch2_ops,
2550                 },
2551         },
2552 };
2553
2554 static struct clk_branch gcc_usb0_aux_clk = {
2555         .halt_reg = 0x3e044,
2556         .clkr = {
2557                 .enable_reg = 0x3e044,
2558                 .enable_mask = BIT(0),
2559                 .hw.init = &(struct clk_init_data){
2560                         .name = "gcc_usb0_aux_clk",
2561                         .parent_hws = (const struct clk_hw *[]){
2562                                 &usb0_aux_clk_src.clkr.hw },
2563                         .num_parents = 1,
2564                         .flags = CLK_SET_RATE_PARENT,
2565                         .ops = &clk_branch2_ops,
2566                 },
2567         },
2568 };
2569
2570 static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
2571         .halt_reg = 0x26040,
2572         .clkr = {
2573                 .enable_reg = 0x26040,
2574                 .enable_mask = BIT(0),
2575                 .hw.init = &(struct clk_init_data){
2576                         .name = "gcc_sys_noc_usb0_axi_clk",
2577                         .parent_hws = (const struct clk_hw *[]){
2578                                 &usb0_master_clk_src.clkr.hw },
2579                         .num_parents = 1,
2580                         .flags = CLK_SET_RATE_PARENT,
2581                         .ops = &clk_branch2_ops,
2582                 },
2583         },
2584 };
2585
2586 static struct clk_branch gcc_usb0_master_clk = {
2587         .halt_reg = 0x3e000,
2588         .clkr = {
2589                 .enable_reg = 0x3e000,
2590                 .enable_mask = BIT(0),
2591                 .hw.init = &(struct clk_init_data){
2592                         .name = "gcc_usb0_master_clk",
2593                         .parent_hws = (const struct clk_hw *[]){
2594                                 &usb0_master_clk_src.clkr.hw },
2595                         .num_parents = 1,
2596                         .flags = CLK_SET_RATE_PARENT,
2597                         .ops = &clk_branch2_ops,
2598                 },
2599         },
2600 };
2601
2602 static struct clk_branch gcc_usb0_mock_utmi_clk = {
2603         .halt_reg = 0x3e008,
2604         .clkr = {
2605                 .enable_reg = 0x3e008,
2606                 .enable_mask = BIT(0),
2607                 .hw.init = &(struct clk_init_data){
2608                         .name = "gcc_usb0_mock_utmi_clk",
2609                         .parent_hws = (const struct clk_hw *[]){
2610                                 &usb0_mock_utmi_clk_src.clkr.hw },
2611                         .num_parents = 1,
2612                         .flags = CLK_SET_RATE_PARENT,
2613                         .ops = &clk_branch2_ops,
2614                 },
2615         },
2616 };
2617
2618 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2619         .halt_reg = 0x3e080,
2620         .clkr = {
2621                 .enable_reg = 0x3e080,
2622                 .enable_mask = BIT(0),
2623                 .hw.init = &(struct clk_init_data){
2624                         .name = "gcc_usb0_phy_cfg_ahb_clk",
2625                         .parent_hws = (const struct clk_hw *[]){
2626                                 &pcnoc_clk_src.hw },
2627                         .num_parents = 1,
2628                         .flags = CLK_SET_RATE_PARENT,
2629                         .ops = &clk_branch2_ops,
2630                 },
2631         },
2632 };
2633
2634 static struct clk_branch gcc_usb0_pipe_clk = {
2635         .halt_reg = 0x3e040,
2636         .halt_check = BRANCH_HALT_DELAY,
2637         .clkr = {
2638                 .enable_reg = 0x3e040,
2639                 .enable_mask = BIT(0),
2640                 .hw.init = &(struct clk_init_data){
2641                         .name = "gcc_usb0_pipe_clk",
2642                         .parent_hws = (const struct clk_hw *[]){
2643                                 &usb0_pipe_clk_src.clkr.hw },
2644                         .num_parents = 1,
2645                         .flags = CLK_SET_RATE_PARENT,
2646                         .ops = &clk_branch2_ops,
2647                 },
2648         },
2649 };
2650
2651 static struct clk_branch gcc_usb0_sleep_clk = {
2652         .halt_reg = 0x3e004,
2653         .clkr = {
2654                 .enable_reg = 0x3e004,
2655                 .enable_mask = BIT(0),
2656                 .hw.init = &(struct clk_init_data){
2657                         .name = "gcc_usb0_sleep_clk",
2658                         .parent_hws = (const struct clk_hw *[]){
2659                                 &gcc_sleep_clk_src.clkr.hw },
2660                         .num_parents = 1,
2661                         .flags = CLK_SET_RATE_PARENT,
2662                         .ops = &clk_branch2_ops,
2663                 },
2664         },
2665 };
2666
2667 static struct clk_branch gcc_usb1_aux_clk = {
2668         .halt_reg = 0x3f044,
2669         .clkr = {
2670                 .enable_reg = 0x3f044,
2671                 .enable_mask = BIT(0),
2672                 .hw.init = &(struct clk_init_data){
2673                         .name = "gcc_usb1_aux_clk",
2674                         .parent_hws = (const struct clk_hw *[]){
2675                                 &usb1_aux_clk_src.clkr.hw },
2676                         .num_parents = 1,
2677                         .flags = CLK_SET_RATE_PARENT,
2678                         .ops = &clk_branch2_ops,
2679                 },
2680         },
2681 };
2682
2683 static struct clk_branch gcc_sys_noc_usb1_axi_clk = {
2684         .halt_reg = 0x26044,
2685         .clkr = {
2686                 .enable_reg = 0x26044,
2687                 .enable_mask = BIT(0),
2688                 .hw.init = &(struct clk_init_data){
2689                         .name = "gcc_sys_noc_usb1_axi_clk",
2690                         .parent_hws = (const struct clk_hw *[]){
2691                                 &usb1_master_clk_src.clkr.hw },
2692                         .num_parents = 1,
2693                         .flags = CLK_SET_RATE_PARENT,
2694                         .ops = &clk_branch2_ops,
2695                 },
2696         },
2697 };
2698
2699 static struct clk_branch gcc_usb1_master_clk = {
2700         .halt_reg = 0x3f000,
2701         .clkr = {
2702                 .enable_reg = 0x3f000,
2703                 .enable_mask = BIT(0),
2704                 .hw.init = &(struct clk_init_data){
2705                         .name = "gcc_usb1_master_clk",
2706                         .parent_hws = (const struct clk_hw *[]){
2707                                 &usb1_master_clk_src.clkr.hw },
2708                         .num_parents = 1,
2709                         .flags = CLK_SET_RATE_PARENT,
2710                         .ops = &clk_branch2_ops,
2711                 },
2712         },
2713 };
2714
2715 static struct clk_branch gcc_usb1_mock_utmi_clk = {
2716         .halt_reg = 0x3f008,
2717         .clkr = {
2718                 .enable_reg = 0x3f008,
2719                 .enable_mask = BIT(0),
2720                 .hw.init = &(struct clk_init_data){
2721                         .name = "gcc_usb1_mock_utmi_clk",
2722                         .parent_hws = (const struct clk_hw *[]){
2723                                 &usb1_mock_utmi_clk_src.clkr.hw },
2724                         .num_parents = 1,
2725                         .flags = CLK_SET_RATE_PARENT,
2726                         .ops = &clk_branch2_ops,
2727                 },
2728         },
2729 };
2730
2731 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
2732         .halt_reg = 0x3f080,
2733         .clkr = {
2734                 .enable_reg = 0x3f080,
2735                 .enable_mask = BIT(0),
2736                 .hw.init = &(struct clk_init_data){
2737                         .name = "gcc_usb1_phy_cfg_ahb_clk",
2738                         .parent_hws = (const struct clk_hw *[]){
2739                                 &pcnoc_clk_src.hw },
2740                         .num_parents = 1,
2741                         .flags = CLK_SET_RATE_PARENT,
2742                         .ops = &clk_branch2_ops,
2743                 },
2744         },
2745 };
2746
2747 static struct clk_branch gcc_usb1_pipe_clk = {
2748         .halt_reg = 0x3f040,
2749         .halt_check = BRANCH_HALT_DELAY,
2750         .clkr = {
2751                 .enable_reg = 0x3f040,
2752                 .enable_mask = BIT(0),
2753                 .hw.init = &(struct clk_init_data){
2754                         .name = "gcc_usb1_pipe_clk",
2755                         .parent_hws = (const struct clk_hw *[]){
2756                                 &usb1_pipe_clk_src.clkr.hw },
2757                         .num_parents = 1,
2758                         .flags = CLK_SET_RATE_PARENT,
2759                         .ops = &clk_branch2_ops,
2760                 },
2761         },
2762 };
2763
2764 static struct clk_branch gcc_usb1_sleep_clk = {
2765         .halt_reg = 0x3f004,
2766         .clkr = {
2767                 .enable_reg = 0x3f004,
2768                 .enable_mask = BIT(0),
2769                 .hw.init = &(struct clk_init_data){
2770                         .name = "gcc_usb1_sleep_clk",
2771                         .parent_hws = (const struct clk_hw *[]){
2772                                 &gcc_sleep_clk_src.clkr.hw },
2773                         .num_parents = 1,
2774                         .flags = CLK_SET_RATE_PARENT,
2775                         .ops = &clk_branch2_ops,
2776                 },
2777         },
2778 };
2779
2780 static struct clk_branch gcc_sdcc1_ahb_clk = {
2781         .halt_reg = 0x4201c,
2782         .clkr = {
2783                 .enable_reg = 0x4201c,
2784                 .enable_mask = BIT(0),
2785                 .hw.init = &(struct clk_init_data){
2786                         .name = "gcc_sdcc1_ahb_clk",
2787                         .parent_hws = (const struct clk_hw *[]){
2788                                 &pcnoc_clk_src.hw },
2789                         .num_parents = 1,
2790                         .flags = CLK_SET_RATE_PARENT,
2791                         .ops = &clk_branch2_ops,
2792                 },
2793         },
2794 };
2795
2796 static struct clk_branch gcc_sdcc1_apps_clk = {
2797         .halt_reg = 0x42018,
2798         .clkr = {
2799                 .enable_reg = 0x42018,
2800                 .enable_mask = BIT(0),
2801                 .hw.init = &(struct clk_init_data){
2802                         .name = "gcc_sdcc1_apps_clk",
2803                         .parent_hws = (const struct clk_hw *[]){
2804                                 &sdcc1_apps_clk_src.clkr.hw },
2805                         .num_parents = 1,
2806                         .flags = CLK_SET_RATE_PARENT,
2807                         .ops = &clk_branch2_ops,
2808                 },
2809         },
2810 };
2811
2812 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2813         .halt_reg = 0x5d014,
2814         .clkr = {
2815                 .enable_reg = 0x5d014,
2816                 .enable_mask = BIT(0),
2817                 .hw.init = &(struct clk_init_data){
2818                         .name = "gcc_sdcc1_ice_core_clk",
2819                         .parent_hws = (const struct clk_hw *[]){
2820                                 &sdcc1_ice_core_clk_src.clkr.hw },
2821                         .num_parents = 1,
2822                         .flags = CLK_SET_RATE_PARENT,
2823                         .ops = &clk_branch2_ops,
2824                 },
2825         },
2826 };
2827
2828 static struct clk_branch gcc_sdcc2_ahb_clk = {
2829         .halt_reg = 0x4301c,
2830         .clkr = {
2831                 .enable_reg = 0x4301c,
2832                 .enable_mask = BIT(0),
2833                 .hw.init = &(struct clk_init_data){
2834                         .name = "gcc_sdcc2_ahb_clk",
2835                         .parent_hws = (const struct clk_hw *[]){
2836                                 &pcnoc_clk_src.hw },
2837                         .num_parents = 1,
2838                         .flags = CLK_SET_RATE_PARENT,
2839                         .ops = &clk_branch2_ops,
2840                 },
2841         },
2842 };
2843
2844 static struct clk_branch gcc_sdcc2_apps_clk = {
2845         .halt_reg = 0x43018,
2846         .clkr = {
2847                 .enable_reg = 0x43018,
2848                 .enable_mask = BIT(0),
2849                 .hw.init = &(struct clk_init_data){
2850                         .name = "gcc_sdcc2_apps_clk",
2851                         .parent_hws = (const struct clk_hw *[]){
2852                                 &sdcc2_apps_clk_src.clkr.hw },
2853                         .num_parents = 1,
2854                         .flags = CLK_SET_RATE_PARENT,
2855                         .ops = &clk_branch2_ops,
2856                 },
2857         },
2858 };
2859
2860 static struct clk_branch gcc_mem_noc_nss_axi_clk = {
2861         .halt_reg = 0x1d03c,
2862         .clkr = {
2863                 .enable_reg = 0x1d03c,
2864                 .enable_mask = BIT(0),
2865                 .hw.init = &(struct clk_init_data){
2866                         .name = "gcc_mem_noc_nss_axi_clk",
2867                         .parent_hws = (const struct clk_hw *[]){
2868                                 &nss_noc_clk_src.hw },
2869                         .num_parents = 1,
2870                         .flags = CLK_SET_RATE_PARENT,
2871                         .ops = &clk_branch2_ops,
2872                 },
2873         },
2874 };
2875
2876 static struct clk_branch gcc_nss_ce_apb_clk = {
2877         .halt_reg = 0x68174,
2878         .clkr = {
2879                 .enable_reg = 0x68174,
2880                 .enable_mask = BIT(0),
2881                 .hw.init = &(struct clk_init_data){
2882                         .name = "gcc_nss_ce_apb_clk",
2883                         .parent_hws = (const struct clk_hw *[]){
2884                                 &nss_ce_clk_src.clkr.hw },
2885                         .num_parents = 1,
2886                         .flags = CLK_SET_RATE_PARENT,
2887                         .ops = &clk_branch2_ops,
2888                 },
2889         },
2890 };
2891
2892 static struct clk_branch gcc_nss_ce_axi_clk = {
2893         .halt_reg = 0x68170,
2894         .clkr = {
2895                 .enable_reg = 0x68170,
2896                 .enable_mask = BIT(0),
2897                 .hw.init = &(struct clk_init_data){
2898                         .name = "gcc_nss_ce_axi_clk",
2899                         .parent_hws = (const struct clk_hw *[]){
2900                                 &nss_ce_clk_src.clkr.hw },
2901                         .num_parents = 1,
2902                         .flags = CLK_SET_RATE_PARENT,
2903                         .ops = &clk_branch2_ops,
2904                 },
2905         },
2906 };
2907
2908 static struct clk_branch gcc_nss_cfg_clk = {
2909         .halt_reg = 0x68160,
2910         .clkr = {
2911                 .enable_reg = 0x68160,
2912                 .enable_mask = BIT(0),
2913                 .hw.init = &(struct clk_init_data){
2914                         .name = "gcc_nss_cfg_clk",
2915                         .parent_hws = (const struct clk_hw *[]){
2916                                 &pcnoc_clk_src.hw },
2917                         .num_parents = 1,
2918                         .flags = CLK_SET_RATE_PARENT,
2919                         .ops = &clk_branch2_ops,
2920                 },
2921         },
2922 };
2923
2924 static struct clk_branch gcc_nss_crypto_clk = {
2925         .halt_reg = 0x68164,
2926         .clkr = {
2927                 .enable_reg = 0x68164,
2928                 .enable_mask = BIT(0),
2929                 .hw.init = &(struct clk_init_data){
2930                         .name = "gcc_nss_crypto_clk",
2931                         .parent_hws = (const struct clk_hw *[]){
2932                                 &nss_crypto_clk_src.clkr.hw },
2933                         .num_parents = 1,
2934                         .flags = CLK_SET_RATE_PARENT,
2935                         .ops = &clk_branch2_ops,
2936                 },
2937         },
2938 };
2939
2940 static struct clk_branch gcc_nss_csr_clk = {
2941         .halt_reg = 0x68318,
2942         .clkr = {
2943                 .enable_reg = 0x68318,
2944                 .enable_mask = BIT(0),
2945                 .hw.init = &(struct clk_init_data){
2946                         .name = "gcc_nss_csr_clk",
2947                         .parent_hws = (const struct clk_hw *[]){
2948                                 &nss_ce_clk_src.clkr.hw },
2949                         .num_parents = 1,
2950                         .flags = CLK_SET_RATE_PARENT,
2951                         .ops = &clk_branch2_ops,
2952                 },
2953         },
2954 };
2955
2956 static struct clk_branch gcc_nss_edma_cfg_clk = {
2957         .halt_reg = 0x6819c,
2958         .clkr = {
2959                 .enable_reg = 0x6819c,
2960                 .enable_mask = BIT(0),
2961                 .hw.init = &(struct clk_init_data){
2962                         .name = "gcc_nss_edma_cfg_clk",
2963                         .parent_hws = (const struct clk_hw *[]){
2964                                 &nss_ppe_clk_src.clkr.hw },
2965                         .num_parents = 1,
2966                         .flags = CLK_SET_RATE_PARENT,
2967                         .ops = &clk_branch2_ops,
2968                 },
2969         },
2970 };
2971
2972 static struct clk_branch gcc_nss_edma_clk = {
2973         .halt_reg = 0x68198,
2974         .clkr = {
2975                 .enable_reg = 0x68198,
2976                 .enable_mask = BIT(0),
2977                 .hw.init = &(struct clk_init_data){
2978                         .name = "gcc_nss_edma_clk",
2979                         .parent_hws = (const struct clk_hw *[]){
2980                                 &nss_ppe_clk_src.clkr.hw },
2981                         .num_parents = 1,
2982                         .flags = CLK_SET_RATE_PARENT,
2983                         .ops = &clk_branch2_ops,
2984                 },
2985         },
2986 };
2987
2988 static struct clk_branch gcc_nss_imem_clk = {
2989         .halt_reg = 0x68178,
2990         .clkr = {
2991                 .enable_reg = 0x68178,
2992                 .enable_mask = BIT(0),
2993                 .hw.init = &(struct clk_init_data){
2994                         .name = "gcc_nss_imem_clk",
2995                         .parent_hws = (const struct clk_hw *[]){
2996                                 &nss_imem_clk_src.clkr.hw },
2997                         .num_parents = 1,
2998                         .flags = CLK_SET_RATE_PARENT,
2999                         .ops = &clk_branch2_ops,
3000                 },
3001         },
3002 };
3003
3004 static struct clk_branch gcc_nss_noc_clk = {
3005         .halt_reg = 0x68168,
3006         .clkr = {
3007                 .enable_reg = 0x68168,
3008                 .enable_mask = BIT(0),
3009                 .hw.init = &(struct clk_init_data){
3010                         .name = "gcc_nss_noc_clk",
3011                         .parent_hws = (const struct clk_hw *[]){
3012                                 &nss_noc_clk_src.hw },
3013                         .num_parents = 1,
3014                         .flags = CLK_SET_RATE_PARENT,
3015                         .ops = &clk_branch2_ops,
3016                 },
3017         },
3018 };
3019
3020 static struct clk_branch gcc_nss_ppe_btq_clk = {
3021         .halt_reg = 0x6833c,
3022         .clkr = {
3023                 .enable_reg = 0x6833c,
3024                 .enable_mask = BIT(0),
3025                 .hw.init = &(struct clk_init_data){
3026                         .name = "gcc_nss_ppe_btq_clk",
3027                         .parent_hws = (const struct clk_hw *[]){
3028                                 &nss_ppe_clk_src.clkr.hw },
3029                         .num_parents = 1,
3030                         .flags = CLK_SET_RATE_PARENT,
3031                         .ops = &clk_branch2_ops,
3032                 },
3033         },
3034 };
3035
3036 static struct clk_branch gcc_nss_ppe_cfg_clk = {
3037         .halt_reg = 0x68194,
3038         .clkr = {
3039                 .enable_reg = 0x68194,
3040                 .enable_mask = BIT(0),
3041                 .hw.init = &(struct clk_init_data){
3042                         .name = "gcc_nss_ppe_cfg_clk",
3043                         .parent_hws = (const struct clk_hw *[]){
3044                                 &nss_ppe_clk_src.clkr.hw },
3045                         .num_parents = 1,
3046                         .flags = CLK_SET_RATE_PARENT,
3047                         .ops = &clk_branch2_ops,
3048                 },
3049         },
3050 };
3051
3052 static struct clk_branch gcc_nss_ppe_clk = {
3053         .halt_reg = 0x68190,
3054         .clkr = {
3055                 .enable_reg = 0x68190,
3056                 .enable_mask = BIT(0),
3057                 .hw.init = &(struct clk_init_data){
3058                         .name = "gcc_nss_ppe_clk",
3059                         .parent_hws = (const struct clk_hw *[]){
3060                                 &nss_ppe_clk_src.clkr.hw },
3061                         .num_parents = 1,
3062                         .flags = CLK_SET_RATE_PARENT,
3063                         .ops = &clk_branch2_ops,
3064                 },
3065         },
3066 };
3067
3068 static struct clk_branch gcc_nss_ppe_ipe_clk = {
3069         .halt_reg = 0x68338,
3070         .clkr = {
3071                 .enable_reg = 0x68338,
3072                 .enable_mask = BIT(0),
3073                 .hw.init = &(struct clk_init_data){
3074                         .name = "gcc_nss_ppe_ipe_clk",
3075                         .parent_hws = (const struct clk_hw *[]){
3076                                 &nss_ppe_clk_src.clkr.hw },
3077                         .num_parents = 1,
3078                         .flags = CLK_SET_RATE_PARENT,
3079                         .ops = &clk_branch2_ops,
3080                 },
3081         },
3082 };
3083
3084 static struct clk_branch gcc_nss_ptp_ref_clk = {
3085         .halt_reg = 0x6816c,
3086         .clkr = {
3087                 .enable_reg = 0x6816c,
3088                 .enable_mask = BIT(0),
3089                 .hw.init = &(struct clk_init_data){
3090                         .name = "gcc_nss_ptp_ref_clk",
3091                         .parent_hws = (const struct clk_hw *[]){
3092                                 &nss_ppe_cdiv_clk_src.hw },
3093                         .num_parents = 1,
3094                         .flags = CLK_SET_RATE_PARENT,
3095                         .ops = &clk_branch2_ops,
3096                 },
3097         },
3098 };
3099
3100 static struct clk_branch gcc_crypto_ppe_clk = {
3101         .halt_reg = 0x68310,
3102         .halt_bit = 31,
3103         .clkr = {
3104                 .enable_reg = 0x68310,
3105                 .enable_mask = BIT(0),
3106                 .hw.init = &(struct clk_init_data){
3107                         .name = "gcc_crypto_ppe_clk",
3108                         .parent_hws = (const struct clk_hw *[]){
3109                                 &nss_ppe_clk_src.clkr.hw },
3110                         .num_parents = 1,
3111                         .flags = CLK_SET_RATE_PARENT,
3112                         .ops = &clk_branch2_ops,
3113                 },
3114         },
3115 };
3116
3117 static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3118         .halt_reg = 0x6830c,
3119         .clkr = {
3120                 .enable_reg = 0x6830c,
3121                 .enable_mask = BIT(0),
3122                 .hw.init = &(struct clk_init_data){
3123                         .name = "gcc_nssnoc_ce_apb_clk",
3124                         .parent_hws = (const struct clk_hw *[]){
3125                                 &nss_ce_clk_src.clkr.hw },
3126                         .num_parents = 1,
3127                         .flags = CLK_SET_RATE_PARENT,
3128                         .ops = &clk_branch2_ops,
3129                 },
3130         },
3131 };
3132
3133 static struct clk_branch gcc_nssnoc_ce_axi_clk = {
3134         .halt_reg = 0x68308,
3135         .clkr = {
3136                 .enable_reg = 0x68308,
3137                 .enable_mask = BIT(0),
3138                 .hw.init = &(struct clk_init_data){
3139                         .name = "gcc_nssnoc_ce_axi_clk",
3140                         .parent_hws = (const struct clk_hw *[]){
3141                                 &nss_ce_clk_src.clkr.hw },
3142                         .num_parents = 1,
3143                         .flags = CLK_SET_RATE_PARENT,
3144                         .ops = &clk_branch2_ops,
3145                 },
3146         },
3147 };
3148
3149 static struct clk_branch gcc_nssnoc_crypto_clk = {
3150         .halt_reg = 0x68314,
3151         .clkr = {
3152                 .enable_reg = 0x68314,
3153                 .enable_mask = BIT(0),
3154                 .hw.init = &(struct clk_init_data){
3155                         .name = "gcc_nssnoc_crypto_clk",
3156                         .parent_hws = (const struct clk_hw *[]){
3157                                 &nss_crypto_clk_src.clkr.hw },
3158                         .num_parents = 1,
3159                         .flags = CLK_SET_RATE_PARENT,
3160                         .ops = &clk_branch2_ops,
3161                 },
3162         },
3163 };
3164
3165 static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
3166         .halt_reg = 0x68304,
3167         .clkr = {
3168                 .enable_reg = 0x68304,
3169                 .enable_mask = BIT(0),
3170                 .hw.init = &(struct clk_init_data){
3171                         .name = "gcc_nssnoc_ppe_cfg_clk",
3172                         .parent_hws = (const struct clk_hw *[]){
3173                                 &nss_ppe_clk_src.clkr.hw },
3174                         .num_parents = 1,
3175                         .flags = CLK_SET_RATE_PARENT,
3176                         .ops = &clk_branch2_ops,
3177                 },
3178         },
3179 };
3180
3181 static struct clk_branch gcc_nssnoc_ppe_clk = {
3182         .halt_reg = 0x68300,
3183         .clkr = {
3184                 .enable_reg = 0x68300,
3185                 .enable_mask = BIT(0),
3186                 .hw.init = &(struct clk_init_data){
3187                         .name = "gcc_nssnoc_ppe_clk",
3188                         .parent_hws = (const struct clk_hw *[]){
3189                                 &nss_ppe_clk_src.clkr.hw },
3190                         .num_parents = 1,
3191                         .flags = CLK_SET_RATE_PARENT,
3192                         .ops = &clk_branch2_ops,
3193                 },
3194         },
3195 };
3196
3197 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3198         .halt_reg = 0x68180,
3199         .clkr = {
3200                 .enable_reg = 0x68180,
3201                 .enable_mask = BIT(0),
3202                 .hw.init = &(struct clk_init_data){
3203                         .name = "gcc_nssnoc_qosgen_ref_clk",
3204                         .parent_hws = (const struct clk_hw *[]){
3205                                 &gcc_xo_clk_src.clkr.hw },
3206                         .num_parents = 1,
3207                         .flags = CLK_SET_RATE_PARENT,
3208                         .ops = &clk_branch2_ops,
3209                 },
3210         },
3211 };
3212
3213 static struct clk_branch gcc_nssnoc_snoc_clk = {
3214         .halt_reg = 0x68188,
3215         .clkr = {
3216                 .enable_reg = 0x68188,
3217                 .enable_mask = BIT(0),
3218                 .hw.init = &(struct clk_init_data){
3219                         .name = "gcc_nssnoc_snoc_clk",
3220                         .parent_hws = (const struct clk_hw *[]){
3221                                 &system_noc_clk_src.hw },
3222                         .num_parents = 1,
3223                         .flags = CLK_SET_RATE_PARENT,
3224                         .ops = &clk_branch2_ops,
3225                 },
3226         },
3227 };
3228
3229 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3230         .halt_reg = 0x68184,
3231         .clkr = {
3232                 .enable_reg = 0x68184,
3233                 .enable_mask = BIT(0),
3234                 .hw.init = &(struct clk_init_data){
3235                         .name = "gcc_nssnoc_timeout_ref_clk",
3236                         .parent_hws = (const struct clk_hw *[]){
3237                                 &gcc_xo_div4_clk_src.hw },
3238                         .num_parents = 1,
3239                         .flags = CLK_SET_RATE_PARENT,
3240                         .ops = &clk_branch2_ops,
3241                 },
3242         },
3243 };
3244
3245 static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
3246         .halt_reg = 0x68270,
3247         .clkr = {
3248                 .enable_reg = 0x68270,
3249                 .enable_mask = BIT(0),
3250                 .hw.init = &(struct clk_init_data){
3251                         .name = "gcc_nssnoc_ubi0_ahb_clk",
3252                         .parent_hws = (const struct clk_hw *[]){
3253                                 &nss_ce_clk_src.clkr.hw },
3254                         .num_parents = 1,
3255                         .flags = CLK_SET_RATE_PARENT,
3256                         .ops = &clk_branch2_ops,
3257                 },
3258         },
3259 };
3260
3261 static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
3262         .halt_reg = 0x68274,
3263         .clkr = {
3264                 .enable_reg = 0x68274,
3265                 .enable_mask = BIT(0),
3266                 .hw.init = &(struct clk_init_data){
3267                         .name = "gcc_nssnoc_ubi1_ahb_clk",
3268                         .parent_hws = (const struct clk_hw *[]){
3269                                 &nss_ce_clk_src.clkr.hw },
3270                         .num_parents = 1,
3271                         .flags = CLK_SET_RATE_PARENT,
3272                         .ops = &clk_branch2_ops,
3273                 },
3274         },
3275 };
3276
3277 static struct clk_branch gcc_ubi0_ahb_clk = {
3278         .halt_reg = 0x6820c,
3279         .halt_check = BRANCH_HALT_DELAY,
3280         .clkr = {
3281                 .enable_reg = 0x6820c,
3282                 .enable_mask = BIT(0),
3283                 .hw.init = &(struct clk_init_data){
3284                         .name = "gcc_ubi0_ahb_clk",
3285                         .parent_hws = (const struct clk_hw *[]){
3286                                 &nss_ce_clk_src.clkr.hw },
3287                         .num_parents = 1,
3288                         .flags = CLK_SET_RATE_PARENT,
3289                         .ops = &clk_branch2_ops,
3290                 },
3291         },
3292 };
3293
3294 static struct clk_branch gcc_ubi0_axi_clk = {
3295         .halt_reg = 0x68200,
3296         .halt_check = BRANCH_HALT_DELAY,
3297         .clkr = {
3298                 .enable_reg = 0x68200,
3299                 .enable_mask = BIT(0),
3300                 .hw.init = &(struct clk_init_data){
3301                         .name = "gcc_ubi0_axi_clk",
3302                         .parent_hws = (const struct clk_hw *[]){
3303                                 &nss_noc_clk_src.hw },
3304                         .num_parents = 1,
3305                         .flags = CLK_SET_RATE_PARENT,
3306                         .ops = &clk_branch2_ops,
3307                 },
3308         },
3309 };
3310
3311 static struct clk_branch gcc_ubi0_nc_axi_clk = {
3312         .halt_reg = 0x68204,
3313         .halt_check = BRANCH_HALT_DELAY,
3314         .clkr = {
3315                 .enable_reg = 0x68204,
3316                 .enable_mask = BIT(0),
3317                 .hw.init = &(struct clk_init_data){
3318                         .name = "gcc_ubi0_nc_axi_clk",
3319                         .parent_hws = (const struct clk_hw *[]){
3320                                 &nss_noc_clk_src.hw },
3321                         .num_parents = 1,
3322                         .flags = CLK_SET_RATE_PARENT,
3323                         .ops = &clk_branch2_ops,
3324                 },
3325         },
3326 };
3327
3328 static struct clk_branch gcc_ubi0_core_clk = {
3329         .halt_reg = 0x68210,
3330         .halt_check = BRANCH_HALT_DELAY,
3331         .clkr = {
3332                 .enable_reg = 0x68210,
3333                 .enable_mask = BIT(0),
3334                 .hw.init = &(struct clk_init_data){
3335                         .name = "gcc_ubi0_core_clk",
3336                         .parent_hws = (const struct clk_hw *[]){
3337                                 &nss_ubi0_div_clk_src.clkr.hw },
3338                         .num_parents = 1,
3339                         .flags = CLK_SET_RATE_PARENT,
3340                         .ops = &clk_branch2_ops,
3341                 },
3342         },
3343 };
3344
3345 static struct clk_branch gcc_ubi0_mpt_clk = {
3346         .halt_reg = 0x68208,
3347         .halt_check = BRANCH_HALT_DELAY,
3348         .clkr = {
3349                 .enable_reg = 0x68208,
3350                 .enable_mask = BIT(0),
3351                 .hw.init = &(struct clk_init_data){
3352                         .name = "gcc_ubi0_mpt_clk",
3353                         .parent_hws = (const struct clk_hw *[]){
3354                                 &ubi_mpt_clk_src.clkr.hw },
3355                         .num_parents = 1,
3356                         .flags = CLK_SET_RATE_PARENT,
3357                         .ops = &clk_branch2_ops,
3358                 },
3359         },
3360 };
3361
3362 static struct clk_branch gcc_ubi1_ahb_clk = {
3363         .halt_reg = 0x6822c,
3364         .halt_check = BRANCH_HALT_DELAY,
3365         .clkr = {
3366                 .enable_reg = 0x6822c,
3367                 .enable_mask = BIT(0),
3368                 .hw.init = &(struct clk_init_data){
3369                         .name = "gcc_ubi1_ahb_clk",
3370                         .parent_hws = (const struct clk_hw *[]){
3371                                 &nss_ce_clk_src.clkr.hw },
3372                         .num_parents = 1,
3373                         .flags = CLK_SET_RATE_PARENT,
3374                         .ops = &clk_branch2_ops,
3375                 },
3376         },
3377 };
3378
3379 static struct clk_branch gcc_ubi1_axi_clk = {
3380         .halt_reg = 0x68220,
3381         .halt_check = BRANCH_HALT_DELAY,
3382         .clkr = {
3383                 .enable_reg = 0x68220,
3384                 .enable_mask = BIT(0),
3385                 .hw.init = &(struct clk_init_data){
3386                         .name = "gcc_ubi1_axi_clk",
3387                         .parent_hws = (const struct clk_hw *[]){
3388                                 &nss_noc_clk_src.hw },
3389                         .num_parents = 1,
3390                         .flags = CLK_SET_RATE_PARENT,
3391                         .ops = &clk_branch2_ops,
3392                 },
3393         },
3394 };
3395
3396 static struct clk_branch gcc_ubi1_nc_axi_clk = {
3397         .halt_reg = 0x68224,
3398         .halt_check = BRANCH_HALT_DELAY,
3399         .clkr = {
3400                 .enable_reg = 0x68224,
3401                 .enable_mask = BIT(0),
3402                 .hw.init = &(struct clk_init_data){
3403                         .name = "gcc_ubi1_nc_axi_clk",
3404                         .parent_hws = (const struct clk_hw *[]){
3405                                 &nss_noc_clk_src.hw },
3406                         .num_parents = 1,
3407                         .flags = CLK_SET_RATE_PARENT,
3408                         .ops = &clk_branch2_ops,
3409                 },
3410         },
3411 };
3412
3413 static struct clk_branch gcc_ubi1_core_clk = {
3414         .halt_reg = 0x68230,
3415         .halt_check = BRANCH_HALT_DELAY,
3416         .clkr = {
3417                 .enable_reg = 0x68230,
3418                 .enable_mask = BIT(0),
3419                 .hw.init = &(struct clk_init_data){
3420                         .name = "gcc_ubi1_core_clk",
3421                         .parent_hws = (const struct clk_hw *[]){
3422                                 &nss_ubi1_div_clk_src.clkr.hw },
3423                         .num_parents = 1,
3424                         .flags = CLK_SET_RATE_PARENT,
3425                         .ops = &clk_branch2_ops,
3426                 },
3427         },
3428 };
3429
3430 static struct clk_branch gcc_ubi1_mpt_clk = {
3431         .halt_reg = 0x68228,
3432         .halt_check = BRANCH_HALT_DELAY,
3433         .clkr = {
3434                 .enable_reg = 0x68228,
3435                 .enable_mask = BIT(0),
3436                 .hw.init = &(struct clk_init_data){
3437                         .name = "gcc_ubi1_mpt_clk",
3438                         .parent_hws = (const struct clk_hw *[]){
3439                                 &ubi_mpt_clk_src.clkr.hw },
3440                         .num_parents = 1,
3441                         .flags = CLK_SET_RATE_PARENT,
3442                         .ops = &clk_branch2_ops,
3443                 },
3444         },
3445 };
3446
3447 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
3448         .halt_reg = 0x56308,
3449         .clkr = {
3450                 .enable_reg = 0x56308,
3451                 .enable_mask = BIT(0),
3452                 .hw.init = &(struct clk_init_data){
3453                         .name = "gcc_cmn_12gpll_ahb_clk",
3454                         .parent_hws = (const struct clk_hw *[]){
3455                                 &pcnoc_clk_src.hw },
3456                         .num_parents = 1,
3457                         .flags = CLK_SET_RATE_PARENT,
3458                         .ops = &clk_branch2_ops,
3459                 },
3460         },
3461 };
3462
3463 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
3464         .halt_reg = 0x5630c,
3465         .clkr = {
3466                 .enable_reg = 0x5630c,
3467                 .enable_mask = BIT(0),
3468                 .hw.init = &(struct clk_init_data){
3469                         .name = "gcc_cmn_12gpll_sys_clk",
3470                         .parent_hws = (const struct clk_hw *[]){
3471                                 &gcc_xo_clk_src.clkr.hw },
3472                         .num_parents = 1,
3473                         .flags = CLK_SET_RATE_PARENT,
3474                         .ops = &clk_branch2_ops,
3475                 },
3476         },
3477 };
3478
3479 static struct clk_branch gcc_mdio_ahb_clk = {
3480         .halt_reg = 0x58004,
3481         .clkr = {
3482                 .enable_reg = 0x58004,
3483                 .enable_mask = BIT(0),
3484                 .hw.init = &(struct clk_init_data){
3485                         .name = "gcc_mdio_ahb_clk",
3486                         .parent_hws = (const struct clk_hw *[]){
3487                                 &pcnoc_clk_src.hw },
3488                         .num_parents = 1,
3489                         .flags = CLK_SET_RATE_PARENT,
3490                         .ops = &clk_branch2_ops,
3491                 },
3492         },
3493 };
3494
3495 static struct clk_branch gcc_uniphy0_ahb_clk = {
3496         .halt_reg = 0x56008,
3497         .clkr = {
3498                 .enable_reg = 0x56008,
3499                 .enable_mask = BIT(0),
3500                 .hw.init = &(struct clk_init_data){
3501                         .name = "gcc_uniphy0_ahb_clk",
3502                         .parent_hws = (const struct clk_hw *[]){
3503                                 &pcnoc_clk_src.hw },
3504                         .num_parents = 1,
3505                         .flags = CLK_SET_RATE_PARENT,
3506                         .ops = &clk_branch2_ops,
3507                 },
3508         },
3509 };
3510
3511 static struct clk_branch gcc_uniphy0_sys_clk = {
3512         .halt_reg = 0x5600c,
3513         .clkr = {
3514                 .enable_reg = 0x5600c,
3515                 .enable_mask = BIT(0),
3516                 .hw.init = &(struct clk_init_data){
3517                         .name = "gcc_uniphy0_sys_clk",
3518                         .parent_hws = (const struct clk_hw *[]){
3519                                 &gcc_xo_clk_src.clkr.hw },
3520                         .num_parents = 1,
3521                         .flags = CLK_SET_RATE_PARENT,
3522                         .ops = &clk_branch2_ops,
3523                 },
3524         },
3525 };
3526
3527 static struct clk_branch gcc_uniphy1_ahb_clk = {
3528         .halt_reg = 0x56108,
3529         .clkr = {
3530                 .enable_reg = 0x56108,
3531                 .enable_mask = BIT(0),
3532                 .hw.init = &(struct clk_init_data){
3533                         .name = "gcc_uniphy1_ahb_clk",
3534                         .parent_hws = (const struct clk_hw *[]){
3535                                 &pcnoc_clk_src.hw },
3536                         .num_parents = 1,
3537                         .flags = CLK_SET_RATE_PARENT,
3538                         .ops = &clk_branch2_ops,
3539                 },
3540         },
3541 };
3542
3543 static struct clk_branch gcc_uniphy1_sys_clk = {
3544         .halt_reg = 0x5610c,
3545         .clkr = {
3546                 .enable_reg = 0x5610c,
3547                 .enable_mask = BIT(0),
3548                 .hw.init = &(struct clk_init_data){
3549                         .name = "gcc_uniphy1_sys_clk",
3550                         .parent_hws = (const struct clk_hw *[]){
3551                                 &gcc_xo_clk_src.clkr.hw },
3552                         .num_parents = 1,
3553                         .flags = CLK_SET_RATE_PARENT,
3554                         .ops = &clk_branch2_ops,
3555                 },
3556         },
3557 };
3558
3559 static struct clk_branch gcc_uniphy2_ahb_clk = {
3560         .halt_reg = 0x56208,
3561         .clkr = {
3562                 .enable_reg = 0x56208,
3563                 .enable_mask = BIT(0),
3564                 .hw.init = &(struct clk_init_data){
3565                         .name = "gcc_uniphy2_ahb_clk",
3566                         .parent_hws = (const struct clk_hw *[]){
3567                                 &pcnoc_clk_src.hw },
3568                         .num_parents = 1,
3569                         .flags = CLK_SET_RATE_PARENT,
3570                         .ops = &clk_branch2_ops,
3571                 },
3572         },
3573 };
3574
3575 static struct clk_branch gcc_uniphy2_sys_clk = {
3576         .halt_reg = 0x5620c,
3577         .clkr = {
3578                 .enable_reg = 0x5620c,
3579                 .enable_mask = BIT(0),
3580                 .hw.init = &(struct clk_init_data){
3581                         .name = "gcc_uniphy2_sys_clk",
3582                         .parent_hws = (const struct clk_hw *[]){
3583                                 &gcc_xo_clk_src.clkr.hw },
3584                         .num_parents = 1,
3585                         .flags = CLK_SET_RATE_PARENT,
3586                         .ops = &clk_branch2_ops,
3587                 },
3588         },
3589 };
3590
3591 static struct clk_branch gcc_nss_port1_rx_clk = {
3592         .halt_reg = 0x68240,
3593         .clkr = {
3594                 .enable_reg = 0x68240,
3595                 .enable_mask = BIT(0),
3596                 .hw.init = &(struct clk_init_data){
3597                         .name = "gcc_nss_port1_rx_clk",
3598                         .parent_hws = (const struct clk_hw *[]){
3599                                 &nss_port1_rx_div_clk_src.clkr.hw },
3600                         .num_parents = 1,
3601                         .flags = CLK_SET_RATE_PARENT,
3602                         .ops = &clk_branch2_ops,
3603                 },
3604         },
3605 };
3606
3607 static struct clk_branch gcc_nss_port1_tx_clk = {
3608         .halt_reg = 0x68244,
3609         .clkr = {
3610                 .enable_reg = 0x68244,
3611                 .enable_mask = BIT(0),
3612                 .hw.init = &(struct clk_init_data){
3613                         .name = "gcc_nss_port1_tx_clk",
3614                         .parent_hws = (const struct clk_hw *[]){
3615                                 &nss_port1_tx_div_clk_src.clkr.hw },
3616                         .num_parents = 1,
3617                         .flags = CLK_SET_RATE_PARENT,
3618                         .ops = &clk_branch2_ops,
3619                 },
3620         },
3621 };
3622
3623 static struct clk_branch gcc_nss_port2_rx_clk = {
3624         .halt_reg = 0x68248,
3625         .clkr = {
3626                 .enable_reg = 0x68248,
3627                 .enable_mask = BIT(0),
3628                 .hw.init = &(struct clk_init_data){
3629                         .name = "gcc_nss_port2_rx_clk",
3630                         .parent_hws = (const struct clk_hw *[]){
3631                                 &nss_port2_rx_div_clk_src.clkr.hw },
3632                         .num_parents = 1,
3633                         .flags = CLK_SET_RATE_PARENT,
3634                         .ops = &clk_branch2_ops,
3635                 },
3636         },
3637 };
3638
3639 static struct clk_branch gcc_nss_port2_tx_clk = {
3640         .halt_reg = 0x6824c,
3641         .clkr = {
3642                 .enable_reg = 0x6824c,
3643                 .enable_mask = BIT(0),
3644                 .hw.init = &(struct clk_init_data){
3645                         .name = "gcc_nss_port2_tx_clk",
3646                         .parent_hws = (const struct clk_hw *[]){
3647                                 &nss_port2_tx_div_clk_src.clkr.hw },
3648                         .num_parents = 1,
3649                         .flags = CLK_SET_RATE_PARENT,
3650                         .ops = &clk_branch2_ops,
3651                 },
3652         },
3653 };
3654
3655 static struct clk_branch gcc_nss_port3_rx_clk = {
3656         .halt_reg = 0x68250,
3657         .clkr = {
3658                 .enable_reg = 0x68250,
3659                 .enable_mask = BIT(0),
3660                 .hw.init = &(struct clk_init_data){
3661                         .name = "gcc_nss_port3_rx_clk",
3662                         .parent_hws = (const struct clk_hw *[]){
3663                                 &nss_port3_rx_div_clk_src.clkr.hw },
3664                         .num_parents = 1,
3665                         .flags = CLK_SET_RATE_PARENT,
3666                         .ops = &clk_branch2_ops,
3667                 },
3668         },
3669 };
3670
3671 static struct clk_branch gcc_nss_port3_tx_clk = {
3672         .halt_reg = 0x68254,
3673         .clkr = {
3674                 .enable_reg = 0x68254,
3675                 .enable_mask = BIT(0),
3676                 .hw.init = &(struct clk_init_data){
3677                         .name = "gcc_nss_port3_tx_clk",
3678                         .parent_hws = (const struct clk_hw *[]){
3679                                 &nss_port3_tx_div_clk_src.clkr.hw },
3680                         .num_parents = 1,
3681                         .flags = CLK_SET_RATE_PARENT,
3682                         .ops = &clk_branch2_ops,
3683                 },
3684         },
3685 };
3686
3687 static struct clk_branch gcc_nss_port4_rx_clk = {
3688         .halt_reg = 0x68258,
3689         .clkr = {
3690                 .enable_reg = 0x68258,
3691                 .enable_mask = BIT(0),
3692                 .hw.init = &(struct clk_init_data){
3693                         .name = "gcc_nss_port4_rx_clk",
3694                         .parent_hws = (const struct clk_hw *[]){
3695                                 &nss_port4_rx_div_clk_src.clkr.hw },
3696                         .num_parents = 1,
3697                         .flags = CLK_SET_RATE_PARENT,
3698                         .ops = &clk_branch2_ops,
3699                 },
3700         },
3701 };
3702
3703 static struct clk_branch gcc_nss_port4_tx_clk = {
3704         .halt_reg = 0x6825c,
3705         .clkr = {
3706                 .enable_reg = 0x6825c,
3707                 .enable_mask = BIT(0),
3708                 .hw.init = &(struct clk_init_data){
3709                         .name = "gcc_nss_port4_tx_clk",
3710                         .parent_hws = (const struct clk_hw *[]){
3711                                 &nss_port4_tx_div_clk_src.clkr.hw },
3712                         .num_parents = 1,
3713                         .flags = CLK_SET_RATE_PARENT,
3714                         .ops = &clk_branch2_ops,
3715                 },
3716         },
3717 };
3718
3719 static struct clk_branch gcc_nss_port5_rx_clk = {
3720         .halt_reg = 0x68260,
3721         .clkr = {
3722                 .enable_reg = 0x68260,
3723                 .enable_mask = BIT(0),
3724                 .hw.init = &(struct clk_init_data){
3725                         .name = "gcc_nss_port5_rx_clk",
3726                         .parent_hws = (const struct clk_hw *[]){
3727                                 &nss_port5_rx_div_clk_src.clkr.hw },
3728                         .num_parents = 1,
3729                         .flags = CLK_SET_RATE_PARENT,
3730                         .ops = &clk_branch2_ops,
3731                 },
3732         },
3733 };
3734
3735 static struct clk_branch gcc_nss_port5_tx_clk = {
3736         .halt_reg = 0x68264,
3737         .clkr = {
3738                 .enable_reg = 0x68264,
3739                 .enable_mask = BIT(0),
3740                 .hw.init = &(struct clk_init_data){
3741                         .name = "gcc_nss_port5_tx_clk",
3742                         .parent_hws = (const struct clk_hw *[]){
3743                                 &nss_port5_tx_div_clk_src.clkr.hw },
3744                         .num_parents = 1,
3745                         .flags = CLK_SET_RATE_PARENT,
3746                         .ops = &clk_branch2_ops,
3747                 },
3748         },
3749 };
3750
3751 static struct clk_branch gcc_nss_port6_rx_clk = {
3752         .halt_reg = 0x68268,
3753         .clkr = {
3754                 .enable_reg = 0x68268,
3755                 .enable_mask = BIT(0),
3756                 .hw.init = &(struct clk_init_data){
3757                         .name = "gcc_nss_port6_rx_clk",
3758                         .parent_hws = (const struct clk_hw *[]){
3759                                 &nss_port6_rx_div_clk_src.clkr.hw },
3760                         .num_parents = 1,
3761                         .flags = CLK_SET_RATE_PARENT,
3762                         .ops = &clk_branch2_ops,
3763                 },
3764         },
3765 };
3766
3767 static struct clk_branch gcc_nss_port6_tx_clk = {
3768         .halt_reg = 0x6826c,
3769         .clkr = {
3770                 .enable_reg = 0x6826c,
3771                 .enable_mask = BIT(0),
3772                 .hw.init = &(struct clk_init_data){
3773                         .name = "gcc_nss_port6_tx_clk",
3774                         .parent_hws = (const struct clk_hw *[]){
3775                                 &nss_port6_tx_div_clk_src.clkr.hw },
3776                         .num_parents = 1,
3777                         .flags = CLK_SET_RATE_PARENT,
3778                         .ops = &clk_branch2_ops,
3779                 },
3780         },
3781 };
3782
3783 static struct clk_branch gcc_port1_mac_clk = {
3784         .halt_reg = 0x68320,
3785         .clkr = {
3786                 .enable_reg = 0x68320,
3787                 .enable_mask = BIT(0),
3788                 .hw.init = &(struct clk_init_data){
3789                         .name = "gcc_port1_mac_clk",
3790                         .parent_hws = (const struct clk_hw *[]){
3791                                 &nss_ppe_clk_src.clkr.hw },
3792                         .num_parents = 1,
3793                         .flags = CLK_SET_RATE_PARENT,
3794                         .ops = &clk_branch2_ops,
3795                 },
3796         },
3797 };
3798
3799 static struct clk_branch gcc_port2_mac_clk = {
3800         .halt_reg = 0x68324,
3801         .clkr = {
3802                 .enable_reg = 0x68324,
3803                 .enable_mask = BIT(0),
3804                 .hw.init = &(struct clk_init_data){
3805                         .name = "gcc_port2_mac_clk",
3806                         .parent_hws = (const struct clk_hw *[]){
3807                                 &nss_ppe_clk_src.clkr.hw },
3808                         .num_parents = 1,
3809                         .flags = CLK_SET_RATE_PARENT,
3810                         .ops = &clk_branch2_ops,
3811                 },
3812         },
3813 };
3814
3815 static struct clk_branch gcc_port3_mac_clk = {
3816         .halt_reg = 0x68328,
3817         .clkr = {
3818                 .enable_reg = 0x68328,
3819                 .enable_mask = BIT(0),
3820                 .hw.init = &(struct clk_init_data){
3821                         .name = "gcc_port3_mac_clk",
3822                         .parent_hws = (const struct clk_hw *[]){
3823                                 &nss_ppe_clk_src.clkr.hw },
3824                         .num_parents = 1,
3825                         .flags = CLK_SET_RATE_PARENT,
3826                         .ops = &clk_branch2_ops,
3827                 },
3828         },
3829 };
3830
3831 static struct clk_branch gcc_port4_mac_clk = {
3832         .halt_reg = 0x6832c,
3833         .clkr = {
3834                 .enable_reg = 0x6832c,
3835                 .enable_mask = BIT(0),
3836                 .hw.init = &(struct clk_init_data){
3837                         .name = "gcc_port4_mac_clk",
3838                         .parent_hws = (const struct clk_hw *[]){
3839                                 &nss_ppe_clk_src.clkr.hw },
3840                         .num_parents = 1,
3841                         .flags = CLK_SET_RATE_PARENT,
3842                         .ops = &clk_branch2_ops,
3843                 },
3844         },
3845 };
3846
3847 static struct clk_branch gcc_port5_mac_clk = {
3848         .halt_reg = 0x68330,
3849         .clkr = {
3850                 .enable_reg = 0x68330,
3851                 .enable_mask = BIT(0),
3852                 .hw.init = &(struct clk_init_data){
3853                         .name = "gcc_port5_mac_clk",
3854                         .parent_hws = (const struct clk_hw *[]){
3855                                 &nss_ppe_clk_src.clkr.hw },
3856                         .num_parents = 1,
3857                         .flags = CLK_SET_RATE_PARENT,
3858                         .ops = &clk_branch2_ops,
3859                 },
3860         },
3861 };
3862
3863 static struct clk_branch gcc_port6_mac_clk = {
3864         .halt_reg = 0x68334,
3865         .clkr = {
3866                 .enable_reg = 0x68334,
3867                 .enable_mask = BIT(0),
3868                 .hw.init = &(struct clk_init_data){
3869                         .name = "gcc_port6_mac_clk",
3870                         .parent_hws = (const struct clk_hw *[]){
3871                                 &nss_ppe_clk_src.clkr.hw },
3872                         .num_parents = 1,
3873                         .flags = CLK_SET_RATE_PARENT,
3874                         .ops = &clk_branch2_ops,
3875                 },
3876         },
3877 };
3878
3879 static struct clk_branch gcc_uniphy0_port1_rx_clk = {
3880         .halt_reg = 0x56010,
3881         .clkr = {
3882                 .enable_reg = 0x56010,
3883                 .enable_mask = BIT(0),
3884                 .hw.init = &(struct clk_init_data){
3885                         .name = "gcc_uniphy0_port1_rx_clk",
3886                         .parent_hws = (const struct clk_hw *[]){
3887                                 &nss_port1_rx_div_clk_src.clkr.hw },
3888                         .num_parents = 1,
3889                         .flags = CLK_SET_RATE_PARENT,
3890                         .ops = &clk_branch2_ops,
3891                 },
3892         },
3893 };
3894
3895 static struct clk_branch gcc_uniphy0_port1_tx_clk = {
3896         .halt_reg = 0x56014,
3897         .clkr = {
3898                 .enable_reg = 0x56014,
3899                 .enable_mask = BIT(0),
3900                 .hw.init = &(struct clk_init_data){
3901                         .name = "gcc_uniphy0_port1_tx_clk",
3902                         .parent_hws = (const struct clk_hw *[]){
3903                                 &nss_port1_tx_div_clk_src.clkr.hw },
3904                         .num_parents = 1,
3905                         .flags = CLK_SET_RATE_PARENT,
3906                         .ops = &clk_branch2_ops,
3907                 },
3908         },
3909 };
3910
3911 static struct clk_branch gcc_uniphy0_port2_rx_clk = {
3912         .halt_reg = 0x56018,
3913         .clkr = {
3914                 .enable_reg = 0x56018,
3915                 .enable_mask = BIT(0),
3916                 .hw.init = &(struct clk_init_data){
3917                         .name = "gcc_uniphy0_port2_rx_clk",
3918                         .parent_hws = (const struct clk_hw *[]){
3919                                 &nss_port2_rx_div_clk_src.clkr.hw },
3920                         .num_parents = 1,
3921                         .flags = CLK_SET_RATE_PARENT,
3922                         .ops = &clk_branch2_ops,
3923                 },
3924         },
3925 };
3926
3927 static struct clk_branch gcc_uniphy0_port2_tx_clk = {
3928         .halt_reg = 0x5601c,
3929         .clkr = {
3930                 .enable_reg = 0x5601c,
3931                 .enable_mask = BIT(0),
3932                 .hw.init = &(struct clk_init_data){
3933                         .name = "gcc_uniphy0_port2_tx_clk",
3934                         .parent_hws = (const struct clk_hw *[]){
3935                                 &nss_port2_tx_div_clk_src.clkr.hw },
3936                         .num_parents = 1,
3937                         .flags = CLK_SET_RATE_PARENT,
3938                         .ops = &clk_branch2_ops,
3939                 },
3940         },
3941 };
3942
3943 static struct clk_branch gcc_uniphy0_port3_rx_clk = {
3944         .halt_reg = 0x56020,
3945         .clkr = {
3946                 .enable_reg = 0x56020,
3947                 .enable_mask = BIT(0),
3948                 .hw.init = &(struct clk_init_data){
3949                         .name = "gcc_uniphy0_port3_rx_clk",
3950                         .parent_hws = (const struct clk_hw *[]){
3951                                 &nss_port3_rx_div_clk_src.clkr.hw },
3952                         .num_parents = 1,
3953                         .flags = CLK_SET_RATE_PARENT,
3954                         .ops = &clk_branch2_ops,
3955                 },
3956         },
3957 };
3958
3959 static struct clk_branch gcc_uniphy0_port3_tx_clk = {
3960         .halt_reg = 0x56024,
3961         .clkr = {
3962                 .enable_reg = 0x56024,
3963                 .enable_mask = BIT(0),
3964                 .hw.init = &(struct clk_init_data){
3965                         .name = "gcc_uniphy0_port3_tx_clk",
3966                         .parent_hws = (const struct clk_hw *[]){
3967                                 &nss_port3_tx_div_clk_src.clkr.hw },
3968                         .num_parents = 1,
3969                         .flags = CLK_SET_RATE_PARENT,
3970                         .ops = &clk_branch2_ops,
3971                 },
3972         },
3973 };
3974
3975 static struct clk_branch gcc_uniphy0_port4_rx_clk = {
3976         .halt_reg = 0x56028,
3977         .clkr = {
3978                 .enable_reg = 0x56028,
3979                 .enable_mask = BIT(0),
3980                 .hw.init = &(struct clk_init_data){
3981                         .name = "gcc_uniphy0_port4_rx_clk",
3982                         .parent_hws = (const struct clk_hw *[]){
3983                                 &nss_port4_rx_div_clk_src.clkr.hw },
3984                         .num_parents = 1,
3985                         .flags = CLK_SET_RATE_PARENT,
3986                         .ops = &clk_branch2_ops,
3987                 },
3988         },
3989 };
3990
3991 static struct clk_branch gcc_uniphy0_port4_tx_clk = {
3992         .halt_reg = 0x5602c,
3993         .clkr = {
3994                 .enable_reg = 0x5602c,
3995                 .enable_mask = BIT(0),
3996                 .hw.init = &(struct clk_init_data){
3997                         .name = "gcc_uniphy0_port4_tx_clk",
3998                         .parent_hws = (const struct clk_hw *[]){
3999                                 &nss_port4_tx_div_clk_src.clkr.hw },
4000                         .num_parents = 1,
4001                         .flags = CLK_SET_RATE_PARENT,
4002                         .ops = &clk_branch2_ops,
4003                 },
4004         },
4005 };
4006
4007 static struct clk_branch gcc_uniphy0_port5_rx_clk = {
4008         .halt_reg = 0x56030,
4009         .clkr = {
4010                 .enable_reg = 0x56030,
4011                 .enable_mask = BIT(0),
4012                 .hw.init = &(struct clk_init_data){
4013                         .name = "gcc_uniphy0_port5_rx_clk",
4014                         .parent_hws = (const struct clk_hw *[]){
4015                                 &nss_port5_rx_div_clk_src.clkr.hw },
4016                         .num_parents = 1,
4017                         .flags = CLK_SET_RATE_PARENT,
4018                         .ops = &clk_branch2_ops,
4019                 },
4020         },
4021 };
4022
4023 static struct clk_branch gcc_uniphy0_port5_tx_clk = {
4024         .halt_reg = 0x56034,
4025         .clkr = {
4026                 .enable_reg = 0x56034,
4027                 .enable_mask = BIT(0),
4028                 .hw.init = &(struct clk_init_data){
4029                         .name = "gcc_uniphy0_port5_tx_clk",
4030                         .parent_hws = (const struct clk_hw *[]){
4031                                 &nss_port5_tx_div_clk_src.clkr.hw },
4032                         .num_parents = 1,
4033                         .flags = CLK_SET_RATE_PARENT,
4034                         .ops = &clk_branch2_ops,
4035                 },
4036         },
4037 };
4038
4039 static struct clk_branch gcc_uniphy1_port5_rx_clk = {
4040         .halt_reg = 0x56110,
4041         .clkr = {
4042                 .enable_reg = 0x56110,
4043                 .enable_mask = BIT(0),
4044                 .hw.init = &(struct clk_init_data){
4045                         .name = "gcc_uniphy1_port5_rx_clk",
4046                         .parent_hws = (const struct clk_hw *[]){
4047                                 &nss_port5_rx_div_clk_src.clkr.hw },
4048                         .num_parents = 1,
4049                         .flags = CLK_SET_RATE_PARENT,
4050                         .ops = &clk_branch2_ops,
4051                 },
4052         },
4053 };
4054
4055 static struct clk_branch gcc_uniphy1_port5_tx_clk = {
4056         .halt_reg = 0x56114,
4057         .clkr = {
4058                 .enable_reg = 0x56114,
4059                 .enable_mask = BIT(0),
4060                 .hw.init = &(struct clk_init_data){
4061                         .name = "gcc_uniphy1_port5_tx_clk",
4062                         .parent_hws = (const struct clk_hw *[]){
4063                                 &nss_port5_tx_div_clk_src.clkr.hw },
4064                         .num_parents = 1,
4065                         .flags = CLK_SET_RATE_PARENT,
4066                         .ops = &clk_branch2_ops,
4067                 },
4068         },
4069 };
4070
4071 static struct clk_branch gcc_uniphy2_port6_rx_clk = {
4072         .halt_reg = 0x56210,
4073         .clkr = {
4074                 .enable_reg = 0x56210,
4075                 .enable_mask = BIT(0),
4076                 .hw.init = &(struct clk_init_data){
4077                         .name = "gcc_uniphy2_port6_rx_clk",
4078                         .parent_hws = (const struct clk_hw *[]){
4079                                 &nss_port6_rx_div_clk_src.clkr.hw },
4080                         .num_parents = 1,
4081                         .flags = CLK_SET_RATE_PARENT,
4082                         .ops = &clk_branch2_ops,
4083                 },
4084         },
4085 };
4086
4087 static struct clk_branch gcc_uniphy2_port6_tx_clk = {
4088         .halt_reg = 0x56214,
4089         .clkr = {
4090                 .enable_reg = 0x56214,
4091                 .enable_mask = BIT(0),
4092                 .hw.init = &(struct clk_init_data){
4093                         .name = "gcc_uniphy2_port6_tx_clk",
4094                         .parent_hws = (const struct clk_hw *[]){
4095                                 &nss_port6_tx_div_clk_src.clkr.hw },
4096                         .num_parents = 1,
4097                         .flags = CLK_SET_RATE_PARENT,
4098                         .ops = &clk_branch2_ops,
4099                 },
4100         },
4101 };
4102
4103 static struct clk_branch gcc_crypto_ahb_clk = {
4104         .halt_reg = 0x16024,
4105         .halt_check = BRANCH_HALT_VOTED,
4106         .clkr = {
4107                 .enable_reg = 0x0b004,
4108                 .enable_mask = BIT(0),
4109                 .hw.init = &(struct clk_init_data){
4110                         .name = "gcc_crypto_ahb_clk",
4111                         .parent_hws = (const struct clk_hw *[]){
4112                                 &pcnoc_clk_src.hw },
4113                         .num_parents = 1,
4114                         .flags = CLK_SET_RATE_PARENT,
4115                         .ops = &clk_branch2_ops,
4116                 },
4117         },
4118 };
4119
4120 static struct clk_branch gcc_crypto_axi_clk = {
4121         .halt_reg = 0x16020,
4122         .halt_check = BRANCH_HALT_VOTED,
4123         .clkr = {
4124                 .enable_reg = 0x0b004,
4125                 .enable_mask = BIT(1),
4126                 .hw.init = &(struct clk_init_data){
4127                         .name = "gcc_crypto_axi_clk",
4128                         .parent_hws = (const struct clk_hw *[]){
4129                                 &pcnoc_clk_src.hw },
4130                         .num_parents = 1,
4131                         .flags = CLK_SET_RATE_PARENT,
4132                         .ops = &clk_branch2_ops,
4133                 },
4134         },
4135 };
4136
4137 static struct clk_branch gcc_crypto_clk = {
4138         .halt_reg = 0x1601c,
4139         .halt_check = BRANCH_HALT_VOTED,
4140         .clkr = {
4141                 .enable_reg = 0x0b004,
4142                 .enable_mask = BIT(2),
4143                 .hw.init = &(struct clk_init_data){
4144                         .name = "gcc_crypto_clk",
4145                         .parent_hws = (const struct clk_hw *[]){
4146                                 &crypto_clk_src.clkr.hw },
4147                         .num_parents = 1,
4148                         .flags = CLK_SET_RATE_PARENT,
4149                         .ops = &clk_branch2_ops,
4150                 },
4151         },
4152 };
4153
4154 static struct clk_branch gcc_gp1_clk = {
4155         .halt_reg = 0x08000,
4156         .clkr = {
4157                 .enable_reg = 0x08000,
4158                 .enable_mask = BIT(0),
4159                 .hw.init = &(struct clk_init_data){
4160                         .name = "gcc_gp1_clk",
4161                         .parent_hws = (const struct clk_hw *[]){
4162                                 &gp1_clk_src.clkr.hw },
4163                         .num_parents = 1,
4164                         .flags = CLK_SET_RATE_PARENT,
4165                         .ops = &clk_branch2_ops,
4166                 },
4167         },
4168 };
4169
4170 static struct clk_branch gcc_gp2_clk = {
4171         .halt_reg = 0x09000,
4172         .clkr = {
4173                 .enable_reg = 0x09000,
4174                 .enable_mask = BIT(0),
4175                 .hw.init = &(struct clk_init_data){
4176                         .name = "gcc_gp2_clk",
4177                         .parent_hws = (const struct clk_hw *[]){
4178                                 &gp2_clk_src.clkr.hw },
4179                         .num_parents = 1,
4180                         .flags = CLK_SET_RATE_PARENT,
4181                         .ops = &clk_branch2_ops,
4182                 },
4183         },
4184 };
4185
4186 static struct clk_branch gcc_gp3_clk = {
4187         .halt_reg = 0x0a000,
4188         .clkr = {
4189                 .enable_reg = 0x0a000,
4190                 .enable_mask = BIT(0),
4191                 .hw.init = &(struct clk_init_data){
4192                         .name = "gcc_gp3_clk",
4193                         .parent_hws = (const struct clk_hw *[]){
4194                                 &gp3_clk_src.clkr.hw },
4195                         .num_parents = 1,
4196                         .flags = CLK_SET_RATE_PARENT,
4197                         .ops = &clk_branch2_ops,
4198                 },
4199         },
4200 };
4201
4202 static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
4203         F(19200000, P_XO, 1, 0, 0),
4204         F(100000000, P_GPLL0, 8, 0, 0),
4205         { }
4206 };
4207
4208 static struct clk_rcg2 pcie0_rchng_clk_src = {
4209         .cmd_rcgr = 0x75070,
4210         .freq_tbl = ftbl_pcie_rchng_clk_src,
4211         .hid_width = 5,
4212         .parent_map = gcc_xo_gpll0_map,
4213         .clkr.hw.init = &(struct clk_init_data){
4214                 .name = "pcie0_rchng_clk_src",
4215                 .parent_data = gcc_xo_gpll0,
4216                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
4217                 .ops = &clk_rcg2_ops,
4218         },
4219 };
4220
4221 static struct clk_branch gcc_pcie0_rchng_clk = {
4222         .halt_reg = 0x75070,
4223         .halt_bit = 31,
4224         .clkr = {
4225                 .enable_reg = 0x75070,
4226                 .enable_mask = BIT(1),
4227                 .hw.init = &(struct clk_init_data){
4228                         .name = "gcc_pcie0_rchng_clk",
4229                         .parent_hws = (const struct clk_hw *[]){
4230                                 &pcie0_rchng_clk_src.clkr.hw,
4231                         },
4232                         .num_parents = 1,
4233                         .flags = CLK_SET_RATE_PARENT,
4234                         .ops = &clk_branch2_ops,
4235                 },
4236         },
4237 };
4238
4239 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
4240         .halt_reg = 0x75048,
4241         .halt_bit = 31,
4242         .clkr = {
4243                 .enable_reg = 0x75048,
4244                 .enable_mask = BIT(0),
4245                 .hw.init = &(struct clk_init_data){
4246                         .name = "gcc_pcie0_axi_s_bridge_clk",
4247                         .parent_hws = (const struct clk_hw *[]){
4248                                 &pcie0_axi_clk_src.clkr.hw,
4249                         },
4250                         .num_parents = 1,
4251                         .flags = CLK_SET_RATE_PARENT,
4252                         .ops = &clk_branch2_ops,
4253                 },
4254         },
4255 };
4256
4257 static struct gdsc usb0_gdsc = {
4258         .gdscr = 0x3e078,
4259         .pd = {
4260                 .name = "usb0_gdsc",
4261         },
4262         .pwrsts = PWRSTS_OFF_ON,
4263 };
4264
4265 static struct gdsc usb1_gdsc = {
4266         .gdscr = 0x3f078,
4267         .pd = {
4268                 .name = "usb1_gdsc",
4269         },
4270         .pwrsts = PWRSTS_OFF_ON,
4271 };
4272
4273 static const struct alpha_pll_config ubi32_pll_config = {
4274         .l = 0x4e,
4275         .config_ctl_val = 0x200d4aa8,
4276         .config_ctl_hi_val = 0x3c2,
4277         .main_output_mask = BIT(0),
4278         .aux_output_mask = BIT(1),
4279         .pre_div_val = 0x0,
4280         .pre_div_mask = BIT(12),
4281         .post_div_val = 0x0,
4282         .post_div_mask = GENMASK(9, 8),
4283 };
4284
4285 static const struct alpha_pll_config nss_crypto_pll_config = {
4286         .l = 0x3e,
4287         .alpha = 0x0,
4288         .alpha_hi = 0x80,
4289         .config_ctl_val = 0x4001055b,
4290         .main_output_mask = BIT(0),
4291         .pre_div_val = 0x0,
4292         .pre_div_mask = GENMASK(14, 12),
4293         .post_div_val = 0x1 << 8,
4294         .post_div_mask = GENMASK(11, 8),
4295         .vco_mask = GENMASK(21, 20),
4296         .vco_val = 0x0,
4297         .alpha_en_mask = BIT(24),
4298 };
4299
4300 static struct clk_hw *gcc_ipq8074_hws[] = {
4301         &gpll0_out_main_div2.hw,
4302         &gpll6_out_main_div2.hw,
4303         &pcnoc_clk_src.hw,
4304         &system_noc_clk_src.hw,
4305         &gcc_xo_div4_clk_src.hw,
4306         &nss_noc_clk_src.hw,
4307         &nss_ppe_cdiv_clk_src.hw,
4308 };
4309
4310 static struct clk_regmap *gcc_ipq8074_clks[] = {
4311         [GPLL0_MAIN] = &gpll0_main.clkr,
4312         [GPLL0] = &gpll0.clkr,
4313         [GPLL2_MAIN] = &gpll2_main.clkr,
4314         [GPLL2] = &gpll2.clkr,
4315         [GPLL4_MAIN] = &gpll4_main.clkr,
4316         [GPLL4] = &gpll4.clkr,
4317         [GPLL6_MAIN] = &gpll6_main.clkr,
4318         [GPLL6] = &gpll6.clkr,
4319         [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4320         [UBI32_PLL] = &ubi32_pll.clkr,
4321         [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4322         [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4323         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4324         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4325         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4326         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4327         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4328         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4329         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4330         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4331         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4332         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4333         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4334         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4335         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4336         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4337         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4338         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4339         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4340         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4341         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4342         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4343         [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4344         [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4345         [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4346         [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
4347         [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
4348         [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
4349         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4350         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4351         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
4352         [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4353         [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4354         [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4355         [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4356         [USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
4357         [USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
4358         [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4359         [USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
4360         [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4361         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4362         [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4363         [NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
4364         [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4365         [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4366         [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4367         [NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
4368         [NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
4369         [UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
4370         [NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
4371         [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4372         [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4373         [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4374         [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4375         [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4376         [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4377         [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4378         [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4379         [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4380         [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4381         [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4382         [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4383         [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4384         [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4385         [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4386         [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4387         [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4388         [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4389         [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4390         [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4391         [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4392         [NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
4393         [NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
4394         [NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
4395         [NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
4396         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4397         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
4398         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
4399         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
4400         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4401         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4402         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4403         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4404         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4405         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4406         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4407         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4408         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4409         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4410         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4411         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
4412         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4413         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4414         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4415         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4416         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4417         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4418         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4419         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4420         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4421         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4422         [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4423         [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4424         [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4425         [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4426         [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4427         [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4428         [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
4429         [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
4430         [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
4431         [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
4432         [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
4433         [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
4434         [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4435         [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4436         [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4437         [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4438         [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4439         [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4440         [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4441         [GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
4442         [GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
4443         [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4444         [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4445         [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4446         [GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
4447         [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4448         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4449         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4450         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4451         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4452         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4453         [GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
4454         [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4455         [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4456         [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4457         [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4458         [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4459         [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4460         [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4461         [GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
4462         [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4463         [GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
4464         [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4465         [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4466         [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4467         [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4468         [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4469         [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4470         [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4471         [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4472         [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4473         [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4474         [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4475         [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4476         [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4477         [GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
4478         [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4479         [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4480         [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4481         [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4482         [GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
4483         [GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
4484         [GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
4485         [GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
4486         [GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
4487         [GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
4488         [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4489         [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4490         [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4491         [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4492         [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4493         [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4494         [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4495         [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
4496         [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
4497         [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4498         [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4499         [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4500         [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4501         [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4502         [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4503         [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4504         [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4505         [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4506         [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4507         [GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
4508         [GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
4509         [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4510         [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4511         [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4512         [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4513         [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4514         [GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
4515         [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4516         [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4517         [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4518         [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4519         [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4520         [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4521         [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4522         [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4523         [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4524         [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4525         [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4526         [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4527         [GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
4528         [GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
4529         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4530         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4531         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4532         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4533         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4534         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4535         [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4536         [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4537         [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
4538         [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
4539 };
4540
4541 static const struct qcom_reset_map gcc_ipq8074_resets[] = {
4542         [GCC_BLSP1_BCR] = { 0x01000, 0 },
4543         [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4544         [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4545         [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4546         [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4547         [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4548         [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4549         [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4550         [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4551         [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4552         [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4553         [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4554         [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4555         [GCC_IMEM_BCR] = { 0x0e000, 0 },
4556         [GCC_SMMU_BCR] = { 0x12000, 0 },
4557         [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4558         [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4559         [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4560         [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4561         [GCC_PRNG_BCR] = { 0x13000, 0 },
4562         [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4563         [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4564         [GCC_WCSS_BCR] = { 0x18000, 0 },
4565         [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4566         [GCC_NSS_BCR] = { 0x19000, 0 },
4567         [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4568         [GCC_ADSS_BCR] = { 0x1c000, 0 },
4569         [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4570         [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4571         [GCC_PCNOC_BCR] = { 0x27018, 0 },
4572         [GCC_TCSR_BCR] = { 0x28000, 0 },
4573         [GCC_QDSS_BCR] = { 0x29000, 0 },
4574         [GCC_DCD_BCR] = { 0x2a000, 0 },
4575         [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4576         [GCC_MPM_BCR] = { 0x2c000, 0 },
4577         [GCC_SPMI_BCR] = { 0x2e000, 0 },
4578         [GCC_SPDM_BCR] = { 0x2f000, 0 },
4579         [GCC_RBCPR_BCR] = { 0x33000, 0 },
4580         [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4581         [GCC_TLMM_BCR] = { 0x34000, 0 },
4582         [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4583         [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4584         [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4585         [GCC_USB0_BCR] = { 0x3e070, 0 },
4586         [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
4587         [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
4588         [GCC_USB1_BCR] = { 0x3f070, 0 },
4589         [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4590         [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4591         [GCC_SDCC1_BCR] = { 0x42000, 0 },
4592         [GCC_SDCC2_BCR] = { 0x43000, 0 },
4593         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4594         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
4595         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
4596         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4597         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4598         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4599         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4600         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4601         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4602         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4603         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4604         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4605         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4606         [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4607         [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4608         [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
4609         [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4610         [GCC_QPIC_BCR] = { 0x57018, 0 },
4611         [GCC_MDIO_BCR] = { 0x58000, 0 },
4612         [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
4613         [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4614         [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4615         [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4616         [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
4617         [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4618         [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4619         [GCC_PCIE0_BCR] = { 0x75004, 0 },
4620         [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4621         [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4622         [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4623         [GCC_PCIE1_BCR] = { 0x76004, 0 },
4624         [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
4625         [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
4626         [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
4627         [GCC_DCC_BCR] = { 0x77000, 0 },
4628         [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4629         [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
4630         [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4631         [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4632         [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4633         [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4634         [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4635         [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4636         [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4637         [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
4638         [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
4639         [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
4640         [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
4641         [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
4642         [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
4643         [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4644         [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
4645         [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4646         [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4647         [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4648         [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4649         [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4650         [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4651         [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4652         [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4653         [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
4654         [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4655         [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4656         [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4657         [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4658         [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4659         [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4660         [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4661         [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4662         [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4663         [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4664         [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4665         [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4666         [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4667         [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4668         [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4669         [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
4670         [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
4671         [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
4672         [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
4673         [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4674         [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
4675         [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
4676         [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4677         [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
4678         [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4679         [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
4680         [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
4681         [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
4682         [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
4683         [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
4684         [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
4685         [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
4686         [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
4687         [GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
4688 };
4689
4690 static struct gdsc *gcc_ipq8074_gdscs[] = {
4691         [USB0_GDSC] = &usb0_gdsc,
4692         [USB1_GDSC] = &usb1_gdsc,
4693 };
4694
4695 static const struct of_device_id gcc_ipq8074_match_table[] = {
4696         { .compatible = "qcom,gcc-ipq8074" },
4697         { }
4698 };
4699 MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
4700
4701 static const struct regmap_config gcc_ipq8074_regmap_config = {
4702         .reg_bits       = 32,
4703         .reg_stride     = 4,
4704         .val_bits       = 32,
4705         .max_register   = 0x7fffc,
4706         .fast_io        = true,
4707 };
4708
4709 static const struct qcom_cc_desc gcc_ipq8074_desc = {
4710         .config = &gcc_ipq8074_regmap_config,
4711         .clks = gcc_ipq8074_clks,
4712         .num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
4713         .resets = gcc_ipq8074_resets,
4714         .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
4715         .clk_hws = gcc_ipq8074_hws,
4716         .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
4717         .gdscs = gcc_ipq8074_gdscs,
4718         .num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs),
4719 };
4720
4721 static int gcc_ipq8074_probe(struct platform_device *pdev)
4722 {
4723         struct regmap *regmap;
4724
4725         regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc);
4726         if (IS_ERR(regmap))
4727                 return PTR_ERR(regmap);
4728
4729         /* SW Workaround for UBI32 Huayra PLL */
4730         regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
4731
4732         clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
4733         clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
4734                                 &nss_crypto_pll_config);
4735
4736         return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap);
4737 }
4738
4739 static struct platform_driver gcc_ipq8074_driver = {
4740         .probe = gcc_ipq8074_probe,
4741         .driver = {
4742                 .name   = "qcom,gcc-ipq8074",
4743                 .of_match_table = gcc_ipq8074_match_table,
4744         },
4745 };
4746
4747 static int __init gcc_ipq8074_init(void)
4748 {
4749         return platform_driver_register(&gcc_ipq8074_driver);
4750 }
4751 core_initcall(gcc_ipq8074_init);
4752
4753 static void __exit gcc_ipq8074_exit(void)
4754 {
4755         platform_driver_unregister(&gcc_ipq8074_driver);
4756 }
4757 module_exit(gcc_ipq8074_exit);
4758
4759 MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
4760 MODULE_LICENSE("GPL v2");
4761 MODULE_ALIAS("platform:gcc-ipq8074");