1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
10 #include <linux/export.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/rational.h>
14 #include <linux/regmap.h>
15 #include <linux/math64.h>
16 #include <linux/minmax.h>
17 #include <linux/slab.h>
19 #include <asm/div64.h>
25 #define CMD_UPDATE BIT(0)
26 #define CMD_ROOT_EN BIT(1)
27 #define CMD_DIRTY_CFG BIT(4)
28 #define CMD_DIRTY_N BIT(5)
29 #define CMD_DIRTY_M BIT(6)
30 #define CMD_DIRTY_D BIT(7)
31 #define CMD_ROOT_OFF BIT(31)
34 #define CFG_SRC_DIV_SHIFT 0
35 #define CFG_SRC_SEL_SHIFT 8
36 #define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
37 #define CFG_MODE_SHIFT 12
38 #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
39 #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
40 #define CFG_HW_CLK_CTRL_MASK BIT(20)
46 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG)
47 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG)
48 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG)
49 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)
51 /* Dynamic Frequency Scaling */
52 #define MAX_PERF_LEVEL 8
53 #define SE_CMD_DFSR_OFFSET 0x14
54 #define SE_CMD_DFS_EN BIT(0)
55 #define SE_PERF_DFSR(level) (0x1c + 0x4 * (level))
56 #define SE_PERF_M_DFSR(level) (0x5c + 0x4 * (level))
57 #define SE_PERF_N_DFSR(level) (0x9c + 0x4 * (level))
64 static int clk_rcg2_is_enabled(struct clk_hw *hw)
66 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
70 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
74 return (cmd & CMD_ROOT_OFF) == 0;
77 static u8 __clk_rcg2_get_parent(struct clk_hw *hw, u32 cfg)
79 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
80 int num_parents = clk_hw_get_num_parents(hw);
83 cfg &= CFG_SRC_SEL_MASK;
84 cfg >>= CFG_SRC_SEL_SHIFT;
86 for (i = 0; i < num_parents; i++)
87 if (cfg == rcg->parent_map[i].cfg)
90 pr_debug("%s: Clock %s has invalid parent, using default.\n",
91 __func__, clk_hw_get_name(hw));
95 static u8 clk_rcg2_get_parent(struct clk_hw *hw)
97 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
101 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
103 pr_debug("%s: Unable to read CFG register for %s\n",
104 __func__, clk_hw_get_name(hw));
108 return __clk_rcg2_get_parent(hw, cfg);
111 static int update_config(struct clk_rcg2 *rcg)
115 struct clk_hw *hw = &rcg->clkr.hw;
116 const char *name = clk_hw_get_name(hw);
118 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
119 CMD_UPDATE, CMD_UPDATE);
123 /* Wait for update to take effect */
124 for (count = 500; count > 0; count--) {
125 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
128 if (!(cmd & CMD_UPDATE))
133 WARN(1, "%s: rcg didn't update its configuration.", name);
137 static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
139 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
141 u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
143 ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
144 CFG_SRC_SEL_MASK, cfg);
148 return update_config(rcg);
152 * Calculate m/n:d rate
155 * rate = ----------- x ---
159 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
177 __clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, u32 cfg)
179 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
180 u32 hid_div, m = 0, n = 0, mode = 0, mask;
182 if (rcg->mnd_width) {
183 mask = BIT(rcg->mnd_width) - 1;
184 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
186 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n);
190 mode = cfg & CFG_MODE_MASK;
191 mode >>= CFG_MODE_SHIFT;
194 mask = BIT(rcg->hid_width) - 1;
195 hid_div = cfg >> CFG_SRC_DIV_SHIFT;
198 return calc_rate(parent_rate, m, n, mode, hid_div);
202 clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
204 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
207 regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
209 return __clk_rcg2_recalc_rate(hw, parent_rate, cfg);
212 static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
213 struct clk_rate_request *req,
214 enum freq_policy policy)
216 unsigned long clk_flags, rate = req->rate;
218 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
223 f = qcom_find_freq_floor(f, rate);
226 f = qcom_find_freq(f, rate);
235 index = qcom_find_src_index(hw, rcg->parent_map, f->src);
239 clk_flags = clk_hw_get_flags(hw);
240 p = clk_hw_get_parent_by_index(hw, index);
244 if (clk_flags & CLK_SET_RATE_PARENT) {
250 rate *= f->pre_div + 1;
260 rate = clk_hw_get_rate(p);
262 req->best_parent_hw = p;
263 req->best_parent_rate = rate;
269 static int clk_rcg2_determine_rate(struct clk_hw *hw,
270 struct clk_rate_request *req)
272 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
274 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL);
277 static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
278 struct clk_rate_request *req)
280 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
282 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
285 static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,
288 u32 cfg, mask, d_val, not2d_val, n_minus_m;
289 struct clk_hw *hw = &rcg->clkr.hw;
290 int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
295 if (rcg->mnd_width && f->n) {
296 mask = BIT(rcg->mnd_width) - 1;
297 ret = regmap_update_bits(rcg->clkr.regmap,
298 RCG_M_OFFSET(rcg), mask, f->m);
302 ret = regmap_update_bits(rcg->clkr.regmap,
303 RCG_N_OFFSET(rcg), mask, ~(f->n - f->m));
307 /* Calculate 2d value */
310 n_minus_m = f->n - f->m;
313 d_val = clamp_t(u32, d_val, f->m, n_minus_m);
314 not2d_val = ~d_val & mask;
316 ret = regmap_update_bits(rcg->clkr.regmap,
317 RCG_D_OFFSET(rcg), mask, not2d_val);
322 mask = BIT(rcg->hid_width) - 1;
323 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK;
324 cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
325 cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
326 if (rcg->mnd_width && f->n && (f->m != f->n))
327 cfg |= CFG_MODE_DUAL_EDGE;
335 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
340 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
344 ret = __clk_rcg2_configure(rcg, f, &cfg);
348 ret = regmap_write(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), cfg);
352 return update_config(rcg);
355 static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
356 enum freq_policy policy)
358 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
359 const struct freq_tbl *f;
363 f = qcom_find_freq_floor(rcg->freq_tbl, rate);
366 f = qcom_find_freq(rcg->freq_tbl, rate);
375 return clk_rcg2_configure(rcg, f);
378 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
379 unsigned long parent_rate)
381 return __clk_rcg2_set_rate(hw, rate, CEIL);
384 static int clk_rcg2_set_floor_rate(struct clk_hw *hw, unsigned long rate,
385 unsigned long parent_rate)
387 return __clk_rcg2_set_rate(hw, rate, FLOOR);
390 static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
391 unsigned long rate, unsigned long parent_rate, u8 index)
393 return __clk_rcg2_set_rate(hw, rate, CEIL);
396 static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw,
397 unsigned long rate, unsigned long parent_rate, u8 index)
399 return __clk_rcg2_set_rate(hw, rate, FLOOR);
402 static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
404 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
405 u32 notn_m, n, m, d, not2d, mask;
407 if (!rcg->mnd_width) {
408 /* 50 % duty-cycle for Non-MND RCGs */
414 regmap_read(rcg->clkr.regmap, RCG_D_OFFSET(rcg), ¬2d);
415 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
416 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m);
418 if (!not2d && !m && !notn_m) {
419 /* 50 % duty-cycle always */
425 mask = BIT(rcg->mnd_width) - 1;
428 d = DIV_ROUND_CLOSEST(d, 2);
430 n = (~(notn_m) + m) & mask;
438 static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
440 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
441 u32 notn_m, n, m, d, not2d, mask, duty_per, cfg;
444 /* Duty-cycle cannot be modified for non-MND RCGs */
448 mask = BIT(rcg->mnd_width) - 1;
450 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m);
451 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
452 regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
454 /* Duty-cycle cannot be modified if MND divider is in bypass mode. */
455 if (!(cfg & CFG_MODE_MASK))
458 n = (~(notn_m) + m) & mask;
460 duty_per = (duty->num * 100) / duty->den;
462 /* Calculate 2d value */
463 d = DIV_ROUND_CLOSEST(n * duty_per * 2, 100);
466 * Check bit widths of 2d. If D is too big reduce duty cycle.
467 * Also make sure it is never zero.
469 d = clamp_val(d, 1, mask);
471 if ((d / 2) > (n - m))
473 else if ((d / 2) < (m / 2))
478 ret = regmap_update_bits(rcg->clkr.regmap, RCG_D_OFFSET(rcg), mask,
483 return update_config(rcg);
486 const struct clk_ops clk_rcg2_ops = {
487 .is_enabled = clk_rcg2_is_enabled,
488 .get_parent = clk_rcg2_get_parent,
489 .set_parent = clk_rcg2_set_parent,
490 .recalc_rate = clk_rcg2_recalc_rate,
491 .determine_rate = clk_rcg2_determine_rate,
492 .set_rate = clk_rcg2_set_rate,
493 .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
494 .get_duty_cycle = clk_rcg2_get_duty_cycle,
495 .set_duty_cycle = clk_rcg2_set_duty_cycle,
497 EXPORT_SYMBOL_GPL(clk_rcg2_ops);
499 const struct clk_ops clk_rcg2_floor_ops = {
500 .is_enabled = clk_rcg2_is_enabled,
501 .get_parent = clk_rcg2_get_parent,
502 .set_parent = clk_rcg2_set_parent,
503 .recalc_rate = clk_rcg2_recalc_rate,
504 .determine_rate = clk_rcg2_determine_floor_rate,
505 .set_rate = clk_rcg2_set_floor_rate,
506 .set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent,
507 .get_duty_cycle = clk_rcg2_get_duty_cycle,
508 .set_duty_cycle = clk_rcg2_set_duty_cycle,
510 EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
512 const struct clk_ops clk_rcg2_mux_closest_ops = {
513 .determine_rate = __clk_mux_determine_rate_closest,
514 .get_parent = clk_rcg2_get_parent,
515 .set_parent = clk_rcg2_set_parent,
517 EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops);
524 static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
525 { 52, 295 }, /* 119 M */
526 { 11, 57 }, /* 130.25 M */
527 { 63, 307 }, /* 138.50 M */
528 { 11, 50 }, /* 148.50 M */
529 { 47, 206 }, /* 154 M */
530 { 31, 100 }, /* 205.25 M */
531 { 107, 269 }, /* 268.50 M */
535 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
536 { 31, 211 }, /* 119 M */
537 { 32, 199 }, /* 130.25 M */
538 { 63, 307 }, /* 138.50 M */
539 { 11, 60 }, /* 148.50 M */
540 { 50, 263 }, /* 154 M */
541 { 31, 120 }, /* 205.25 M */
542 { 119, 359 }, /* 268.50 M */
546 static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
547 unsigned long parent_rate)
549 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
550 struct freq_tbl f = *rcg->freq_tbl;
551 const struct frac_entry *frac;
553 s64 src_rate = parent_rate;
555 u32 mask = BIT(rcg->hid_width) - 1;
558 if (src_rate == 810000000)
559 frac = frac_table_810m;
561 frac = frac_table_675m;
563 for (; frac->num; frac++) {
565 request *= frac->den;
566 request = div_s64(request, frac->num);
567 if ((src_rate < (request - delta)) ||
568 (src_rate > (request + delta)))
571 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
574 f.pre_div >>= CFG_SRC_DIV_SHIFT;
579 return clk_rcg2_configure(rcg, &f);
585 static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
586 unsigned long rate, unsigned long parent_rate, u8 index)
588 /* Parent index is set statically in frequency table */
589 return clk_edp_pixel_set_rate(hw, rate, parent_rate);
592 static int clk_edp_pixel_determine_rate(struct clk_hw *hw,
593 struct clk_rate_request *req)
595 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
596 const struct freq_tbl *f = rcg->freq_tbl;
597 const struct frac_entry *frac;
600 u32 mask = BIT(rcg->hid_width) - 1;
602 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
604 /* Force the correct parent */
605 req->best_parent_hw = clk_hw_get_parent_by_index(hw, index);
606 req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw);
608 if (req->best_parent_rate == 810000000)
609 frac = frac_table_810m;
611 frac = frac_table_675m;
613 for (; frac->num; frac++) {
615 request *= frac->den;
616 request = div_s64(request, frac->num);
617 if ((req->best_parent_rate < (request - delta)) ||
618 (req->best_parent_rate > (request + delta)))
621 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
623 hid_div >>= CFG_SRC_DIV_SHIFT;
626 req->rate = calc_rate(req->best_parent_rate,
627 frac->num, frac->den,
628 !!frac->den, hid_div);
635 const struct clk_ops clk_edp_pixel_ops = {
636 .is_enabled = clk_rcg2_is_enabled,
637 .get_parent = clk_rcg2_get_parent,
638 .set_parent = clk_rcg2_set_parent,
639 .recalc_rate = clk_rcg2_recalc_rate,
640 .set_rate = clk_edp_pixel_set_rate,
641 .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
642 .determine_rate = clk_edp_pixel_determine_rate,
644 EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
646 static int clk_byte_determine_rate(struct clk_hw *hw,
647 struct clk_rate_request *req)
649 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
650 const struct freq_tbl *f = rcg->freq_tbl;
651 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
652 unsigned long parent_rate, div;
653 u32 mask = BIT(rcg->hid_width) - 1;
659 req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index);
660 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate);
662 div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1;
663 div = min_t(u32, div, mask);
665 req->rate = calc_rate(parent_rate, 0, 0, 0, div);
670 static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
671 unsigned long parent_rate)
673 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
674 struct freq_tbl f = *rcg->freq_tbl;
676 u32 mask = BIT(rcg->hid_width) - 1;
678 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
679 div = min_t(u32, div, mask);
683 return clk_rcg2_configure(rcg, &f);
686 static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
687 unsigned long rate, unsigned long parent_rate, u8 index)
689 /* Parent index is set statically in frequency table */
690 return clk_byte_set_rate(hw, rate, parent_rate);
693 const struct clk_ops clk_byte_ops = {
694 .is_enabled = clk_rcg2_is_enabled,
695 .get_parent = clk_rcg2_get_parent,
696 .set_parent = clk_rcg2_set_parent,
697 .recalc_rate = clk_rcg2_recalc_rate,
698 .set_rate = clk_byte_set_rate,
699 .set_rate_and_parent = clk_byte_set_rate_and_parent,
700 .determine_rate = clk_byte_determine_rate,
702 EXPORT_SYMBOL_GPL(clk_byte_ops);
704 static int clk_byte2_determine_rate(struct clk_hw *hw,
705 struct clk_rate_request *req)
707 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
708 unsigned long parent_rate, div;
709 u32 mask = BIT(rcg->hid_width) - 1;
711 unsigned long rate = req->rate;
716 p = req->best_parent_hw;
717 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, rate);
719 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
720 div = min_t(u32, div, mask);
722 req->rate = calc_rate(parent_rate, 0, 0, 0, div);
727 static int clk_byte2_set_rate(struct clk_hw *hw, unsigned long rate,
728 unsigned long parent_rate)
730 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
731 struct freq_tbl f = { 0 };
733 int i, num_parents = clk_hw_get_num_parents(hw);
734 u32 mask = BIT(rcg->hid_width) - 1;
737 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
738 div = min_t(u32, div, mask);
742 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
743 cfg &= CFG_SRC_SEL_MASK;
744 cfg >>= CFG_SRC_SEL_SHIFT;
746 for (i = 0; i < num_parents; i++) {
747 if (cfg == rcg->parent_map[i].cfg) {
748 f.src = rcg->parent_map[i].src;
749 return clk_rcg2_configure(rcg, &f);
756 static int clk_byte2_set_rate_and_parent(struct clk_hw *hw,
757 unsigned long rate, unsigned long parent_rate, u8 index)
759 /* Read the hardware to determine parent during set_rate */
760 return clk_byte2_set_rate(hw, rate, parent_rate);
763 const struct clk_ops clk_byte2_ops = {
764 .is_enabled = clk_rcg2_is_enabled,
765 .get_parent = clk_rcg2_get_parent,
766 .set_parent = clk_rcg2_set_parent,
767 .recalc_rate = clk_rcg2_recalc_rate,
768 .set_rate = clk_byte2_set_rate,
769 .set_rate_and_parent = clk_byte2_set_rate_and_parent,
770 .determine_rate = clk_byte2_determine_rate,
772 EXPORT_SYMBOL_GPL(clk_byte2_ops);
774 static const struct frac_entry frac_table_pixel[] = {
783 static int clk_pixel_determine_rate(struct clk_hw *hw,
784 struct clk_rate_request *req)
786 unsigned long request, src_rate;
788 const struct frac_entry *frac = frac_table_pixel;
790 for (; frac->num; frac++) {
791 request = (req->rate * frac->den) / frac->num;
793 src_rate = clk_hw_round_rate(req->best_parent_hw, request);
794 if ((src_rate < (request - delta)) ||
795 (src_rate > (request + delta)))
798 req->best_parent_rate = src_rate;
799 req->rate = (src_rate * frac->num) / frac->den;
806 static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
807 unsigned long parent_rate)
809 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
810 struct freq_tbl f = { 0 };
811 const struct frac_entry *frac = frac_table_pixel;
812 unsigned long request;
814 u32 mask = BIT(rcg->hid_width) - 1;
816 int i, num_parents = clk_hw_get_num_parents(hw);
818 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
819 cfg &= CFG_SRC_SEL_MASK;
820 cfg >>= CFG_SRC_SEL_SHIFT;
822 for (i = 0; i < num_parents; i++)
823 if (cfg == rcg->parent_map[i].cfg) {
824 f.src = rcg->parent_map[i].src;
828 for (; frac->num; frac++) {
829 request = (rate * frac->den) / frac->num;
831 if ((parent_rate < (request - delta)) ||
832 (parent_rate > (request + delta)))
835 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
838 f.pre_div >>= CFG_SRC_DIV_SHIFT;
843 return clk_rcg2_configure(rcg, &f);
848 static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
849 unsigned long parent_rate, u8 index)
851 return clk_pixel_set_rate(hw, rate, parent_rate);
854 const struct clk_ops clk_pixel_ops = {
855 .is_enabled = clk_rcg2_is_enabled,
856 .get_parent = clk_rcg2_get_parent,
857 .set_parent = clk_rcg2_set_parent,
858 .recalc_rate = clk_rcg2_recalc_rate,
859 .set_rate = clk_pixel_set_rate,
860 .set_rate_and_parent = clk_pixel_set_rate_and_parent,
861 .determine_rate = clk_pixel_determine_rate,
863 EXPORT_SYMBOL_GPL(clk_pixel_ops);
865 static int clk_gfx3d_determine_rate(struct clk_hw *hw,
866 struct clk_rate_request *req)
868 struct clk_rate_request parent_req = { .min_rate = 0, .max_rate = ULONG_MAX };
869 struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw);
870 struct clk_hw *xo, *p0, *p1, *p2;
871 unsigned long p0_rate;
872 u8 mux_div = cgfx->div;
879 * This function does ping-pong the RCG between PLLs: if we don't
880 * have at least one fixed PLL and two variable ones,
881 * then it's not going to work correctly.
883 if (WARN_ON(!p0 || !p1 || !p2))
886 xo = clk_hw_get_parent_by_index(hw, 0);
887 if (req->rate == clk_hw_get_rate(xo)) {
888 req->best_parent_hw = xo;
895 parent_req.rate = req->rate * mux_div;
897 /* This has to be a fixed rate PLL */
898 p0_rate = clk_hw_get_rate(p0);
900 if (parent_req.rate == p0_rate) {
901 req->rate = req->best_parent_rate = p0_rate;
902 req->best_parent_hw = p0;
906 if (req->best_parent_hw == p0) {
907 /* Are we going back to a previously used rate? */
908 if (clk_hw_get_rate(p2) == parent_req.rate)
909 req->best_parent_hw = p2;
911 req->best_parent_hw = p1;
912 } else if (req->best_parent_hw == p2) {
913 req->best_parent_hw = p1;
915 req->best_parent_hw = p2;
918 clk_hw_get_rate_range(req->best_parent_hw,
919 &parent_req.min_rate, &parent_req.max_rate);
921 if (req->min_rate > parent_req.min_rate)
922 parent_req.min_rate = req->min_rate;
924 if (req->max_rate < parent_req.max_rate)
925 parent_req.max_rate = req->max_rate;
927 ret = __clk_determine_rate(req->best_parent_hw, &parent_req);
931 req->rate = req->best_parent_rate = parent_req.rate;
932 req->rate /= mux_div;
937 static int clk_gfx3d_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
938 unsigned long parent_rate, u8 index)
940 struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw);
941 struct clk_rcg2 *rcg = &cgfx->rcg;
945 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
946 /* On some targets, the GFX3D RCG may need to divide PLL frequency */
948 cfg |= ((2 * cgfx->div) - 1) << CFG_SRC_DIV_SHIFT;
950 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
954 return update_config(rcg);
957 static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
958 unsigned long parent_rate)
961 * We should never get here; clk_gfx3d_determine_rate() should always
962 * make us use a different parent than what we're currently using, so
963 * clk_gfx3d_set_rate_and_parent() should always be called.
968 const struct clk_ops clk_gfx3d_ops = {
969 .is_enabled = clk_rcg2_is_enabled,
970 .get_parent = clk_rcg2_get_parent,
971 .set_parent = clk_rcg2_set_parent,
972 .recalc_rate = clk_rcg2_recalc_rate,
973 .set_rate = clk_gfx3d_set_rate,
974 .set_rate_and_parent = clk_gfx3d_set_rate_and_parent,
975 .determine_rate = clk_gfx3d_determine_rate,
977 EXPORT_SYMBOL_GPL(clk_gfx3d_ops);
979 static int clk_rcg2_set_force_enable(struct clk_hw *hw)
981 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
982 const char *name = clk_hw_get_name(hw);
985 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
986 CMD_ROOT_EN, CMD_ROOT_EN);
990 /* wait for RCG to turn ON */
991 for (count = 500; count > 0; count--) {
992 if (clk_rcg2_is_enabled(hw))
998 pr_err("%s: RCG did not turn on\n", name);
1002 static int clk_rcg2_clear_force_enable(struct clk_hw *hw)
1004 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1006 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
1011 clk_rcg2_shared_force_enable_clear(struct clk_hw *hw, const struct freq_tbl *f)
1013 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1016 ret = clk_rcg2_set_force_enable(hw);
1020 ret = clk_rcg2_configure(rcg, f);
1024 return clk_rcg2_clear_force_enable(hw);
1027 static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
1028 unsigned long parent_rate)
1030 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1031 const struct freq_tbl *f;
1033 f = qcom_find_freq(rcg->freq_tbl, rate);
1038 * In case clock is disabled, update the M, N and D registers, cache
1039 * the CFG value in parked_cfg and don't hit the update bit of CMD
1042 if (!clk_hw_is_enabled(hw))
1043 return __clk_rcg2_configure(rcg, f, &rcg->parked_cfg);
1045 return clk_rcg2_shared_force_enable_clear(hw, f);
1048 static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw,
1049 unsigned long rate, unsigned long parent_rate, u8 index)
1051 return clk_rcg2_shared_set_rate(hw, rate, parent_rate);
1054 static int clk_rcg2_shared_enable(struct clk_hw *hw)
1056 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1060 * Set the update bit because required configuration has already
1061 * been written in clk_rcg2_shared_set_rate()
1063 ret = clk_rcg2_set_force_enable(hw);
1067 /* Write back the stored configuration corresponding to current rate */
1068 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg->parked_cfg);
1072 ret = update_config(rcg);
1076 return clk_rcg2_clear_force_enable(hw);
1079 static void clk_rcg2_shared_disable(struct clk_hw *hw)
1081 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1084 * Store current configuration as switching to safe source would clear
1085 * the SRC and DIV of CFG register
1087 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg);
1090 * Park the RCG at a safe configuration - sourced off of safe source.
1091 * Force enable and disable the RCG while configuring it to safeguard
1092 * against any update signal coming from the downstream clock.
1093 * The current parent is still prepared and enabled at this point, and
1094 * the safe source is always on while application processor subsystem
1095 * is online. Therefore, the RCG can safely switch its parent.
1097 clk_rcg2_set_force_enable(hw);
1099 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
1100 rcg->safe_src_index << CFG_SRC_SEL_SHIFT);
1104 clk_rcg2_clear_force_enable(hw);
1107 static u8 clk_rcg2_shared_get_parent(struct clk_hw *hw)
1109 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1111 /* If the shared rcg is parked use the cached cfg instead */
1112 if (!clk_hw_is_enabled(hw))
1113 return __clk_rcg2_get_parent(hw, rcg->parked_cfg);
1115 return clk_rcg2_get_parent(hw);
1118 static int clk_rcg2_shared_set_parent(struct clk_hw *hw, u8 index)
1120 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1122 /* If the shared rcg is parked only update the cached cfg */
1123 if (!clk_hw_is_enabled(hw)) {
1124 rcg->parked_cfg &= ~CFG_SRC_SEL_MASK;
1125 rcg->parked_cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
1130 return clk_rcg2_set_parent(hw, index);
1133 static unsigned long
1134 clk_rcg2_shared_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1136 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1138 /* If the shared rcg is parked use the cached cfg instead */
1139 if (!clk_hw_is_enabled(hw))
1140 return __clk_rcg2_recalc_rate(hw, parent_rate, rcg->parked_cfg);
1142 return clk_rcg2_recalc_rate(hw, parent_rate);
1145 const struct clk_ops clk_rcg2_shared_ops = {
1146 .enable = clk_rcg2_shared_enable,
1147 .disable = clk_rcg2_shared_disable,
1148 .get_parent = clk_rcg2_shared_get_parent,
1149 .set_parent = clk_rcg2_shared_set_parent,
1150 .recalc_rate = clk_rcg2_shared_recalc_rate,
1151 .determine_rate = clk_rcg2_determine_rate,
1152 .set_rate = clk_rcg2_shared_set_rate,
1153 .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
1155 EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
1157 /* Common APIs to be used for DFS based RCGR */
1158 static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
1161 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1163 unsigned long prate = 0;
1164 u32 val, mask, cfg, mode, src;
1167 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);
1169 mask = BIT(rcg->hid_width) - 1;
1172 f->pre_div = cfg & mask;
1174 src = cfg & CFG_SRC_SEL_MASK;
1175 src >>= CFG_SRC_SEL_SHIFT;
1177 num_parents = clk_hw_get_num_parents(hw);
1178 for (i = 0; i < num_parents; i++) {
1179 if (src == rcg->parent_map[i].cfg) {
1180 f->src = rcg->parent_map[i].src;
1181 p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);
1182 prate = clk_hw_get_rate(p);
1186 mode = cfg & CFG_MODE_MASK;
1187 mode >>= CFG_MODE_SHIFT;
1189 mask = BIT(rcg->mnd_width) - 1;
1190 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),
1195 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l),
1203 f->freq = calc_rate(prate, f->m, f->n, mode, f->pre_div);
1206 static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg)
1208 struct freq_tbl *freq_tbl;
1211 /* Allocate space for 1 extra since table is NULL terminated */
1212 freq_tbl = kcalloc(MAX_PERF_LEVEL + 1, sizeof(*freq_tbl), GFP_KERNEL);
1215 rcg->freq_tbl = freq_tbl;
1217 for (i = 0; i < MAX_PERF_LEVEL; i++)
1218 clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i);
1223 static int clk_rcg2_dfs_determine_rate(struct clk_hw *hw,
1224 struct clk_rate_request *req)
1226 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1229 if (!rcg->freq_tbl) {
1230 ret = clk_rcg2_dfs_populate_freq_table(rcg);
1232 pr_err("Failed to update DFS tables for %s\n",
1233 clk_hw_get_name(hw));
1238 return clk_rcg2_determine_rate(hw, req);
1241 static unsigned long
1242 clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1244 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1245 u32 level, mask, cfg, m = 0, n = 0, mode, pre_div;
1247 regmap_read(rcg->clkr.regmap,
1248 rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level);
1249 level &= GENMASK(4, 1);
1253 return rcg->freq_tbl[level].freq;
1256 * Assume that parent_rate is actually the parent because
1257 * we can't do any better at figuring it out when the table
1258 * hasn't been populated yet. We only populate the table
1259 * in determine_rate because we can't guarantee the parents
1260 * will be registered with the framework until then.
1262 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level),
1265 mask = BIT(rcg->hid_width) - 1;
1268 pre_div = cfg & mask;
1270 mode = cfg & CFG_MODE_MASK;
1271 mode >>= CFG_MODE_SHIFT;
1273 mask = BIT(rcg->mnd_width) - 1;
1274 regmap_read(rcg->clkr.regmap,
1275 rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m);
1278 regmap_read(rcg->clkr.regmap,
1279 rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n);
1285 return calc_rate(parent_rate, m, n, mode, pre_div);
1288 static const struct clk_ops clk_rcg2_dfs_ops = {
1289 .is_enabled = clk_rcg2_is_enabled,
1290 .get_parent = clk_rcg2_get_parent,
1291 .determine_rate = clk_rcg2_dfs_determine_rate,
1292 .recalc_rate = clk_rcg2_dfs_recalc_rate,
1295 static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
1296 struct regmap *regmap)
1298 struct clk_rcg2 *rcg = data->rcg;
1299 struct clk_init_data *init = data->init;
1303 ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val);
1307 if (!(val & SE_CMD_DFS_EN))
1311 * Rate changes with consumer writing a register in
1312 * their own I/O region
1314 init->flags |= CLK_GET_RATE_NOCACHE;
1315 init->ops = &clk_rcg2_dfs_ops;
1317 rcg->freq_tbl = NULL;
1322 int qcom_cc_register_rcg_dfs(struct regmap *regmap,
1323 const struct clk_rcg_dfs_data *rcgs, size_t len)
1327 for (i = 0; i < len; i++) {
1328 ret = clk_rcg2_enable_dfs(&rcgs[i], regmap);
1335 EXPORT_SYMBOL_GPL(qcom_cc_register_rcg_dfs);
1337 static int clk_rcg2_dp_set_rate(struct clk_hw *hw, unsigned long rate,
1338 unsigned long parent_rate)
1340 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1341 struct freq_tbl f = { 0 };
1342 u32 mask = BIT(rcg->hid_width) - 1;
1344 int i, num_parents = clk_hw_get_num_parents(hw);
1345 unsigned long num, den;
1347 rational_best_approximation(parent_rate, rate,
1348 GENMASK(rcg->mnd_width - 1, 0),
1349 GENMASK(rcg->mnd_width - 1, 0), &den, &num);
1354 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
1356 cfg &= CFG_SRC_SEL_MASK;
1357 cfg >>= CFG_SRC_SEL_SHIFT;
1359 for (i = 0; i < num_parents; i++) {
1360 if (cfg == rcg->parent_map[i].cfg) {
1361 f.src = rcg->parent_map[i].src;
1366 f.pre_div = hid_div;
1367 f.pre_div >>= CFG_SRC_DIV_SHIFT;
1378 return clk_rcg2_configure(rcg, &f);
1381 static int clk_rcg2_dp_set_rate_and_parent(struct clk_hw *hw,
1382 unsigned long rate, unsigned long parent_rate, u8 index)
1384 return clk_rcg2_dp_set_rate(hw, rate, parent_rate);
1387 static int clk_rcg2_dp_determine_rate(struct clk_hw *hw,
1388 struct clk_rate_request *req)
1390 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1391 unsigned long num, den;
1394 /* Parent rate is a fixed phy link rate */
1395 rational_best_approximation(req->best_parent_rate, req->rate,
1396 GENMASK(rcg->mnd_width - 1, 0),
1397 GENMASK(rcg->mnd_width - 1, 0), &den, &num);
1402 tmp = req->best_parent_rate * num;
1409 const struct clk_ops clk_dp_ops = {
1410 .is_enabled = clk_rcg2_is_enabled,
1411 .get_parent = clk_rcg2_get_parent,
1412 .set_parent = clk_rcg2_set_parent,
1413 .recalc_rate = clk_rcg2_recalc_rate,
1414 .set_rate = clk_rcg2_dp_set_rate,
1415 .set_rate_and_parent = clk_rcg2_dp_set_rate_and_parent,
1416 .determine_rate = clk_rcg2_dp_determine_rate,
1418 EXPORT_SYMBOL_GPL(clk_dp_ops);