1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
7 #include <linux/kernel.h>
8 #include <linux/export.h>
9 #include <linux/clk-provider.h>
10 #include <linux/regmap.h>
11 #include <linux/delay.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
17 # define PLL_OUTCTRL BIT(0)
18 # define PLL_BYPASSNL BIT(1)
19 # define PLL_RESET_N BIT(2)
20 # define PLL_OFFLINE_REQ BIT(7)
21 # define PLL_LOCK_COUNT_SHIFT 8
22 # define PLL_LOCK_COUNT_MASK 0x3f
23 # define PLL_BIAS_COUNT_SHIFT 14
24 # define PLL_BIAS_COUNT_MASK 0x3f
25 # define PLL_VOTE_FSM_ENA BIT(20)
26 # define PLL_FSM_ENA BIT(20)
27 # define PLL_VOTE_FSM_RESET BIT(21)
28 # define PLL_UPDATE BIT(22)
29 # define PLL_UPDATE_BYPASS BIT(23)
30 # define PLL_FSM_LEGACY_MODE BIT(24)
31 # define PLL_OFFLINE_ACK BIT(28)
32 # define ALPHA_PLL_ACK_LATCH BIT(29)
33 # define PLL_ACTIVE_FLAG BIT(30)
34 # define PLL_LOCK_DET BIT(31)
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
42 # define PLL_POST_DIV_SHIFT 8
43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
44 # define PLL_ALPHA_EN BIT(24)
45 # define PLL_ALPHA_MODE BIT(25)
46 # define PLL_VCO_SHIFT 20
47 # define PLL_VCO_MASK 0x3
49 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
50 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
52 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
53 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
54 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
55 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
56 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
57 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
58 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
59 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
60 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
62 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
63 [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
64 [PLL_OFF_L_VAL] = 0x04,
65 [PLL_OFF_ALPHA_VAL] = 0x08,
66 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
67 [PLL_OFF_USER_CTL] = 0x10,
68 [PLL_OFF_USER_CTL_U] = 0x14,
69 [PLL_OFF_CONFIG_CTL] = 0x18,
70 [PLL_OFF_TEST_CTL] = 0x1c,
71 [PLL_OFF_TEST_CTL_U] = 0x20,
72 [PLL_OFF_STATUS] = 0x24,
74 [CLK_ALPHA_PLL_TYPE_HUAYRA] = {
75 [PLL_OFF_L_VAL] = 0x04,
76 [PLL_OFF_ALPHA_VAL] = 0x08,
77 [PLL_OFF_USER_CTL] = 0x10,
78 [PLL_OFF_CONFIG_CTL] = 0x14,
79 [PLL_OFF_CONFIG_CTL_U] = 0x18,
80 [PLL_OFF_TEST_CTL] = 0x1c,
81 [PLL_OFF_TEST_CTL_U] = 0x20,
82 [PLL_OFF_STATUS] = 0x24,
84 [CLK_ALPHA_PLL_TYPE_BRAMMO] = {
85 [PLL_OFF_L_VAL] = 0x04,
86 [PLL_OFF_ALPHA_VAL] = 0x08,
87 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
88 [PLL_OFF_USER_CTL] = 0x10,
89 [PLL_OFF_CONFIG_CTL] = 0x18,
90 [PLL_OFF_TEST_CTL] = 0x1c,
91 [PLL_OFF_STATUS] = 0x24,
93 [CLK_ALPHA_PLL_TYPE_FABIA] = {
94 [PLL_OFF_L_VAL] = 0x04,
95 [PLL_OFF_USER_CTL] = 0x0c,
96 [PLL_OFF_USER_CTL_U] = 0x10,
97 [PLL_OFF_CONFIG_CTL] = 0x14,
98 [PLL_OFF_CONFIG_CTL_U] = 0x18,
99 [PLL_OFF_TEST_CTL] = 0x1c,
100 [PLL_OFF_TEST_CTL_U] = 0x20,
101 [PLL_OFF_STATUS] = 0x24,
102 [PLL_OFF_OPMODE] = 0x2c,
103 [PLL_OFF_FRAC] = 0x38,
105 [CLK_ALPHA_PLL_TYPE_TRION] = {
106 [PLL_OFF_L_VAL] = 0x04,
107 [PLL_OFF_CAL_L_VAL] = 0x08,
108 [PLL_OFF_USER_CTL] = 0x0c,
109 [PLL_OFF_USER_CTL_U] = 0x10,
110 [PLL_OFF_USER_CTL_U1] = 0x14,
111 [PLL_OFF_CONFIG_CTL] = 0x18,
112 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
113 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
114 [PLL_OFF_TEST_CTL] = 0x24,
115 [PLL_OFF_TEST_CTL_U] = 0x28,
116 [PLL_OFF_TEST_CTL_U1] = 0x2c,
117 [PLL_OFF_STATUS] = 0x30,
118 [PLL_OFF_OPMODE] = 0x38,
119 [PLL_OFF_ALPHA_VAL] = 0x40,
121 [CLK_ALPHA_PLL_TYPE_AGERA] = {
122 [PLL_OFF_L_VAL] = 0x04,
123 [PLL_OFF_ALPHA_VAL] = 0x08,
124 [PLL_OFF_USER_CTL] = 0x0c,
125 [PLL_OFF_CONFIG_CTL] = 0x10,
126 [PLL_OFF_CONFIG_CTL_U] = 0x14,
127 [PLL_OFF_TEST_CTL] = 0x18,
128 [PLL_OFF_TEST_CTL_U] = 0x1c,
129 [PLL_OFF_STATUS] = 0x2c,
131 [CLK_ALPHA_PLL_TYPE_ZONDA] = {
132 [PLL_OFF_L_VAL] = 0x04,
133 [PLL_OFF_ALPHA_VAL] = 0x08,
134 [PLL_OFF_USER_CTL] = 0x0c,
135 [PLL_OFF_CONFIG_CTL] = 0x10,
136 [PLL_OFF_CONFIG_CTL_U] = 0x14,
137 [PLL_OFF_CONFIG_CTL_U1] = 0x18,
138 [PLL_OFF_TEST_CTL] = 0x1c,
139 [PLL_OFF_TEST_CTL_U] = 0x20,
140 [PLL_OFF_TEST_CTL_U1] = 0x24,
141 [PLL_OFF_OPMODE] = 0x28,
142 [PLL_OFF_STATUS] = 0x38,
144 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
145 [PLL_OFF_OPMODE] = 0x04,
146 [PLL_OFF_STATUS] = 0x0c,
147 [PLL_OFF_L_VAL] = 0x10,
148 [PLL_OFF_ALPHA_VAL] = 0x14,
149 [PLL_OFF_USER_CTL] = 0x18,
150 [PLL_OFF_USER_CTL_U] = 0x1c,
151 [PLL_OFF_CONFIG_CTL] = 0x20,
152 [PLL_OFF_CONFIG_CTL_U] = 0x24,
153 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
154 [PLL_OFF_TEST_CTL] = 0x2c,
155 [PLL_OFF_TEST_CTL_U] = 0x30,
156 [PLL_OFF_TEST_CTL_U1] = 0x34,
158 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = {
159 [PLL_OFF_OPMODE] = 0x04,
160 [PLL_OFF_STATE] = 0x08,
161 [PLL_OFF_STATUS] = 0x0c,
162 [PLL_OFF_L_VAL] = 0x10,
163 [PLL_OFF_ALPHA_VAL] = 0x14,
164 [PLL_OFF_USER_CTL] = 0x18,
165 [PLL_OFF_USER_CTL_U] = 0x1c,
166 [PLL_OFF_CONFIG_CTL] = 0x20,
167 [PLL_OFF_CONFIG_CTL_U] = 0x24,
168 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
169 [PLL_OFF_TEST_CTL] = 0x2c,
170 [PLL_OFF_TEST_CTL_U] = 0x30,
171 [PLL_OFF_TEST_CTL_U1] = 0x34,
172 [PLL_OFF_TEST_CTL_U2] = 0x38,
174 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
175 [PLL_OFF_OPMODE] = 0x04,
176 [PLL_OFF_STATUS] = 0x0c,
177 [PLL_OFF_L_VAL] = 0x10,
178 [PLL_OFF_USER_CTL] = 0x14,
179 [PLL_OFF_USER_CTL_U] = 0x18,
180 [PLL_OFF_CONFIG_CTL] = 0x1c,
181 [PLL_OFF_CONFIG_CTL_U] = 0x20,
182 [PLL_OFF_CONFIG_CTL_U1] = 0x24,
183 [PLL_OFF_TEST_CTL] = 0x28,
184 [PLL_OFF_TEST_CTL_U] = 0x2c,
186 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
187 [PLL_OFF_L_VAL] = 0x04,
188 [PLL_OFF_ALPHA_VAL] = 0x08,
189 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
190 [PLL_OFF_TEST_CTL] = 0x10,
191 [PLL_OFF_TEST_CTL_U] = 0x14,
192 [PLL_OFF_USER_CTL] = 0x18,
193 [PLL_OFF_USER_CTL_U] = 0x1c,
194 [PLL_OFF_CONFIG_CTL] = 0x20,
195 [PLL_OFF_STATUS] = 0x24,
197 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = {
198 [PLL_OFF_L_VAL] = 0x04,
199 [PLL_OFF_ALPHA_VAL] = 0x08,
200 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
201 [PLL_OFF_TEST_CTL] = 0x10,
202 [PLL_OFF_TEST_CTL_U] = 0x14,
203 [PLL_OFF_USER_CTL] = 0x18,
204 [PLL_OFF_CONFIG_CTL] = 0x1C,
205 [PLL_OFF_STATUS] = 0x20,
207 [CLK_ALPHA_PLL_TYPE_STROMER] = {
208 [PLL_OFF_L_VAL] = 0x08,
209 [PLL_OFF_ALPHA_VAL] = 0x10,
210 [PLL_OFF_ALPHA_VAL_U] = 0x14,
211 [PLL_OFF_USER_CTL] = 0x18,
212 [PLL_OFF_USER_CTL_U] = 0x1c,
213 [PLL_OFF_CONFIG_CTL] = 0x20,
214 [PLL_OFF_CONFIG_CTL_U] = 0xff,
215 [PLL_OFF_TEST_CTL] = 0x30,
216 [PLL_OFF_TEST_CTL_U] = 0x34,
217 [PLL_OFF_STATUS] = 0x28,
219 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
220 [PLL_OFF_L_VAL] = 0x04,
221 [PLL_OFF_USER_CTL] = 0x08,
222 [PLL_OFF_USER_CTL_U] = 0x0c,
223 [PLL_OFF_CONFIG_CTL] = 0x10,
224 [PLL_OFF_TEST_CTL] = 0x14,
225 [PLL_OFF_TEST_CTL_U] = 0x18,
226 [PLL_OFF_STATUS] = 0x1c,
227 [PLL_OFF_ALPHA_VAL] = 0x24,
228 [PLL_OFF_ALPHA_VAL_U] = 0x28,
231 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
234 * Even though 40 bits are present, use only 32 for ease of calculation.
236 #define ALPHA_REG_BITWIDTH 40
237 #define ALPHA_REG_16BIT_WIDTH 16
238 #define ALPHA_BITWIDTH 32U
239 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
241 #define ALPHA_PLL_STATUS_REG_SHIFT 8
243 #define PLL_HUAYRA_M_WIDTH 8
244 #define PLL_HUAYRA_M_SHIFT 8
245 #define PLL_HUAYRA_M_MASK 0xff
246 #define PLL_HUAYRA_N_SHIFT 0
247 #define PLL_HUAYRA_N_MASK 0xff
248 #define PLL_HUAYRA_ALPHA_WIDTH 16
250 #define PLL_STANDBY 0x0
252 #define PLL_OUT_MASK 0x7
253 #define PLL_RATE_MARGIN 500
255 /* TRION PLL specific settings and offsets */
256 #define TRION_PLL_CAL_VAL 0x44
257 #define TRION_PCAL_DONE BIT(26)
259 /* LUCID PLL specific settings and offsets */
260 #define LUCID_PCAL_DONE BIT(27)
262 /* LUCID 5LPE PLL specific settings and offsets */
263 #define LUCID_5LPE_PCAL_DONE BIT(11)
264 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13)
265 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
266 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
268 /* LUCID EVO PLL specific settings and offsets */
269 #define LUCID_EVO_PCAL_NOT_DONE BIT(8)
270 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
271 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
272 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
274 /* ZONDA PLL specific */
275 #define ZONDA_PLL_OUT_MASK 0xf
276 #define ZONDA_STAY_IN_CFA BIT(16)
277 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
279 #define pll_alpha_width(p) \
280 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
281 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
283 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
285 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
286 struct clk_alpha_pll, clkr)
288 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
289 struct clk_alpha_pll_postdiv, clkr)
291 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
297 const char *name = clk_hw_get_name(&pll->clkr.hw);
299 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
303 for (count = 200; count > 0; count--) {
304 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
307 if (inverse && !(val & mask))
309 else if ((val & mask) == mask)
315 WARN(1, "%s failed to %s!\n", name, action);
319 #define wait_for_pll_enable_active(pll) \
320 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
322 #define wait_for_pll_enable_lock(pll) \
323 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
325 #define wait_for_zonda_pll_freq_lock(pll) \
326 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
328 #define wait_for_pll_disable(pll) \
329 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
331 #define wait_for_pll_offline(pll) \
332 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
334 #define wait_for_pll_update(pll) \
335 wait_for_pll(pll, PLL_UPDATE, 1, "update")
337 #define wait_for_pll_update_ack_set(pll) \
338 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
340 #define wait_for_pll_update_ack_clear(pll) \
341 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
343 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg,
347 regmap_write(regmap, reg, val);
350 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
351 const struct alpha_pll_config *config)
355 regmap_write(regmap, PLL_L_VAL(pll), config->l);
356 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
357 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
359 if (pll_has_64bit_config(pll))
360 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
361 config->config_ctl_hi_val);
363 if (pll_alpha_width(pll) > 32)
364 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
366 val = config->main_output_mask;
367 val |= config->aux_output_mask;
368 val |= config->aux2_output_mask;
369 val |= config->early_output_mask;
370 val |= config->pre_div_val;
371 val |= config->post_div_val;
372 val |= config->vco_val;
373 val |= config->alpha_en_mask;
374 val |= config->alpha_mode_mask;
376 mask = config->main_output_mask;
377 mask |= config->aux_output_mask;
378 mask |= config->aux2_output_mask;
379 mask |= config->early_output_mask;
380 mask |= config->pre_div_mask;
381 mask |= config->post_div_mask;
382 mask |= config->vco_mask;
384 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
386 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
387 config->test_ctl_val);
388 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
389 config->test_ctl_hi_val);
391 if (pll->flags & SUPPORTS_FSM_MODE)
392 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
394 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
396 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
399 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
402 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
408 if (pll->flags & SUPPORTS_OFFLINE_REQ)
409 val &= ~PLL_OFFLINE_REQ;
411 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
415 /* Make sure enable request goes through before waiting for update */
418 return wait_for_pll_enable_active(pll);
421 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
424 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
427 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
431 if (pll->flags & SUPPORTS_OFFLINE_REQ) {
432 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
433 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
437 ret = wait_for_pll_offline(pll);
443 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
448 wait_for_pll_disable(pll);
451 static int pll_is_enabled(struct clk_hw *hw, u32 mask)
454 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
457 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
461 return !!(val & mask);
464 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
466 return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
469 static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
471 return pll_is_enabled(hw, PLL_LOCK_DET);
474 static int clk_alpha_pll_enable(struct clk_hw *hw)
477 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
480 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
481 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
485 /* If in FSM mode, just vote for it */
486 if (val & PLL_VOTE_FSM_ENA) {
487 ret = clk_enable_regmap(hw);
490 return wait_for_pll_enable_active(pll);
493 /* Skip if already enabled */
494 if ((val & mask) == mask)
497 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
498 PLL_BYPASSNL, PLL_BYPASSNL);
503 * H/W requires a 5us delay between disabling the bypass and
504 * de-asserting the reset.
509 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
510 PLL_RESET_N, PLL_RESET_N);
514 ret = wait_for_pll_enable_lock(pll);
518 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
519 PLL_OUTCTRL, PLL_OUTCTRL);
521 /* Ensure that the write above goes through before returning. */
526 static void clk_alpha_pll_disable(struct clk_hw *hw)
529 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
532 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
536 /* If in FSM mode, just unvote it */
537 if (val & PLL_VOTE_FSM_ENA) {
538 clk_disable_regmap(hw);
543 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
545 /* Delay of 2 output clock ticks required until output is disabled */
549 mask = PLL_RESET_N | PLL_BYPASSNL;
550 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
554 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
556 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
560 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
567 remainder = do_div(quotient, prate);
575 /* Upper ALPHA_BITWIDTH bits of Alpha */
576 quotient = remainder << ALPHA_SHIFT(alpha_width);
578 remainder = do_div(quotient, prate);
584 return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
587 static const struct pll_vco *
588 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
590 const struct pll_vco *v = pll->vco_table;
591 const struct pll_vco *end = v + pll->num_vco;
594 if (rate >= v->min_freq && rate <= v->max_freq)
601 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
603 u32 l, low, high, ctl;
604 u64 a = 0, prate = parent_rate;
605 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
606 u32 alpha_width = pll_alpha_width(pll);
608 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
610 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
611 if (ctl & PLL_ALPHA_EN) {
612 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
613 if (alpha_width > 32) {
614 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
616 a = (u64)high << 32 | low;
618 a = low & GENMASK(alpha_width - 1, 0);
621 if (alpha_width > ALPHA_BITWIDTH)
622 a >>= alpha_width - ALPHA_BITWIDTH;
625 return alpha_pll_calc_rate(prate, l, a, alpha_width);
629 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
634 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
636 /* Latch the input to the PLL */
637 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
640 /* Wait for 2 reference cycle before checking ACK bit */
644 * PLL will latch the new L, Alpha and freq control word.
645 * PLL will respond by raising PLL_ACK_LATCH output when new programming
646 * has been latched in and PLL is being updated. When
647 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
648 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
650 if (mode & PLL_UPDATE_BYPASS) {
651 ret = wait_for_pll_update_ack_set(pll);
655 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
657 ret = wait_for_pll_update(pll);
662 ret = wait_for_pll_update_ack_clear(pll);
666 /* Wait for PLL output to stabilize */
672 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
673 int (*is_enabled)(struct clk_hw *))
675 if (!is_enabled(&pll->clkr.hw) ||
676 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
679 return __clk_alpha_pll_update_latch(pll);
682 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
684 int (*is_enabled)(struct clk_hw *))
686 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
687 const struct pll_vco *vco;
688 u32 l, alpha_width = pll_alpha_width(pll);
691 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
692 vco = alpha_pll_find_vco(pll, rate);
693 if (pll->vco_table && !vco) {
694 pr_err("%s: alpha pll not in a valid vco range\n",
695 clk_hw_get_name(hw));
699 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
701 if (alpha_width > ALPHA_BITWIDTH)
702 a <<= alpha_width - ALPHA_BITWIDTH;
704 if (alpha_width > 32)
705 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
707 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
710 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
711 PLL_VCO_MASK << PLL_VCO_SHIFT,
712 vco->val << PLL_VCO_SHIFT);
715 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
716 PLL_ALPHA_EN, PLL_ALPHA_EN);
718 return clk_alpha_pll_update_latch(pll, is_enabled);
721 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
724 return __clk_alpha_pll_set_rate(hw, rate, prate,
725 clk_alpha_pll_is_enabled);
728 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
731 return __clk_alpha_pll_set_rate(hw, rate, prate,
732 clk_alpha_pll_hwfsm_is_enabled);
735 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
736 unsigned long *prate)
738 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
739 u32 l, alpha_width = pll_alpha_width(pll);
741 unsigned long min_freq, max_freq;
743 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
744 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
747 min_freq = pll->vco_table[0].min_freq;
748 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
750 return clamp(rate, min_freq, max_freq);
754 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
757 * a contains 16 bit alpha_val in two’s complement number in the range
760 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
763 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
767 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
774 remainder = do_div(quotient, prate);
782 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
783 remainder = do_div(quotient, prate);
789 * alpha_val should be in two’s complement number in the range
790 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
791 * since alpha value will be subtracted in this case.
793 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
797 return alpha_huayra_pll_calc_rate(prate, *l, *a);
801 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
803 u64 rate = parent_rate, tmp;
804 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
805 u32 l, alpha = 0, ctl, alpha_m, alpha_n;
807 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
808 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
810 if (ctl & PLL_ALPHA_EN) {
811 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
813 * Depending upon alpha_mode, it can be treated as M/N value or
814 * as a two’s complement number. When alpha_mode=1,
815 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
819 * M is a signed number (-128 to 127) and N is unsigned
820 * (0 to 255). M/N has to be within +/-0.5.
822 * When alpha_mode=0, it is a two’s complement number in the
825 * Fout=FIN*(L+(alpha_val)/2^16)
827 * where alpha_val is two’s complement number.
829 if (!(ctl & PLL_ALPHA_MODE))
830 return alpha_huayra_pll_calc_rate(rate, l, alpha);
832 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
833 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
837 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
838 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
840 do_div(tmp, alpha_n);
844 do_div(tmp, alpha_n);
851 return alpha_huayra_pll_calc_rate(rate, l, alpha);
854 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
857 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
858 u32 l, a, ctl, cur_alpha = 0;
860 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
862 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
864 if (ctl & PLL_ALPHA_EN)
865 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
868 * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
869 * without having to go through the power on sequence.
871 if (clk_alpha_pll_is_enabled(hw)) {
872 if (cur_alpha != a) {
873 pr_err("%s: clock needs to be gated\n",
874 clk_hw_get_name(hw));
878 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
879 /* Ensure that the write above goes to detect L val change. */
881 return wait_for_pll_enable_lock(pll);
884 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
885 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
888 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
891 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
892 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
897 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
898 unsigned long *prate)
902 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
905 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
906 struct regmap *regmap)
908 u32 mode_val, opmode_val;
911 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
912 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
916 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL));
919 static int clk_trion_pll_is_enabled(struct clk_hw *hw)
921 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
923 return trion_pll_is_enabled(pll, pll->clkr.regmap);
926 static int clk_trion_pll_enable(struct clk_hw *hw)
928 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
929 struct regmap *regmap = pll->clkr.regmap;
933 ret = regmap_read(regmap, PLL_MODE(pll), &val);
937 /* If in FSM mode, just vote for it */
938 if (val & PLL_VOTE_FSM_ENA) {
939 ret = clk_enable_regmap(hw);
942 return wait_for_pll_enable_active(pll);
945 /* Set operation mode to RUN */
946 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
948 ret = wait_for_pll_enable_lock(pll);
952 /* Enable the PLL outputs */
953 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
954 PLL_OUT_MASK, PLL_OUT_MASK);
958 /* Enable the global PLL outputs */
959 return regmap_update_bits(regmap, PLL_MODE(pll),
960 PLL_OUTCTRL, PLL_OUTCTRL);
963 static void clk_trion_pll_disable(struct clk_hw *hw)
965 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
966 struct regmap *regmap = pll->clkr.regmap;
970 ret = regmap_read(regmap, PLL_MODE(pll), &val);
974 /* If in FSM mode, just unvote it */
975 if (val & PLL_VOTE_FSM_ENA) {
976 clk_disable_regmap(hw);
980 /* Disable the global PLL output */
981 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
985 /* Disable the PLL outputs */
986 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
991 /* Place the PLL mode in STANDBY */
992 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
993 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
997 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
999 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1000 u32 l, frac, alpha_width = pll_alpha_width(pll);
1002 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1003 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
1005 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1008 const struct clk_ops clk_alpha_pll_fixed_ops = {
1009 .enable = clk_alpha_pll_enable,
1010 .disable = clk_alpha_pll_disable,
1011 .is_enabled = clk_alpha_pll_is_enabled,
1012 .recalc_rate = clk_alpha_pll_recalc_rate,
1014 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
1016 const struct clk_ops clk_alpha_pll_ops = {
1017 .enable = clk_alpha_pll_enable,
1018 .disable = clk_alpha_pll_disable,
1019 .is_enabled = clk_alpha_pll_is_enabled,
1020 .recalc_rate = clk_alpha_pll_recalc_rate,
1021 .round_rate = clk_alpha_pll_round_rate,
1022 .set_rate = clk_alpha_pll_set_rate,
1024 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
1026 const struct clk_ops clk_alpha_pll_huayra_ops = {
1027 .enable = clk_alpha_pll_enable,
1028 .disable = clk_alpha_pll_disable,
1029 .is_enabled = clk_alpha_pll_is_enabled,
1030 .recalc_rate = alpha_pll_huayra_recalc_rate,
1031 .round_rate = alpha_pll_huayra_round_rate,
1032 .set_rate = alpha_pll_huayra_set_rate,
1034 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
1036 const struct clk_ops clk_alpha_pll_hwfsm_ops = {
1037 .enable = clk_alpha_pll_hwfsm_enable,
1038 .disable = clk_alpha_pll_hwfsm_disable,
1039 .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
1040 .recalc_rate = clk_alpha_pll_recalc_rate,
1041 .round_rate = clk_alpha_pll_round_rate,
1042 .set_rate = clk_alpha_pll_hwfsm_set_rate,
1044 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
1046 const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
1047 .enable = clk_trion_pll_enable,
1048 .disable = clk_trion_pll_disable,
1049 .is_enabled = clk_trion_pll_is_enabled,
1050 .recalc_rate = clk_trion_pll_recalc_rate,
1051 .round_rate = clk_alpha_pll_round_rate,
1053 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
1055 static unsigned long
1056 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1058 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1061 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1063 ctl >>= PLL_POST_DIV_SHIFT;
1064 ctl &= PLL_POST_DIV_MASK(pll);
1066 return parent_rate >> fls(ctl);
1069 static const struct clk_div_table clk_alpha_div_table[] = {
1078 static const struct clk_div_table clk_alpha_2bit_div_table[] = {
1086 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1087 unsigned long *prate)
1089 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1090 const struct clk_div_table *table;
1092 if (pll->width == 2)
1093 table = clk_alpha_2bit_div_table;
1095 table = clk_alpha_div_table;
1097 return divider_round_rate(hw, rate, prate, table,
1098 pll->width, CLK_DIVIDER_POWER_OF_TWO);
1102 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
1103 unsigned long *prate)
1105 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1108 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1110 ctl >>= PLL_POST_DIV_SHIFT;
1111 ctl &= BIT(pll->width) - 1;
1112 div = 1 << fls(ctl);
1114 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
1115 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
1117 return DIV_ROUND_UP_ULL((u64)*prate, div);
1120 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1121 unsigned long parent_rate)
1123 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1126 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
1127 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
1129 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1130 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1131 div << PLL_POST_DIV_SHIFT);
1134 const struct clk_ops clk_alpha_pll_postdiv_ops = {
1135 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1136 .round_rate = clk_alpha_pll_postdiv_round_rate,
1137 .set_rate = clk_alpha_pll_postdiv_set_rate,
1139 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
1141 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
1142 .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
1143 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1145 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
1147 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1148 const struct alpha_pll_config *config)
1152 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1153 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha);
1154 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1155 config->config_ctl_val);
1156 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1157 config->config_ctl_hi_val);
1158 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1159 config->user_ctl_val);
1160 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1161 config->user_ctl_hi_val);
1162 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1163 config->test_ctl_val);
1164 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1165 config->test_ctl_hi_val);
1167 if (config->post_div_mask) {
1168 mask = config->post_div_mask;
1169 val = config->post_div_val;
1170 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1173 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
1174 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
1175 PLL_FSM_LEGACY_MODE);
1177 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1180 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1182 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
1184 static int alpha_pll_fabia_enable(struct clk_hw *hw)
1187 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1188 u32 val, opmode_val;
1189 struct regmap *regmap = pll->clkr.regmap;
1191 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1195 /* If in FSM mode, just vote for it */
1196 if (val & PLL_VOTE_FSM_ENA) {
1197 ret = clk_enable_regmap(hw);
1200 return wait_for_pll_enable_active(pll);
1203 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1207 /* Skip If PLL is already running */
1208 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
1211 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1215 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1219 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
1224 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1228 ret = wait_for_pll_enable_lock(pll);
1232 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1233 PLL_OUT_MASK, PLL_OUT_MASK);
1237 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
1241 static void alpha_pll_fabia_disable(struct clk_hw *hw)
1244 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1246 struct regmap *regmap = pll->clkr.regmap;
1248 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1252 /* If in FSM mode, just unvote it */
1253 if (val & PLL_FSM_ENA) {
1254 clk_disable_regmap(hw);
1258 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1262 /* Disable main outputs */
1263 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1267 /* Place the PLL in STANDBY */
1268 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1271 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
1272 unsigned long parent_rate)
1274 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1275 u32 l, frac, alpha_width = pll_alpha_width(pll);
1277 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1278 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
1280 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1284 * Due to limited number of bits for fractional rate programming, the
1285 * rounded up rate could be marginally higher than the requested rate.
1287 static int alpha_pll_check_rate_margin(struct clk_hw *hw,
1288 unsigned long rrate, unsigned long rate)
1290 unsigned long rate_margin = rate + PLL_RATE_MARGIN;
1292 if (rrate > rate_margin || rrate < rate) {
1293 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
1294 clk_hw_get_name(hw), rrate, rate, rate_margin);
1301 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1302 unsigned long prate)
1304 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1305 u32 l, alpha_width = pll_alpha_width(pll);
1306 unsigned long rrate;
1310 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1312 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1316 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1317 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1319 return __clk_alpha_pll_update_latch(pll);
1322 static int alpha_pll_fabia_prepare(struct clk_hw *hw)
1324 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1325 const struct pll_vco *vco;
1326 struct clk_hw *parent_hw;
1327 unsigned long cal_freq, rrate;
1328 u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1329 const char *name = clk_hw_get_name(hw);
1333 /* Check if calibration needs to be done i.e. PLL is in reset */
1334 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1338 /* Return early if calibration is not needed. */
1339 if (val & PLL_RESET_N)
1342 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
1344 pr_err("%s: alpha pll not in a valid vco range\n", name);
1348 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
1349 pll->vco_table[0].max_freq) * 54, 100);
1351 parent_hw = clk_hw_get_parent(hw);
1355 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw),
1356 &cal_l, &a, alpha_width);
1358 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq);
1362 /* Setup PLL for calibration frequency */
1363 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
1365 /* Bringup the PLL at calibration frequency */
1366 ret = clk_alpha_pll_enable(hw);
1368 pr_err("%s: alpha pll calibration failed\n", name);
1372 clk_alpha_pll_disable(hw);
1377 const struct clk_ops clk_alpha_pll_fabia_ops = {
1378 .prepare = alpha_pll_fabia_prepare,
1379 .enable = alpha_pll_fabia_enable,
1380 .disable = alpha_pll_fabia_disable,
1381 .is_enabled = clk_alpha_pll_is_enabled,
1382 .set_rate = alpha_pll_fabia_set_rate,
1383 .recalc_rate = alpha_pll_fabia_recalc_rate,
1384 .round_rate = clk_alpha_pll_round_rate,
1386 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1388 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1389 .enable = alpha_pll_fabia_enable,
1390 .disable = alpha_pll_fabia_disable,
1391 .is_enabled = clk_alpha_pll_is_enabled,
1392 .recalc_rate = alpha_pll_fabia_recalc_rate,
1393 .round_rate = clk_alpha_pll_round_rate,
1395 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1397 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1398 unsigned long parent_rate)
1400 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1401 u32 i, div = 1, val;
1404 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1408 val >>= pll->post_div_shift;
1409 val &= BIT(pll->width) - 1;
1411 for (i = 0; i < pll->num_post_div; i++) {
1412 if (pll->post_div_table[i].val == val) {
1413 div = pll->post_div_table[i].div;
1418 return (parent_rate / div);
1421 static unsigned long
1422 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1424 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1425 struct regmap *regmap = pll->clkr.regmap;
1426 u32 i, div = 1, val;
1428 regmap_read(regmap, PLL_USER_CTL(pll), &val);
1430 val >>= pll->post_div_shift;
1431 val &= PLL_POST_DIV_MASK(pll);
1433 for (i = 0; i < pll->num_post_div; i++) {
1434 if (pll->post_div_table[i].val == val) {
1435 div = pll->post_div_table[i].div;
1440 return (parent_rate / div);
1444 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1445 unsigned long *prate)
1447 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1449 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1450 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1454 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1455 unsigned long parent_rate)
1457 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1458 struct regmap *regmap = pll->clkr.regmap;
1459 int i, val = 0, div;
1461 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1462 for (i = 0; i < pll->num_post_div; i++) {
1463 if (pll->post_div_table[i].div == div) {
1464 val = pll->post_div_table[i].val;
1469 return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1470 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1471 val << PLL_POST_DIV_SHIFT);
1474 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
1475 .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1476 .round_rate = clk_trion_pll_postdiv_round_rate,
1477 .set_rate = clk_trion_pll_postdiv_set_rate,
1479 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
1481 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1482 unsigned long rate, unsigned long *prate)
1484 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1486 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1487 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1490 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1491 unsigned long rate, unsigned long parent_rate)
1493 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1494 int i, val = 0, div, ret;
1497 * If the PLL is in FSM mode, then treat set_rate callback as a
1500 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1504 if (val & PLL_VOTE_FSM_ENA)
1507 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1508 for (i = 0; i < pll->num_post_div; i++) {
1509 if (pll->post_div_table[i].div == div) {
1510 val = pll->post_div_table[i].val;
1515 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1516 (BIT(pll->width) - 1) << pll->post_div_shift,
1517 val << pll->post_div_shift);
1520 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1521 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1522 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1523 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1525 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
1528 * clk_trion_pll_configure - configure the trion pll
1530 * @pll: clk alpha pll
1531 * @regmap: register map
1532 * @config: configuration to apply for pll
1534 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1535 const struct alpha_pll_config *config)
1538 * If the bootloader left the PLL enabled it's likely that there are
1539 * RCGs that will lock up if we disable the PLL below.
1541 if (trion_pll_is_enabled(pll, regmap)) {
1542 pr_debug("Trion PLL is already enabled, skipping configuration\n");
1546 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1547 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1548 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1549 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1550 config->config_ctl_val);
1551 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1552 config->config_ctl_hi_val);
1553 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1554 config->config_ctl_hi1_val);
1555 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1556 config->user_ctl_val);
1557 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1558 config->user_ctl_hi_val);
1559 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1560 config->user_ctl_hi1_val);
1561 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1562 config->test_ctl_val);
1563 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1564 config->test_ctl_hi_val);
1565 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1566 config->test_ctl_hi1_val);
1568 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1571 /* Disable PLL output */
1572 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1574 /* Set operation mode to OFF */
1575 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1577 /* Place the PLL in STANDBY mode */
1578 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1580 EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
1583 * The TRION PLL requires a power-on self-calibration which happens when the
1584 * PLL comes out of reset. Calibrate in case it is not completed.
1586 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
1588 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1592 /* Return early if calibration is not needed. */
1593 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
1594 if (val & pcal_done)
1597 /* On/off to calibrate */
1598 ret = clk_trion_pll_enable(hw);
1600 clk_trion_pll_disable(hw);
1605 static int alpha_pll_trion_prepare(struct clk_hw *hw)
1607 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
1610 static int alpha_pll_lucid_prepare(struct clk_hw *hw)
1612 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
1615 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1616 unsigned long prate, u32 latch_bit, u32 latch_ack)
1618 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1619 unsigned long rrate;
1620 u32 val, l, alpha_width = pll_alpha_width(pll);
1624 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1626 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1630 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1631 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1633 /* Latch the PLL input */
1634 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);
1638 /* Wait for 2 reference cycles before checking the ACK bit. */
1640 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1641 if (!(val & latch_ack)) {
1642 pr_err("Lucid PLL latch failed. Output may be unstable!\n");
1646 /* Return the latch input to 0 */
1647 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);
1651 if (clk_hw_is_enabled(hw)) {
1652 ret = wait_for_pll_enable_lock(pll);
1657 /* Wait for PLL output to stabilize */
1662 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1663 unsigned long prate)
1665 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);
1668 const struct clk_ops clk_alpha_pll_trion_ops = {
1669 .prepare = alpha_pll_trion_prepare,
1670 .enable = clk_trion_pll_enable,
1671 .disable = clk_trion_pll_disable,
1672 .is_enabled = clk_trion_pll_is_enabled,
1673 .recalc_rate = clk_trion_pll_recalc_rate,
1674 .round_rate = clk_alpha_pll_round_rate,
1675 .set_rate = alpha_pll_trion_set_rate,
1677 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
1679 const struct clk_ops clk_alpha_pll_lucid_ops = {
1680 .prepare = alpha_pll_lucid_prepare,
1681 .enable = clk_trion_pll_enable,
1682 .disable = clk_trion_pll_disable,
1683 .is_enabled = clk_trion_pll_is_enabled,
1684 .recalc_rate = clk_trion_pll_recalc_rate,
1685 .round_rate = clk_alpha_pll_round_rate,
1686 .set_rate = alpha_pll_trion_set_rate,
1688 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
1690 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
1691 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1692 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1693 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1695 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
1697 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1698 const struct alpha_pll_config *config)
1700 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1701 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1702 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1703 config->user_ctl_val);
1704 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1705 config->config_ctl_val);
1706 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1707 config->config_ctl_hi_val);
1708 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1709 config->test_ctl_val);
1710 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1711 config->test_ctl_hi_val);
1713 EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
1715 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
1716 unsigned long prate)
1718 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1719 u32 l, alpha_width = pll_alpha_width(pll);
1721 unsigned long rrate;
1724 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1725 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1729 /* change L_VAL without having to go through the power on sequence */
1730 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1731 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1733 if (clk_hw_is_enabled(hw))
1734 return wait_for_pll_enable_lock(pll);
1739 const struct clk_ops clk_alpha_pll_agera_ops = {
1740 .enable = clk_alpha_pll_enable,
1741 .disable = clk_alpha_pll_disable,
1742 .is_enabled = clk_alpha_pll_is_enabled,
1743 .recalc_rate = alpha_pll_fabia_recalc_rate,
1744 .round_rate = clk_alpha_pll_round_rate,
1745 .set_rate = clk_alpha_pll_agera_set_rate,
1747 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
1749 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
1751 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1755 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1759 /* If in FSM mode, just vote for it */
1760 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1761 ret = clk_enable_regmap(hw);
1764 return wait_for_pll_enable_lock(pll);
1767 /* Check if PLL is already enabled, return if enabled */
1768 ret = trion_pll_is_enabled(pll, pll->clkr.regmap);
1772 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1776 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
1778 ret = wait_for_pll_enable_lock(pll);
1782 /* Enable the PLL outputs */
1783 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
1787 /* Enable the global PLL outputs */
1788 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
1791 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
1793 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1797 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1801 /* If in FSM mode, just unvote it */
1802 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1803 clk_disable_regmap(hw);
1807 /* Disable the global PLL output */
1808 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1812 /* Disable the PLL outputs */
1813 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1817 /* Place the PLL mode in STANDBY */
1818 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
1822 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1823 * when the PLL comes out of reset. Calibrate in case it is not completed.
1825 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
1827 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1832 /* Return early if calibration is not needed. */
1833 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1834 if (val & LUCID_5LPE_PCAL_DONE)
1837 p = clk_hw_get_parent(hw);
1841 ret = alpha_pll_lucid_5lpe_enable(hw);
1845 alpha_pll_lucid_5lpe_disable(hw);
1850 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
1851 unsigned long prate)
1853 return __alpha_pll_trion_set_rate(hw, rate, prate,
1854 LUCID_5LPE_PLL_LATCH_INPUT,
1855 LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
1858 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1859 unsigned long parent_rate,
1860 unsigned long enable_vote_run)
1862 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1863 struct regmap *regmap = pll->clkr.regmap;
1864 int i, val, div, ret;
1868 * If the PLL is in FSM mode, then treat set_rate callback as a
1871 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
1875 if (val & enable_vote_run)
1878 if (!pll->post_div_table) {
1879 pr_err("Missing the post_div_table for the %s PLL\n",
1880 clk_hw_get_name(&pll->clkr.hw));
1884 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1885 for (i = 0; i < pll->num_post_div; i++) {
1886 if (pll->post_div_table[i].div == div) {
1887 val = pll->post_div_table[i].val;
1892 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
1893 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1894 mask, val << pll->post_div_shift);
1897 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1898 unsigned long parent_rate)
1900 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
1903 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
1904 .prepare = alpha_pll_lucid_5lpe_prepare,
1905 .enable = alpha_pll_lucid_5lpe_enable,
1906 .disable = alpha_pll_lucid_5lpe_disable,
1907 .is_enabled = clk_trion_pll_is_enabled,
1908 .recalc_rate = clk_trion_pll_recalc_rate,
1909 .round_rate = clk_alpha_pll_round_rate,
1910 .set_rate = alpha_pll_lucid_5lpe_set_rate,
1912 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
1914 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
1915 .enable = alpha_pll_lucid_5lpe_enable,
1916 .disable = alpha_pll_lucid_5lpe_disable,
1917 .is_enabled = clk_trion_pll_is_enabled,
1918 .recalc_rate = clk_trion_pll_recalc_rate,
1919 .round_rate = clk_alpha_pll_round_rate,
1921 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
1923 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
1924 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1925 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1926 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
1928 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
1930 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1931 const struct alpha_pll_config *config)
1933 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1934 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1935 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
1936 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
1937 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
1938 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
1939 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
1940 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
1941 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
1942 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
1943 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
1945 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);
1947 /* Disable PLL output */
1948 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1950 /* Set operation mode to OFF */
1951 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1953 /* Place the PLL in STANDBY mode */
1954 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1956 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure);
1958 static int clk_zonda_pll_enable(struct clk_hw *hw)
1960 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1961 struct regmap *regmap = pll->clkr.regmap;
1965 regmap_read(regmap, PLL_MODE(pll), &val);
1967 /* If in FSM mode, just vote for it */
1968 if (val & PLL_VOTE_FSM_ENA) {
1969 ret = clk_enable_regmap(hw);
1972 return wait_for_pll_enable_active(pll);
1975 /* Get the PLL out of bypass mode */
1976 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
1979 * H/W requires a 1us delay between disabling the bypass and
1980 * de-asserting the reset.
1984 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1986 /* Set operation mode to RUN */
1987 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1989 regmap_read(regmap, PLL_TEST_CTL(pll), &val);
1991 /* If cfa mode then poll for freq lock */
1992 if (val & ZONDA_STAY_IN_CFA)
1993 ret = wait_for_zonda_pll_freq_lock(pll);
1995 ret = wait_for_pll_enable_lock(pll);
1999 /* Enable the PLL outputs */
2000 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
2002 /* Enable the global PLL outputs */
2003 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2008 static void clk_zonda_pll_disable(struct clk_hw *hw)
2010 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2011 struct regmap *regmap = pll->clkr.regmap;
2014 regmap_read(regmap, PLL_MODE(pll), &val);
2016 /* If in FSM mode, just unvote it */
2017 if (val & PLL_VOTE_FSM_ENA) {
2018 clk_disable_regmap(hw);
2022 /* Disable the global PLL output */
2023 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2025 /* Disable the PLL outputs */
2026 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
2028 /* Put the PLL in bypass and reset */
2029 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
2031 /* Place the PLL mode in OFF state */
2032 regmap_write(regmap, PLL_OPMODE(pll), 0x0);
2035 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
2036 unsigned long prate)
2038 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2039 unsigned long rrate;
2041 u32 l, alpha_width = pll_alpha_width(pll);
2045 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2047 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
2051 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2052 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2054 /* Wait before polling for the frequency latch */
2057 /* Read stay in cfa mode */
2058 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
2060 /* If cfa mode then poll for freq lock */
2061 if (test_ctl_val & ZONDA_STAY_IN_CFA)
2062 ret = wait_for_zonda_pll_freq_lock(pll);
2064 ret = wait_for_pll_enable_lock(pll);
2068 /* Wait for PLL output to stabilize */
2073 const struct clk_ops clk_alpha_pll_zonda_ops = {
2074 .enable = clk_zonda_pll_enable,
2075 .disable = clk_zonda_pll_disable,
2076 .is_enabled = clk_trion_pll_is_enabled,
2077 .recalc_rate = clk_trion_pll_recalc_rate,
2078 .round_rate = clk_alpha_pll_round_rate,
2079 .set_rate = clk_zonda_pll_set_rate,
2081 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
2083 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2084 const struct alpha_pll_config *config)
2086 u32 lval = config->l;
2088 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2089 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2090 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2091 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2092 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2093 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2094 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2095 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2096 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2097 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2098 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2100 /* Disable PLL output */
2101 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2103 /* Set operation mode to STANDBY and de-assert the reset */
2104 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2105 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2107 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
2109 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
2111 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2112 struct regmap *regmap = pll->clkr.regmap;
2116 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2120 /* If in FSM mode, just vote for it */
2121 if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2122 ret = clk_enable_regmap(hw);
2125 return wait_for_pll_enable_lock(pll);
2128 /* Check if PLL is already enabled */
2129 ret = trion_pll_is_enabled(pll, regmap);
2133 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw));
2137 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2141 /* Set operation mode to RUN */
2142 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2144 ret = wait_for_pll_enable_lock(pll);
2148 /* Enable the PLL outputs */
2149 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
2153 /* Enable the global PLL outputs */
2154 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2158 /* Ensure that the write above goes through before returning. */
2163 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset)
2165 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2166 struct regmap *regmap = pll->clkr.regmap;
2170 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2174 /* If in FSM mode, just unvote it */
2175 if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2176 clk_disable_regmap(hw);
2180 /* Disable the global PLL output */
2181 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2185 /* Disable the PLL outputs */
2186 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
2190 /* Place the PLL mode in STANDBY */
2191 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2194 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0);
2197 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset)
2199 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2204 /* Return early if calibration is not needed. */
2205 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
2206 if (!(val & LUCID_EVO_PCAL_NOT_DONE))
2209 p = clk_hw_get_parent(hw);
2213 ret = alpha_pll_lucid_evo_enable(hw);
2217 _alpha_pll_lucid_evo_disable(hw, reset);
2222 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
2224 _alpha_pll_lucid_evo_disable(hw, false);
2227 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
2229 return _alpha_pll_lucid_evo_prepare(hw, false);
2232 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw)
2234 _alpha_pll_lucid_evo_disable(hw, true);
2237 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw)
2239 return _alpha_pll_lucid_evo_prepare(hw, true);
2242 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
2243 unsigned long parent_rate)
2245 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2246 struct regmap *regmap = pll->clkr.regmap;
2249 regmap_read(regmap, PLL_L_VAL(pll), &l);
2250 l &= LUCID_EVO_PLL_L_VAL_MASK;
2251 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
2253 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
2256 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2257 unsigned long parent_rate)
2259 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
2262 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
2263 .enable = alpha_pll_lucid_evo_enable,
2264 .disable = alpha_pll_lucid_evo_disable,
2265 .is_enabled = clk_trion_pll_is_enabled,
2266 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2267 .round_rate = clk_alpha_pll_round_rate,
2269 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
2271 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
2272 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2273 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2274 .set_rate = clk_lucid_evo_pll_postdiv_set_rate,
2276 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
2278 const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
2279 .prepare = alpha_pll_lucid_evo_prepare,
2280 .enable = alpha_pll_lucid_evo_enable,
2281 .disable = alpha_pll_lucid_evo_disable,
2282 .is_enabled = clk_trion_pll_is_enabled,
2283 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2284 .round_rate = clk_alpha_pll_round_rate,
2285 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2287 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
2289 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
2290 .prepare = alpha_pll_reset_lucid_evo_prepare,
2291 .enable = alpha_pll_lucid_evo_enable,
2292 .disable = alpha_pll_reset_lucid_evo_disable,
2293 .is_enabled = clk_trion_pll_is_enabled,
2294 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2295 .round_rate = clk_alpha_pll_round_rate,
2296 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2298 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
2300 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2301 const struct alpha_pll_config *config)
2303 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2304 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2305 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2306 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2307 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2308 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2309 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2310 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2312 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2314 regmap_update_bits(regmap, PLL_MODE(pll),
2315 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL,
2316 PLL_RESET_N | PLL_BYPASSNL);
2318 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure);
2320 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
2321 unsigned long parent_rate)
2323 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2326 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
2328 return parent_rate * l;
2331 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
2332 unsigned long *prate)
2334 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2335 unsigned long min_freq, max_freq;
2339 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
2340 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
2343 min_freq = pll->vco_table[0].min_freq;
2344 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
2346 return clamp(rate, min_freq, max_freq);
2349 const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
2350 .enable = alpha_pll_lucid_5lpe_enable,
2351 .disable = alpha_pll_lucid_5lpe_disable,
2352 .is_enabled = clk_trion_pll_is_enabled,
2353 .recalc_rate = clk_rivian_evo_pll_recalc_rate,
2354 .round_rate = clk_rivian_evo_pll_round_rate,
2356 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
2358 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2359 const struct alpha_pll_config *config)
2361 u32 val, val_u, mask, mask_u;
2363 regmap_write(regmap, PLL_L_VAL(pll), config->l);
2364 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2365 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2367 if (pll_has_64bit_config(pll))
2368 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
2369 config->config_ctl_hi_val);
2371 if (pll_alpha_width(pll) > 32)
2372 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
2374 val = config->main_output_mask;
2375 val |= config->aux_output_mask;
2376 val |= config->aux2_output_mask;
2377 val |= config->early_output_mask;
2378 val |= config->pre_div_val;
2379 val |= config->post_div_val;
2380 val |= config->vco_val;
2381 val |= config->alpha_en_mask;
2382 val |= config->alpha_mode_mask;
2384 mask = config->main_output_mask;
2385 mask |= config->aux_output_mask;
2386 mask |= config->aux2_output_mask;
2387 mask |= config->early_output_mask;
2388 mask |= config->pre_div_mask;
2389 mask |= config->post_div_mask;
2390 mask |= config->vco_mask;
2391 mask |= config->alpha_en_mask;
2392 mask |= config->alpha_mode_mask;
2394 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
2396 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
2397 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT;
2398 val_u |= config->lock_det;
2400 mask_u = config->status_mask;
2401 mask_u |= config->lock_det;
2403 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
2404 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2405 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2407 if (pll->flags & SUPPORTS_FSM_MODE)
2408 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
2410 EXPORT_SYMBOL_GPL(clk_stromer_pll_configure);
2412 static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
2413 struct clk_rate_request *req)
2418 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate,
2419 &l, &a, ALPHA_REG_BITWIDTH);
2424 static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
2425 unsigned long prate)
2427 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2432 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
2434 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2435 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2436 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2437 a >> ALPHA_BITWIDTH);
2439 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2440 PLL_ALPHA_EN, PLL_ALPHA_EN);
2442 if (!clk_hw_is_enabled(hw))
2446 * Stromer PLL supports Dynamic programming.
2447 * It allows the PLL frequency to be changed on-the-fly without first
2448 * execution of a shutdown procedure followed by a bring up procedure.
2450 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
2453 ret = wait_for_pll_update(pll);
2457 return wait_for_pll_enable_lock(pll);
2460 const struct clk_ops clk_alpha_pll_stromer_ops = {
2461 .enable = clk_alpha_pll_enable,
2462 .disable = clk_alpha_pll_disable,
2463 .is_enabled = clk_alpha_pll_is_enabled,
2464 .recalc_rate = clk_alpha_pll_recalc_rate,
2465 .determine_rate = clk_alpha_pll_stromer_determine_rate,
2466 .set_rate = clk_alpha_pll_stromer_set_rate,
2468 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);