1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell PXA family clocks
5 * Copyright (C) 2014 Robert Jarzmik
7 * Common clock code for PXA clocks ("CKEN" type clocks + DT)
10 #include <linux/clk-provider.h>
11 #include <linux/clkdev.h>
14 #include <linux/soc/pxa/smemc.h>
16 #include <dt-bindings/clock/pxa-clock.h>
20 #define MHz (1000 * 1000)
22 #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
23 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
24 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
25 #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
26 #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
27 #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
28 #define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
29 #define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
30 #define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
31 #define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
32 #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
33 #define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
34 #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
35 #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
36 #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
37 #define MDREFR_DRI_MASK 0xFFF
39 static DEFINE_SPINLOCK(pxa_clk_lock);
41 static struct clk *pxa_clocks[CLK_MAX];
42 static struct clk_onecell_data onecell_data = {
49 struct clk_fixed_factor lp;
50 struct clk_fixed_factor hp;
52 bool (*is_in_low_power)(void);
55 #define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk, hw)
57 static unsigned long cken_recalc_rate(struct clk_hw *hw,
58 unsigned long parent_rate)
60 struct pxa_clk *pclk = to_pxa_clk(hw);
61 struct clk_fixed_factor *fix;
63 if (!pclk->is_in_low_power || pclk->is_in_low_power())
67 __clk_hw_set_clk(&fix->hw, hw);
68 return clk_fixed_factor_ops.recalc_rate(&fix->hw, parent_rate);
71 static const struct clk_ops cken_rate_ops = {
72 .recalc_rate = cken_recalc_rate,
75 static u8 cken_get_parent(struct clk_hw *hw)
77 struct pxa_clk *pclk = to_pxa_clk(hw);
79 if (!pclk->is_in_low_power)
81 return pclk->is_in_low_power() ? 0 : 1;
84 static const struct clk_ops cken_mux_ops = {
85 .get_parent = cken_get_parent,
86 .set_parent = dummy_clk_set_parent,
89 void __init clkdev_pxa_register(int ckid, const char *con_id,
90 const char *dev_id, struct clk *clk)
92 if (!IS_ERR(clk) && (ckid != CLK_NONE))
93 pxa_clocks[ckid] = clk;
95 clk_register_clkdev(clk, con_id, dev_id);
98 int __init clk_pxa_cken_init(const struct desc_clk_cken *clks,
99 int nb_clks, void __iomem *clk_regs)
102 struct pxa_clk *pxa_clk;
105 for (i = 0; i < nb_clks; i++) {
106 pxa_clk = kzalloc(sizeof(*pxa_clk), GFP_KERNEL);
109 pxa_clk->is_in_low_power = clks[i].is_in_low_power;
110 pxa_clk->lp = clks[i].lp;
111 pxa_clk->hp = clks[i].hp;
112 pxa_clk->gate = clks[i].gate;
113 pxa_clk->gate.reg = clk_regs + clks[i].cken_reg;
114 pxa_clk->gate.lock = &pxa_clk_lock;
115 clk = clk_register_composite(NULL, clks[i].name,
116 clks[i].parent_names, 2,
117 &pxa_clk->hw, &cken_mux_ops,
118 &pxa_clk->hw, &cken_rate_ops,
119 &pxa_clk->gate.hw, &clk_gate_ops,
121 clkdev_pxa_register(clks[i].ckid, clks[i].con_id,
122 clks[i].dev_id, clk);
127 void __init clk_pxa_dt_common_init(struct device_node *np)
129 of_clk_add_provider(np, of_clk_src_onecell_get, &onecell_data);
132 void pxa2xx_core_turbo_switch(bool on)
135 unsigned int unused, clkcfg;
137 local_irq_save(flags);
139 asm("mrc p14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
140 clkcfg &= ~CLKCFG_TURBO & ~CLKCFG_HALFTURBO;
142 clkcfg |= CLKCFG_TURBO;
143 clkcfg |= CLKCFG_FCS;
148 "1: mcr p14, 0, %1, c6, c0, 0\n"
152 : "=&r" (unused) : "r" (clkcfg));
154 local_irq_restore(flags);
157 void pxa2xx_cpll_change(struct pxa2xx_freq *freq,
158 u32 (*mdrefr_dri)(unsigned int),
161 unsigned int clkcfg = freq->clkcfg;
162 unsigned int unused, preset_mdrefr, postset_mdrefr;
164 void __iomem *mdrefr = pxa_smemc_get_mdrefr();
166 local_irq_save(flags);
168 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
169 * we need to preset the smaller DRI before the change. If we're
170 * speeding up we need to set the larger DRI value after the change.
172 preset_mdrefr = postset_mdrefr = readl(mdrefr);
173 if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(freq->membus_khz)) {
174 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
175 preset_mdrefr |= mdrefr_dri(freq->membus_khz);
178 (postset_mdrefr & ~MDREFR_DRI_MASK) |
179 mdrefr_dri(freq->membus_khz);
181 /* If we're dividing the memory clock by two for the SDRAM clock, this
182 * must be set prior to the change. Clearing the divide must be done
186 preset_mdrefr |= MDREFR_DB2_MASK;
187 postset_mdrefr |= MDREFR_DB2_MASK;
189 postset_mdrefr &= ~MDREFR_DB2_MASK;
192 /* Set new the CCCR and prepare CLKCFG */
193 writel(freq->cccr, cccr);
199 "1: str %3, [%1] /* preset the MDREFR */\n"
200 " mcr p14, 0, %2, c6, c0, 0 /* set CLKCFG[FCS] */\n"
201 " str %4, [%1] /* postset the MDREFR */\n"
206 : "r" (mdrefr), "r" (clkcfg), "r" (preset_mdrefr),
210 local_irq_restore(flags);
213 int pxa2xx_determine_rate(struct clk_rate_request *req,
214 struct pxa2xx_freq *freqs, int nb_freqs)
216 int i, closest_below = -1, closest_above = -1;
219 for (i = 0; i < nb_freqs; i++) {
220 rate = freqs[i].cpll;
221 if (rate == req->rate)
223 if (rate < req->min_rate)
225 if (rate > req->max_rate)
227 if (rate <= req->rate)
229 if ((rate >= req->rate) && (closest_above == -1))
233 req->best_parent_hw = NULL;
237 } else if (closest_below >= 0) {
238 rate = freqs[closest_below].cpll;
239 } else if (closest_above >= 0) {
240 rate = freqs[closest_above].cpll;
242 pr_debug("%s(rate=%lu) no match\n", __func__, req->rate);
246 pr_debug("%s(rate=%lu) rate=%lu\n", __func__, req->rate, rate);