1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell Armada 37xx SoC Peripheral clocks
5 * Copyright (C) 2016 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Most of the peripheral clocks can be modelled like this:
10 * _____ _______ _______
11 * TBG-A-P --| | | | | | ______
12 * TBG-B-P --| Mux |--| /div1 |--| /div2 |--| Gate |--> perip_clk
13 * TBG-A-S --| | | | | | |______|
14 * TBG-B-S --|_____| |_______| |_______|
16 * However some clocks may use only one or two block or and use the
17 * xtal clock as parent.
20 #include <linux/clk-provider.h>
22 #include <linux/mfd/syscon.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/regmap.h>
27 #include <linux/slab.h>
36 #define ARMADA_37XX_DVFS_LOAD_1 1
37 #define LOAD_LEVEL_NR 4
39 #define ARMADA_37XX_NB_L0L1 0x18
40 #define ARMADA_37XX_NB_L2L3 0x1C
41 #define ARMADA_37XX_NB_TBG_DIV_OFF 13
42 #define ARMADA_37XX_NB_TBG_DIV_MASK 0x7
43 #define ARMADA_37XX_NB_CLK_SEL_OFF 11
44 #define ARMADA_37XX_NB_CLK_SEL_MASK 0x1
45 #define ARMADA_37XX_NB_TBG_SEL_OFF 9
46 #define ARMADA_37XX_NB_TBG_SEL_MASK 0x3
47 #define ARMADA_37XX_NB_CONFIG_SHIFT 16
48 #define ARMADA_37XX_NB_DYN_MOD 0x24
49 #define ARMADA_37XX_NB_DFS_EN 31
50 #define ARMADA_37XX_NB_CPU_LOAD 0x30
51 #define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3
52 #define ARMADA_37XX_DVFS_LOAD_0 0
53 #define ARMADA_37XX_DVFS_LOAD_1 1
54 #define ARMADA_37XX_DVFS_LOAD_2 2
55 #define ARMADA_37XX_DVFS_LOAD_3 3
57 struct clk_periph_driver_data {
58 struct clk_hw_onecell_data *hw_data;
62 /* Storage registers for suspend/resume operations */
71 struct clk_double_div {
81 void __iomem *reg_mux;
84 void __iomem *reg_div;
86 struct regmap *nb_pm_base;
89 #define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw)
90 #define to_clk_pm_cpu(_hw) container_of(_hw, struct clk_pm_cpu, hw)
92 struct clk_periph_data {
94 const char * const *parent_names;
96 struct clk_hw *mux_hw;
97 struct clk_hw *rate_hw;
98 struct clk_hw *gate_hw;
99 struct clk_hw *muxrate_hw;
103 static const struct clk_div_table clk_table6[] = {
104 { .val = 1, .div = 1, },
105 { .val = 2, .div = 2, },
106 { .val = 3, .div = 3, },
107 { .val = 4, .div = 4, },
108 { .val = 5, .div = 5, },
109 { .val = 6, .div = 6, },
110 { .val = 0, .div = 0, }, /* last entry */
113 static const struct clk_div_table clk_table1[] = {
114 { .val = 0, .div = 1, },
115 { .val = 1, .div = 2, },
116 { .val = 0, .div = 0, }, /* last entry */
119 static const struct clk_div_table clk_table2[] = {
120 { .val = 0, .div = 2, },
121 { .val = 1, .div = 4, },
122 { .val = 0, .div = 0, }, /* last entry */
125 static const struct clk_ops clk_double_div_ops;
126 static const struct clk_ops clk_pm_cpu_ops;
128 #define PERIPH_GATE(_name, _bit) \
129 struct clk_gate gate_##_name = { \
130 .reg = (void *)CLK_DIS, \
132 .hw.init = &(struct clk_init_data){ \
133 .ops = &clk_gate_ops, \
137 #define PERIPH_MUX(_name, _shift) \
138 struct clk_mux mux_##_name = { \
139 .reg = (void *)TBG_SEL, \
142 .hw.init = &(struct clk_init_data){ \
143 .ops = &clk_mux_ro_ops, \
147 #define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \
148 struct clk_double_div rate_##_name = { \
149 .reg1 = (void *)_reg1, \
150 .reg2 = (void *)_reg2, \
153 .hw.init = &(struct clk_init_data){ \
154 .ops = &clk_double_div_ops, \
158 #define PERIPH_DIV(_name, _reg, _shift, _table) \
159 struct clk_divider rate_##_name = { \
160 .reg = (void *)_reg, \
163 .hw.init = &(struct clk_init_data){ \
164 .ops = &clk_divider_ro_ops, \
168 #define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \
169 struct clk_pm_cpu muxrate_##_name = { \
170 .reg_mux = (void *)TBG_SEL, \
172 .shift_mux = _shift1, \
173 .reg_div = (void *)_reg, \
174 .shift_div = _shift2, \
175 .hw.init = &(struct clk_init_data){ \
176 .ops = &clk_pm_cpu_ops, \
180 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\
181 static PERIPH_GATE(_name, _bit); \
182 static PERIPH_MUX(_name, _shift); \
183 static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
185 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \
186 static PERIPH_GATE(_name, _bit); \
187 static PERIPH_MUX(_name, _shift); \
188 static PERIPH_DIV(_name, _reg, _shift1, _table);
190 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \
191 static PERIPH_GATE(_name, _bit); \
192 static PERIPH_DIV(_name, _reg, _shift, _table);
194 #define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\
195 static PERIPH_MUX(_name, _shift); \
196 static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
198 #define REF_CLK_FULL(_name) \
200 .parent_names = (const char *[]){ "TBG-A-P", \
201 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
203 .mux_hw = &mux_##_name.hw, \
204 .gate_hw = &gate_##_name.hw, \
205 .rate_hw = &rate_##_name.hw, \
208 #define REF_CLK_FULL_DD(_name) \
210 .parent_names = (const char *[]){ "TBG-A-P", \
211 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
213 .mux_hw = &mux_##_name.hw, \
214 .gate_hw = &gate_##_name.hw, \
215 .rate_hw = &rate_##_name.hw, \
216 .is_double_div = true, \
219 #define REF_CLK_GATE(_name, _parent_name) \
221 .parent_names = (const char *[]){ _parent_name}, \
223 .gate_hw = &gate_##_name.hw, \
226 #define REF_CLK_GATE_DIV(_name, _parent_name) \
228 .parent_names = (const char *[]){ _parent_name}, \
230 .gate_hw = &gate_##_name.hw, \
231 .rate_hw = &rate_##_name.hw, \
234 #define REF_CLK_PM_CPU(_name) \
236 .parent_names = (const char *[]){ "TBG-A-P", \
237 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
239 .muxrate_hw = &muxrate_##_name.hw, \
242 #define REF_CLK_MUX_DD(_name) \
244 .parent_names = (const char *[]){ "TBG-A-P", \
245 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
247 .mux_hw = &mux_##_name.hw, \
248 .rate_hw = &rate_##_name.hw, \
249 .is_double_div = true, \
252 /* NB periph clocks */
253 PERIPH_CLK_FULL_DD(mmc, 2, 0, DIV_SEL2, DIV_SEL2, 16, 13);
254 PERIPH_CLK_FULL_DD(sata_host, 3, 2, DIV_SEL2, DIV_SEL2, 10, 7);
255 PERIPH_CLK_FULL_DD(sec_at, 6, 4, DIV_SEL1, DIV_SEL1, 3, 0);
256 PERIPH_CLK_FULL_DD(sec_dap, 7, 6, DIV_SEL1, DIV_SEL1, 9, 6);
257 PERIPH_CLK_FULL_DD(tscem, 8, 8, DIV_SEL1, DIV_SEL1, 15, 12);
258 PERIPH_CLK_FULL(tscem_tmx, 10, 10, DIV_SEL1, 18, clk_table6);
259 static PERIPH_GATE(avs, 11);
260 PERIPH_CLK_FULL_DD(pwm, 13, 14, DIV_SEL0, DIV_SEL0, 3, 0);
261 PERIPH_CLK_FULL_DD(sqf, 12, 12, DIV_SEL1, DIV_SEL1, 27, 24);
262 static PERIPH_GATE(i2c_2, 16);
263 static PERIPH_GATE(i2c_1, 17);
264 PERIPH_CLK_GATE_DIV(ddr_phy, 19, DIV_SEL0, 18, clk_table2);
265 PERIPH_CLK_FULL_DD(ddr_fclk, 21, 16, DIV_SEL0, DIV_SEL0, 15, 12);
266 PERIPH_CLK_FULL(trace, 22, 18, DIV_SEL0, 20, clk_table6);
267 PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL0, 23, clk_table6);
268 PERIPH_CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19);
269 static PERIPH_PM_CPU(cpu, 22, DIV_SEL0, 28);
271 static struct clk_periph_data data_nb[] = {
272 REF_CLK_FULL_DD(mmc),
273 REF_CLK_FULL_DD(sata_host),
274 REF_CLK_FULL_DD(sec_at),
275 REF_CLK_FULL_DD(sec_dap),
276 REF_CLK_FULL_DD(tscem),
277 REF_CLK_FULL(tscem_tmx),
278 REF_CLK_GATE(avs, "xtal"),
279 REF_CLK_FULL_DD(sqf),
280 REF_CLK_FULL_DD(pwm),
281 REF_CLK_GATE(i2c_2, "xtal"),
282 REF_CLK_GATE(i2c_1, "xtal"),
283 REF_CLK_GATE_DIV(ddr_phy, "TBG-A-S"),
284 REF_CLK_FULL_DD(ddr_fclk),
286 REF_CLK_FULL(counter),
287 REF_CLK_FULL_DD(eip97),
292 /* SB periph clocks */
293 PERIPH_CLK_MUX_DD(gbe_50, 6, DIV_SEL2, DIV_SEL2, 6, 9);
294 PERIPH_CLK_MUX_DD(gbe_core, 8, DIV_SEL1, DIV_SEL1, 18, 21);
295 PERIPH_CLK_MUX_DD(gbe_125, 10, DIV_SEL1, DIV_SEL1, 6, 9);
296 static PERIPH_GATE(gbe1_50, 0);
297 static PERIPH_GATE(gbe0_50, 1);
298 static PERIPH_GATE(gbe1_125, 2);
299 static PERIPH_GATE(gbe0_125, 3);
300 PERIPH_CLK_GATE_DIV(gbe1_core, 4, DIV_SEL1, 13, clk_table1);
301 PERIPH_CLK_GATE_DIV(gbe0_core, 5, DIV_SEL1, 14, clk_table1);
302 PERIPH_CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, clk_table1);
303 PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6);
304 PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12);
305 PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18);
307 static struct clk_periph_data data_sb[] = {
308 REF_CLK_MUX_DD(gbe_50),
309 REF_CLK_MUX_DD(gbe_core),
310 REF_CLK_MUX_DD(gbe_125),
311 REF_CLK_GATE(gbe1_50, "gbe_50"),
312 REF_CLK_GATE(gbe0_50, "gbe_50"),
313 REF_CLK_GATE(gbe1_125, "gbe_125"),
314 REF_CLK_GATE(gbe0_125, "gbe_125"),
315 REF_CLK_GATE_DIV(gbe1_core, "gbe_core"),
316 REF_CLK_GATE_DIV(gbe0_core, "gbe_core"),
317 REF_CLK_GATE_DIV(gbe_bm, "gbe_core"),
318 REF_CLK_FULL_DD(sdio),
319 REF_CLK_FULL_DD(usb32_usb2_sys),
320 REF_CLK_FULL_DD(usb32_ss_sys),
324 static unsigned int get_div(void __iomem *reg, int shift)
328 val = (readl(reg) >> shift) & 0x7;
334 static unsigned long clk_double_div_recalc_rate(struct clk_hw *hw,
335 unsigned long parent_rate)
337 struct clk_double_div *double_div = to_clk_double_div(hw);
340 div = get_div(double_div->reg1, double_div->shift1);
341 div *= get_div(double_div->reg2, double_div->shift2);
343 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
346 static const struct clk_ops clk_double_div_ops = {
347 .recalc_rate = clk_double_div_recalc_rate,
350 static void armada_3700_pm_dvfs_update_regs(unsigned int load_level,
352 unsigned int *offset)
354 if (load_level <= ARMADA_37XX_DVFS_LOAD_1)
355 *reg = ARMADA_37XX_NB_L0L1;
357 *reg = ARMADA_37XX_NB_L2L3;
359 if (load_level == ARMADA_37XX_DVFS_LOAD_0 ||
360 load_level == ARMADA_37XX_DVFS_LOAD_2)
361 *offset += ARMADA_37XX_NB_CONFIG_SHIFT;
364 static bool armada_3700_pm_dvfs_is_enabled(struct regmap *base)
366 unsigned int val, reg = ARMADA_37XX_NB_DYN_MOD;
371 regmap_read(base, reg, &val);
373 return !!(val & BIT(ARMADA_37XX_NB_DFS_EN));
376 static unsigned int armada_3700_pm_dvfs_get_cpu_div(struct regmap *base)
378 unsigned int reg = ARMADA_37XX_NB_CPU_LOAD;
379 unsigned int offset = ARMADA_37XX_NB_TBG_DIV_OFF;
380 unsigned int load_level, div;
383 * This function is always called after the function
384 * armada_3700_pm_dvfs_is_enabled, so no need to check again
385 * if the base is valid.
387 regmap_read(base, reg, &load_level);
390 * The register and the offset inside this register accessed to
391 * read the current divider depend on the load level
393 load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
394 armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
396 regmap_read(base, reg, &div);
398 return (div >> offset) & ARMADA_37XX_NB_TBG_DIV_MASK;
401 static unsigned int armada_3700_pm_dvfs_get_cpu_parent(struct regmap *base)
403 unsigned int reg = ARMADA_37XX_NB_CPU_LOAD;
404 unsigned int offset = ARMADA_37XX_NB_TBG_SEL_OFF;
405 unsigned int load_level, sel;
408 * This function is always called after the function
409 * armada_3700_pm_dvfs_is_enabled, so no need to check again
410 * if the base is valid
412 regmap_read(base, reg, &load_level);
415 * The register and the offset inside this register accessed to
416 * read the current divider depend on the load level
418 load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
419 armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
421 regmap_read(base, reg, &sel);
423 return (sel >> offset) & ARMADA_37XX_NB_TBG_SEL_MASK;
426 static u8 clk_pm_cpu_get_parent(struct clk_hw *hw)
428 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
431 if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base)) {
432 val = armada_3700_pm_dvfs_get_cpu_parent(pm_cpu->nb_pm_base);
434 val = readl(pm_cpu->reg_mux) >> pm_cpu->shift_mux;
435 val &= pm_cpu->mask_mux;
441 static int clk_pm_cpu_set_parent(struct clk_hw *hw, u8 index)
443 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
444 struct regmap *base = pm_cpu->nb_pm_base;
448 * We set the clock parent only if the DVFS is available but
451 if (IS_ERR(base) || armada_3700_pm_dvfs_is_enabled(base))
454 /* Set the parent clock for all the load level */
455 for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
456 unsigned int reg, mask, val,
457 offset = ARMADA_37XX_NB_TBG_SEL_OFF;
459 armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
461 val = index << offset;
462 mask = ARMADA_37XX_NB_TBG_SEL_MASK << offset;
463 regmap_update_bits(base, reg, mask, val);
468 static unsigned long clk_pm_cpu_recalc_rate(struct clk_hw *hw,
469 unsigned long parent_rate)
471 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
474 if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base))
475 div = armada_3700_pm_dvfs_get_cpu_div(pm_cpu->nb_pm_base);
477 div = get_div(pm_cpu->reg_div, pm_cpu->shift_div);
478 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
481 static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
482 unsigned long *parent_rate)
484 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
485 struct regmap *base = pm_cpu->nb_pm_base;
486 unsigned int div = *parent_rate / rate;
487 unsigned int load_level;
488 /* only available when DVFS is enabled */
489 if (!armada_3700_pm_dvfs_is_enabled(base))
492 for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
493 unsigned int reg, val, offset = ARMADA_37XX_NB_TBG_DIV_OFF;
495 armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
497 regmap_read(base, reg, &val);
500 val &= ARMADA_37XX_NB_TBG_DIV_MASK;
503 * We found a load level matching the target
504 * divider, switch to this load level and
507 return *parent_rate / div;
510 /* We didn't find any valid divider */
515 * Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz
516 * respectively) to L0 frequency (1.2 Ghz) requires a significant
517 * amount of time to let VDD stabilize to the appropriate
518 * voltage. This amount of time is large enough that it cannot be
519 * covered by the hardware countdown register. Due to this, the CPU
520 * might start operating at L0 before the voltage is stabilized,
521 * leading to CPU stalls.
523 * To work around this problem, we prevent switching directly from the
524 * L2/L3 frequencies to the L0 frequency, and instead switch to the L1
525 * frequency in-between. The sequence therefore becomes:
526 * 1. First switch from L2/L3(200/300MHz) to L1(600MHZ)
527 * 2. Sleep 20ms for stabling VDD voltage
528 * 3. Then switch from L1(600MHZ) to L0(1200Mhz).
530 static void clk_pm_cpu_set_rate_wa(unsigned long rate, struct regmap *base)
532 unsigned int cur_level;
534 if (rate != 1200 * 1000 * 1000)
537 regmap_read(base, ARMADA_37XX_NB_CPU_LOAD, &cur_level);
538 cur_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
539 if (cur_level <= ARMADA_37XX_DVFS_LOAD_1)
542 regmap_update_bits(base, ARMADA_37XX_NB_CPU_LOAD,
543 ARMADA_37XX_NB_CPU_LOAD_MASK,
544 ARMADA_37XX_DVFS_LOAD_1);
548 static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
549 unsigned long parent_rate)
551 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
552 struct regmap *base = pm_cpu->nb_pm_base;
553 unsigned int div = parent_rate / rate;
554 unsigned int load_level;
556 /* only available when DVFS is enabled */
557 if (!armada_3700_pm_dvfs_is_enabled(base))
560 for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
561 unsigned int reg, mask, val,
562 offset = ARMADA_37XX_NB_TBG_DIV_OFF;
564 armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
566 regmap_read(base, reg, &val);
568 val &= ARMADA_37XX_NB_TBG_DIV_MASK;
572 * We found a load level matching the target
573 * divider, switch to this load level and
576 reg = ARMADA_37XX_NB_CPU_LOAD;
577 mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
579 clk_pm_cpu_set_rate_wa(rate, base);
581 regmap_update_bits(base, reg, mask, load_level);
587 /* We didn't find any valid divider */
591 static const struct clk_ops clk_pm_cpu_ops = {
592 .get_parent = clk_pm_cpu_get_parent,
593 .set_parent = clk_pm_cpu_set_parent,
594 .round_rate = clk_pm_cpu_round_rate,
595 .set_rate = clk_pm_cpu_set_rate,
596 .recalc_rate = clk_pm_cpu_recalc_rate,
599 static const struct of_device_id armada_3700_periph_clock_of_match[] = {
600 { .compatible = "marvell,armada-3700-periph-clock-nb",
602 { .compatible = "marvell,armada-3700-periph-clock-sb",
607 static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
608 void __iomem *reg, spinlock_t *lock,
609 struct device *dev, struct clk_hw **hw)
611 const struct clk_ops *mux_ops = NULL, *gate_ops = NULL,
613 struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *rate_hw = NULL;
618 mux_hw = data->mux_hw;
619 mux = to_clk_mux(mux_hw);
621 mux_ops = mux_hw->init->ops;
622 mux->reg = reg + (u64)mux->reg;
626 struct clk_gate *gate;
628 gate_hw = data->gate_hw;
629 gate = to_clk_gate(gate_hw);
631 gate_ops = gate_hw->init->ops;
632 gate->reg = reg + (u64)gate->reg;
633 gate->flags = CLK_GATE_SET_TO_DISABLE;
637 rate_hw = data->rate_hw;
638 rate_ops = rate_hw->init->ops;
639 if (data->is_double_div) {
640 struct clk_double_div *rate;
642 rate = to_clk_double_div(rate_hw);
643 rate->reg1 = reg + (u64)rate->reg1;
644 rate->reg2 = reg + (u64)rate->reg2;
646 struct clk_divider *rate = to_clk_divider(rate_hw);
647 const struct clk_div_table *clkt;
650 rate->reg = reg + (u64)rate->reg;
651 for (clkt = rate->table; clkt->div; clkt++)
653 rate->width = order_base_2(table_size);
658 if (data->muxrate_hw) {
659 struct clk_pm_cpu *pmcpu_clk;
660 struct clk_hw *muxrate_hw = data->muxrate_hw;
663 pmcpu_clk = to_clk_pm_cpu(muxrate_hw);
664 pmcpu_clk->reg_mux = reg + (u64)pmcpu_clk->reg_mux;
665 pmcpu_clk->reg_div = reg + (u64)pmcpu_clk->reg_div;
668 rate_hw = muxrate_hw;
669 mux_ops = muxrate_hw->init->ops;
670 rate_ops = muxrate_hw->init->ops;
672 map = syscon_regmap_lookup_by_compatible(
673 "marvell,armada-3700-nb-pm");
674 pmcpu_clk->nb_pm_base = map;
677 *hw = clk_hw_register_composite(dev, data->name, data->parent_names,
678 data->num_parents, mux_hw,
679 mux_ops, rate_hw, rate_ops,
680 gate_hw, gate_ops, CLK_IGNORE_UNUSED);
682 return PTR_ERR_OR_ZERO(*hw);
685 static int __maybe_unused armada_3700_periph_clock_suspend(struct device *dev)
687 struct clk_periph_driver_data *data = dev_get_drvdata(dev);
689 data->tbg_sel = readl(data->reg + TBG_SEL);
690 data->div_sel0 = readl(data->reg + DIV_SEL0);
691 data->div_sel1 = readl(data->reg + DIV_SEL1);
692 data->div_sel2 = readl(data->reg + DIV_SEL2);
693 data->clk_sel = readl(data->reg + CLK_SEL);
694 data->clk_dis = readl(data->reg + CLK_DIS);
699 static int __maybe_unused armada_3700_periph_clock_resume(struct device *dev)
701 struct clk_periph_driver_data *data = dev_get_drvdata(dev);
703 /* Follow the same order than what the Cortex-M3 does (ATF code) */
704 writel(data->clk_dis, data->reg + CLK_DIS);
705 writel(data->div_sel0, data->reg + DIV_SEL0);
706 writel(data->div_sel1, data->reg + DIV_SEL1);
707 writel(data->div_sel2, data->reg + DIV_SEL2);
708 writel(data->tbg_sel, data->reg + TBG_SEL);
709 writel(data->clk_sel, data->reg + CLK_SEL);
714 static const struct dev_pm_ops armada_3700_periph_clock_pm_ops = {
715 SET_SYSTEM_SLEEP_PM_OPS(armada_3700_periph_clock_suspend,
716 armada_3700_periph_clock_resume)
719 static int armada_3700_periph_clock_probe(struct platform_device *pdev)
721 struct clk_periph_driver_data *driver_data;
722 struct device_node *np = pdev->dev.of_node;
723 const struct clk_periph_data *data;
724 struct device *dev = &pdev->dev;
725 int num_periph = 0, i, ret;
726 struct resource *res;
728 data = of_device_get_match_data(dev);
732 while (data[num_periph].name)
735 driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL);
739 driver_data->hw_data = devm_kzalloc(dev,
740 struct_size(driver_data->hw_data,
743 if (!driver_data->hw_data)
745 driver_data->hw_data->num = num_periph;
747 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
748 driver_data->reg = devm_ioremap_resource(dev, res);
749 if (IS_ERR(driver_data->reg))
750 return PTR_ERR(driver_data->reg);
752 spin_lock_init(&driver_data->lock);
754 for (i = 0; i < num_periph; i++) {
755 struct clk_hw **hw = &driver_data->hw_data->hws[i];
756 if (armada_3700_add_composite_clk(&data[i], driver_data->reg,
757 &driver_data->lock, dev, hw))
758 dev_err(dev, "Can't register periph clock %s\n",
762 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
763 driver_data->hw_data);
765 for (i = 0; i < num_periph; i++)
766 clk_hw_unregister(driver_data->hw_data->hws[i]);
770 platform_set_drvdata(pdev, driver_data);
774 static int armada_3700_periph_clock_remove(struct platform_device *pdev)
776 struct clk_periph_driver_data *data = platform_get_drvdata(pdev);
777 struct clk_hw_onecell_data *hw_data = data->hw_data;
780 of_clk_del_provider(pdev->dev.of_node);
782 for (i = 0; i < hw_data->num; i++)
783 clk_hw_unregister(hw_data->hws[i]);
788 static struct platform_driver armada_3700_periph_clock_driver = {
789 .probe = armada_3700_periph_clock_probe,
790 .remove = armada_3700_periph_clock_remove,
792 .name = "marvell-armada-3700-periph-clock",
793 .of_match_table = armada_3700_periph_clock_of_match,
794 .pm = &armada_3700_periph_clock_pm_ops,
798 builtin_platform_driver(armada_3700_periph_clock_driver);