1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 AmLogic, Inc.
4 * Michael Turquette <mturquette@baylibre.com>
8 #include <linux/clk-provider.h>
9 #include <linux/init.h>
10 #include <linux/of_device.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
17 #include "clk-regmap.h"
19 static DEFINE_SPINLOCK(meson_clk_lock);
21 static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
56 static const struct pll_params_table gxl_gp0_pll_params_table[] = {
85 static struct clk_regmap gxbb_fixed_pll_dco = {
86 .data = &(struct meson_clk_pll_data){
88 .reg_off = HHI_MPLL_CNTL,
93 .reg_off = HHI_MPLL_CNTL,
98 .reg_off = HHI_MPLL_CNTL,
103 .reg_off = HHI_MPLL_CNTL2,
108 .reg_off = HHI_MPLL_CNTL,
113 .reg_off = HHI_MPLL_CNTL,
118 .hw.init = &(struct clk_init_data){
119 .name = "fixed_pll_dco",
120 .ops = &meson_clk_pll_ro_ops,
121 .parent_names = (const char *[]){ "xtal" },
126 static struct clk_regmap gxbb_fixed_pll = {
127 .data = &(struct clk_regmap_div_data){
128 .offset = HHI_MPLL_CNTL,
131 .flags = CLK_DIVIDER_POWER_OF_TWO,
133 .hw.init = &(struct clk_init_data){
135 .ops = &clk_regmap_divider_ro_ops,
136 .parent_names = (const char *[]){ "fixed_pll_dco" },
139 * This clock won't ever change at runtime so
140 * CLK_SET_RATE_PARENT is not required
145 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
148 .hw.init = &(struct clk_init_data){
149 .name = "hdmi_pll_pre_mult",
150 .ops = &clk_fixed_factor_ops,
151 .parent_names = (const char *[]){ "xtal" },
156 static struct clk_regmap gxbb_hdmi_pll_dco = {
157 .data = &(struct meson_clk_pll_data){
159 .reg_off = HHI_HDMI_PLL_CNTL,
164 .reg_off = HHI_HDMI_PLL_CNTL,
169 .reg_off = HHI_HDMI_PLL_CNTL,
174 .reg_off = HHI_HDMI_PLL_CNTL2,
179 .reg_off = HHI_HDMI_PLL_CNTL,
184 .reg_off = HHI_HDMI_PLL_CNTL,
189 .hw.init = &(struct clk_init_data){
190 .name = "hdmi_pll_dco",
191 .ops = &meson_clk_pll_ro_ops,
192 .parent_names = (const char *[]){ "hdmi_pll_pre_mult" },
195 * Display directly handle hdmi pll registers ATM, we need
196 * NOCACHE to keep our view of the clock as accurate as possible
198 .flags = CLK_GET_RATE_NOCACHE,
202 static struct clk_regmap gxbb_hdmi_pll_od = {
203 .data = &(struct clk_regmap_div_data){
204 .offset = HHI_HDMI_PLL_CNTL2,
207 .flags = CLK_DIVIDER_POWER_OF_TWO,
209 .hw.init = &(struct clk_init_data){
210 .name = "hdmi_pll_od",
211 .ops = &clk_regmap_divider_ro_ops,
212 .parent_names = (const char *[]){ "hdmi_pll_dco" },
214 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
218 static struct clk_regmap gxbb_hdmi_pll_od2 = {
219 .data = &(struct clk_regmap_div_data){
220 .offset = HHI_HDMI_PLL_CNTL2,
223 .flags = CLK_DIVIDER_POWER_OF_TWO,
225 .hw.init = &(struct clk_init_data){
226 .name = "hdmi_pll_od2",
227 .ops = &clk_regmap_divider_ro_ops,
228 .parent_names = (const char *[]){ "hdmi_pll_od" },
230 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
234 static struct clk_regmap gxbb_hdmi_pll = {
235 .data = &(struct clk_regmap_div_data){
236 .offset = HHI_HDMI_PLL_CNTL2,
239 .flags = CLK_DIVIDER_POWER_OF_TWO,
241 .hw.init = &(struct clk_init_data){
243 .ops = &clk_regmap_divider_ro_ops,
244 .parent_names = (const char *[]){ "hdmi_pll_od2" },
246 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
250 static struct clk_regmap gxl_hdmi_pll_od = {
251 .data = &(struct clk_regmap_div_data){
252 .offset = HHI_HDMI_PLL_CNTL + 8,
255 .flags = CLK_DIVIDER_POWER_OF_TWO,
257 .hw.init = &(struct clk_init_data){
258 .name = "hdmi_pll_od",
259 .ops = &clk_regmap_divider_ro_ops,
260 .parent_names = (const char *[]){ "hdmi_pll_dco" },
262 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
266 static struct clk_regmap gxl_hdmi_pll_od2 = {
267 .data = &(struct clk_regmap_div_data){
268 .offset = HHI_HDMI_PLL_CNTL + 8,
271 .flags = CLK_DIVIDER_POWER_OF_TWO,
273 .hw.init = &(struct clk_init_data){
274 .name = "hdmi_pll_od2",
275 .ops = &clk_regmap_divider_ro_ops,
276 .parent_names = (const char *[]){ "hdmi_pll_od" },
278 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
282 static struct clk_regmap gxl_hdmi_pll = {
283 .data = &(struct clk_regmap_div_data){
284 .offset = HHI_HDMI_PLL_CNTL + 8,
287 .flags = CLK_DIVIDER_POWER_OF_TWO,
289 .hw.init = &(struct clk_init_data){
291 .ops = &clk_regmap_divider_ro_ops,
292 .parent_names = (const char *[]){ "hdmi_pll_od2" },
294 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
298 static struct clk_regmap gxbb_sys_pll_dco = {
299 .data = &(struct meson_clk_pll_data){
301 .reg_off = HHI_SYS_PLL_CNTL,
306 .reg_off = HHI_SYS_PLL_CNTL,
311 .reg_off = HHI_SYS_PLL_CNTL,
316 .reg_off = HHI_SYS_PLL_CNTL,
321 .reg_off = HHI_SYS_PLL_CNTL,
326 .hw.init = &(struct clk_init_data){
327 .name = "sys_pll_dco",
328 .ops = &meson_clk_pll_ro_ops,
329 .parent_names = (const char *[]){ "xtal" },
334 static struct clk_regmap gxbb_sys_pll = {
335 .data = &(struct clk_regmap_div_data){
336 .offset = HHI_SYS_PLL_CNTL,
339 .flags = CLK_DIVIDER_POWER_OF_TWO,
341 .hw.init = &(struct clk_init_data){
343 .ops = &clk_regmap_divider_ro_ops,
344 .parent_names = (const char *[]){ "sys_pll_dco" },
346 .flags = CLK_SET_RATE_PARENT,
350 static const struct reg_sequence gxbb_gp0_init_regs[] = {
351 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },
352 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },
353 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d },
356 static struct clk_regmap gxbb_gp0_pll_dco = {
357 .data = &(struct meson_clk_pll_data){
359 .reg_off = HHI_GP0_PLL_CNTL,
364 .reg_off = HHI_GP0_PLL_CNTL,
369 .reg_off = HHI_GP0_PLL_CNTL,
374 .reg_off = HHI_GP0_PLL_CNTL,
379 .reg_off = HHI_GP0_PLL_CNTL,
383 .table = gxbb_gp0_pll_params_table,
384 .init_regs = gxbb_gp0_init_regs,
385 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
387 .hw.init = &(struct clk_init_data){
388 .name = "gp0_pll_dco",
389 .ops = &meson_clk_pll_ops,
390 .parent_names = (const char *[]){ "xtal" },
395 static const struct reg_sequence gxl_gp0_init_regs[] = {
396 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
397 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
398 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
399 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
400 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
403 static struct clk_regmap gxl_gp0_pll_dco = {
404 .data = &(struct meson_clk_pll_data){
406 .reg_off = HHI_GP0_PLL_CNTL,
411 .reg_off = HHI_GP0_PLL_CNTL,
416 .reg_off = HHI_GP0_PLL_CNTL,
421 .reg_off = HHI_GP0_PLL_CNTL1,
426 .reg_off = HHI_GP0_PLL_CNTL,
431 .reg_off = HHI_GP0_PLL_CNTL,
435 .table = gxl_gp0_pll_params_table,
436 .init_regs = gxl_gp0_init_regs,
437 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
439 .hw.init = &(struct clk_init_data){
440 .name = "gp0_pll_dco",
441 .ops = &meson_clk_pll_ops,
442 .parent_names = (const char *[]){ "xtal" },
447 static struct clk_regmap gxbb_gp0_pll = {
448 .data = &(struct clk_regmap_div_data){
449 .offset = HHI_GP0_PLL_CNTL,
452 .flags = CLK_DIVIDER_POWER_OF_TWO,
454 .hw.init = &(struct clk_init_data){
456 .ops = &clk_regmap_divider_ops,
457 .parent_names = (const char *[]){ "gp0_pll_dco" },
459 .flags = CLK_SET_RATE_PARENT,
463 static struct clk_fixed_factor gxbb_fclk_div2_div = {
466 .hw.init = &(struct clk_init_data){
467 .name = "fclk_div2_div",
468 .ops = &clk_fixed_factor_ops,
469 .parent_names = (const char *[]){ "fixed_pll" },
474 static struct clk_regmap gxbb_fclk_div2 = {
475 .data = &(struct clk_regmap_gate_data){
476 .offset = HHI_MPLL_CNTL6,
479 .hw.init = &(struct clk_init_data){
481 .ops = &clk_regmap_gate_ops,
482 .parent_names = (const char *[]){ "fclk_div2_div" },
484 .flags = CLK_IS_CRITICAL,
488 static struct clk_fixed_factor gxbb_fclk_div3_div = {
491 .hw.init = &(struct clk_init_data){
492 .name = "fclk_div3_div",
493 .ops = &clk_fixed_factor_ops,
494 .parent_names = (const char *[]){ "fixed_pll" },
499 static struct clk_regmap gxbb_fclk_div3 = {
500 .data = &(struct clk_regmap_gate_data){
501 .offset = HHI_MPLL_CNTL6,
504 .hw.init = &(struct clk_init_data){
506 .ops = &clk_regmap_gate_ops,
507 .parent_names = (const char *[]){ "fclk_div3_div" },
512 static struct clk_fixed_factor gxbb_fclk_div4_div = {
515 .hw.init = &(struct clk_init_data){
516 .name = "fclk_div4_div",
517 .ops = &clk_fixed_factor_ops,
518 .parent_names = (const char *[]){ "fixed_pll" },
523 static struct clk_regmap gxbb_fclk_div4 = {
524 .data = &(struct clk_regmap_gate_data){
525 .offset = HHI_MPLL_CNTL6,
528 .hw.init = &(struct clk_init_data){
530 .ops = &clk_regmap_gate_ops,
531 .parent_names = (const char *[]){ "fclk_div4_div" },
536 static struct clk_fixed_factor gxbb_fclk_div5_div = {
539 .hw.init = &(struct clk_init_data){
540 .name = "fclk_div5_div",
541 .ops = &clk_fixed_factor_ops,
542 .parent_names = (const char *[]){ "fixed_pll" },
547 static struct clk_regmap gxbb_fclk_div5 = {
548 .data = &(struct clk_regmap_gate_data){
549 .offset = HHI_MPLL_CNTL6,
552 .hw.init = &(struct clk_init_data){
554 .ops = &clk_regmap_gate_ops,
555 .parent_names = (const char *[]){ "fclk_div5_div" },
560 static struct clk_fixed_factor gxbb_fclk_div7_div = {
563 .hw.init = &(struct clk_init_data){
564 .name = "fclk_div7_div",
565 .ops = &clk_fixed_factor_ops,
566 .parent_names = (const char *[]){ "fixed_pll" },
571 static struct clk_regmap gxbb_fclk_div7 = {
572 .data = &(struct clk_regmap_gate_data){
573 .offset = HHI_MPLL_CNTL6,
576 .hw.init = &(struct clk_init_data){
578 .ops = &clk_regmap_gate_ops,
579 .parent_names = (const char *[]){ "fclk_div7_div" },
584 static struct clk_regmap gxbb_mpll_prediv = {
585 .data = &(struct clk_regmap_div_data){
586 .offset = HHI_MPLL_CNTL5,
590 .hw.init = &(struct clk_init_data){
591 .name = "mpll_prediv",
592 .ops = &clk_regmap_divider_ro_ops,
593 .parent_names = (const char *[]){ "fixed_pll" },
598 static struct clk_regmap gxbb_mpll0_div = {
599 .data = &(struct meson_clk_mpll_data){
601 .reg_off = HHI_MPLL_CNTL7,
606 .reg_off = HHI_MPLL_CNTL7,
611 .reg_off = HHI_MPLL_CNTL7,
616 .reg_off = HHI_MPLL_CNTL,
620 .lock = &meson_clk_lock,
622 .hw.init = &(struct clk_init_data){
624 .ops = &meson_clk_mpll_ops,
625 .parent_names = (const char *[]){ "mpll_prediv" },
630 static struct clk_regmap gxbb_mpll0 = {
631 .data = &(struct clk_regmap_gate_data){
632 .offset = HHI_MPLL_CNTL7,
635 .hw.init = &(struct clk_init_data){
637 .ops = &clk_regmap_gate_ops,
638 .parent_names = (const char *[]){ "mpll0_div" },
640 .flags = CLK_SET_RATE_PARENT,
644 static struct clk_regmap gxbb_mpll1_div = {
645 .data = &(struct meson_clk_mpll_data){
647 .reg_off = HHI_MPLL_CNTL8,
652 .reg_off = HHI_MPLL_CNTL8,
657 .reg_off = HHI_MPLL_CNTL8,
661 .lock = &meson_clk_lock,
663 .hw.init = &(struct clk_init_data){
665 .ops = &meson_clk_mpll_ops,
666 .parent_names = (const char *[]){ "mpll_prediv" },
671 static struct clk_regmap gxbb_mpll1 = {
672 .data = &(struct clk_regmap_gate_data){
673 .offset = HHI_MPLL_CNTL8,
676 .hw.init = &(struct clk_init_data){
678 .ops = &clk_regmap_gate_ops,
679 .parent_names = (const char *[]){ "mpll1_div" },
681 .flags = CLK_SET_RATE_PARENT,
685 static struct clk_regmap gxbb_mpll2_div = {
686 .data = &(struct meson_clk_mpll_data){
688 .reg_off = HHI_MPLL_CNTL9,
693 .reg_off = HHI_MPLL_CNTL9,
698 .reg_off = HHI_MPLL_CNTL9,
702 .lock = &meson_clk_lock,
704 .hw.init = &(struct clk_init_data){
706 .ops = &meson_clk_mpll_ops,
707 .parent_names = (const char *[]){ "mpll_prediv" },
712 static struct clk_regmap gxbb_mpll2 = {
713 .data = &(struct clk_regmap_gate_data){
714 .offset = HHI_MPLL_CNTL9,
717 .hw.init = &(struct clk_init_data){
719 .ops = &clk_regmap_gate_ops,
720 .parent_names = (const char *[]){ "mpll2_div" },
722 .flags = CLK_SET_RATE_PARENT,
726 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
727 static const char * const clk81_parent_names[] = {
728 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
729 "fclk_div3", "fclk_div5"
732 static struct clk_regmap gxbb_mpeg_clk_sel = {
733 .data = &(struct clk_regmap_mux_data){
734 .offset = HHI_MPEG_CLK_CNTL,
737 .table = mux_table_clk81,
739 .hw.init = &(struct clk_init_data){
740 .name = "mpeg_clk_sel",
741 .ops = &clk_regmap_mux_ro_ops,
743 * bits 14:12 selects from 8 possible parents:
744 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
745 * fclk_div4, fclk_div3, fclk_div5
747 .parent_names = clk81_parent_names,
748 .num_parents = ARRAY_SIZE(clk81_parent_names),
752 static struct clk_regmap gxbb_mpeg_clk_div = {
753 .data = &(struct clk_regmap_div_data){
754 .offset = HHI_MPEG_CLK_CNTL,
758 .hw.init = &(struct clk_init_data){
759 .name = "mpeg_clk_div",
760 .ops = &clk_regmap_divider_ro_ops,
761 .parent_names = (const char *[]){ "mpeg_clk_sel" },
766 /* the mother of dragons gates */
767 static struct clk_regmap gxbb_clk81 = {
768 .data = &(struct clk_regmap_gate_data){
769 .offset = HHI_MPEG_CLK_CNTL,
772 .hw.init = &(struct clk_init_data){
774 .ops = &clk_regmap_gate_ops,
775 .parent_names = (const char *[]){ "mpeg_clk_div" },
777 .flags = CLK_IS_CRITICAL,
781 static struct clk_regmap gxbb_sar_adc_clk_sel = {
782 .data = &(struct clk_regmap_mux_data){
783 .offset = HHI_SAR_CLK_CNTL,
787 .hw.init = &(struct clk_init_data){
788 .name = "sar_adc_clk_sel",
789 .ops = &clk_regmap_mux_ops,
790 /* NOTE: The datasheet doesn't list the parents for bit 10 */
791 .parent_names = (const char *[]){ "xtal", "clk81", },
796 static struct clk_regmap gxbb_sar_adc_clk_div = {
797 .data = &(struct clk_regmap_div_data){
798 .offset = HHI_SAR_CLK_CNTL,
802 .hw.init = &(struct clk_init_data){
803 .name = "sar_adc_clk_div",
804 .ops = &clk_regmap_divider_ops,
805 .parent_names = (const char *[]){ "sar_adc_clk_sel" },
810 static struct clk_regmap gxbb_sar_adc_clk = {
811 .data = &(struct clk_regmap_gate_data){
812 .offset = HHI_SAR_CLK_CNTL,
815 .hw.init = &(struct clk_init_data){
816 .name = "sar_adc_clk",
817 .ops = &clk_regmap_gate_ops,
818 .parent_names = (const char *[]){ "sar_adc_clk_div" },
820 .flags = CLK_SET_RATE_PARENT,
825 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
826 * muxed by a glitch-free switch.
829 static const char * const gxbb_mali_0_1_parent_names[] = {
830 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
831 "fclk_div4", "fclk_div3", "fclk_div5"
834 static struct clk_regmap gxbb_mali_0_sel = {
835 .data = &(struct clk_regmap_mux_data){
836 .offset = HHI_MALI_CLK_CNTL,
840 .hw.init = &(struct clk_init_data){
841 .name = "mali_0_sel",
842 .ops = &clk_regmap_mux_ops,
844 * bits 10:9 selects from 8 possible parents:
845 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
846 * fclk_div4, fclk_div3, fclk_div5
848 .parent_names = gxbb_mali_0_1_parent_names,
850 .flags = CLK_SET_RATE_NO_REPARENT,
854 static struct clk_regmap gxbb_mali_0_div = {
855 .data = &(struct clk_regmap_div_data){
856 .offset = HHI_MALI_CLK_CNTL,
860 .hw.init = &(struct clk_init_data){
861 .name = "mali_0_div",
862 .ops = &clk_regmap_divider_ops,
863 .parent_names = (const char *[]){ "mali_0_sel" },
865 .flags = CLK_SET_RATE_NO_REPARENT,
869 static struct clk_regmap gxbb_mali_0 = {
870 .data = &(struct clk_regmap_gate_data){
871 .offset = HHI_MALI_CLK_CNTL,
874 .hw.init = &(struct clk_init_data){
876 .ops = &clk_regmap_gate_ops,
877 .parent_names = (const char *[]){ "mali_0_div" },
879 .flags = CLK_SET_RATE_PARENT,
883 static struct clk_regmap gxbb_mali_1_sel = {
884 .data = &(struct clk_regmap_mux_data){
885 .offset = HHI_MALI_CLK_CNTL,
889 .hw.init = &(struct clk_init_data){
890 .name = "mali_1_sel",
891 .ops = &clk_regmap_mux_ops,
893 * bits 10:9 selects from 8 possible parents:
894 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
895 * fclk_div4, fclk_div3, fclk_div5
897 .parent_names = gxbb_mali_0_1_parent_names,
899 .flags = CLK_SET_RATE_NO_REPARENT,
903 static struct clk_regmap gxbb_mali_1_div = {
904 .data = &(struct clk_regmap_div_data){
905 .offset = HHI_MALI_CLK_CNTL,
909 .hw.init = &(struct clk_init_data){
910 .name = "mali_1_div",
911 .ops = &clk_regmap_divider_ops,
912 .parent_names = (const char *[]){ "mali_1_sel" },
914 .flags = CLK_SET_RATE_NO_REPARENT,
918 static struct clk_regmap gxbb_mali_1 = {
919 .data = &(struct clk_regmap_gate_data){
920 .offset = HHI_MALI_CLK_CNTL,
923 .hw.init = &(struct clk_init_data){
925 .ops = &clk_regmap_gate_ops,
926 .parent_names = (const char *[]){ "mali_1_div" },
928 .flags = CLK_SET_RATE_PARENT,
932 static const char * const gxbb_mali_parent_names[] = {
936 static struct clk_regmap gxbb_mali = {
937 .data = &(struct clk_regmap_mux_data){
938 .offset = HHI_MALI_CLK_CNTL,
942 .hw.init = &(struct clk_init_data){
944 .ops = &clk_regmap_mux_ops,
945 .parent_names = gxbb_mali_parent_names,
947 .flags = CLK_SET_RATE_NO_REPARENT,
951 static struct clk_regmap gxbb_cts_amclk_sel = {
952 .data = &(struct clk_regmap_mux_data){
953 .offset = HHI_AUD_CLK_CNTL,
956 .table = (u32[]){ 1, 2, 3 },
957 .flags = CLK_MUX_ROUND_CLOSEST,
959 .hw.init = &(struct clk_init_data){
960 .name = "cts_amclk_sel",
961 .ops = &clk_regmap_mux_ops,
962 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
967 static struct clk_regmap gxbb_cts_amclk_div = {
968 .data = &(struct clk_regmap_div_data) {
969 .offset = HHI_AUD_CLK_CNTL,
972 .flags = CLK_DIVIDER_ROUND_CLOSEST,
974 .hw.init = &(struct clk_init_data){
975 .name = "cts_amclk_div",
976 .ops = &clk_regmap_divider_ops,
977 .parent_names = (const char *[]){ "cts_amclk_sel" },
979 .flags = CLK_SET_RATE_PARENT,
983 static struct clk_regmap gxbb_cts_amclk = {
984 .data = &(struct clk_regmap_gate_data){
985 .offset = HHI_AUD_CLK_CNTL,
988 .hw.init = &(struct clk_init_data){
990 .ops = &clk_regmap_gate_ops,
991 .parent_names = (const char *[]){ "cts_amclk_div" },
993 .flags = CLK_SET_RATE_PARENT,
997 static struct clk_regmap gxbb_cts_mclk_i958_sel = {
998 .data = &(struct clk_regmap_mux_data){
999 .offset = HHI_AUD_CLK_CNTL2,
1002 .table = (u32[]){ 1, 2, 3 },
1003 .flags = CLK_MUX_ROUND_CLOSEST,
1005 .hw.init = &(struct clk_init_data) {
1006 .name = "cts_mclk_i958_sel",
1007 .ops = &clk_regmap_mux_ops,
1008 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
1013 static struct clk_regmap gxbb_cts_mclk_i958_div = {
1014 .data = &(struct clk_regmap_div_data){
1015 .offset = HHI_AUD_CLK_CNTL2,
1018 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1020 .hw.init = &(struct clk_init_data) {
1021 .name = "cts_mclk_i958_div",
1022 .ops = &clk_regmap_divider_ops,
1023 .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
1025 .flags = CLK_SET_RATE_PARENT,
1029 static struct clk_regmap gxbb_cts_mclk_i958 = {
1030 .data = &(struct clk_regmap_gate_data){
1031 .offset = HHI_AUD_CLK_CNTL2,
1034 .hw.init = &(struct clk_init_data){
1035 .name = "cts_mclk_i958",
1036 .ops = &clk_regmap_gate_ops,
1037 .parent_names = (const char *[]){ "cts_mclk_i958_div" },
1039 .flags = CLK_SET_RATE_PARENT,
1043 static struct clk_regmap gxbb_cts_i958 = {
1044 .data = &(struct clk_regmap_mux_data){
1045 .offset = HHI_AUD_CLK_CNTL2,
1049 .hw.init = &(struct clk_init_data){
1051 .ops = &clk_regmap_mux_ops,
1052 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
1055 *The parent is specific to origin of the audio data. Let the
1056 * consumer choose the appropriate parent
1058 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1062 static struct clk_regmap gxbb_32k_clk_div = {
1063 .data = &(struct clk_regmap_div_data){
1064 .offset = HHI_32K_CLK_CNTL,
1068 .hw.init = &(struct clk_init_data){
1069 .name = "32k_clk_div",
1070 .ops = &clk_regmap_divider_ops,
1071 .parent_names = (const char *[]){ "32k_clk_sel" },
1073 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1077 static struct clk_regmap gxbb_32k_clk = {
1078 .data = &(struct clk_regmap_gate_data){
1079 .offset = HHI_32K_CLK_CNTL,
1082 .hw.init = &(struct clk_init_data){
1084 .ops = &clk_regmap_gate_ops,
1085 .parent_names = (const char *[]){ "32k_clk_div" },
1087 .flags = CLK_SET_RATE_PARENT,
1091 static const char * const gxbb_32k_clk_parent_names[] = {
1092 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
1095 static struct clk_regmap gxbb_32k_clk_sel = {
1096 .data = &(struct clk_regmap_mux_data){
1097 .offset = HHI_32K_CLK_CNTL,
1101 .hw.init = &(struct clk_init_data){
1102 .name = "32k_clk_sel",
1103 .ops = &clk_regmap_mux_ops,
1104 .parent_names = gxbb_32k_clk_parent_names,
1106 .flags = CLK_SET_RATE_PARENT,
1110 static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
1111 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
1114 * Following these parent clocks, we should also have had mpll2, mpll3
1115 * and gp0_pll but these clocks are too precious to be used here. All
1116 * the necessary rates for MMC and NAND operation can be acheived using
1117 * xtal or fclk_div clocks
1122 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1123 .data = &(struct clk_regmap_mux_data){
1124 .offset = HHI_SD_EMMC_CLK_CNTL,
1128 .hw.init = &(struct clk_init_data) {
1129 .name = "sd_emmc_a_clk0_sel",
1130 .ops = &clk_regmap_mux_ops,
1131 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1132 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1133 .flags = CLK_SET_RATE_PARENT,
1137 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1138 .data = &(struct clk_regmap_div_data){
1139 .offset = HHI_SD_EMMC_CLK_CNTL,
1142 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1144 .hw.init = &(struct clk_init_data) {
1145 .name = "sd_emmc_a_clk0_div",
1146 .ops = &clk_regmap_divider_ops,
1147 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
1149 .flags = CLK_SET_RATE_PARENT,
1153 static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1154 .data = &(struct clk_regmap_gate_data){
1155 .offset = HHI_SD_EMMC_CLK_CNTL,
1158 .hw.init = &(struct clk_init_data){
1159 .name = "sd_emmc_a_clk0",
1160 .ops = &clk_regmap_gate_ops,
1161 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
1163 .flags = CLK_SET_RATE_PARENT,
1168 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1169 .data = &(struct clk_regmap_mux_data){
1170 .offset = HHI_SD_EMMC_CLK_CNTL,
1174 .hw.init = &(struct clk_init_data) {
1175 .name = "sd_emmc_b_clk0_sel",
1176 .ops = &clk_regmap_mux_ops,
1177 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1178 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1179 .flags = CLK_SET_RATE_PARENT,
1183 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1184 .data = &(struct clk_regmap_div_data){
1185 .offset = HHI_SD_EMMC_CLK_CNTL,
1188 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1190 .hw.init = &(struct clk_init_data) {
1191 .name = "sd_emmc_b_clk0_div",
1192 .ops = &clk_regmap_divider_ops,
1193 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
1195 .flags = CLK_SET_RATE_PARENT,
1199 static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1200 .data = &(struct clk_regmap_gate_data){
1201 .offset = HHI_SD_EMMC_CLK_CNTL,
1204 .hw.init = &(struct clk_init_data){
1205 .name = "sd_emmc_b_clk0",
1206 .ops = &clk_regmap_gate_ops,
1207 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
1209 .flags = CLK_SET_RATE_PARENT,
1213 /* EMMC/NAND clock */
1214 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1215 .data = &(struct clk_regmap_mux_data){
1216 .offset = HHI_NAND_CLK_CNTL,
1220 .hw.init = &(struct clk_init_data) {
1221 .name = "sd_emmc_c_clk0_sel",
1222 .ops = &clk_regmap_mux_ops,
1223 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1224 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1225 .flags = CLK_SET_RATE_PARENT,
1229 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1230 .data = &(struct clk_regmap_div_data){
1231 .offset = HHI_NAND_CLK_CNTL,
1234 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1236 .hw.init = &(struct clk_init_data) {
1237 .name = "sd_emmc_c_clk0_div",
1238 .ops = &clk_regmap_divider_ops,
1239 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1241 .flags = CLK_SET_RATE_PARENT,
1245 static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1246 .data = &(struct clk_regmap_gate_data){
1247 .offset = HHI_NAND_CLK_CNTL,
1250 .hw.init = &(struct clk_init_data){
1251 .name = "sd_emmc_c_clk0",
1252 .ops = &clk_regmap_gate_ops,
1253 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1255 .flags = CLK_SET_RATE_PARENT,
1261 static const char * const gxbb_vpu_parent_names[] = {
1262 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1265 static struct clk_regmap gxbb_vpu_0_sel = {
1266 .data = &(struct clk_regmap_mux_data){
1267 .offset = HHI_VPU_CLK_CNTL,
1271 .hw.init = &(struct clk_init_data){
1272 .name = "vpu_0_sel",
1273 .ops = &clk_regmap_mux_ops,
1275 * bits 9:10 selects from 4 possible parents:
1276 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1278 .parent_names = gxbb_vpu_parent_names,
1279 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1280 .flags = CLK_SET_RATE_NO_REPARENT,
1284 static struct clk_regmap gxbb_vpu_0_div = {
1285 .data = &(struct clk_regmap_div_data){
1286 .offset = HHI_VPU_CLK_CNTL,
1290 .hw.init = &(struct clk_init_data){
1291 .name = "vpu_0_div",
1292 .ops = &clk_regmap_divider_ops,
1293 .parent_names = (const char *[]){ "vpu_0_sel" },
1295 .flags = CLK_SET_RATE_PARENT,
1299 static struct clk_regmap gxbb_vpu_0 = {
1300 .data = &(struct clk_regmap_gate_data){
1301 .offset = HHI_VPU_CLK_CNTL,
1304 .hw.init = &(struct clk_init_data) {
1306 .ops = &clk_regmap_gate_ops,
1307 .parent_names = (const char *[]){ "vpu_0_div" },
1309 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1313 static struct clk_regmap gxbb_vpu_1_sel = {
1314 .data = &(struct clk_regmap_mux_data){
1315 .offset = HHI_VPU_CLK_CNTL,
1319 .hw.init = &(struct clk_init_data){
1320 .name = "vpu_1_sel",
1321 .ops = &clk_regmap_mux_ops,
1323 * bits 25:26 selects from 4 possible parents:
1324 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1326 .parent_names = gxbb_vpu_parent_names,
1327 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1328 .flags = CLK_SET_RATE_NO_REPARENT,
1332 static struct clk_regmap gxbb_vpu_1_div = {
1333 .data = &(struct clk_regmap_div_data){
1334 .offset = HHI_VPU_CLK_CNTL,
1338 .hw.init = &(struct clk_init_data){
1339 .name = "vpu_1_div",
1340 .ops = &clk_regmap_divider_ops,
1341 .parent_names = (const char *[]){ "vpu_1_sel" },
1343 .flags = CLK_SET_RATE_PARENT,
1347 static struct clk_regmap gxbb_vpu_1 = {
1348 .data = &(struct clk_regmap_gate_data){
1349 .offset = HHI_VPU_CLK_CNTL,
1352 .hw.init = &(struct clk_init_data) {
1354 .ops = &clk_regmap_gate_ops,
1355 .parent_names = (const char *[]){ "vpu_1_div" },
1357 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1361 static struct clk_regmap gxbb_vpu = {
1362 .data = &(struct clk_regmap_mux_data){
1363 .offset = HHI_VPU_CLK_CNTL,
1367 .hw.init = &(struct clk_init_data){
1369 .ops = &clk_regmap_mux_ops,
1371 * bit 31 selects from 2 possible parents:
1374 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1376 .flags = CLK_SET_RATE_NO_REPARENT,
1382 static const char * const gxbb_vapb_parent_names[] = {
1383 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1386 static struct clk_regmap gxbb_vapb_0_sel = {
1387 .data = &(struct clk_regmap_mux_data){
1388 .offset = HHI_VAPBCLK_CNTL,
1392 .hw.init = &(struct clk_init_data){
1393 .name = "vapb_0_sel",
1394 .ops = &clk_regmap_mux_ops,
1396 * bits 9:10 selects from 4 possible parents:
1397 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1399 .parent_names = gxbb_vapb_parent_names,
1400 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1401 .flags = CLK_SET_RATE_NO_REPARENT,
1405 static struct clk_regmap gxbb_vapb_0_div = {
1406 .data = &(struct clk_regmap_div_data){
1407 .offset = HHI_VAPBCLK_CNTL,
1411 .hw.init = &(struct clk_init_data){
1412 .name = "vapb_0_div",
1413 .ops = &clk_regmap_divider_ops,
1414 .parent_names = (const char *[]){ "vapb_0_sel" },
1416 .flags = CLK_SET_RATE_PARENT,
1420 static struct clk_regmap gxbb_vapb_0 = {
1421 .data = &(struct clk_regmap_gate_data){
1422 .offset = HHI_VAPBCLK_CNTL,
1425 .hw.init = &(struct clk_init_data) {
1427 .ops = &clk_regmap_gate_ops,
1428 .parent_names = (const char *[]){ "vapb_0_div" },
1430 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1434 static struct clk_regmap gxbb_vapb_1_sel = {
1435 .data = &(struct clk_regmap_mux_data){
1436 .offset = HHI_VAPBCLK_CNTL,
1440 .hw.init = &(struct clk_init_data){
1441 .name = "vapb_1_sel",
1442 .ops = &clk_regmap_mux_ops,
1444 * bits 25:26 selects from 4 possible parents:
1445 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1447 .parent_names = gxbb_vapb_parent_names,
1448 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1449 .flags = CLK_SET_RATE_NO_REPARENT,
1453 static struct clk_regmap gxbb_vapb_1_div = {
1454 .data = &(struct clk_regmap_div_data){
1455 .offset = HHI_VAPBCLK_CNTL,
1459 .hw.init = &(struct clk_init_data){
1460 .name = "vapb_1_div",
1461 .ops = &clk_regmap_divider_ops,
1462 .parent_names = (const char *[]){ "vapb_1_sel" },
1464 .flags = CLK_SET_RATE_PARENT,
1468 static struct clk_regmap gxbb_vapb_1 = {
1469 .data = &(struct clk_regmap_gate_data){
1470 .offset = HHI_VAPBCLK_CNTL,
1473 .hw.init = &(struct clk_init_data) {
1475 .ops = &clk_regmap_gate_ops,
1476 .parent_names = (const char *[]){ "vapb_1_div" },
1478 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1482 static struct clk_regmap gxbb_vapb_sel = {
1483 .data = &(struct clk_regmap_mux_data){
1484 .offset = HHI_VAPBCLK_CNTL,
1488 .hw.init = &(struct clk_init_data){
1490 .ops = &clk_regmap_mux_ops,
1492 * bit 31 selects from 2 possible parents:
1495 .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
1497 .flags = CLK_SET_RATE_NO_REPARENT,
1501 static struct clk_regmap gxbb_vapb = {
1502 .data = &(struct clk_regmap_gate_data){
1503 .offset = HHI_VAPBCLK_CNTL,
1506 .hw.init = &(struct clk_init_data) {
1508 .ops = &clk_regmap_gate_ops,
1509 .parent_names = (const char *[]){ "vapb_sel" },
1511 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1517 static const char * const gxbb_vdec_parent_names[] = {
1518 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1521 static struct clk_regmap gxbb_vdec_1_sel = {
1522 .data = &(struct clk_regmap_mux_data){
1523 .offset = HHI_VDEC_CLK_CNTL,
1526 .flags = CLK_MUX_ROUND_CLOSEST,
1528 .hw.init = &(struct clk_init_data){
1529 .name = "vdec_1_sel",
1530 .ops = &clk_regmap_mux_ops,
1531 .parent_names = gxbb_vdec_parent_names,
1532 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
1533 .flags = CLK_SET_RATE_PARENT,
1537 static struct clk_regmap gxbb_vdec_1_div = {
1538 .data = &(struct clk_regmap_div_data){
1539 .offset = HHI_VDEC_CLK_CNTL,
1543 .hw.init = &(struct clk_init_data){
1544 .name = "vdec_1_div",
1545 .ops = &clk_regmap_divider_ops,
1546 .parent_names = (const char *[]){ "vdec_1_sel" },
1548 .flags = CLK_SET_RATE_PARENT,
1552 static struct clk_regmap gxbb_vdec_1 = {
1553 .data = &(struct clk_regmap_gate_data){
1554 .offset = HHI_VDEC_CLK_CNTL,
1557 .hw.init = &(struct clk_init_data) {
1559 .ops = &clk_regmap_gate_ops,
1560 .parent_names = (const char *[]){ "vdec_1_div" },
1562 .flags = CLK_SET_RATE_PARENT,
1566 static struct clk_regmap gxbb_vdec_hevc_sel = {
1567 .data = &(struct clk_regmap_mux_data){
1568 .offset = HHI_VDEC2_CLK_CNTL,
1571 .flags = CLK_MUX_ROUND_CLOSEST,
1573 .hw.init = &(struct clk_init_data){
1574 .name = "vdec_hevc_sel",
1575 .ops = &clk_regmap_mux_ops,
1576 .parent_names = gxbb_vdec_parent_names,
1577 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
1578 .flags = CLK_SET_RATE_PARENT,
1582 static struct clk_regmap gxbb_vdec_hevc_div = {
1583 .data = &(struct clk_regmap_div_data){
1584 .offset = HHI_VDEC2_CLK_CNTL,
1588 .hw.init = &(struct clk_init_data){
1589 .name = "vdec_hevc_div",
1590 .ops = &clk_regmap_divider_ops,
1591 .parent_names = (const char *[]){ "vdec_hevc_sel" },
1593 .flags = CLK_SET_RATE_PARENT,
1597 static struct clk_regmap gxbb_vdec_hevc = {
1598 .data = &(struct clk_regmap_gate_data){
1599 .offset = HHI_VDEC2_CLK_CNTL,
1602 .hw.init = &(struct clk_init_data) {
1603 .name = "vdec_hevc",
1604 .ops = &clk_regmap_gate_ops,
1605 .parent_names = (const char *[]){ "vdec_hevc_div" },
1607 .flags = CLK_SET_RATE_PARENT,
1611 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
1612 9, 10, 11, 13, 14, };
1613 static const char * const gen_clk_parent_names[] = {
1614 "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2",
1615 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
1618 static struct clk_regmap gxbb_gen_clk_sel = {
1619 .data = &(struct clk_regmap_mux_data){
1620 .offset = HHI_GEN_CLK_CNTL,
1623 .table = mux_table_gen_clk,
1625 .hw.init = &(struct clk_init_data){
1626 .name = "gen_clk_sel",
1627 .ops = &clk_regmap_mux_ops,
1629 * bits 15:12 selects from 14 possible parents:
1630 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
1631 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
1632 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
1634 .parent_names = gen_clk_parent_names,
1635 .num_parents = ARRAY_SIZE(gen_clk_parent_names),
1639 static struct clk_regmap gxbb_gen_clk_div = {
1640 .data = &(struct clk_regmap_div_data){
1641 .offset = HHI_GEN_CLK_CNTL,
1645 .hw.init = &(struct clk_init_data){
1646 .name = "gen_clk_div",
1647 .ops = &clk_regmap_divider_ops,
1648 .parent_names = (const char *[]){ "gen_clk_sel" },
1650 .flags = CLK_SET_RATE_PARENT,
1654 static struct clk_regmap gxbb_gen_clk = {
1655 .data = &(struct clk_regmap_gate_data){
1656 .offset = HHI_GEN_CLK_CNTL,
1659 .hw.init = &(struct clk_init_data){
1661 .ops = &clk_regmap_gate_ops,
1662 .parent_names = (const char *[]){ "gen_clk_div" },
1664 .flags = CLK_SET_RATE_PARENT,
1668 /* Everything Else (EE) domain gates */
1669 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
1670 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
1671 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
1672 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
1673 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
1674 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
1675 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
1676 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
1677 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
1678 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
1679 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
1680 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
1681 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
1682 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
1683 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
1684 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
1685 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
1686 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
1687 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
1688 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
1689 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
1690 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
1692 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
1693 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
1694 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
1695 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
1696 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
1697 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
1698 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
1699 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
1700 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
1701 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
1702 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
1703 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
1704 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
1705 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
1706 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
1707 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
1708 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
1709 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
1710 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
1711 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
1712 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
1713 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
1714 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
1715 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
1716 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
1718 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1719 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1720 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
1721 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
1722 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
1723 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
1724 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
1725 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
1726 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
1727 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
1728 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
1729 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1730 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
1732 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
1733 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
1734 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
1735 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
1736 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
1737 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
1738 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
1739 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
1740 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
1741 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
1742 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
1743 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
1744 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
1745 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
1746 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
1747 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
1749 /* Always On (AO) domain gates */
1751 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
1752 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
1753 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
1754 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
1755 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
1757 /* Array of all clocks provided by this provider */
1759 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
1761 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
1762 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
1763 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
1764 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
1765 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
1766 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
1767 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
1768 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
1769 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
1770 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
1771 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
1772 [CLKID_CLK81] = &gxbb_clk81.hw,
1773 [CLKID_MPLL0] = &gxbb_mpll0.hw,
1774 [CLKID_MPLL1] = &gxbb_mpll1.hw,
1775 [CLKID_MPLL2] = &gxbb_mpll2.hw,
1776 [CLKID_DDR] = &gxbb_ddr.hw,
1777 [CLKID_DOS] = &gxbb_dos.hw,
1778 [CLKID_ISA] = &gxbb_isa.hw,
1779 [CLKID_PL301] = &gxbb_pl301.hw,
1780 [CLKID_PERIPHS] = &gxbb_periphs.hw,
1781 [CLKID_SPICC] = &gxbb_spicc.hw,
1782 [CLKID_I2C] = &gxbb_i2c.hw,
1783 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
1784 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
1785 [CLKID_RNG0] = &gxbb_rng0.hw,
1786 [CLKID_UART0] = &gxbb_uart0.hw,
1787 [CLKID_SDHC] = &gxbb_sdhc.hw,
1788 [CLKID_STREAM] = &gxbb_stream.hw,
1789 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
1790 [CLKID_SDIO] = &gxbb_sdio.hw,
1791 [CLKID_ABUF] = &gxbb_abuf.hw,
1792 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
1793 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
1794 [CLKID_SPI] = &gxbb_spi.hw,
1795 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
1796 [CLKID_ETH] = &gxbb_eth.hw,
1797 [CLKID_DEMUX] = &gxbb_demux.hw,
1798 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
1799 [CLKID_IEC958] = &gxbb_iec958.hw,
1800 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
1801 [CLKID_AMCLK] = &gxbb_amclk.hw,
1802 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
1803 [CLKID_MIXER] = &gxbb_mixer.hw,
1804 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
1805 [CLKID_ADC] = &gxbb_adc.hw,
1806 [CLKID_BLKMV] = &gxbb_blkmv.hw,
1807 [CLKID_AIU] = &gxbb_aiu.hw,
1808 [CLKID_UART1] = &gxbb_uart1.hw,
1809 [CLKID_G2D] = &gxbb_g2d.hw,
1810 [CLKID_USB0] = &gxbb_usb0.hw,
1811 [CLKID_USB1] = &gxbb_usb1.hw,
1812 [CLKID_RESET] = &gxbb_reset.hw,
1813 [CLKID_NAND] = &gxbb_nand.hw,
1814 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
1815 [CLKID_USB] = &gxbb_usb.hw,
1816 [CLKID_VDIN1] = &gxbb_vdin1.hw,
1817 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
1818 [CLKID_EFUSE] = &gxbb_efuse.hw,
1819 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
1820 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
1821 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
1822 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
1823 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
1824 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
1825 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
1826 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
1827 [CLKID_DVIN] = &gxbb_dvin.hw,
1828 [CLKID_UART2] = &gxbb_uart2.hw,
1829 [CLKID_SANA] = &gxbb_sana.hw,
1830 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
1831 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
1832 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
1833 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
1834 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
1835 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
1836 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
1837 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
1838 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
1839 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
1840 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
1841 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
1842 [CLKID_ENC480P] = &gxbb_enc480p.hw,
1843 [CLKID_RNG1] = &gxbb_rng1.hw,
1844 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
1845 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
1846 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
1847 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
1848 [CLKID_EDP] = &gxbb_edp.hw,
1849 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
1850 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
1851 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
1852 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
1853 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
1854 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
1855 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
1856 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
1857 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
1858 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
1859 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
1860 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
1861 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
1862 [CLKID_MALI_0] = &gxbb_mali_0.hw,
1863 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
1864 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
1865 [CLKID_MALI_1] = &gxbb_mali_1.hw,
1866 [CLKID_MALI] = &gxbb_mali.hw,
1867 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
1868 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
1869 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
1870 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
1871 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
1872 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
1873 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
1874 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
1875 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
1876 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
1877 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
1878 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
1879 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
1880 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
1881 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
1882 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
1883 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
1884 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
1885 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
1886 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
1887 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
1888 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
1889 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
1890 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
1891 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
1892 [CLKID_VPU] = &gxbb_vpu.hw,
1893 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
1894 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
1895 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
1896 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
1897 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
1898 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
1899 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
1900 [CLKID_VAPB] = &gxbb_vapb.hw,
1901 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
1902 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
1903 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
1904 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
1905 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
1906 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
1907 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
1908 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
1909 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
1910 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
1911 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
1912 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
1913 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
1914 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
1915 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
1916 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
1917 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
1918 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
1919 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
1920 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
1921 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
1922 [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
1923 [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
1924 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
1925 [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
1931 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1933 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
1934 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
1935 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
1936 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
1937 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
1938 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
1939 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
1940 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
1941 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
1942 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
1943 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
1944 [CLKID_CLK81] = &gxbb_clk81.hw,
1945 [CLKID_MPLL0] = &gxbb_mpll0.hw,
1946 [CLKID_MPLL1] = &gxbb_mpll1.hw,
1947 [CLKID_MPLL2] = &gxbb_mpll2.hw,
1948 [CLKID_DDR] = &gxbb_ddr.hw,
1949 [CLKID_DOS] = &gxbb_dos.hw,
1950 [CLKID_ISA] = &gxbb_isa.hw,
1951 [CLKID_PL301] = &gxbb_pl301.hw,
1952 [CLKID_PERIPHS] = &gxbb_periphs.hw,
1953 [CLKID_SPICC] = &gxbb_spicc.hw,
1954 [CLKID_I2C] = &gxbb_i2c.hw,
1955 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
1956 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
1957 [CLKID_RNG0] = &gxbb_rng0.hw,
1958 [CLKID_UART0] = &gxbb_uart0.hw,
1959 [CLKID_SDHC] = &gxbb_sdhc.hw,
1960 [CLKID_STREAM] = &gxbb_stream.hw,
1961 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
1962 [CLKID_SDIO] = &gxbb_sdio.hw,
1963 [CLKID_ABUF] = &gxbb_abuf.hw,
1964 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
1965 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
1966 [CLKID_SPI] = &gxbb_spi.hw,
1967 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
1968 [CLKID_ETH] = &gxbb_eth.hw,
1969 [CLKID_DEMUX] = &gxbb_demux.hw,
1970 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
1971 [CLKID_IEC958] = &gxbb_iec958.hw,
1972 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
1973 [CLKID_AMCLK] = &gxbb_amclk.hw,
1974 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
1975 [CLKID_MIXER] = &gxbb_mixer.hw,
1976 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
1977 [CLKID_ADC] = &gxbb_adc.hw,
1978 [CLKID_BLKMV] = &gxbb_blkmv.hw,
1979 [CLKID_AIU] = &gxbb_aiu.hw,
1980 [CLKID_UART1] = &gxbb_uart1.hw,
1981 [CLKID_G2D] = &gxbb_g2d.hw,
1982 [CLKID_USB0] = &gxbb_usb0.hw,
1983 [CLKID_USB1] = &gxbb_usb1.hw,
1984 [CLKID_RESET] = &gxbb_reset.hw,
1985 [CLKID_NAND] = &gxbb_nand.hw,
1986 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
1987 [CLKID_USB] = &gxbb_usb.hw,
1988 [CLKID_VDIN1] = &gxbb_vdin1.hw,
1989 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
1990 [CLKID_EFUSE] = &gxbb_efuse.hw,
1991 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
1992 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
1993 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
1994 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
1995 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
1996 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
1997 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
1998 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
1999 [CLKID_DVIN] = &gxbb_dvin.hw,
2000 [CLKID_UART2] = &gxbb_uart2.hw,
2001 [CLKID_SANA] = &gxbb_sana.hw,
2002 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
2003 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2004 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
2005 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
2006 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
2007 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
2008 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
2009 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
2010 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
2011 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
2012 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
2013 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
2014 [CLKID_ENC480P] = &gxbb_enc480p.hw,
2015 [CLKID_RNG1] = &gxbb_rng1.hw,
2016 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
2017 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
2018 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
2019 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
2020 [CLKID_EDP] = &gxbb_edp.hw,
2021 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
2022 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
2023 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
2024 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
2025 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
2026 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
2027 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
2028 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
2029 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
2030 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
2031 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
2032 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
2033 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
2034 [CLKID_MALI_0] = &gxbb_mali_0.hw,
2035 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
2036 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
2037 [CLKID_MALI_1] = &gxbb_mali_1.hw,
2038 [CLKID_MALI] = &gxbb_mali.hw,
2039 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
2040 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
2041 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
2042 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
2043 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
2044 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
2045 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
2046 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
2047 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
2048 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
2049 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
2050 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
2051 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
2052 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
2053 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
2054 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
2055 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
2056 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
2057 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
2058 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
2059 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
2060 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
2061 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
2062 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
2063 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
2064 [CLKID_VPU] = &gxbb_vpu.hw,
2065 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
2066 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
2067 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
2068 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
2069 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
2070 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
2071 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
2072 [CLKID_VAPB] = &gxbb_vapb.hw,
2073 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
2074 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
2075 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
2076 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
2077 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
2078 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
2079 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
2080 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
2081 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
2082 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
2083 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
2084 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
2085 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
2086 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
2087 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
2088 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
2089 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
2090 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
2091 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
2092 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
2093 [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
2094 [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
2095 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
2096 [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
2102 static struct clk_regmap *const gxbb_clk_regmaps[] = {
2109 static struct clk_regmap *const gxl_clk_regmaps[] = {
2116 static struct clk_regmap *const gx_clk_regmaps[] = {
2164 &gxbb_hdmi_intr_sync,
2166 &gxbb_usb1_ddr_bridge,
2167 &gxbb_usb0_ddr_bridge,
2173 &gxbb_sec_ahb_ahb3_bridge,
2179 &gxbb_gclk_venci_int0,
2180 &gxbb_gclk_vencp_int,
2186 &gxbb_gclk_venci_int1,
2187 &gxbb_vclk2_venclmcc,
2203 &gxbb_cts_mclk_i958,
2205 &gxbb_sd_emmc_a_clk0,
2206 &gxbb_sd_emmc_b_clk0,
2207 &gxbb_sd_emmc_c_clk0,
2214 &gxbb_sar_adc_clk_div,
2217 &gxbb_cts_mclk_i958_div,
2219 &gxbb_sd_emmc_a_clk0_div,
2220 &gxbb_sd_emmc_b_clk0_div,
2221 &gxbb_sd_emmc_c_clk0_div,
2227 &gxbb_sar_adc_clk_sel,
2231 &gxbb_cts_amclk_sel,
2232 &gxbb_cts_mclk_i958_sel,
2235 &gxbb_sd_emmc_a_clk0_sel,
2236 &gxbb_sd_emmc_b_clk0_sel,
2237 &gxbb_sd_emmc_c_clk0_sel,
2250 &gxbb_cts_amclk_div,
2262 &gxbb_vdec_hevc_sel,
2263 &gxbb_vdec_hevc_div,
2268 &gxbb_fixed_pll_dco,
2275 struct clk_regmap *const *regmap_clks;
2276 unsigned int regmap_clks_count;
2277 struct clk_hw_onecell_data *hw_onecell_data;
2280 static const struct clkc_data gxbb_clkc_data = {
2281 .regmap_clks = gxbb_clk_regmaps,
2282 .regmap_clks_count = ARRAY_SIZE(gxbb_clk_regmaps),
2283 .hw_onecell_data = &gxbb_hw_onecell_data,
2286 static const struct clkc_data gxl_clkc_data = {
2287 .regmap_clks = gxl_clk_regmaps,
2288 .regmap_clks_count = ARRAY_SIZE(gxl_clk_regmaps),
2289 .hw_onecell_data = &gxl_hw_onecell_data,
2292 static const struct of_device_id clkc_match_table[] = {
2293 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
2294 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
2298 static int gxbb_clkc_probe(struct platform_device *pdev)
2300 const struct clkc_data *clkc_data;
2303 struct device *dev = &pdev->dev;
2305 clkc_data = of_device_get_match_data(dev);
2309 /* Get the hhi system controller node if available */
2310 map = syscon_node_to_regmap(of_get_parent(dev->of_node));
2312 dev_err(dev, "failed to get HHI regmap\n");
2313 return PTR_ERR(map);
2316 /* Populate regmap for the common regmap backed clocks */
2317 for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++)
2318 gx_clk_regmaps[i]->map = map;
2320 /* Populate regmap for soc specific clocks */
2321 for (i = 0; i < clkc_data->regmap_clks_count; i++)
2322 clkc_data->regmap_clks[i]->map = map;
2324 /* Register all clks */
2325 for (i = 0; i < clkc_data->hw_onecell_data->num; i++) {
2326 /* array might be sparse */
2327 if (!clkc_data->hw_onecell_data->hws[i])
2330 ret = devm_clk_hw_register(dev,
2331 clkc_data->hw_onecell_data->hws[i]);
2333 dev_err(dev, "Clock registration failed\n");
2338 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
2339 clkc_data->hw_onecell_data);
2342 static struct platform_driver gxbb_driver = {
2343 .probe = gxbb_clkc_probe,
2345 .name = "gxbb-clkc",
2346 .of_match_table = clkc_match_table,
2350 builtin_platform_driver(gxbb_driver);