1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
6 * Copyright (c) 2018 Baylibre, SAS.
7 * Author: Jerome Brunet <jbrunet@baylibre.com>
11 * In the most basic form, a Meson PLL is composed as follows:
14 * +--------------------------------+
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
24 * +--------------------------------+
26 * out = in * (m + frac / frac_max) / n
29 #include <linux/clk-provider.h>
30 #include <linux/delay.h>
31 #include <linux/err.h>
33 #include <linux/math64.h>
34 #include <linux/module.h>
35 #include <linux/of_address.h>
36 #include <linux/slab.h>
37 #include <linux/string.h>
41 static inline struct meson_clk_pll_data *
42 meson_clk_pll_data(struct clk_regmap *clk)
44 return (struct meson_clk_pll_data *)clk->data;
47 static unsigned long __pll_params_to_rate(unsigned long parent_rate,
48 const struct pll_params_table *pllt,
50 struct meson_clk_pll_data *pll)
52 u64 rate = (u64)parent_rate * pllt->m;
54 if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
55 u64 frac_rate = (u64)parent_rate * frac;
57 rate += DIV_ROUND_UP_ULL(frac_rate,
58 (1 << pll->frac.width));
61 return DIV_ROUND_UP_ULL(rate, pllt->n);
64 static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
65 unsigned long parent_rate)
67 struct clk_regmap *clk = to_clk_regmap(hw);
68 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
69 struct pll_params_table pllt;
72 pllt.n = meson_parm_read(clk->map, &pll->n);
73 pllt.m = meson_parm_read(clk->map, &pll->m);
75 frac = MESON_PARM_APPLICABLE(&pll->frac) ?
76 meson_parm_read(clk->map, &pll->frac) :
79 return __pll_params_to_rate(parent_rate, &pllt, frac, pll);
82 static u16 __pll_params_with_frac(unsigned long rate,
83 unsigned long parent_rate,
84 const struct pll_params_table *pllt,
85 struct meson_clk_pll_data *pll)
87 u16 frac_max = (1 << pll->frac.width);
88 u64 val = (u64)rate * pllt->n;
90 if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)
91 val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate);
93 val = div_u64(val * frac_max, parent_rate);
95 val -= pllt->m * frac_max;
97 return min((u16)val, (u16)(frac_max - 1));
100 static bool meson_clk_pll_is_better(unsigned long rate,
103 struct meson_clk_pll_data *pll)
105 if (!(pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) ||
106 MESON_PARM_APPLICABLE(&pll->frac)) {
108 if (now < rate && best < now)
112 if (abs(now - rate) < abs(best - rate))
119 static const struct pll_params_table *
120 meson_clk_get_pll_settings(unsigned long rate,
121 unsigned long parent_rate,
122 struct meson_clk_pll_data *pll)
124 const struct pll_params_table *table = pll->table;
125 unsigned long best = 0, now = 0;
126 unsigned int i, best_i = 0;
131 for (i = 0; table[i].n; i++) {
132 now = __pll_params_to_rate(parent_rate, &table[i], 0, pll);
134 /* If we get an exact match, don't bother any further */
137 } else if (meson_clk_pll_is_better(rate, best, now, pll)) {
143 return (struct pll_params_table *)&table[best_i];
146 static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
147 unsigned long *parent_rate)
149 struct clk_regmap *clk = to_clk_regmap(hw);
150 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
151 const struct pll_params_table *pllt =
152 meson_clk_get_pll_settings(rate, *parent_rate, pll);
157 return meson_clk_pll_recalc_rate(hw, *parent_rate);
159 round = __pll_params_to_rate(*parent_rate, pllt, 0, pll);
161 if (!MESON_PARM_APPLICABLE(&pll->frac) || rate == round)
165 * The rate provided by the setting is not an exact match, let's
166 * try to improve the result using the fractional parameter
168 frac = __pll_params_with_frac(rate, *parent_rate, pllt, pll);
170 return __pll_params_to_rate(*parent_rate, pllt, frac, pll);
173 static int meson_clk_pll_wait_lock(struct clk_hw *hw)
175 struct clk_regmap *clk = to_clk_regmap(hw);
176 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
177 int delay = 24000000;
180 /* Is the clock locked now ? */
181 if (meson_parm_read(clk->map, &pll->l))
190 static void meson_clk_pll_init(struct clk_hw *hw)
192 struct clk_regmap *clk = to_clk_regmap(hw);
193 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
195 if (pll->init_count) {
196 meson_parm_write(clk->map, &pll->rst, 1);
197 regmap_multi_reg_write(clk->map, pll->init_regs,
199 meson_parm_write(clk->map, &pll->rst, 0);
203 static int meson_clk_pll_is_enabled(struct clk_hw *hw)
205 struct clk_regmap *clk = to_clk_regmap(hw);
206 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
208 if (meson_parm_read(clk->map, &pll->rst) ||
209 !meson_parm_read(clk->map, &pll->en) ||
210 !meson_parm_read(clk->map, &pll->l))
216 static int meson_clk_pll_enable(struct clk_hw *hw)
218 struct clk_regmap *clk = to_clk_regmap(hw);
219 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
221 /* do nothing if the PLL is already enabled */
222 if (clk_hw_is_enabled(hw))
225 /* Make sure the pll is in reset */
226 meson_parm_write(clk->map, &pll->rst, 1);
229 meson_parm_write(clk->map, &pll->en, 1);
231 /* Take the pll out reset */
232 meson_parm_write(clk->map, &pll->rst, 0);
234 if (meson_clk_pll_wait_lock(hw))
240 static void meson_clk_pll_disable(struct clk_hw *hw)
242 struct clk_regmap *clk = to_clk_regmap(hw);
243 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
245 /* Put the pll is in reset */
246 meson_parm_write(clk->map, &pll->rst, 1);
248 /* Disable the pll */
249 meson_parm_write(clk->map, &pll->en, 0);
252 static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
253 unsigned long parent_rate)
255 struct clk_regmap *clk = to_clk_regmap(hw);
256 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
257 const struct pll_params_table *pllt;
258 unsigned int enabled;
259 unsigned long old_rate;
262 if (parent_rate == 0 || rate == 0)
267 pllt = meson_clk_get_pll_settings(rate, parent_rate, pll);
271 enabled = meson_parm_read(clk->map, &pll->en);
273 meson_clk_pll_disable(hw);
275 meson_parm_write(clk->map, &pll->n, pllt->n);
276 meson_parm_write(clk->map, &pll->m, pllt->m);
279 if (MESON_PARM_APPLICABLE(&pll->frac)) {
280 frac = __pll_params_with_frac(rate, parent_rate, pllt, pll);
281 meson_parm_write(clk->map, &pll->frac, frac);
284 /* If the pll is stopped, bail out now */
288 if (meson_clk_pll_enable(hw)) {
289 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
292 * FIXME: Do we really need/want this HACK ?
293 * It looks unsafe. what happens if the clock gets into a
294 * broken state and we can't lock back on the old_rate ? Looks
295 * like an infinite recursion is possible
297 meson_clk_pll_set_rate(hw, old_rate, parent_rate);
303 const struct clk_ops meson_clk_pll_ops = {
304 .init = meson_clk_pll_init,
305 .recalc_rate = meson_clk_pll_recalc_rate,
306 .round_rate = meson_clk_pll_round_rate,
307 .set_rate = meson_clk_pll_set_rate,
308 .is_enabled = meson_clk_pll_is_enabled,
309 .enable = meson_clk_pll_enable,
310 .disable = meson_clk_pll_disable
313 const struct clk_ops meson_clk_pll_ro_ops = {
314 .recalc_rate = meson_clk_pll_recalc_rate,
315 .is_enabled = meson_clk_pll_is_enabled,