drivers/clk/meson/axg-audio.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2018 BayLibre, SAS.
   4  * Author: Jerome Brunet <jbrunet@baylibre.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/clk-provider.h>
   9 #include <linux/init.h>
  10 #include <linux/of_device.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/regmap.h>
  14 #include <linux/reset.h>
  15 #include <linux/reset-controller.h>
  16 #include <linux/slab.h>
  17
  18 #include "axg-audio.h"
  19 #include "clk-regmap.h"
  20 #include "clk-phase.h"
  21 #include "sclk-div.h"
  22
  23 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) {                  \
  24         .data = &(struct clk_regmap_gate_data){                         \
  25                 .offset = (_reg),                                       \
  26                 .bit_idx = (_bit),                                      \
  27         },                                                              \
  28         .hw.init = &(struct clk_init_data) {                            \
  29                 .name = "aud_"#_name,                                   \
  30                 .ops = &clk_regmap_gate_ops,                            \
  31                 .parent_names = (const char *[]){ #_pname },            \
  32                 .num_parents = 1,                                       \
  33                 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags),             \
  34         },                                                              \
  35 }
  36
  37 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \
  38         .data = &(struct clk_regmap_mux_data){                          \
  39                 .offset = (_reg),                                       \
  40                 .mask = (_mask),                                        \
  41                 .shift = (_shift),                                      \
  42                 .flags = (_dflags),                                     \
  43         },                                                              \
  44         .hw.init = &(struct clk_init_data){                             \
  45                 .name = "aud_"#_name,                                   \
  46                 .ops = &clk_regmap_mux_ops,                             \
  47                 .parent_data = _pdata,                                  \
  48                 .num_parents = ARRAY_SIZE(_pdata),                      \
  49                 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags),             \
  50         },                                                              \
  51 }
  52
  53 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \
  54         .data = &(struct clk_regmap_div_data){                          \
  55                 .offset = (_reg),                                       \
  56                 .shift = (_shift),                                      \
  57                 .width = (_width),                                      \
  58                 .flags = (_dflags),                                     \
  59         },                                                              \
  60         .hw.init = &(struct clk_init_data){                             \
  61                 .name = "aud_"#_name,                                   \
  62                 .ops = &clk_regmap_divider_ops,                         \
  63                 .parent_names = (const char *[]){ #_pname },            \
  64                 .num_parents = 1,                                       \
  65                 .flags = (_iflags),                                     \
  66         },                                                              \
  67 }
  68
  69 #define AUD_PCLK_GATE(_name, _reg, _bit) {                              \
  70         .data = &(struct clk_regmap_gate_data){                         \
  71                 .offset = (_reg),                                       \
  72                 .bit_idx = (_bit),                                      \
  73         },                                                              \
  74         .hw.init = &(struct clk_init_data) {                            \
  75                 .name = "aud_"#_name,                                   \
  76                 .ops = &clk_regmap_gate_ops,                            \
  77                 .parent_names = (const char *[]){ "aud_top" },          \
  78                 .num_parents = 1,                                       \
  79         },                                                              \
  80 }
  81
  82 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width,               \
  83                      _hi_shift, _hi_width, _pname, _iflags) {           \
  84         .data = &(struct meson_sclk_div_data) {                         \
  85                 .div = {                                                \
  86                         .reg_off = (_reg),                              \
  87                         .shift   = (_div_shift),                        \
  88                         .width   = (_div_width),                        \
  89                 },                                                      \
  90                 .hi = {                                                 \
  91                         .reg_off = (_reg),                              \
  92                         .shift   = (_hi_shift),                         \
  93                         .width   = (_hi_width),                         \
  94                 },                                                      \
  95         },                                                              \
  96         .hw.init = &(struct clk_init_data) {                            \
  97                 .name = "aud_"#_name,                                   \
  98                 .ops = &meson_sclk_div_ops,                             \
  99                 .parent_names = (const char *[]){ #_pname },            \
 100                 .num_parents = 1,                                       \
 101                 .flags = (_iflags),                                     \
 102         },                                                              \
 103 }
 104
 105 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2,    \
 106                      _pname, _iflags) {                                 \
 107         .data = &(struct meson_clk_triphase_data) {                     \
 108                 .ph0 = {                                                \
 109                         .reg_off = (_reg),                              \
 110                         .shift   = (_shift0),                           \
 111                         .width   = (_width),                            \
 112                 },                                                      \
 113                 .ph1 = {                                                \
 114                         .reg_off = (_reg),                              \
 115                         .shift   = (_shift1),                           \
 116                         .width   = (_width),                            \
 117                 },                                                      \
 118                 .ph2 = {                                                \
 119                         .reg_off = (_reg),                              \
 120                         .shift   = (_shift2),                           \
 121                         .width   = (_width),                            \
 122                 },                                                      \
 123         },                                                              \
 124         .hw.init = &(struct clk_init_data) {                            \
 125                 .name = "aud_"#_name,                                   \
 126                 .ops = &meson_clk_triphase_ops,                         \
 127                 .parent_names = (const char *[]){ #_pname },            \
 128                 .num_parents = 1,                                       \
 129                 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags),             \
 130         },                                                              \
 131 }
 132
 133 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) {       \
 134         .data = &(struct meson_clk_phase_data) {                        \
 135                 .ph = {                                                 \
 136                         .reg_off = (_reg),                              \
 137                         .shift   = (_shift),                            \
 138                         .width   = (_width),                            \
 139                 },                                                      \
 140         },                                                              \
 141         .hw.init = &(struct clk_init_data) {                            \
 142                 .name = "aud_"#_name,                                   \
 143                 .ops = &meson_clk_phase_ops,                            \
 144                 .parent_names = (const char *[]){ #_pname },            \
 145                 .num_parents = 1,                                       \
 146                 .flags = (_iflags),                                     \
 147         },                                                              \
 148 }
 149
 150 /* Audio Master Clocks */
 151 static const struct clk_parent_data mst_mux_parent_data[] = {
 152         { .fw_name = "mst_in0", },
 153         { .fw_name = "mst_in1", },
 154         { .fw_name = "mst_in2", },
 155         { .fw_name = "mst_in3", },
 156         { .fw_name = "mst_in4", },
 157         { .fw_name = "mst_in5", },
 158         { .fw_name = "mst_in6", },
 159         { .fw_name = "mst_in7", },
 160 };
 161
 162 #define AUD_MST_MUX(_name, _reg, _flag)                                 \
 163         AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag,                      \
 164                 mst_mux_parent_data, 0)
 165 #define AUD_MST_DIV(_name, _reg, _flag)                                 \
 166         AUD_DIV(_name##_div, _reg, 0, 16, _flag,                        \
 167                 aud_##_name##_sel, CLK_SET_RATE_PARENT)
 168 #define AUD_MST_MCLK_GATE(_name, _reg)                                  \
 169         AUD_GATE(_name, _reg, 31, aud_##_name##_div,                    \
 170                  CLK_SET_RATE_PARENT)
 171
 172 #define AUD_MST_MCLK_MUX(_name, _reg)                                   \
 173         AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
 174 #define AUD_MST_MCLK_DIV(_name, _reg)                                   \
 175         AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
 176
 177 #define AUD_MST_SYS_MUX(_name, _reg)                                    \
 178         AUD_MST_MUX(_name, _reg, 0)
 179 #define AUD_MST_SYS_DIV(_name, _reg)                                    \
 180         AUD_MST_DIV(_name, _reg, 0)
 181
 182 /* Sample Clocks */
 183 #define AUD_MST_SCLK_PRE_EN(_name, _reg)                                \
 184         AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,                   \
 185                  aud_mst_##_name##_mclk, 0)
 186 #define AUD_MST_SCLK_DIV(_name, _reg)                                   \
 187         AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,        \
 188                      aud_mst_##_name##_sclk_pre_en,                     \
 189                      CLK_SET_RATE_PARENT)
 190 #define AUD_MST_SCLK_POST_EN(_name, _reg)                               \
 191         AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,                  \
 192                  aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
 193 #define AUD_MST_SCLK(_name, _reg)                                       \
 194         AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4,              \
 195                      aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
 196
 197 #define AUD_MST_LRCLK_DIV(_name, _reg)                                  \
 198         AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10,      \
 199                      aud_mst_##_name##_sclk_post_en, 0)
 200 #define AUD_MST_LRCLK(_name, _reg)                                      \
 201         AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5,             \
 202                      aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
 203
 204 /* TDM bit clock sources */
 205 static const struct clk_parent_data tdm_sclk_parent_data[] = {
 206         { .name = "aud_mst_a_sclk", .index = -1, },
 207         { .name = "aud_mst_b_sclk", .index = -1, },
 208         { .name = "aud_mst_c_sclk", .index = -1, },
 209         { .name = "aud_mst_d_sclk", .index = -1, },
 210         { .name = "aud_mst_e_sclk", .index = -1, },
 211         { .name = "aud_mst_f_sclk", .index = -1, },
 212         { .fw_name = "slv_sclk0", },
 213         { .fw_name = "slv_sclk1", },
 214         { .fw_name = "slv_sclk2", },
 215         { .fw_name = "slv_sclk3", },
 216         { .fw_name = "slv_sclk4", },
 217         { .fw_name = "slv_sclk5", },
 218         { .fw_name = "slv_sclk6", },
 219         { .fw_name = "slv_sclk7", },
 220         { .fw_name = "slv_sclk8", },
 221         { .fw_name = "slv_sclk9", },
 222 };
 223
 224 /* TDM sample clock sources */
 225 static const struct clk_parent_data tdm_lrclk_parent_data[] = {
 226         { .name = "aud_mst_a_lrclk", .index = -1, },
 227         { .name = "aud_mst_b_lrclk", .index = -1, },
 228         { .name = "aud_mst_c_lrclk", .index = -1, },
 229         { .name = "aud_mst_d_lrclk", .index = -1, },
 230         { .name = "aud_mst_e_lrclk", .index = -1, },
 231         { .name = "aud_mst_f_lrclk", .index = -1, },
 232         { .fw_name = "slv_lrclk0", },
 233         { .fw_name = "slv_lrclk1", },
 234         { .fw_name = "slv_lrclk2", },
 235         { .fw_name = "slv_lrclk3", },
 236         { .fw_name = "slv_lrclk4", },
 237         { .fw_name = "slv_lrclk5", },
 238         { .fw_name = "slv_lrclk6", },
 239         { .fw_name = "slv_lrclk7", },
 240         { .fw_name = "slv_lrclk8", },
 241         { .fw_name = "slv_lrclk9", },
 242 };
 243
 244 #define AUD_TDM_SCLK_MUX(_name, _reg)                                   \
 245         AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,                   \
 246                 CLK_MUX_ROUND_CLOSEST, tdm_sclk_parent_data, 0)
 247 #define AUD_TDM_SCLK_PRE_EN(_name, _reg)                                \
 248         AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,                    \
 249                  aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
 250 #define AUD_TDM_SCLK_POST_EN(_name, _reg)                               \
 251         AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,                   \
 252                  aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
 253 #define AUD_TDM_SCLK(_name, _reg)                                       \
 254         AUD_PHASE(tdm##_name##_sclk, _reg, 1, 29,                       \
 255                   aud_tdm##_name##_sclk_post_en,                        \
 256                   CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
 257
 258 #define AUD_TDM_LRLCK(_name, _reg)                                      \
 259         AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20,                      \
 260                 CLK_MUX_ROUND_CLOSEST, tdm_lrclk_parent_data, 0)
 261
 262 /* Pad master clock sources */
 263 static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {
 264         { .name = "aud_mst_a_mclk", .index = -1,  },
 265         { .name = "aud_mst_b_mclk", .index = -1,  },
 266         { .name = "aud_mst_c_mclk", .index = -1,  },
 267         { .name = "aud_mst_d_mclk", .index = -1,  },
 268         { .name = "aud_mst_e_mclk", .index = -1,  },
 269         { .name = "aud_mst_f_mclk", .index = -1,  },
 270 };
 271
 272 /* Pad bit clock sources */
 273 static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
 274         { .name = "aud_mst_a_sclk", .index = -1, },
 275         { .name = "aud_mst_b_sclk", .index = -1, },
 276         { .name = "aud_mst_c_sclk", .index = -1, },
 277         { .name = "aud_mst_d_sclk", .index = -1, },
 278         { .name = "aud_mst_e_sclk", .index = -1, },
 279         { .name = "aud_mst_f_sclk", .index = -1, },
 280 };
 281
 282 /* Pad sample clock sources */
 283 static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
 284         { .name = "aud_mst_a_lrclk", .index = -1, },
 285         { .name = "aud_mst_b_lrclk", .index = -1, },
 286         { .name = "aud_mst_c_lrclk", .index = -1, },
 287         { .name = "aud_mst_d_lrclk", .index = -1, },
 288         { .name = "aud_mst_e_lrclk", .index = -1, },
 289         { .name = "aud_mst_f_lrclk", .index = -1, },
 290 };
 291
 292 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents)         \
 293         AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents,          \
 294                 CLK_SET_RATE_NO_REPARENT)
 295
 296 /* Common Clocks */
 297 static struct clk_regmap ddr_arb =
 298         AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0);
 299 static struct clk_regmap pdm =
 300         AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1);
 301 static struct clk_regmap tdmin_a =
 302         AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2);
 303 static struct clk_regmap tdmin_b =
 304         AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3);
 305 static struct clk_regmap tdmin_c =
 306         AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4);
 307 static struct clk_regmap tdmin_lb =
 308         AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5);
 309 static struct clk_regmap tdmout_a =
 310         AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6);
 311 static struct clk_regmap tdmout_b =
 312         AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7);
 313 static struct clk_regmap tdmout_c =
 314         AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8);
 315 static struct clk_regmap frddr_a =
 316         AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9);
 317 static struct clk_regmap frddr_b =
 318         AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10);
 319 static struct clk_regmap frddr_c =
 320         AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11);
 321 static struct clk_regmap toddr_a =
 322         AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12);
 323 static struct clk_regmap toddr_b =
 324         AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13);
 325 static struct clk_regmap toddr_c =
 326         AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14);
 327 static struct clk_regmap loopback =
 328         AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15);
 329 static struct clk_regmap spdifin =
 330         AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16);
 331 static struct clk_regmap spdifout =
 332         AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17);
 333 static struct clk_regmap resample =
 334         AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18);
 335 static struct clk_regmap power_detect =
 336         AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19);
 337
 338 static struct clk_regmap spdifout_clk_sel =
 339         AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
 340 static struct clk_regmap pdm_dclk_sel =
 341         AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
 342 static struct clk_regmap spdifin_clk_sel =
 343         AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
 344 static struct clk_regmap pdm_sysclk_sel =
 345         AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
 346 static struct clk_regmap spdifout_b_clk_sel =
 347         AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
 348
 349 static struct clk_regmap spdifout_clk_div =
 350         AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
 351 static struct clk_regmap pdm_dclk_div =
 352         AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
 353 static struct clk_regmap spdifin_clk_div =
 354         AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
 355 static struct clk_regmap pdm_sysclk_div =
 356         AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
 357 static struct clk_regmap spdifout_b_clk_div =
 358         AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
 359
 360 static struct clk_regmap spdifout_clk =
 361         AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
 362 static struct clk_regmap spdifin_clk =
 363         AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
 364 static struct clk_regmap pdm_dclk =
 365         AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
 366 static struct clk_regmap pdm_sysclk =
 367         AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
 368 static struct clk_regmap spdifout_b_clk =
 369         AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
 370
 371 static struct clk_regmap mst_a_sclk_pre_en =
 372         AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
 373 static struct clk_regmap mst_b_sclk_pre_en =
 374         AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
 375 static struct clk_regmap mst_c_sclk_pre_en =
 376         AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
 377 static struct clk_regmap mst_d_sclk_pre_en =
 378         AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
 379 static struct clk_regmap mst_e_sclk_pre_en =
 380         AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
 381 static struct clk_regmap mst_f_sclk_pre_en =
 382         AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
 383
 384 static struct clk_regmap mst_a_sclk_div =
 385         AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
 386 static struct clk_regmap mst_b_sclk_div =
 387         AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
 388 static struct clk_regmap mst_c_sclk_div =
 389         AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
 390 static struct clk_regmap mst_d_sclk_div =
 391         AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
 392 static struct clk_regmap mst_e_sclk_div =
 393         AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
 394 static struct clk_regmap mst_f_sclk_div =
 395         AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
 396
 397 static struct clk_regmap mst_a_sclk_post_en =
 398         AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
 399 static struct clk_regmap mst_b_sclk_post_en =
 400         AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
 401 static struct clk_regmap mst_c_sclk_post_en =
 402         AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
 403 static struct clk_regmap mst_d_sclk_post_en =
 404         AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
 405 static struct clk_regmap mst_e_sclk_post_en =
 406         AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
 407 static struct clk_regmap mst_f_sclk_post_en =
 408         AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
 409
 410 static struct clk_regmap mst_a_sclk =
 411         AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
 412 static struct clk_regmap mst_b_sclk =
 413         AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
 414 static struct clk_regmap mst_c_sclk =
 415         AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
 416 static struct clk_regmap mst_d_sclk =
 417         AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
 418 static struct clk_regmap mst_e_sclk =
 419         AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
 420 static struct clk_regmap mst_f_sclk =
 421         AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
 422
 423 static struct clk_regmap mst_a_lrclk_div =
 424         AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
 425 static struct clk_regmap mst_b_lrclk_div =
 426         AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
 427 static struct clk_regmap mst_c_lrclk_div =
 428         AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
 429 static struct clk_regmap mst_d_lrclk_div =
 430         AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
 431 static struct clk_regmap mst_e_lrclk_div =
 432         AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
 433 static struct clk_regmap mst_f_lrclk_div =
 434         AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
 435
 436 static struct clk_regmap mst_a_lrclk =
 437         AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
 438 static struct clk_regmap mst_b_lrclk =
 439         AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
 440 static struct clk_regmap mst_c_lrclk =
 441         AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
 442 static struct clk_regmap mst_d_lrclk =
 443         AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
 444 static struct clk_regmap mst_e_lrclk =
 445         AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
 446 static struct clk_regmap mst_f_lrclk =
 447         AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
 448
 449 static struct clk_regmap tdmin_a_sclk_sel =
 450         AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
 451 static struct clk_regmap tdmin_b_sclk_sel =
 452         AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
 453 static struct clk_regmap tdmin_c_sclk_sel =
 454         AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);
 455 static struct clk_regmap tdmin_lb_sclk_sel =
 456         AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
 457 static struct clk_regmap tdmout_a_sclk_sel =
 458         AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
 459 static struct clk_regmap tdmout_b_sclk_sel =
 460         AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
 461 static struct clk_regmap tdmout_c_sclk_sel =
 462         AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 463
 464 static struct clk_regmap tdmin_a_sclk_pre_en =
 465         AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
 466 static struct clk_regmap tdmin_b_sclk_pre_en =
 467         AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
 468 static struct clk_regmap tdmin_c_sclk_pre_en =
 469         AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
 470 static struct clk_regmap tdmin_lb_sclk_pre_en =
 471         AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
 472 static struct clk_regmap tdmout_a_sclk_pre_en =
 473         AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
 474 static struct clk_regmap tdmout_b_sclk_pre_en =
 475         AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
 476 static struct clk_regmap tdmout_c_sclk_pre_en =
 477         AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 478
 479 static struct clk_regmap tdmin_a_sclk_post_en =
 480         AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
 481 static struct clk_regmap tdmin_b_sclk_post_en =
 482         AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
 483 static struct clk_regmap tdmin_c_sclk_post_en =
 484         AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
 485 static struct clk_regmap tdmin_lb_sclk_post_en =
 486         AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
 487 static struct clk_regmap tdmout_a_sclk_post_en =
 488         AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
 489 static struct clk_regmap tdmout_b_sclk_post_en =
 490         AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
 491 static struct clk_regmap tdmout_c_sclk_post_en =
 492         AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 493
 494 static struct clk_regmap tdmin_a_sclk =
 495         AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
 496 static struct clk_regmap tdmin_b_sclk =
 497         AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
 498 static struct clk_regmap tdmin_c_sclk =
 499         AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
 500 static struct clk_regmap tdmin_lb_sclk =
 501         AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
 502 static struct clk_regmap tdmout_a_sclk =
 503         AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
 504 static struct clk_regmap tdmout_b_sclk =
 505         AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
 506 static struct clk_regmap tdmout_c_sclk =
 507         AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 508
 509 static struct clk_regmap tdmin_a_lrclk =
 510         AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
 511 static struct clk_regmap tdmin_b_lrclk =
 512         AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
 513 static struct clk_regmap tdmin_c_lrclk =
 514         AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
 515 static struct clk_regmap tdmin_lb_lrclk =
 516         AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
 517 static struct clk_regmap tdmout_a_lrclk =
 518         AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
 519 static struct clk_regmap tdmout_b_lrclk =
 520         AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
 521 static struct clk_regmap tdmout_c_lrclk =
 522         AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 523
 524 /* AXG/G12A Clocks */
 525 static struct clk_hw axg_aud_top = {
 526         .init = &(struct clk_init_data) {
 527                 /* Provide aud_top signal name on axg and g12a */
 528                 .name = "aud_top",
 529                 .ops = &(const struct clk_ops) {},
 530                 .parent_data = &(const struct clk_parent_data) {
 531                         .fw_name = "pclk",
 532                 },
 533                 .num_parents = 1,
 534         },
 535 };
 536
 537 static struct clk_regmap mst_a_mclk_sel =
 538         AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
 539 static struct clk_regmap mst_b_mclk_sel =
 540         AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
 541 static struct clk_regmap mst_c_mclk_sel =
 542         AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
 543 static struct clk_regmap mst_d_mclk_sel =
 544         AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
 545 static struct clk_regmap mst_e_mclk_sel =
 546         AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
 547 static struct clk_regmap mst_f_mclk_sel =
 548         AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
 549
 550 static struct clk_regmap mst_a_mclk_div =
 551         AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
 552 static struct clk_regmap mst_b_mclk_div =
 553         AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
 554 static struct clk_regmap mst_c_mclk_div =
 555         AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
 556 static struct clk_regmap mst_d_mclk_div =
 557         AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
 558 static struct clk_regmap mst_e_mclk_div =
 559         AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
 560 static struct clk_regmap mst_f_mclk_div =
 561         AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
 562
 563 static struct clk_regmap mst_a_mclk =
 564         AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
 565 static struct clk_regmap mst_b_mclk =
 566         AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
 567 static struct clk_regmap mst_c_mclk =
 568         AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
 569 static struct clk_regmap mst_d_mclk =
 570         AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
 571 static struct clk_regmap mst_e_mclk =
 572         AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);
 573 static struct clk_regmap mst_f_mclk =
 574         AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);
 575
 576 /* G12a clocks */
 577 static struct clk_regmap g12a_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
 578         mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
 579 static struct clk_regmap g12a_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
 580         mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
 581 static struct clk_regmap g12a_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
 582         lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
 583 static struct clk_regmap g12a_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
 584         lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
 585 static struct clk_regmap g12a_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
 586         lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
 587 static struct clk_regmap g12a_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
 588         sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
 589 static struct clk_regmap g12a_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
 590         sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
 591 static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
 592         sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
 593
 594 /* G12a/SM1 clocks */
 595 static struct clk_regmap toram =
 596         AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20);
 597 static struct clk_regmap spdifout_b =
 598         AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21);
 599 static struct clk_regmap eqdrc =
 600         AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22);
 601
 602 /* SM1 Clocks */
 603 static struct clk_regmap sm1_clk81_en = {
 604         .data = &(struct clk_regmap_gate_data){
 605                 .offset = AUDIO_CLK81_EN,
 606                 .bit_idx = 31,
 607         },
 608         .hw.init = &(struct clk_init_data) {
 609                 .name = "aud_clk81_en",
 610                 .ops = &clk_regmap_gate_ops,
 611                 .parent_data = &(const struct clk_parent_data) {
 612                         .fw_name = "pclk",
 613                 },
 614                 .num_parents = 1,
 615         },
 616 };
 617
 618 static struct clk_regmap sm1_sysclk_a_div = {
 619         .data = &(struct clk_regmap_div_data){
 620                 .offset = AUDIO_CLK81_CTRL,
 621                 .shift = 0,
 622                 .width = 8,
 623         },
 624         .hw.init = &(struct clk_init_data) {
 625                 .name = "aud_sysclk_a_div",
 626                 .ops = &clk_regmap_divider_ops,
 627                 .parent_hws = (const struct clk_hw *[]) {
 628                         &sm1_clk81_en.hw,
 629                 },
 630                 .num_parents = 1,
 631                 .flags = CLK_SET_RATE_PARENT,
 632         },
 633 };
 634
 635 static struct clk_regmap sm1_sysclk_a_en = {
 636         .data = &(struct clk_regmap_gate_data){
 637                 .offset = AUDIO_CLK81_CTRL,
 638                 .bit_idx = 8,
 639         },
 640         .hw.init = &(struct clk_init_data) {
 641                 .name = "aud_sysclk_a_en",
 642                 .ops = &clk_regmap_gate_ops,
 643                 .parent_hws = (const struct clk_hw *[]) {
 644                         &sm1_sysclk_a_div.hw,
 645                 },
 646                 .num_parents = 1,
 647                 .flags = CLK_SET_RATE_PARENT,
 648         },
 649 };
 650
 651 static struct clk_regmap sm1_sysclk_b_div = {
 652         .data = &(struct clk_regmap_div_data){
 653                 .offset = AUDIO_CLK81_CTRL,
 654                 .shift = 16,
 655                 .width = 8,
 656         },
 657         .hw.init = &(struct clk_init_data) {
 658                 .name = "aud_sysclk_b_div",
 659                 .ops = &clk_regmap_divider_ops,
 660                 .parent_hws = (const struct clk_hw *[]) {
 661                         &sm1_clk81_en.hw,
 662                 },
 663                 .num_parents = 1,
 664                 .flags = CLK_SET_RATE_PARENT,
 665         },
 666 };
 667
 668 static struct clk_regmap sm1_sysclk_b_en = {
 669         .data = &(struct clk_regmap_gate_data){
 670                 .offset = AUDIO_CLK81_CTRL,
 671                 .bit_idx = 24,
 672         },
 673         .hw.init = &(struct clk_init_data) {
 674                 .name = "aud_sysclk_b_en",
 675                 .ops = &clk_regmap_gate_ops,
 676                 .parent_hws = (const struct clk_hw *[]) {
 677                         &sm1_sysclk_b_div.hw,
 678                 },
 679                 .num_parents = 1,
 680                 .flags = CLK_SET_RATE_PARENT,
 681         },
 682 };
 683
 684 static const struct clk_hw *sm1_aud_top_parents[] = {
 685         &sm1_sysclk_a_en.hw,
 686         &sm1_sysclk_b_en.hw,
 687 };
 688
 689 static struct clk_regmap sm1_aud_top = {
 690         .data = &(struct clk_regmap_mux_data){
 691                 .offset = AUDIO_CLK81_CTRL,
 692                 .mask = 0x1,
 693                 .shift = 31,
 694         },
 695         .hw.init = &(struct clk_init_data){
 696                 .name = "aud_top",
 697                 .ops = &clk_regmap_mux_ops,
 698                 .parent_hws = sm1_aud_top_parents,
 699                 .num_parents = ARRAY_SIZE(sm1_aud_top_parents),
 700                 .flags = CLK_SET_RATE_NO_REPARENT,
 701         },
 702 };
 703
 704 static struct clk_regmap resample_b =
 705         AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26);
 706 static struct clk_regmap tovad =
 707         AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27);
 708 static struct clk_regmap locker =
 709         AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28);
 710 static struct clk_regmap spdifin_lb =
 711         AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29);
 712 static struct clk_regmap frddr_d =
 713         AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0);
 714 static struct clk_regmap toddr_d =
 715         AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1);
 716 static struct clk_regmap loopback_b =
 717         AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2);
 718
 719 static struct clk_regmap sm1_mst_a_mclk_sel =
 720         AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
 721 static struct clk_regmap sm1_mst_b_mclk_sel =
 722         AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
 723 static struct clk_regmap sm1_mst_c_mclk_sel =
 724         AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
 725 static struct clk_regmap sm1_mst_d_mclk_sel =
 726         AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
 727 static struct clk_regmap sm1_mst_e_mclk_sel =
 728         AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
 729 static struct clk_regmap sm1_mst_f_mclk_sel =
 730         AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
 731
 732 static struct clk_regmap sm1_mst_a_mclk_div =
 733         AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
 734 static struct clk_regmap sm1_mst_b_mclk_div =
 735         AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
 736 static struct clk_regmap sm1_mst_c_mclk_div =
 737         AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
 738 static struct clk_regmap sm1_mst_d_mclk_div =
 739         AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
 740 static struct clk_regmap sm1_mst_e_mclk_div =
 741         AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
 742 static struct clk_regmap sm1_mst_f_mclk_div =
 743         AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
 744
 745 static struct clk_regmap sm1_mst_a_mclk =
 746         AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
 747 static struct clk_regmap sm1_mst_b_mclk =
 748         AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
 749 static struct clk_regmap sm1_mst_c_mclk =
 750         AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
 751 static struct clk_regmap sm1_mst_d_mclk =
 752         AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
 753 static struct clk_regmap sm1_mst_e_mclk =
 754         AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
 755 static struct clk_regmap sm1_mst_f_mclk =
 756         AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
 757
 758 static struct clk_regmap sm1_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
 759         tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
 760 static struct clk_regmap sm1_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
 761         tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
 762 static struct clk_regmap sm1_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
 763         tdm_lrclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
 764 static struct clk_regmap sm1_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
 765         tdm_lrclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
 766 static struct clk_regmap sm1_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
 767         tdm_lrclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
 768 static struct clk_regmap sm1_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
 769         tdm_sclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
 770 static struct clk_regmap sm1_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
 771         tdm_sclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
 772 static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
 773         tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
 774
 775 /*
 776  * Array of all clocks provided by this provider
 777  * The input clocks of the controller will be populated at runtime
 778  */
 779 static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
 780         .hws = {
 781                 [AUD_CLKID_DDR_ARB]             = &ddr_arb.hw,
 782                 [AUD_CLKID_PDM]                 = &pdm.hw,
 783                 [AUD_CLKID_TDMIN_A]             = &tdmin_a.hw,
 784                 [AUD_CLKID_TDMIN_B]             = &tdmin_b.hw,
 785                 [AUD_CLKID_TDMIN_C]             = &tdmin_c.hw,
 786                 [AUD_CLKID_TDMIN_LB]            = &tdmin_lb.hw,
 787                 [AUD_CLKID_TDMOUT_A]            = &tdmout_a.hw,
 788                 [AUD_CLKID_TDMOUT_B]            = &tdmout_b.hw,
 789                 [AUD_CLKID_TDMOUT_C]            = &tdmout_c.hw,
 790                 [AUD_CLKID_FRDDR_A]             = &frddr_a.hw,
 791                 [AUD_CLKID_FRDDR_B]             = &frddr_b.hw,
 792                 [AUD_CLKID_FRDDR_C]             = &frddr_c.hw,
 793                 [AUD_CLKID_TODDR_A]             = &toddr_a.hw,
 794                 [AUD_CLKID_TODDR_B]             = &toddr_b.hw,
 795                 [AUD_CLKID_TODDR_C]             = &toddr_c.hw,
 796                 [AUD_CLKID_LOOPBACK]            = &loopback.hw,
 797                 [AUD_CLKID_SPDIFIN]             = &spdifin.hw,
 798                 [AUD_CLKID_SPDIFOUT]            = &spdifout.hw,
 799                 [AUD_CLKID_RESAMPLE]            = &resample.hw,
 800                 [AUD_CLKID_POWER_DETECT]        = &power_detect.hw,
 801                 [AUD_CLKID_MST_A_MCLK_SEL]      = &mst_a_mclk_sel.hw,
 802                 [AUD_CLKID_MST_B_MCLK_SEL]      = &mst_b_mclk_sel.hw,
 803                 [AUD_CLKID_MST_C_MCLK_SEL]      = &mst_c_mclk_sel.hw,
 804                 [AUD_CLKID_MST_D_MCLK_SEL]      = &mst_d_mclk_sel.hw,
 805                 [AUD_CLKID_MST_E_MCLK_SEL]      = &mst_e_mclk_sel.hw,
 806                 [AUD_CLKID_MST_F_MCLK_SEL]      = &mst_f_mclk_sel.hw,
 807                 [AUD_CLKID_MST_A_MCLK_DIV]      = &mst_a_mclk_div.hw,
 808                 [AUD_CLKID_MST_B_MCLK_DIV]      = &mst_b_mclk_div.hw,
 809                 [AUD_CLKID_MST_C_MCLK_DIV]      = &mst_c_mclk_div.hw,
 810                 [AUD_CLKID_MST_D_MCLK_DIV]      = &mst_d_mclk_div.hw,
 811                 [AUD_CLKID_MST_E_MCLK_DIV]      = &mst_e_mclk_div.hw,
 812                 [AUD_CLKID_MST_F_MCLK_DIV]      = &mst_f_mclk_div.hw,
 813                 [AUD_CLKID_MST_A_MCLK]          = &mst_a_mclk.hw,
 814                 [AUD_CLKID_MST_B_MCLK]          = &mst_b_mclk.hw,
 815                 [AUD_CLKID_MST_C_MCLK]          = &mst_c_mclk.hw,
 816                 [AUD_CLKID_MST_D_MCLK]          = &mst_d_mclk.hw,
 817                 [AUD_CLKID_MST_E_MCLK]          = &mst_e_mclk.hw,
 818                 [AUD_CLKID_MST_F_MCLK]          = &mst_f_mclk.hw,
 819                 [AUD_CLKID_SPDIFOUT_CLK_SEL]    = &spdifout_clk_sel.hw,
 820                 [AUD_CLKID_SPDIFOUT_CLK_DIV]    = &spdifout_clk_div.hw,
 821                 [AUD_CLKID_SPDIFOUT_CLK]        = &spdifout_clk.hw,
 822                 [AUD_CLKID_SPDIFIN_CLK_SEL]     = &spdifin_clk_sel.hw,
 823                 [AUD_CLKID_SPDIFIN_CLK_DIV]     = &spdifin_clk_div.hw,
 824                 [AUD_CLKID_SPDIFIN_CLK]         = &spdifin_clk.hw,
 825                 [AUD_CLKID_PDM_DCLK_SEL]        = &pdm_dclk_sel.hw,
 826                 [AUD_CLKID_PDM_DCLK_DIV]        = &pdm_dclk_div.hw,
 827                 [AUD_CLKID_PDM_DCLK]            = &pdm_dclk.hw,
 828                 [AUD_CLKID_PDM_SYSCLK_SEL]      = &pdm_sysclk_sel.hw,
 829                 [AUD_CLKID_PDM_SYSCLK_DIV]      = &pdm_sysclk_div.hw,
 830                 [AUD_CLKID_PDM_SYSCLK]          = &pdm_sysclk.hw,
 831                 [AUD_CLKID_MST_A_SCLK_PRE_EN]   = &mst_a_sclk_pre_en.hw,
 832                 [AUD_CLKID_MST_B_SCLK_PRE_EN]   = &mst_b_sclk_pre_en.hw,
 833                 [AUD_CLKID_MST_C_SCLK_PRE_EN]   = &mst_c_sclk_pre_en.hw,
 834                 [AUD_CLKID_MST_D_SCLK_PRE_EN]   = &mst_d_sclk_pre_en.hw,
 835                 [AUD_CLKID_MST_E_SCLK_PRE_EN]   = &mst_e_sclk_pre_en.hw,
 836                 [AUD_CLKID_MST_F_SCLK_PRE_EN]   = &mst_f_sclk_pre_en.hw,
 837                 [AUD_CLKID_MST_A_SCLK_DIV]      = &mst_a_sclk_div.hw,
 838                 [AUD_CLKID_MST_B_SCLK_DIV]      = &mst_b_sclk_div.hw,
 839                 [AUD_CLKID_MST_C_SCLK_DIV]      = &mst_c_sclk_div.hw,
 840                 [AUD_CLKID_MST_D_SCLK_DIV]      = &mst_d_sclk_div.hw,
 841                 [AUD_CLKID_MST_E_SCLK_DIV]      = &mst_e_sclk_div.hw,
 842                 [AUD_CLKID_MST_F_SCLK_DIV]      = &mst_f_sclk_div.hw,
 843                 [AUD_CLKID_MST_A_SCLK_POST_EN]  = &mst_a_sclk_post_en.hw,
 844                 [AUD_CLKID_MST_B_SCLK_POST_EN]  = &mst_b_sclk_post_en.hw,
 845                 [AUD_CLKID_MST_C_SCLK_POST_EN]  = &mst_c_sclk_post_en.hw,
 846                 [AUD_CLKID_MST_D_SCLK_POST_EN]  = &mst_d_sclk_post_en.hw,
 847                 [AUD_CLKID_MST_E_SCLK_POST_EN]  = &mst_e_sclk_post_en.hw,
 848                 [AUD_CLKID_MST_F_SCLK_POST_EN]  = &mst_f_sclk_post_en.hw,
 849                 [AUD_CLKID_MST_A_SCLK]          = &mst_a_sclk.hw,
 850                 [AUD_CLKID_MST_B_SCLK]          = &mst_b_sclk.hw,
 851                 [AUD_CLKID_MST_C_SCLK]          = &mst_c_sclk.hw,
 852                 [AUD_CLKID_MST_D_SCLK]          = &mst_d_sclk.hw,
 853                 [AUD_CLKID_MST_E_SCLK]          = &mst_e_sclk.hw,
 854                 [AUD_CLKID_MST_F_SCLK]          = &mst_f_sclk.hw,
 855                 [AUD_CLKID_MST_A_LRCLK_DIV]     = &mst_a_lrclk_div.hw,
 856                 [AUD_CLKID_MST_B_LRCLK_DIV]     = &mst_b_lrclk_div.hw,
 857                 [AUD_CLKID_MST_C_LRCLK_DIV]     = &mst_c_lrclk_div.hw,
 858                 [AUD_CLKID_MST_D_LRCLK_DIV]     = &mst_d_lrclk_div.hw,
 859                 [AUD_CLKID_MST_E_LRCLK_DIV]     = &mst_e_lrclk_div.hw,
 860                 [AUD_CLKID_MST_F_LRCLK_DIV]     = &mst_f_lrclk_div.hw,
 861                 [AUD_CLKID_MST_A_LRCLK]         = &mst_a_lrclk.hw,
 862                 [AUD_CLKID_MST_B_LRCLK]         = &mst_b_lrclk.hw,
 863                 [AUD_CLKID_MST_C_LRCLK]         = &mst_c_lrclk.hw,
 864                 [AUD_CLKID_MST_D_LRCLK]         = &mst_d_lrclk.hw,
 865                 [AUD_CLKID_MST_E_LRCLK]         = &mst_e_lrclk.hw,
 866                 [AUD_CLKID_MST_F_LRCLK]         = &mst_f_lrclk.hw,
 867                 [AUD_CLKID_TDMIN_A_SCLK_SEL]    = &tdmin_a_sclk_sel.hw,
 868                 [AUD_CLKID_TDMIN_B_SCLK_SEL]    = &tdmin_b_sclk_sel.hw,
 869                 [AUD_CLKID_TDMIN_C_SCLK_SEL]    = &tdmin_c_sclk_sel.hw,
 870                 [AUD_CLKID_TDMIN_LB_SCLK_SEL]   = &tdmin_lb_sclk_sel.hw,
 871                 [AUD_CLKID_TDMOUT_A_SCLK_SEL]   = &tdmout_a_sclk_sel.hw,
 872                 [AUD_CLKID_TDMOUT_B_SCLK_SEL]   = &tdmout_b_sclk_sel.hw,
 873                 [AUD_CLKID_TDMOUT_C_SCLK_SEL]   = &tdmout_c_sclk_sel.hw,
 874                 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
 875                 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
 876                 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
 877                 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
 878                 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
 879                 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
 880                 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
 881                 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
 882                 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
 883                 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
 884                 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
 885                 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
 886                 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
 887                 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
 888                 [AUD_CLKID_TDMIN_A_SCLK]        = &tdmin_a_sclk.hw,
 889                 [AUD_CLKID_TDMIN_B_SCLK]        = &tdmin_b_sclk.hw,
 890                 [AUD_CLKID_TDMIN_C_SCLK]        = &tdmin_c_sclk.hw,
 891                 [AUD_CLKID_TDMIN_LB_SCLK]       = &tdmin_lb_sclk.hw,
 892                 [AUD_CLKID_TDMOUT_A_SCLK]       = &tdmout_a_sclk.hw,
 893                 [AUD_CLKID_TDMOUT_B_SCLK]       = &tdmout_b_sclk.hw,
 894                 [AUD_CLKID_TDMOUT_C_SCLK]       = &tdmout_c_sclk.hw,
 895                 [AUD_CLKID_TDMIN_A_LRCLK]       = &tdmin_a_lrclk.hw,
 896                 [AUD_CLKID_TDMIN_B_LRCLK]       = &tdmin_b_lrclk.hw,
 897                 [AUD_CLKID_TDMIN_C_LRCLK]       = &tdmin_c_lrclk.hw,
 898                 [AUD_CLKID_TDMIN_LB_LRCLK]      = &tdmin_lb_lrclk.hw,
 899                 [AUD_CLKID_TDMOUT_A_LRCLK]      = &tdmout_a_lrclk.hw,
 900                 [AUD_CLKID_TDMOUT_B_LRCLK]      = &tdmout_b_lrclk.hw,
 901                 [AUD_CLKID_TDMOUT_C_LRCLK]      = &tdmout_c_lrclk.hw,
 902                 [AUD_CLKID_TOP]                 = &axg_aud_top,
 903                 [NR_CLKS] = NULL,
 904         },
 905         .num = NR_CLKS,
 906 };
 907
 908 /*
 909  * Array of all G12A clocks provided by this provider
 910  * The input clocks of the controller will be populated at runtime
 911  */
 912 static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
 913         .hws = {
 914                 [AUD_CLKID_DDR_ARB]             = &ddr_arb.hw,
 915                 [AUD_CLKID_PDM]                 = &pdm.hw,
 916                 [AUD_CLKID_TDMIN_A]             = &tdmin_a.hw,
 917                 [AUD_CLKID_TDMIN_B]             = &tdmin_b.hw,
 918                 [AUD_CLKID_TDMIN_C]             = &tdmin_c.hw,
 919                 [AUD_CLKID_TDMIN_LB]            = &tdmin_lb.hw,
 920                 [AUD_CLKID_TDMOUT_A]            = &tdmout_a.hw,
 921                 [AUD_CLKID_TDMOUT_B]            = &tdmout_b.hw,
 922                 [AUD_CLKID_TDMOUT_C]            = &tdmout_c.hw,
 923                 [AUD_CLKID_FRDDR_A]             = &frddr_a.hw,
 924                 [AUD_CLKID_FRDDR_B]             = &frddr_b.hw,
 925                 [AUD_CLKID_FRDDR_C]             = &frddr_c.hw,
 926                 [AUD_CLKID_TODDR_A]             = &toddr_a.hw,
 927                 [AUD_CLKID_TODDR_B]             = &toddr_b.hw,
 928                 [AUD_CLKID_TODDR_C]             = &toddr_c.hw,
 929                 [AUD_CLKID_LOOPBACK]            = &loopback.hw,
 930                 [AUD_CLKID_SPDIFIN]             = &spdifin.hw,
 931                 [AUD_CLKID_SPDIFOUT]            = &spdifout.hw,
 932                 [AUD_CLKID_RESAMPLE]            = &resample.hw,
 933                 [AUD_CLKID_POWER_DETECT]        = &power_detect.hw,
 934                 [AUD_CLKID_SPDIFOUT_B]          = &spdifout_b.hw,
 935                 [AUD_CLKID_MST_A_MCLK_SEL]      = &mst_a_mclk_sel.hw,
 936                 [AUD_CLKID_MST_B_MCLK_SEL]      = &mst_b_mclk_sel.hw,
 937                 [AUD_CLKID_MST_C_MCLK_SEL]      = &mst_c_mclk_sel.hw,
 938                 [AUD_CLKID_MST_D_MCLK_SEL]      = &mst_d_mclk_sel.hw,
 939                 [AUD_CLKID_MST_E_MCLK_SEL]      = &mst_e_mclk_sel.hw,
 940                 [AUD_CLKID_MST_F_MCLK_SEL]      = &mst_f_mclk_sel.hw,
 941                 [AUD_CLKID_MST_A_MCLK_DIV]      = &mst_a_mclk_div.hw,
 942                 [AUD_CLKID_MST_B_MCLK_DIV]      = &mst_b_mclk_div.hw,
 943                 [AUD_CLKID_MST_C_MCLK_DIV]      = &mst_c_mclk_div.hw,
 944                 [AUD_CLKID_MST_D_MCLK_DIV]      = &mst_d_mclk_div.hw,
 945                 [AUD_CLKID_MST_E_MCLK_DIV]      = &mst_e_mclk_div.hw,
 946                 [AUD_CLKID_MST_F_MCLK_DIV]      = &mst_f_mclk_div.hw,
 947                 [AUD_CLKID_MST_A_MCLK]          = &mst_a_mclk.hw,
 948                 [AUD_CLKID_MST_B_MCLK]          = &mst_b_mclk.hw,
 949                 [AUD_CLKID_MST_C_MCLK]          = &mst_c_mclk.hw,
 950                 [AUD_CLKID_MST_D_MCLK]          = &mst_d_mclk.hw,
 951                 [AUD_CLKID_MST_E_MCLK]          = &mst_e_mclk.hw,
 952                 [AUD_CLKID_MST_F_MCLK]          = &mst_f_mclk.hw,
 953                 [AUD_CLKID_SPDIFOUT_CLK_SEL]    = &spdifout_clk_sel.hw,
 954                 [AUD_CLKID_SPDIFOUT_CLK_DIV]    = &spdifout_clk_div.hw,
 955                 [AUD_CLKID_SPDIFOUT_CLK]        = &spdifout_clk.hw,
 956                 [AUD_CLKID_SPDIFOUT_B_CLK_SEL]  = &spdifout_b_clk_sel.hw,
 957                 [AUD_CLKID_SPDIFOUT_B_CLK_DIV]  = &spdifout_b_clk_div.hw,
 958                 [AUD_CLKID_SPDIFOUT_B_CLK]      = &spdifout_b_clk.hw,
 959                 [AUD_CLKID_SPDIFIN_CLK_SEL]     = &spdifin_clk_sel.hw,
 960                 [AUD_CLKID_SPDIFIN_CLK_DIV]     = &spdifin_clk_div.hw,
 961                 [AUD_CLKID_SPDIFIN_CLK]         = &spdifin_clk.hw,
 962                 [AUD_CLKID_PDM_DCLK_SEL]        = &pdm_dclk_sel.hw,
 963                 [AUD_CLKID_PDM_DCLK_DIV]        = &pdm_dclk_div.hw,
 964                 [AUD_CLKID_PDM_DCLK]            = &pdm_dclk.hw,
 965                 [AUD_CLKID_PDM_SYSCLK_SEL]      = &pdm_sysclk_sel.hw,
 966                 [AUD_CLKID_PDM_SYSCLK_DIV]      = &pdm_sysclk_div.hw,
 967                 [AUD_CLKID_PDM_SYSCLK]          = &pdm_sysclk.hw,
 968                 [AUD_CLKID_MST_A_SCLK_PRE_EN]   = &mst_a_sclk_pre_en.hw,
 969                 [AUD_CLKID_MST_B_SCLK_PRE_EN]   = &mst_b_sclk_pre_en.hw,
 970                 [AUD_CLKID_MST_C_SCLK_PRE_EN]   = &mst_c_sclk_pre_en.hw,
 971                 [AUD_CLKID_MST_D_SCLK_PRE_EN]   = &mst_d_sclk_pre_en.hw,
 972                 [AUD_CLKID_MST_E_SCLK_PRE_EN]   = &mst_e_sclk_pre_en.hw,
 973                 [AUD_CLKID_MST_F_SCLK_PRE_EN]   = &mst_f_sclk_pre_en.hw,
 974                 [AUD_CLKID_MST_A_SCLK_DIV]      = &mst_a_sclk_div.hw,
 975                 [AUD_CLKID_MST_B_SCLK_DIV]      = &mst_b_sclk_div.hw,
 976                 [AUD_CLKID_MST_C_SCLK_DIV]      = &mst_c_sclk_div.hw,
 977                 [AUD_CLKID_MST_D_SCLK_DIV]      = &mst_d_sclk_div.hw,
 978                 [AUD_CLKID_MST_E_SCLK_DIV]      = &mst_e_sclk_div.hw,
 979                 [AUD_CLKID_MST_F_SCLK_DIV]      = &mst_f_sclk_div.hw,
 980                 [AUD_CLKID_MST_A_SCLK_POST_EN]  = &mst_a_sclk_post_en.hw,
 981                 [AUD_CLKID_MST_B_SCLK_POST_EN]  = &mst_b_sclk_post_en.hw,
 982                 [AUD_CLKID_MST_C_SCLK_POST_EN]  = &mst_c_sclk_post_en.hw,
 983                 [AUD_CLKID_MST_D_SCLK_POST_EN]  = &mst_d_sclk_post_en.hw,
 984                 [AUD_CLKID_MST_E_SCLK_POST_EN]  = &mst_e_sclk_post_en.hw,
 985                 [AUD_CLKID_MST_F_SCLK_POST_EN]  = &mst_f_sclk_post_en.hw,
 986                 [AUD_CLKID_MST_A_SCLK]          = &mst_a_sclk.hw,
 987                 [AUD_CLKID_MST_B_SCLK]          = &mst_b_sclk.hw,
 988                 [AUD_CLKID_MST_C_SCLK]          = &mst_c_sclk.hw,
 989                 [AUD_CLKID_MST_D_SCLK]          = &mst_d_sclk.hw,
 990                 [AUD_CLKID_MST_E_SCLK]          = &mst_e_sclk.hw,
 991                 [AUD_CLKID_MST_F_SCLK]          = &mst_f_sclk.hw,
 992                 [AUD_CLKID_MST_A_LRCLK_DIV]     = &mst_a_lrclk_div.hw,
 993                 [AUD_CLKID_MST_B_LRCLK_DIV]     = &mst_b_lrclk_div.hw,
 994                 [AUD_CLKID_MST_C_LRCLK_DIV]     = &mst_c_lrclk_div.hw,
 995                 [AUD_CLKID_MST_D_LRCLK_DIV]     = &mst_d_lrclk_div.hw,
 996                 [AUD_CLKID_MST_E_LRCLK_DIV]     = &mst_e_lrclk_div.hw,
 997                 [AUD_CLKID_MST_F_LRCLK_DIV]     = &mst_f_lrclk_div.hw,
 998                 [AUD_CLKID_MST_A_LRCLK]         = &mst_a_lrclk.hw,
 999                 [AUD_CLKID_MST_B_LRCLK]         = &mst_b_lrclk.hw,
1000                 [AUD_CLKID_MST_C_LRCLK]         = &mst_c_lrclk.hw,
1001                 [AUD_CLKID_MST_D_LRCLK]         = &mst_d_lrclk.hw,
1002                 [AUD_CLKID_MST_E_LRCLK]         = &mst_e_lrclk.hw,
1003                 [AUD_CLKID_MST_F_LRCLK]         = &mst_f_lrclk.hw,
1004                 [AUD_CLKID_TDMIN_A_SCLK_SEL]    = &tdmin_a_sclk_sel.hw,
1005                 [AUD_CLKID_TDMIN_B_SCLK_SEL]    = &tdmin_b_sclk_sel.hw,
1006                 [AUD_CLKID_TDMIN_C_SCLK_SEL]    = &tdmin_c_sclk_sel.hw,
1007                 [AUD_CLKID_TDMIN_LB_SCLK_SEL]   = &tdmin_lb_sclk_sel.hw,
1008                 [AUD_CLKID_TDMOUT_A_SCLK_SEL]   = &tdmout_a_sclk_sel.hw,
1009                 [AUD_CLKID_TDMOUT_B_SCLK_SEL]   = &tdmout_b_sclk_sel.hw,
1010                 [AUD_CLKID_TDMOUT_C_SCLK_SEL]   = &tdmout_c_sclk_sel.hw,
1011                 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
1012                 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
1013                 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
1014                 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1015                 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1016                 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1017                 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1018                 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1019                 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1020                 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1021                 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1022                 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1023                 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1024                 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1025                 [AUD_CLKID_TDMIN_A_SCLK]        = &tdmin_a_sclk.hw,
1026                 [AUD_CLKID_TDMIN_B_SCLK]        = &tdmin_b_sclk.hw,
1027                 [AUD_CLKID_TDMIN_C_SCLK]        = &tdmin_c_sclk.hw,
1028                 [AUD_CLKID_TDMIN_LB_SCLK]       = &tdmin_lb_sclk.hw,
1029                 [AUD_CLKID_TDMOUT_A_SCLK]       = &tdmout_a_sclk.hw,
1030                 [AUD_CLKID_TDMOUT_B_SCLK]       = &tdmout_b_sclk.hw,
1031                 [AUD_CLKID_TDMOUT_C_SCLK]       = &tdmout_c_sclk.hw,
1032                 [AUD_CLKID_TDMIN_A_LRCLK]       = &tdmin_a_lrclk.hw,
1033                 [AUD_CLKID_TDMIN_B_LRCLK]       = &tdmin_b_lrclk.hw,
1034                 [AUD_CLKID_TDMIN_C_LRCLK]       = &tdmin_c_lrclk.hw,
1035                 [AUD_CLKID_TDMIN_LB_LRCLK]      = &tdmin_lb_lrclk.hw,
1036                 [AUD_CLKID_TDMOUT_A_LRCLK]      = &tdmout_a_lrclk.hw,
1037                 [AUD_CLKID_TDMOUT_B_LRCLK]      = &tdmout_b_lrclk.hw,
1038                 [AUD_CLKID_TDMOUT_C_LRCLK]      = &tdmout_c_lrclk.hw,
1039                 [AUD_CLKID_TDM_MCLK_PAD0]       = &g12a_tdm_mclk_pad_0.hw,
1040                 [AUD_CLKID_TDM_MCLK_PAD1]       = &g12a_tdm_mclk_pad_1.hw,
1041                 [AUD_CLKID_TDM_LRCLK_PAD0]      = &g12a_tdm_lrclk_pad_0.hw,
1042                 [AUD_CLKID_TDM_LRCLK_PAD1]      = &g12a_tdm_lrclk_pad_1.hw,
1043                 [AUD_CLKID_TDM_LRCLK_PAD2]      = &g12a_tdm_lrclk_pad_2.hw,
1044                 [AUD_CLKID_TDM_SCLK_PAD0]       = &g12a_tdm_sclk_pad_0.hw,
1045                 [AUD_CLKID_TDM_SCLK_PAD1]       = &g12a_tdm_sclk_pad_1.hw,
1046                 [AUD_CLKID_TDM_SCLK_PAD2]       = &g12a_tdm_sclk_pad_2.hw,
1047                 [AUD_CLKID_TOP]                 = &axg_aud_top,
1048                 [NR_CLKS] = NULL,
1049         },
1050         .num = NR_CLKS,
1051 };
1052
1053 /*
1054  * Array of all SM1 clocks provided by this provider
1055  * The input clocks of the controller will be populated at runtime
1056  */
1057 static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
1058         .hws = {
1059                 [AUD_CLKID_DDR_ARB]             = &ddr_arb.hw,
1060                 [AUD_CLKID_PDM]                 = &pdm.hw,
1061                 [AUD_CLKID_TDMIN_A]             = &tdmin_a.hw,
1062                 [AUD_CLKID_TDMIN_B]             = &tdmin_b.hw,
1063                 [AUD_CLKID_TDMIN_C]             = &tdmin_c.hw,
1064                 [AUD_CLKID_TDMIN_LB]            = &tdmin_lb.hw,
1065                 [AUD_CLKID_TDMOUT_A]            = &tdmout_a.hw,
1066                 [AUD_CLKID_TDMOUT_B]            = &tdmout_b.hw,
1067                 [AUD_CLKID_TDMOUT_C]            = &tdmout_c.hw,
1068                 [AUD_CLKID_FRDDR_A]             = &frddr_a.hw,
1069                 [AUD_CLKID_FRDDR_B]             = &frddr_b.hw,
1070                 [AUD_CLKID_FRDDR_C]             = &frddr_c.hw,
1071                 [AUD_CLKID_TODDR_A]             = &toddr_a.hw,
1072                 [AUD_CLKID_TODDR_B]             = &toddr_b.hw,
1073                 [AUD_CLKID_TODDR_C]             = &toddr_c.hw,
1074                 [AUD_CLKID_LOOPBACK]            = &loopback.hw,
1075                 [AUD_CLKID_SPDIFIN]             = &spdifin.hw,
1076                 [AUD_CLKID_SPDIFOUT]            = &spdifout.hw,
1077                 [AUD_CLKID_RESAMPLE]            = &resample.hw,
1078                 [AUD_CLKID_SPDIFOUT_B]          = &spdifout_b.hw,
1079                 [AUD_CLKID_MST_A_MCLK_SEL]      = &sm1_mst_a_mclk_sel.hw,
1080                 [AUD_CLKID_MST_B_MCLK_SEL]      = &sm1_mst_b_mclk_sel.hw,
1081                 [AUD_CLKID_MST_C_MCLK_SEL]      = &sm1_mst_c_mclk_sel.hw,
1082                 [AUD_CLKID_MST_D_MCLK_SEL]      = &sm1_mst_d_mclk_sel.hw,
1083                 [AUD_CLKID_MST_E_MCLK_SEL]      = &sm1_mst_e_mclk_sel.hw,
1084                 [AUD_CLKID_MST_F_MCLK_SEL]      = &sm1_mst_f_mclk_sel.hw,
1085                 [AUD_CLKID_MST_A_MCLK_DIV]      = &sm1_mst_a_mclk_div.hw,
1086                 [AUD_CLKID_MST_B_MCLK_DIV]      = &sm1_mst_b_mclk_div.hw,
1087                 [AUD_CLKID_MST_C_MCLK_DIV]      = &sm1_mst_c_mclk_div.hw,
1088                 [AUD_CLKID_MST_D_MCLK_DIV]      = &sm1_mst_d_mclk_div.hw,
1089                 [AUD_CLKID_MST_E_MCLK_DIV]      = &sm1_mst_e_mclk_div.hw,
1090                 [AUD_CLKID_MST_F_MCLK_DIV]      = &sm1_mst_f_mclk_div.hw,
1091                 [AUD_CLKID_MST_A_MCLK]          = &sm1_mst_a_mclk.hw,
1092                 [AUD_CLKID_MST_B_MCLK]          = &sm1_mst_b_mclk.hw,
1093                 [AUD_CLKID_MST_C_MCLK]          = &sm1_mst_c_mclk.hw,
1094                 [AUD_CLKID_MST_D_MCLK]          = &sm1_mst_d_mclk.hw,
1095                 [AUD_CLKID_MST_E_MCLK]          = &sm1_mst_e_mclk.hw,
1096                 [AUD_CLKID_MST_F_MCLK]          = &sm1_mst_f_mclk.hw,
1097                 [AUD_CLKID_SPDIFOUT_CLK_SEL]    = &spdifout_clk_sel.hw,
1098                 [AUD_CLKID_SPDIFOUT_CLK_DIV]    = &spdifout_clk_div.hw,
1099                 [AUD_CLKID_SPDIFOUT_CLK]        = &spdifout_clk.hw,
1100                 [AUD_CLKID_SPDIFOUT_B_CLK_SEL]  = &spdifout_b_clk_sel.hw,
1101                 [AUD_CLKID_SPDIFOUT_B_CLK_DIV]  = &spdifout_b_clk_div.hw,
1102                 [AUD_CLKID_SPDIFOUT_B_CLK]      = &spdifout_b_clk.hw,
1103                 [AUD_CLKID_SPDIFIN_CLK_SEL]     = &spdifin_clk_sel.hw,
1104                 [AUD_CLKID_SPDIFIN_CLK_DIV]     = &spdifin_clk_div.hw,
1105                 [AUD_CLKID_SPDIFIN_CLK]         = &spdifin_clk.hw,
1106                 [AUD_CLKID_PDM_DCLK_SEL]        = &pdm_dclk_sel.hw,
1107                 [AUD_CLKID_PDM_DCLK_DIV]        = &pdm_dclk_div.hw,
1108                 [AUD_CLKID_PDM_DCLK]            = &pdm_dclk.hw,
1109                 [AUD_CLKID_PDM_SYSCLK_SEL]      = &pdm_sysclk_sel.hw,
1110                 [AUD_CLKID_PDM_SYSCLK_DIV]      = &pdm_sysclk_div.hw,
1111                 [AUD_CLKID_PDM_SYSCLK]          = &pdm_sysclk.hw,
1112                 [AUD_CLKID_MST_A_SCLK_PRE_EN]   = &mst_a_sclk_pre_en.hw,
1113                 [AUD_CLKID_MST_B_SCLK_PRE_EN]   = &mst_b_sclk_pre_en.hw,
1114                 [AUD_CLKID_MST_C_SCLK_PRE_EN]   = &mst_c_sclk_pre_en.hw,
1115                 [AUD_CLKID_MST_D_SCLK_PRE_EN]   = &mst_d_sclk_pre_en.hw,
1116                 [AUD_CLKID_MST_E_SCLK_PRE_EN]   = &mst_e_sclk_pre_en.hw,
1117                 [AUD_CLKID_MST_F_SCLK_PRE_EN]   = &mst_f_sclk_pre_en.hw,
1118                 [AUD_CLKID_MST_A_SCLK_DIV]      = &mst_a_sclk_div.hw,
1119                 [AUD_CLKID_MST_B_SCLK_DIV]      = &mst_b_sclk_div.hw,
1120                 [AUD_CLKID_MST_C_SCLK_DIV]      = &mst_c_sclk_div.hw,
1121                 [AUD_CLKID_MST_D_SCLK_DIV]      = &mst_d_sclk_div.hw,
1122                 [AUD_CLKID_MST_E_SCLK_DIV]      = &mst_e_sclk_div.hw,
1123                 [AUD_CLKID_MST_F_SCLK_DIV]      = &mst_f_sclk_div.hw,
1124                 [AUD_CLKID_MST_A_SCLK_POST_EN]  = &mst_a_sclk_post_en.hw,
1125                 [AUD_CLKID_MST_B_SCLK_POST_EN]  = &mst_b_sclk_post_en.hw,
1126                 [AUD_CLKID_MST_C_SCLK_POST_EN]  = &mst_c_sclk_post_en.hw,
1127                 [AUD_CLKID_MST_D_SCLK_POST_EN]  = &mst_d_sclk_post_en.hw,
1128                 [AUD_CLKID_MST_E_SCLK_POST_EN]  = &mst_e_sclk_post_en.hw,
1129                 [AUD_CLKID_MST_F_SCLK_POST_EN]  = &mst_f_sclk_post_en.hw,
1130                 [AUD_CLKID_MST_A_SCLK]          = &mst_a_sclk.hw,
1131                 [AUD_CLKID_MST_B_SCLK]          = &mst_b_sclk.hw,
1132                 [AUD_CLKID_MST_C_SCLK]          = &mst_c_sclk.hw,
1133                 [AUD_CLKID_MST_D_SCLK]          = &mst_d_sclk.hw,
1134                 [AUD_CLKID_MST_E_SCLK]          = &mst_e_sclk.hw,
1135                 [AUD_CLKID_MST_F_SCLK]          = &mst_f_sclk.hw,
1136                 [AUD_CLKID_MST_A_LRCLK_DIV]     = &mst_a_lrclk_div.hw,
1137                 [AUD_CLKID_MST_B_LRCLK_DIV]     = &mst_b_lrclk_div.hw,
1138                 [AUD_CLKID_MST_C_LRCLK_DIV]     = &mst_c_lrclk_div.hw,
1139                 [AUD_CLKID_MST_D_LRCLK_DIV]     = &mst_d_lrclk_div.hw,
1140                 [AUD_CLKID_MST_E_LRCLK_DIV]     = &mst_e_lrclk_div.hw,
1141                 [AUD_CLKID_MST_F_LRCLK_DIV]     = &mst_f_lrclk_div.hw,
1142                 [AUD_CLKID_MST_A_LRCLK]         = &mst_a_lrclk.hw,
1143                 [AUD_CLKID_MST_B_LRCLK]         = &mst_b_lrclk.hw,
1144                 [AUD_CLKID_MST_C_LRCLK]         = &mst_c_lrclk.hw,
1145                 [AUD_CLKID_MST_D_LRCLK]         = &mst_d_lrclk.hw,
1146                 [AUD_CLKID_MST_E_LRCLK]         = &mst_e_lrclk.hw,
1147                 [AUD_CLKID_MST_F_LRCLK]         = &mst_f_lrclk.hw,
1148                 [AUD_CLKID_TDMIN_A_SCLK_SEL]    = &tdmin_a_sclk_sel.hw,
1149                 [AUD_CLKID_TDMIN_B_SCLK_SEL]    = &tdmin_b_sclk_sel.hw,
1150                 [AUD_CLKID_TDMIN_C_SCLK_SEL]    = &tdmin_c_sclk_sel.hw,
1151                 [AUD_CLKID_TDMIN_LB_SCLK_SEL]   = &tdmin_lb_sclk_sel.hw,
1152                 [AUD_CLKID_TDMOUT_A_SCLK_SEL]   = &tdmout_a_sclk_sel.hw,
1153                 [AUD_CLKID_TDMOUT_B_SCLK_SEL]   = &tdmout_b_sclk_sel.hw,
1154                 [AUD_CLKID_TDMOUT_C_SCLK_SEL]   = &tdmout_c_sclk_sel.hw,
1155                 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
1156                 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
1157                 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
1158                 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1159                 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1160                 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1161                 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1162                 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1163                 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1164                 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1165                 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1166                 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1167                 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1168                 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1169                 [AUD_CLKID_TDMIN_A_SCLK]        = &tdmin_a_sclk.hw,
1170                 [AUD_CLKID_TDMIN_B_SCLK]        = &tdmin_b_sclk.hw,
1171                 [AUD_CLKID_TDMIN_C_SCLK]        = &tdmin_c_sclk.hw,
1172                 [AUD_CLKID_TDMIN_LB_SCLK]       = &tdmin_lb_sclk.hw,
1173                 [AUD_CLKID_TDMOUT_A_SCLK]       = &tdmout_a_sclk.hw,
1174                 [AUD_CLKID_TDMOUT_B_SCLK]       = &tdmout_b_sclk.hw,
1175                 [AUD_CLKID_TDMOUT_C_SCLK]       = &tdmout_c_sclk.hw,
1176                 [AUD_CLKID_TDMIN_A_LRCLK]       = &tdmin_a_lrclk.hw,
1177                 [AUD_CLKID_TDMIN_B_LRCLK]       = &tdmin_b_lrclk.hw,
1178                 [AUD_CLKID_TDMIN_C_LRCLK]       = &tdmin_c_lrclk.hw,
1179                 [AUD_CLKID_TDMIN_LB_LRCLK]      = &tdmin_lb_lrclk.hw,
1180                 [AUD_CLKID_TDMOUT_A_LRCLK]      = &tdmout_a_lrclk.hw,
1181                 [AUD_CLKID_TDMOUT_B_LRCLK]      = &tdmout_b_lrclk.hw,
1182                 [AUD_CLKID_TDMOUT_C_LRCLK]      = &tdmout_c_lrclk.hw,
1183                 [AUD_CLKID_TDM_MCLK_PAD0]       = &sm1_tdm_mclk_pad_0.hw,
1184                 [AUD_CLKID_TDM_MCLK_PAD1]       = &sm1_tdm_mclk_pad_1.hw,
1185                 [AUD_CLKID_TDM_LRCLK_PAD0]      = &sm1_tdm_lrclk_pad_0.hw,
1186                 [AUD_CLKID_TDM_LRCLK_PAD1]      = &sm1_tdm_lrclk_pad_1.hw,
1187                 [AUD_CLKID_TDM_LRCLK_PAD2]      = &sm1_tdm_lrclk_pad_2.hw,
1188                 [AUD_CLKID_TDM_SCLK_PAD0]       = &sm1_tdm_sclk_pad_0.hw,
1189                 [AUD_CLKID_TDM_SCLK_PAD1]       = &sm1_tdm_sclk_pad_1.hw,
1190                 [AUD_CLKID_TDM_SCLK_PAD2]       = &sm1_tdm_sclk_pad_2.hw,
1191                 [AUD_CLKID_TOP]                 = &sm1_aud_top.hw,
1192                 [AUD_CLKID_TORAM]               = &toram.hw,
1193                 [AUD_CLKID_EQDRC]               = &eqdrc.hw,
1194                 [AUD_CLKID_RESAMPLE_B]          = &resample_b.hw,
1195                 [AUD_CLKID_TOVAD]               = &tovad.hw,
1196                 [AUD_CLKID_LOCKER]              = &locker.hw,
1197                 [AUD_CLKID_SPDIFIN_LB]          = &spdifin_lb.hw,
1198                 [AUD_CLKID_FRDDR_D]             = &frddr_d.hw,
1199                 [AUD_CLKID_TODDR_D]             = &toddr_d.hw,
1200                 [AUD_CLKID_LOOPBACK_B]          = &loopback_b.hw,
1201                 [AUD_CLKID_CLK81_EN]            = &sm1_clk81_en.hw,
1202                 [AUD_CLKID_SYSCLK_A_DIV]        = &sm1_sysclk_a_div.hw,
1203                 [AUD_CLKID_SYSCLK_A_EN]         = &sm1_sysclk_a_en.hw,
1204                 [AUD_CLKID_SYSCLK_B_DIV]        = &sm1_sysclk_b_div.hw,
1205                 [AUD_CLKID_SYSCLK_B_EN]         = &sm1_sysclk_b_en.hw,
1206                 [NR_CLKS] = NULL,
1207         },
1208         .num = NR_CLKS,
1209 };
1210
1211
1212 /* Convenience table to populate regmap in .probe()
1213  * Note that this table is shared between both AXG and G12A,
1214  * with spdifout_b clocks being exclusive to G12A. Since those
1215  * clocks are not declared within the AXG onecell table, we do not
1216  * feel the need to have separate AXG/G12A regmap tables.
1217  */
1218 static struct clk_regmap *const axg_clk_regmaps[] = {
1219         &ddr_arb,
1220         &pdm,
1221         &tdmin_a,
1222         &tdmin_b,
1223         &tdmin_c,
1224         &tdmin_lb,
1225         &tdmout_a,
1226         &tdmout_b,
1227         &tdmout_c,
1228         &frddr_a,
1229         &frddr_b,
1230         &frddr_c,
1231         &toddr_a,
1232         &toddr_b,
1233         &toddr_c,
1234         &loopback,
1235         &spdifin,
1236         &spdifout,
1237         &resample,
1238         &power_detect,
1239         &spdifout_b,
1240         &mst_a_mclk_sel,
1241         &mst_b_mclk_sel,
1242         &mst_c_mclk_sel,
1243         &mst_d_mclk_sel,
1244         &mst_e_mclk_sel,
1245         &mst_f_mclk_sel,
1246         &mst_a_mclk_div,
1247         &mst_b_mclk_div,
1248         &mst_c_mclk_div,
1249         &mst_d_mclk_div,
1250         &mst_e_mclk_div,
1251         &mst_f_mclk_div,
1252         &mst_a_mclk,
1253         &mst_b_mclk,
1254         &mst_c_mclk,
1255         &mst_d_mclk,
1256         &mst_e_mclk,
1257         &mst_f_mclk,
1258         &spdifout_clk_sel,
1259         &spdifout_clk_div,
1260         &spdifout_clk,
1261         &spdifin_clk_sel,
1262         &spdifin_clk_div,
1263         &spdifin_clk,
1264         &pdm_dclk_sel,
1265         &pdm_dclk_div,
1266         &pdm_dclk,
1267         &pdm_sysclk_sel,
1268         &pdm_sysclk_div,
1269         &pdm_sysclk,
1270         &mst_a_sclk_pre_en,
1271         &mst_b_sclk_pre_en,
1272         &mst_c_sclk_pre_en,
1273         &mst_d_sclk_pre_en,
1274         &mst_e_sclk_pre_en,
1275         &mst_f_sclk_pre_en,
1276         &mst_a_sclk_div,
1277         &mst_b_sclk_div,
1278         &mst_c_sclk_div,
1279         &mst_d_sclk_div,
1280         &mst_e_sclk_div,
1281         &mst_f_sclk_div,
1282         &mst_a_sclk_post_en,
1283         &mst_b_sclk_post_en,
1284         &mst_c_sclk_post_en,
1285         &mst_d_sclk_post_en,
1286         &mst_e_sclk_post_en,
1287         &mst_f_sclk_post_en,
1288         &mst_a_sclk,
1289         &mst_b_sclk,
1290         &mst_c_sclk,
1291         &mst_d_sclk,
1292         &mst_e_sclk,
1293         &mst_f_sclk,
1294         &mst_a_lrclk_div,
1295         &mst_b_lrclk_div,
1296         &mst_c_lrclk_div,
1297         &mst_d_lrclk_div,
1298         &mst_e_lrclk_div,
1299         &mst_f_lrclk_div,
1300         &mst_a_lrclk,
1301         &mst_b_lrclk,
1302         &mst_c_lrclk,
1303         &mst_d_lrclk,
1304         &mst_e_lrclk,
1305         &mst_f_lrclk,
1306         &tdmin_a_sclk_sel,
1307         &tdmin_b_sclk_sel,
1308         &tdmin_c_sclk_sel,
1309         &tdmin_lb_sclk_sel,
1310         &tdmout_a_sclk_sel,
1311         &tdmout_b_sclk_sel,
1312         &tdmout_c_sclk_sel,
1313         &tdmin_a_sclk_pre_en,
1314         &tdmin_b_sclk_pre_en,
1315         &tdmin_c_sclk_pre_en,
1316         &tdmin_lb_sclk_pre_en,
1317         &tdmout_a_sclk_pre_en,
1318         &tdmout_b_sclk_pre_en,
1319         &tdmout_c_sclk_pre_en,
1320         &tdmin_a_sclk_post_en,
1321         &tdmin_b_sclk_post_en,
1322         &tdmin_c_sclk_post_en,
1323         &tdmin_lb_sclk_post_en,
1324         &tdmout_a_sclk_post_en,
1325         &tdmout_b_sclk_post_en,
1326         &tdmout_c_sclk_post_en,
1327         &tdmin_a_sclk,
1328         &tdmin_b_sclk,
1329         &tdmin_c_sclk,
1330         &tdmin_lb_sclk,
1331         &tdmout_a_sclk,
1332         &tdmout_b_sclk,
1333         &tdmout_c_sclk,
1334         &tdmin_a_lrclk,
1335         &tdmin_b_lrclk,
1336         &tdmin_c_lrclk,
1337         &tdmin_lb_lrclk,
1338         &tdmout_a_lrclk,
1339         &tdmout_b_lrclk,
1340         &tdmout_c_lrclk,
1341         &spdifout_b_clk_sel,
1342         &spdifout_b_clk_div,
1343         &spdifout_b_clk,
1344         &g12a_tdm_mclk_pad_0,
1345         &g12a_tdm_mclk_pad_1,
1346         &g12a_tdm_lrclk_pad_0,
1347         &g12a_tdm_lrclk_pad_1,
1348         &g12a_tdm_lrclk_pad_2,
1349         &g12a_tdm_sclk_pad_0,
1350         &g12a_tdm_sclk_pad_1,
1351         &g12a_tdm_sclk_pad_2,
1352         &toram,
1353         &eqdrc,
1354 };
1355
1356 static struct clk_regmap *const sm1_clk_regmaps[] = {
1357         &ddr_arb,
1358         &pdm,
1359         &tdmin_a,
1360         &tdmin_b,
1361         &tdmin_c,
1362         &tdmin_lb,
1363         &tdmout_a,
1364         &tdmout_b,
1365         &tdmout_c,
1366         &frddr_a,
1367         &frddr_b,
1368         &frddr_c,
1369         &toddr_a,
1370         &toddr_b,
1371         &toddr_c,
1372         &loopback,
1373         &spdifin,
1374         &spdifout,
1375         &resample,
1376         &spdifout_b,
1377         &sm1_mst_a_mclk_sel,
1378         &sm1_mst_b_mclk_sel,
1379         &sm1_mst_c_mclk_sel,
1380         &sm1_mst_d_mclk_sel,
1381         &sm1_mst_e_mclk_sel,
1382         &sm1_mst_f_mclk_sel,
1383         &sm1_mst_a_mclk_div,
1384         &sm1_mst_b_mclk_div,
1385         &sm1_mst_c_mclk_div,
1386         &sm1_mst_d_mclk_div,
1387         &sm1_mst_e_mclk_div,
1388         &sm1_mst_f_mclk_div,
1389         &sm1_mst_a_mclk,
1390         &sm1_mst_b_mclk,
1391         &sm1_mst_c_mclk,
1392         &sm1_mst_d_mclk,
1393         &sm1_mst_e_mclk,
1394         &sm1_mst_f_mclk,
1395         &spdifout_clk_sel,
1396         &spdifout_clk_div,
1397         &spdifout_clk,
1398         &spdifin_clk_sel,
1399         &spdifin_clk_div,
1400         &spdifin_clk,
1401         &pdm_dclk_sel,
1402         &pdm_dclk_div,
1403         &pdm_dclk,
1404         &pdm_sysclk_sel,
1405         &pdm_sysclk_div,
1406         &pdm_sysclk,
1407         &mst_a_sclk_pre_en,
1408         &mst_b_sclk_pre_en,
1409         &mst_c_sclk_pre_en,
1410         &mst_d_sclk_pre_en,
1411         &mst_e_sclk_pre_en,
1412         &mst_f_sclk_pre_en,
1413         &mst_a_sclk_div,
1414         &mst_b_sclk_div,
1415         &mst_c_sclk_div,
1416         &mst_d_sclk_div,
1417         &mst_e_sclk_div,
1418         &mst_f_sclk_div,
1419         &mst_a_sclk_post_en,
1420         &mst_b_sclk_post_en,
1421         &mst_c_sclk_post_en,
1422         &mst_d_sclk_post_en,
1423         &mst_e_sclk_post_en,
1424         &mst_f_sclk_post_en,
1425         &mst_a_sclk,
1426         &mst_b_sclk,
1427         &mst_c_sclk,
1428         &mst_d_sclk,
1429         &mst_e_sclk,
1430         &mst_f_sclk,
1431         &mst_a_lrclk_div,
1432         &mst_b_lrclk_div,
1433         &mst_c_lrclk_div,
1434         &mst_d_lrclk_div,
1435         &mst_e_lrclk_div,
1436         &mst_f_lrclk_div,
1437         &mst_a_lrclk,
1438         &mst_b_lrclk,
1439         &mst_c_lrclk,
1440         &mst_d_lrclk,
1441         &mst_e_lrclk,
1442         &mst_f_lrclk,
1443         &tdmin_a_sclk_sel,
1444         &tdmin_b_sclk_sel,
1445         &tdmin_c_sclk_sel,
1446         &tdmin_lb_sclk_sel,
1447         &tdmout_a_sclk_sel,
1448         &tdmout_b_sclk_sel,
1449         &tdmout_c_sclk_sel,
1450         &tdmin_a_sclk_pre_en,
1451         &tdmin_b_sclk_pre_en,
1452         &tdmin_c_sclk_pre_en,
1453         &tdmin_lb_sclk_pre_en,
1454         &tdmout_a_sclk_pre_en,
1455         &tdmout_b_sclk_pre_en,
1456         &tdmout_c_sclk_pre_en,
1457         &tdmin_a_sclk_post_en,
1458         &tdmin_b_sclk_post_en,
1459         &tdmin_c_sclk_post_en,
1460         &tdmin_lb_sclk_post_en,
1461         &tdmout_a_sclk_post_en,
1462         &tdmout_b_sclk_post_en,
1463         &tdmout_c_sclk_post_en,
1464         &tdmin_a_sclk,
1465         &tdmin_b_sclk,
1466         &tdmin_c_sclk,
1467         &tdmin_lb_sclk,
1468         &tdmout_a_sclk,
1469         &tdmout_b_sclk,
1470         &tdmout_c_sclk,
1471         &tdmin_a_lrclk,
1472         &tdmin_b_lrclk,
1473         &tdmin_c_lrclk,
1474         &tdmin_lb_lrclk,
1475         &tdmout_a_lrclk,
1476         &tdmout_b_lrclk,
1477         &tdmout_c_lrclk,
1478         &spdifout_b_clk_sel,
1479         &spdifout_b_clk_div,
1480         &spdifout_b_clk,
1481         &sm1_tdm_mclk_pad_0,
1482         &sm1_tdm_mclk_pad_1,
1483         &sm1_tdm_lrclk_pad_0,
1484         &sm1_tdm_lrclk_pad_1,
1485         &sm1_tdm_lrclk_pad_2,
1486         &sm1_tdm_sclk_pad_0,
1487         &sm1_tdm_sclk_pad_1,
1488         &sm1_tdm_sclk_pad_2,
1489         &sm1_aud_top,
1490         &toram,
1491         &eqdrc,
1492         &resample_b,
1493         &tovad,
1494         &locker,
1495         &spdifin_lb,
1496         &frddr_d,
1497         &toddr_d,
1498         &loopback_b,
1499         &sm1_clk81_en,
1500         &sm1_sysclk_a_div,
1501         &sm1_sysclk_a_en,
1502         &sm1_sysclk_b_div,
1503         &sm1_sysclk_b_en,
1504 };
1505
1506 static int devm_clk_get_enable(struct device *dev, char *id)
1507 {
1508         struct clk *clk;
1509         int ret;
1510
1511         clk = devm_clk_get(dev, id);
1512         if (IS_ERR(clk)) {
1513                 ret = PTR_ERR(clk);
1514                 if (ret != -EPROBE_DEFER)
1515                         dev_err(dev, "failed to get %s", id);
1516                 return ret;
1517         }
1518
1519         ret = clk_prepare_enable(clk);
1520         if (ret) {
1521                 dev_err(dev, "failed to enable %s", id);
1522                 return ret;
1523         }
1524
1525         ret = devm_add_action_or_reset(dev,
1526                                        (void(*)(void *))clk_disable_unprepare,
1527                                        clk);
1528         if (ret) {
1529                 dev_err(dev, "failed to add reset action on %s", id);
1530                 return ret;
1531         }
1532
1533         return 0;
1534 }
1535
1536 struct axg_audio_reset_data {
1537         struct reset_controller_dev rstc;
1538         struct regmap *map;
1539         unsigned int offset;
1540 };
1541
1542 static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
1543                                         unsigned long id,
1544                                         unsigned int *reg,
1545                                         unsigned int *bit)
1546 {
1547         unsigned int stride = regmap_get_reg_stride(rst->map);
1548
1549         *reg = (id / (stride * BITS_PER_BYTE)) * stride;
1550         *reg += rst->offset;
1551         *bit = id % (stride * BITS_PER_BYTE);
1552 }
1553
1554 static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
1555                                 unsigned long id, bool assert)
1556 {
1557         struct axg_audio_reset_data *rst =
1558                 container_of(rcdev, struct axg_audio_reset_data, rstc);
1559         unsigned int offset, bit;
1560
1561         axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
1562
1563         regmap_update_bits(rst->map, offset, BIT(bit),
1564                         assert ? BIT(bit) : 0);
1565
1566         return 0;
1567 }
1568
1569 static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
1570                                 unsigned long id)
1571 {
1572         struct axg_audio_reset_data *rst =
1573                 container_of(rcdev, struct axg_audio_reset_data, rstc);
1574         unsigned int val, offset, bit;
1575
1576         axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
1577
1578         regmap_read(rst->map, offset, &val);
1579
1580         return !!(val & BIT(bit));
1581 }
1582
1583 static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
1584                                 unsigned long id)
1585 {
1586         return axg_audio_reset_update(rcdev, id, true);
1587 }
1588
1589 static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
1590                                 unsigned long id)
1591 {
1592         return axg_audio_reset_update(rcdev, id, false);
1593 }
1594
1595 static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
1596                                 unsigned long id)
1597 {
1598         int ret;
1599
1600         ret = axg_audio_reset_assert(rcdev, id);
1601         if (ret)
1602                 return ret;
1603
1604         return axg_audio_reset_deassert(rcdev, id);
1605 }
1606
1607 static const struct reset_control_ops axg_audio_rstc_ops = {
1608         .assert = axg_audio_reset_assert,
1609         .deassert = axg_audio_reset_deassert,
1610         .reset = axg_audio_reset_toggle,
1611         .status = axg_audio_reset_status,
1612 };
1613
1614 static const struct regmap_config axg_audio_regmap_cfg = {
1615         .reg_bits       = 32,
1616         .val_bits       = 32,
1617         .reg_stride     = 4,
1618         .max_register   = AUDIO_CLK_SPDIFOUT_B_CTRL,
1619 };
1620
1621 struct audioclk_data {
1622         struct clk_regmap *const *regmap_clks;
1623         unsigned int regmap_clk_num;
1624         struct clk_hw_onecell_data *hw_onecell_data;
1625         unsigned int reset_offset;
1626         unsigned int reset_num;
1627 };
1628
1629 static int axg_audio_clkc_probe(struct platform_device *pdev)
1630 {
1631         struct device *dev = &pdev->dev;
1632         const struct audioclk_data *data;
1633         struct axg_audio_reset_data *rst;
1634         struct regmap *map;
1635         void __iomem *regs;
1636         struct clk_hw *hw;
1637         int ret, i;
1638
1639         data = of_device_get_match_data(dev);
1640         if (!data)
1641                 return -EINVAL;
1642
1643         regs = devm_platform_ioremap_resource(pdev, 0);
1644         if (IS_ERR(regs))
1645                 return PTR_ERR(regs);
1646
1647         map = devm_regmap_init_mmio(dev, regs, &axg_audio_regmap_cfg);
1648         if (IS_ERR(map)) {
1649                 dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(map));
1650                 return PTR_ERR(map);
1651         }
1652
1653         /* Get the mandatory peripheral clock */
1654         ret = devm_clk_get_enable(dev, "pclk");
1655         if (ret)
1656                 return ret;
1657
1658         ret = device_reset(dev);
1659         if (ret) {
1660                 dev_err(dev, "failed to reset device\n");
1661                 return ret;
1662         }
1663
1664         /* Populate regmap for the regmap backed clocks */
1665         for (i = 0; i < data->regmap_clk_num; i++)
1666                 data->regmap_clks[i]->map = map;
1667
1668         /* Take care to skip the registered input clocks */
1669         for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
1670                 const char *name;
1671
1672                 hw = data->hw_onecell_data->hws[i];
1673                 /* array might be sparse */
1674                 if (!hw)
1675                         continue;
1676
1677                 name = hw->init->name;
1678
1679                 ret = devm_clk_hw_register(dev, hw);
1680                 if (ret) {
1681                         dev_err(dev, "failed to register clock %s\n", name);
1682                         return ret;
1683                 }
1684         }
1685
1686         ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1687                                         data->hw_onecell_data);
1688         if (ret)
1689                 return ret;
1690
1691         /* Stop here if there is no reset */
1692         if (!data->reset_num)
1693                 return 0;
1694
1695         rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
1696         if (!rst)
1697                 return -ENOMEM;
1698
1699         rst->map = map;
1700         rst->offset = data->reset_offset;
1701         rst->rstc.nr_resets = data->reset_num;
1702         rst->rstc.ops = &axg_audio_rstc_ops;
1703         rst->rstc.of_node = dev->of_node;
1704         rst->rstc.owner = THIS_MODULE;
1705
1706         return devm_reset_controller_register(dev, &rst->rstc);
1707 }
1708
1709 static const struct audioclk_data axg_audioclk_data = {
1710         .regmap_clks = axg_clk_regmaps,
1711         .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
1712         .hw_onecell_data = &axg_audio_hw_onecell_data,
1713 };
1714
1715 static const struct audioclk_data g12a_audioclk_data = {
1716         .regmap_clks = axg_clk_regmaps,
1717         .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
1718         .hw_onecell_data = &g12a_audio_hw_onecell_data,
1719         .reset_offset = AUDIO_SW_RESET,
1720         .reset_num = 26,
1721 };
1722
1723 static const struct audioclk_data sm1_audioclk_data = {
1724         .regmap_clks = sm1_clk_regmaps,
1725         .regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
1726         .hw_onecell_data = &sm1_audio_hw_onecell_data,
1727         .reset_offset = AUDIO_SM1_SW_RESET0,
1728         .reset_num = 39,
1729 };
1730
1731 static const struct of_device_id clkc_match_table[] = {
1732         {
1733                 .compatible = "amlogic,axg-audio-clkc",
1734                 .data = &axg_audioclk_data
1735         }, {
1736                 .compatible = "amlogic,g12a-audio-clkc",
1737                 .data = &g12a_audioclk_data
1738         }, {
1739                 .compatible = "amlogic,sm1-audio-clkc",
1740                 .data = &sm1_audioclk_data
1741         }, {}
1742 };
1743 MODULE_DEVICE_TABLE(of, clkc_match_table);
1744
1745 static struct platform_driver axg_audio_driver = {
1746         .probe          = axg_audio_clkc_probe,
1747         .driver         = {
1748                 .name   = "axg-audio-clkc",
1749                 .of_match_table = clkc_match_table,
1750         },
1751 };
1752 module_platform_driver(axg_audio_driver);
1753
1754 MODULE_DESCRIPTION("Amlogic AXG/G12A/SM1 Audio Clock driver");
1755 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
1756 MODULE_LICENSE("GPL v2");