1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright (c) 2022 MediaTek Inc.
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
6 #include <linux/clk-provider.h>
7 #include <linux/platform_device.h>
8 #include <dt-bindings/clock/mt8186-clk.h>
13 static const struct mtk_gate_regs img_cg_regs = {
19 #define GATE_IMG(_id, _name, _parent, _shift) \
20 GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
22 static const struct mtk_gate img1_clks[] = {
23 GATE_IMG(CLK_IMG1_LARB9_IMG1, "img1_larb9_img1", "top_img1", 0),
24 GATE_IMG(CLK_IMG1_LARB10_IMG1, "img1_larb10_img1", "top_img1", 1),
25 GATE_IMG(CLK_IMG1_DIP, "img1_dip", "top_img1", 2),
26 GATE_IMG(CLK_IMG1_GALS_IMG1, "img1_gals_img1", "top_img1", 12),
29 static const struct mtk_gate img2_clks[] = {
30 GATE_IMG(CLK_IMG2_LARB9_IMG2, "img2_larb9_img2", "top_img1", 0),
31 GATE_IMG(CLK_IMG2_LARB10_IMG2, "img2_larb10_img2", "top_img1", 1),
32 GATE_IMG(CLK_IMG2_MFB, "img2_mfb", "top_img1", 6),
33 GATE_IMG(CLK_IMG2_WPE, "img2_wpe", "top_img1", 7),
34 GATE_IMG(CLK_IMG2_MSS, "img2_mss", "top_img1", 8),
35 GATE_IMG(CLK_IMG2_GALS_IMG2, "img2_gals_img2", "top_img1", 12),
38 static const struct mtk_clk_desc img1_desc = {
40 .num_clks = ARRAY_SIZE(img1_clks),
43 static const struct mtk_clk_desc img2_desc = {
45 .num_clks = ARRAY_SIZE(img2_clks),
48 static const struct of_device_id of_match_clk_mt8186_img[] = {
50 .compatible = "mediatek,mt8186-imgsys1",
53 .compatible = "mediatek,mt8186-imgsys2",
60 static struct platform_driver clk_mt8186_img_drv = {
61 .probe = mtk_clk_simple_probe,
62 .remove = mtk_clk_simple_remove,
64 .name = "clk-mt8186-img",
65 .of_match_table = of_match_clk_mt8186_img,
68 builtin_platform_driver(clk_mt8186_img_drv);