drivers/clk/mediatek/clk-mt7622.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017 MediaTek Inc.
   4  * Author: Chen Zhong <chen.zhong@mediatek.com>
   5  *         Sean Wang <sean.wang@mediatek.com>
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13
  14 #include "clk-cpumux.h"
  15 #include "clk-gate.h"
  16 #include "clk-mtk.h"
  17 #include "clk-pll.h"
  18
  19 #include <dt-bindings/clock/mt7622-clk.h>
  20 #include <linux/clk.h> /* for consumer */
  21
  22 #define MT7622_PLL_FMAX         (2500UL * MHZ)
  23 #define CON0_MT7622_RST_BAR     BIT(27)
  24
  25 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
  26                         _pd_reg, _pd_shift, _tuner_reg, _pcw_reg,       \
  27                         _pcw_shift, _div_table, _parent_name) {         \
  28                 .id = _id,                                              \
  29                 .name = _name,                                          \
  30                 .reg = _reg,                                            \
  31                 .pwr_reg = _pwr_reg,                                    \
  32                 .en_mask = _en_mask,                                    \
  33                 .flags = _flags,                                        \
  34                 .rst_bar_mask = CON0_MT7622_RST_BAR,                    \
  35                 .fmax = MT7622_PLL_FMAX,                                \
  36                 .pcwbits = _pcwbits,                                    \
  37                 .pd_reg = _pd_reg,                                      \
  38                 .pd_shift = _pd_shift,                                  \
  39                 .tuner_reg = _tuner_reg,                                \
  40                 .pcw_reg = _pcw_reg,                                    \
  41                 .pcw_shift = _pcw_shift,                                \
  42                 .div_table = _div_table,                                \
  43                 .parent_name = _parent_name,                            \
  44         }
  45
  46 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,     \
  47                         _pd_reg, _pd_shift, _tuner_reg, _pcw_reg,       \
  48                         _pcw_shift)                                     \
  49         PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
  50                  _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,  \
  51                  NULL, "clkxtal")
  52
  53 #define GATE_APMIXED(_id, _name, _parent, _shift)                       \
  54         GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift,         \
  55                  &mtk_clk_gate_ops_no_setclr_inv)
  56
  57 #define GATE_INFRA(_id, _name, _parent, _shift)                         \
  58         GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  59
  60 #define GATE_TOP0(_id, _name, _parent, _shift)                          \
  61         GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
  62
  63 #define GATE_TOP1(_id, _name, _parent, _shift)                          \
  64         GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
  65
  66 #define GATE_PERI0(_id, _name, _parent, _shift)                         \
  67         GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  68
  69 #define GATE_PERI1(_id, _name, _parent, _shift)                         \
  70         GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  71
  72 static DEFINE_SPINLOCK(mt7622_clk_lock);
  73
  74 static const char * const infra_mux1_parents[] = {
  75         "clkxtal",
  76         "armpll",
  77         "main_core_en",
  78         "armpll"
  79 };
  80
  81 static const char * const axi_parents[] = {
  82         "clkxtal",
  83         "syspll1_d2",
  84         "syspll_d5",
  85         "syspll1_d4",
  86         "univpll_d5",
  87         "univpll2_d2",
  88         "univpll_d7"
  89 };
  90
  91 static const char * const mem_parents[] = {
  92         "clkxtal",
  93         "dmpll_ck"
  94 };
  95
  96 static const char * const ddrphycfg_parents[] = {
  97         "clkxtal",
  98         "syspll1_d8"
  99 };
 100
 101 static const char * const eth_parents[] = {
 102         "clkxtal",
 103         "syspll1_d2",
 104         "univpll1_d2",
 105         "syspll1_d4",
 106         "univpll_d5",
 107         "clk_null",
 108         "univpll_d7"
 109 };
 110
 111 static const char * const pwm_parents[] = {
 112         "clkxtal",
 113         "univpll2_d4"
 114 };
 115
 116 static const char * const f10m_ref_parents[] = {
 117         "clkxtal",
 118         "syspll4_d16"
 119 };
 120
 121 static const char * const nfi_infra_parents[] = {
 122         "clkxtal",
 123         "clkxtal",
 124         "clkxtal",
 125         "clkxtal",
 126         "clkxtal",
 127         "clkxtal",
 128         "clkxtal",
 129         "clkxtal",
 130         "univpll2_d8",
 131         "syspll1_d8",
 132         "univpll1_d8",
 133         "syspll4_d2",
 134         "univpll2_d4",
 135         "univpll3_d2",
 136         "syspll1_d4"
 137 };
 138
 139 static const char * const flash_parents[] = {
 140         "clkxtal",
 141         "univpll_d80_d4",
 142         "syspll2_d8",
 143         "syspll3_d4",
 144         "univpll3_d4",
 145         "univpll1_d8",
 146         "syspll2_d4",
 147         "univpll2_d4"
 148 };
 149
 150 static const char * const uart_parents[] = {
 151         "clkxtal",
 152         "univpll2_d8"
 153 };
 154
 155 static const char * const spi0_parents[] = {
 156         "clkxtal",
 157         "syspll3_d2",
 158         "clkxtal",
 159         "syspll2_d4",
 160         "syspll4_d2",
 161         "univpll2_d4",
 162         "univpll1_d8",
 163         "clkxtal"
 164 };
 165
 166 static const char * const spi1_parents[] = {
 167         "clkxtal",
 168         "syspll3_d2",
 169         "clkxtal",
 170         "syspll4_d4",
 171         "syspll4_d2",
 172         "univpll2_d4",
 173         "univpll1_d8",
 174         "clkxtal"
 175 };
 176
 177 static const char * const msdc30_0_parents[] = {
 178         "clkxtal",
 179         "univpll2_d16",
 180         "univ48m"
 181 };
 182
 183 static const char * const a1sys_hp_parents[] = {
 184         "clkxtal",
 185         "aud1pll_ck",
 186         "aud2pll_ck",
 187         "clkxtal"
 188 };
 189
 190 static const char * const intdir_parents[] = {
 191         "clkxtal",
 192         "syspll_d2",
 193         "univpll_d2",
 194         "sgmiipll_ck"
 195 };
 196
 197 static const char * const aud_intbus_parents[] = {
 198         "clkxtal",
 199         "syspll1_d4",
 200         "syspll4_d2",
 201         "syspll3_d2"
 202 };
 203
 204 static const char * const pmicspi_parents[] = {
 205         "clkxtal",
 206         "clk_null",
 207         "clk_null",
 208         "clk_null",
 209         "clk_null",
 210         "univpll2_d16"
 211 };
 212
 213 static const char * const atb_parents[] = {
 214         "clkxtal",
 215         "syspll1_d2",
 216         "syspll_d5"
 217 };
 218
 219 static const char * const audio_parents[] = {
 220         "clkxtal",
 221         "syspll3_d4",
 222         "syspll4_d4",
 223         "univpll1_d16"
 224 };
 225
 226 static const char * const usb20_parents[] = {
 227         "clkxtal",
 228         "univpll3_d4",
 229         "syspll1_d8",
 230         "clkxtal"
 231 };
 232
 233 static const char * const aud1_parents[] = {
 234         "clkxtal",
 235         "aud1pll_ck"
 236 };
 237
 238 static const char * const aud2_parents[] = {
 239         "clkxtal",
 240         "aud2pll_ck"
 241 };
 242
 243 static const char * const asm_l_parents[] = {
 244         "clkxtal",
 245         "syspll_d5",
 246         "univpll2_d2",
 247         "univpll2_d4"
 248 };
 249
 250 static const char * const apll1_ck_parents[] = {
 251         "aud1_sel",
 252         "aud2_sel"
 253 };
 254
 255 static const char * const peribus_ck_parents[] = {
 256         "syspll1_d8",
 257         "syspll1_d4"
 258 };
 259
 260 static const struct mtk_gate_regs apmixed_cg_regs = {
 261         .set_ofs = 0x8,
 262         .clr_ofs = 0x8,
 263         .sta_ofs = 0x8,
 264 };
 265
 266 static const struct mtk_gate_regs infra_cg_regs = {
 267         .set_ofs = 0x40,
 268         .clr_ofs = 0x44,
 269         .sta_ofs = 0x48,
 270 };
 271
 272 static const struct mtk_gate_regs top0_cg_regs = {
 273         .set_ofs = 0x120,
 274         .clr_ofs = 0x120,
 275         .sta_ofs = 0x120,
 276 };
 277
 278 static const struct mtk_gate_regs top1_cg_regs = {
 279         .set_ofs = 0x128,
 280         .clr_ofs = 0x128,
 281         .sta_ofs = 0x128,
 282 };
 283
 284 static const struct mtk_gate_regs peri0_cg_regs = {
 285         .set_ofs = 0x8,
 286         .clr_ofs = 0x10,
 287         .sta_ofs = 0x18,
 288 };
 289
 290 static const struct mtk_gate_regs peri1_cg_regs = {
 291         .set_ofs = 0xC,
 292         .clr_ofs = 0x14,
 293         .sta_ofs = 0x1C,
 294 };
 295
 296 static const struct mtk_pll_data plls[] = {
 297         PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
 298             PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
 299         PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
 300             HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
 301         PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
 302             HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
 303         PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
 304             0, 21, 0x0300, 1, 0, 0x0304, 0),
 305         PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
 306             0, 21, 0x0314, 1, 0, 0x0318, 0),
 307         PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0,
 308             0, 31, 0x0324, 1, 0, 0x0328, 0),
 309         PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0,
 310             0, 31, 0x0334, 1, 0, 0x0338, 0),
 311         PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0,
 312             0, 21, 0x0344, 1, 0, 0x0348, 0),
 313         PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
 314             0, 21, 0x0358, 1, 0, 0x035C, 0),
 315 };
 316
 317 static const struct mtk_gate apmixed_clks[] = {
 318         GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
 319 };
 320
 321 static const struct mtk_gate infra_clks[] = {
 322         GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
 323         GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
 324         GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
 325         GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
 326         GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
 327         GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
 328 };
 329
 330 static const struct mtk_fixed_clk top_fixed_clks[] = {
 331         FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
 332                   31250000),
 333         FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
 334                   31250000),
 335         FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
 336                   125000000),
 337         FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
 338                   125000000),
 339         FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
 340                   250000000),
 341         FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
 342                   250000000),
 343         FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
 344                   33333333),
 345         FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
 346                   50000000),
 347         FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
 348                   50000000),
 349         FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
 350                   50000000),
 351 };
 352
 353 static const struct mtk_fixed_factor top_divs[] = {
 354         FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
 355         FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
 356         FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
 357         FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
 358         FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
 359         FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
 360         FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
 361         FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
 362         FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
 363         FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
 364         FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
 365         FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
 366         FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
 367         FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
 368         FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
 369         FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
 370         FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
 371         FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
 372         FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
 373         FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
 374         FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
 375         FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
 376         FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
 377         FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
 378         FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
 379         FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32),
 380         FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
 381         FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
 382         FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
 383         FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
 384         FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
 385         FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
 386         FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
 387         FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
 388         FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
 389         FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
 390         FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
 391         FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1),
 392         FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
 393         FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1),
 394         FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1),
 395         FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2),
 396         FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4),
 397         FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
 398         FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
 399         FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
 400 };
 401
 402 static const struct mtk_gate top_clks[] = {
 403         /* TOP0 */
 404         GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
 405         GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
 406         GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
 407                   2),
 408         GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
 409                   3),
 410         GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
 411                   4),
 412         GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
 413                   5),
 414
 415         /* TOP1 */
 416         GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
 417         GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
 418 };
 419
 420 static const struct mtk_clk_divider top_adj_divs[] = {
 421         DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel",
 422                 0x120, 24, 3),
 423         DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel",
 424                 0x120, 28, 3),
 425         DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel",
 426                 0x124, 0, 7),
 427         DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel",
 428                 0x124, 8, 7),
 429         DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck",
 430                 0x124, 16, 7),
 431         DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel",
 432                 0x124, 24, 7),
 433         DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel",
 434                 0x128, 8, 7),
 435         DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel",
 436                 0x128, 24, 7),
 437 };
 438
 439 static const struct mtk_gate peri_clks[] = {
 440         /* PERI0 */
 441         GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
 442         GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
 443         GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
 444         GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
 445         GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
 446         GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
 447         GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
 448         GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
 449         GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
 450         GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
 451         GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
 452         GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
 453         GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
 454         GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
 455         GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
 456         GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
 457         GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
 458         GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
 459         GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
 460         GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
 461         GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
 462         GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
 463         GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
 464         GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
 465         GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
 466         GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
 467         GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
 468
 469         /* PERI1 */
 470         GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
 471         GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
 472 };
 473
 474 static struct mtk_composite infra_muxes[] = {
 475         MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,
 476             0x000, 2, 2),
 477 };
 478
 479 static struct mtk_composite top_muxes[] = {
 480         /* CLK_CFG_0 */
 481         MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
 482                  0x040, 0, 3, 7),
 483         MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
 484                  0x040, 8, 1, 15),
 485         MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
 486                  0x040, 16, 1, 23),
 487         MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
 488                  0x040, 24, 3, 31),
 489
 490         /* CLK_CFG_1 */
 491         MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
 492                  0x050, 0, 2, 7),
 493         MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
 494                  0x050, 8, 1, 15),
 495         MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
 496                  0x050, 16, 4, 23),
 497         MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
 498                  0x050, 24, 3, 31),
 499
 500         /* CLK_CFG_2 */
 501         MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
 502                  0x060, 0, 1, 7),
 503         MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
 504                  0x060, 8, 3, 15),
 505         MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
 506                  0x060, 16, 3, 23),
 507         MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
 508                  0x060, 24, 3, 31),
 509
 510         /* CLK_CFG_3 */
 511         MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
 512                  0x070, 0, 3, 7),
 513         MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
 514                  0x070, 8, 3, 15),
 515         MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
 516                  0x070, 16, 2, 23),
 517         MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
 518                  0x070, 24, 2, 31),
 519
 520         /* CLK_CFG_4 */
 521         MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
 522                  0x080, 0, 2, 7),
 523         MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
 524                  0x080, 8, 2, 15),
 525         MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
 526                  0x080, 16, 3, 23),
 527         MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
 528                  0x080, 24, 2, 31),
 529
 530         /* CLK_CFG_5 */
 531         MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
 532                  0x090, 0, 2, 7),
 533         MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
 534                  0x090, 8, 3, 15),
 535         MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
 536                  0x090, 16, 2, 23),
 537         MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
 538                  0x090, 24, 2, 31),
 539
 540         /* CLK_CFG_6 */
 541         MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
 542                  0x0A0, 0, 1, 7),
 543         MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
 544                  0x0A0, 8, 1, 15),
 545         MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
 546                  0x0A0, 16, 1, 23),
 547         MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
 548                  0x0A0, 24, 1, 31),
 549
 550         /* CLK_CFG_7 */
 551         MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
 552                  0x0B0, 0, 2, 7),
 553         MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
 554                  0x0B0, 8, 2, 15),
 555         MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,
 556                  0x0B0, 16, 2, 23),
 557
 558         /* CLK_AUDDIV_0 */
 559         MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents,
 560             0x120, 6, 1),
 561         MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents,
 562             0x120, 7, 1),
 563         MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents,
 564             0x120, 8, 1),
 565         MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents,
 566             0x120, 9, 1),
 567         MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents,
 568             0x120, 10, 1),
 569         MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents,
 570             0x120, 11, 1),
 571 };
 572
 573 static struct mtk_composite peri_muxes[] = {
 574         /* PERI_GLOBALCON_CKSEL */
 575         MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
 576 };
 577
 578 static u16 infrasys_rst_ofs[] = { 0x30, };
 579 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
 580
 581 static const struct mtk_clk_rst_desc clk_rst_desc[] = {
 582         /* infrasys */
 583         {
 584                 .version = MTK_RST_SIMPLE,
 585                 .rst_bank_ofs = infrasys_rst_ofs,
 586                 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
 587         },
 588         /* pericfg */
 589         {
 590                 .version = MTK_RST_SIMPLE,
 591                 .rst_bank_ofs = pericfg_rst_ofs,
 592                 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
 593         },
 594 };
 595
 596 static int mtk_topckgen_init(struct platform_device *pdev)
 597 {
 598         struct clk_hw_onecell_data *clk_data;
 599         void __iomem *base;
 600         struct device_node *node = pdev->dev.of_node;
 601
 602         base = devm_platform_ioremap_resource(pdev, 0);
 603         if (IS_ERR(base))
 604                 return PTR_ERR(base);
 605
 606         clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
 607
 608         mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
 609                                     clk_data);
 610
 611         mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
 612                                  clk_data);
 613
 614         mtk_clk_register_composites(&pdev->dev, top_muxes,
 615                                     ARRAY_SIZE(top_muxes), base,
 616                                     &mt7622_clk_lock, clk_data);
 617
 618         mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
 619                                   base, &mt7622_clk_lock, clk_data);
 620
 621         mtk_clk_register_gates(&pdev->dev, node, top_clks,
 622                                ARRAY_SIZE(top_clks), clk_data);
 623
 624         clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
 625         clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
 626         clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
 627
 628         return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 629 }
 630
 631 static int mtk_infrasys_init(struct platform_device *pdev)
 632 {
 633         struct device_node *node = pdev->dev.of_node;
 634         struct clk_hw_onecell_data *clk_data;
 635         int r;
 636
 637         clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
 638
 639         mtk_clk_register_gates(&pdev->dev, node, infra_clks,
 640                                ARRAY_SIZE(infra_clks), clk_data);
 641
 642         mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
 643                                   ARRAY_SIZE(infra_muxes), clk_data);
 644
 645         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
 646                                    clk_data);
 647         if (r)
 648                 return r;
 649
 650         mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 651
 652         return 0;
 653 }
 654
 655 static int mtk_apmixedsys_init(struct platform_device *pdev)
 656 {
 657         struct clk_hw_onecell_data *clk_data;
 658         struct device_node *node = pdev->dev.of_node;
 659
 660         clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
 661         if (!clk_data)
 662                 return -ENOMEM;
 663
 664         mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
 665                               clk_data);
 666
 667         mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
 668                                ARRAY_SIZE(apmixed_clks), clk_data);
 669
 670         clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
 671         clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk);
 672
 673         return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 674 }
 675
 676 static int mtk_pericfg_init(struct platform_device *pdev)
 677 {
 678         struct clk_hw_onecell_data *clk_data;
 679         void __iomem *base;
 680         int r;
 681         struct device_node *node = pdev->dev.of_node;
 682
 683         base = devm_platform_ioremap_resource(pdev, 0);
 684         if (IS_ERR(base))
 685                 return PTR_ERR(base);
 686
 687         clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
 688
 689         mtk_clk_register_gates(&pdev->dev, node, peri_clks,
 690                                ARRAY_SIZE(peri_clks), clk_data);
 691
 692         mtk_clk_register_composites(&pdev->dev, peri_muxes,
 693                                     ARRAY_SIZE(peri_muxes), base,
 694                                     &mt7622_clk_lock, clk_data);
 695
 696         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 697         if (r)
 698                 return r;
 699
 700         clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
 701
 702         mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 703
 704         return 0;
 705 }
 706
 707 static const struct of_device_id of_match_clk_mt7622[] = {
 708         {
 709                 .compatible = "mediatek,mt7622-apmixedsys",
 710                 .data = mtk_apmixedsys_init,
 711         }, {
 712                 .compatible = "mediatek,mt7622-infracfg",
 713                 .data = mtk_infrasys_init,
 714         }, {
 715                 .compatible = "mediatek,mt7622-topckgen",
 716                 .data = mtk_topckgen_init,
 717         }, {
 718                 .compatible = "mediatek,mt7622-pericfg",
 719                 .data = mtk_pericfg_init,
 720         }, {
 721                 /* sentinel */
 722         }
 723 };
 724
 725 static int clk_mt7622_probe(struct platform_device *pdev)
 726 {
 727         int (*clk_init)(struct platform_device *);
 728         int r;
 729
 730         clk_init = of_device_get_match_data(&pdev->dev);
 731         if (!clk_init)
 732                 return -EINVAL;
 733
 734         r = clk_init(pdev);
 735         if (r)
 736                 dev_err(&pdev->dev,
 737                         "could not register clock provider: %s: %d\n",
 738                         pdev->name, r);
 739
 740         return r;
 741 }
 742
 743 static struct platform_driver clk_mt7622_drv = {
 744         .probe = clk_mt7622_probe,
 745         .driver = {
 746                 .name = "clk-mt7622",
 747                 .of_match_table = of_match_clk_mt7622,
 748         },
 749 };
 750
 751 static int clk_mt7622_init(void)
 752 {
 753         return platform_driver_register(&clk_mt7622_drv);
 754 }
 755
 756 arch_initcall(clk_mt7622_init);