1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017 MediaTek Inc.
4 * Author: Chen Zhong <chen.zhong@mediatek.com>
5 * Sean Wang <sean.wang@mediatek.com>
8 #include <linux/clk-provider.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
17 #include <dt-bindings/clock/mt7622-clk.h>
19 #define GATE_ETH(_id, _name, _parent, _shift) { \
22 .parent_name = _parent, \
23 .regs = ð_cg_regs, \
25 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
28 static const struct mtk_gate_regs eth_cg_regs = {
34 static const struct mtk_gate eth_clks[] = {
35 GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
36 GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
37 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
38 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
39 GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
42 static const struct mtk_gate_regs sgmii_cg_regs = {
48 #define GATE_SGMII(_id, _name, _parent, _shift) { \
51 .parent_name = _parent, \
52 .regs = &sgmii_cg_regs, \
54 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
57 static const struct mtk_gate sgmii_clks[] = {
58 GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
60 GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
61 "ssusb_eq_rx250m", 3),
62 GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
64 GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
68 static int clk_mt7622_ethsys_init(struct platform_device *pdev)
70 struct clk_hw_onecell_data *clk_data;
71 struct device_node *node = pdev->dev.of_node;
74 clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
76 mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
79 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
82 "could not register clock provider: %s: %d\n",
85 mtk_register_reset_controller(node, 1, 0x34);
90 static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
92 struct clk_hw_onecell_data *clk_data;
93 struct device_node *node = pdev->dev.of_node;
96 clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
98 mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
101 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
104 "could not register clock provider: %s: %d\n",
110 static const struct of_device_id of_match_clk_mt7622_eth[] = {
112 .compatible = "mediatek,mt7622-ethsys",
113 .data = clk_mt7622_ethsys_init,
115 .compatible = "mediatek,mt7622-sgmiisys",
116 .data = clk_mt7622_sgmiisys_init,
122 static int clk_mt7622_eth_probe(struct platform_device *pdev)
124 int (*clk_init)(struct platform_device *);
127 clk_init = of_device_get_match_data(&pdev->dev);
134 "could not register clock provider: %s: %d\n",
140 static struct platform_driver clk_mt7622_eth_drv = {
141 .probe = clk_mt7622_eth_probe,
143 .name = "clk-mt7622-eth",
144 .of_match_table = of_match_clk_mt7622_eth,
148 builtin_platform_driver(clk_mt7622_eth_drv);