drivers/clk/mediatek/clk-fhctl.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2022 MediaTek Inc.
   4  * Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
   5  */
   6
   7 #include <linux/io.h>
   8 #include <linux/iopoll.h>
   9
  10 #include "clk-mtk.h"
  11 #include "clk-pllfh.h"
  12 #include "clk-fhctl.h"
  13
  14 #define PERCENT_TO_DDSLMT(dds, percent_m10) \
  15         ((((dds) * (percent_m10)) >> 5) / 100)
  16
  17 static const struct fhctl_offset fhctl_offset = {
  18         .offset_hp_en = 0x0,
  19         .offset_clk_con = 0x8,
  20         .offset_rst_con = 0xc,
  21         .offset_slope0 = 0x10,
  22         .offset_slope1 = 0x14,
  23         .offset_cfg = 0x0,
  24         .offset_updnlmt = 0x4,
  25         .offset_dds = 0x8,
  26         .offset_dvfs = 0xc,
  27         .offset_mon = 0x10,
  28 };
  29
  30 const struct fhctl_offset *fhctl_get_offset_table(void)
  31 {
  32         return &fhctl_offset;
  33 }
  34
  35 static void dump_hw(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
  36                     const struct fh_pll_data *data)
  37 {
  38         pr_info("hp_en<%x>,clk_con<%x>,slope0<%x>,slope1<%x>\n",
  39                 readl(regs->reg_hp_en), readl(regs->reg_clk_con),
  40                 readl(regs->reg_slope0), readl(regs->reg_slope1));
  41         pr_info("cfg<%x>,lmt<%x>,dds<%x>,dvfs<%x>,mon<%x>\n",
  42                 readl(regs->reg_cfg), readl(regs->reg_updnlmt),
  43                 readl(regs->reg_dds), readl(regs->reg_dvfs),
  44                 readl(regs->reg_mon));
  45         pr_info("pcw<%x>\n", readl(pll->pcw_addr));
  46 }
  47
  48 static int fhctl_set_ssc_regs(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
  49                               const struct fh_pll_data *data, u32 rate)
  50 {
  51         u32 updnlmt_val, r;
  52
  53         writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg);
  54         writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg);
  55         writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg);
  56
  57         if (rate > 0) {
  58                 /* Set the relative parameter registers (dt/df/upbnd/downbnd) */
  59                 r = readl(regs->reg_cfg);
  60                 r &= ~(data->msk_frddsx_dys);
  61                 r |= (data->df_val << (ffs(data->msk_frddsx_dys) - 1));
  62                 writel(r, regs->reg_cfg);
  63
  64                 r = readl(regs->reg_cfg);
  65                 r &= ~(data->msk_frddsx_dts);
  66                 r |= (data->dt_val << (ffs(data->msk_frddsx_dts) - 1));
  67                 writel(r, regs->reg_cfg);
  68
  69                 writel((readl(pll->pcw_addr) & data->dds_mask) | data->tgl_org,
  70                         regs->reg_dds);
  71
  72                 /* Calculate UPDNLMT */
  73                 updnlmt_val = PERCENT_TO_DDSLMT((readl(regs->reg_dds) &
  74                                                  data->dds_mask), rate) <<
  75                                                  data->updnlmt_shft;
  76
  77                 writel(updnlmt_val, regs->reg_updnlmt);
  78                 writel(readl(regs->reg_hp_en) | BIT(data->fh_id),
  79                        regs->reg_hp_en);
  80                 /* Enable SSC */
  81                 writel(readl(regs->reg_cfg) | data->frddsx_en, regs->reg_cfg);
  82                 /* Enable Hopping control */
  83                 writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
  84
  85         } else {
  86                 /* Switch to APMIXEDSYS control */
  87                 writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id),
  88                        regs->reg_hp_en);
  89                 /* Wait for DDS to be stable */
  90                 udelay(30);
  91         }
  92
  93         return 0;
  94 }
  95
  96 static int hopping_hw_flow(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
  97                            const struct fh_pll_data *data,
  98                            struct fh_pll_state *state, unsigned int new_dds)
  99 {
 100         u32 dds_mask = data->dds_mask;
 101         u32 mon_dds = 0;
 102         u32 con_pcw_tmp;
 103         int ret;
 104
 105         if (state->ssc_rate)
 106                 fhctl_set_ssc_regs(pll, regs, data, 0);
 107
 108         writel((readl(pll->pcw_addr) & dds_mask) | data->tgl_org,
 109                 regs->reg_dds);
 110
 111         writel(readl(regs->reg_cfg) | data->sfstrx_en, regs->reg_cfg);
 112         writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
 113         writel(data->slope0_value, regs->reg_slope0);
 114         writel(data->slope1_value, regs->reg_slope1);
 115
 116         writel(readl(regs->reg_hp_en) | BIT(data->fh_id), regs->reg_hp_en);
 117         writel((new_dds) | (data->dvfs_tri), regs->reg_dvfs);
 118
 119         /* Wait 1000 us until DDS stable */
 120         ret = readl_poll_timeout_atomic(regs->reg_mon, mon_dds,
 121                                        (mon_dds & dds_mask) == new_dds,
 122                                         10, 1000);
 123         if (ret) {
 124                 pr_warn("%s: FHCTL hopping timeout\n", pll->data->name);
 125                 dump_hw(pll, regs, data);
 126         }
 127
 128         con_pcw_tmp = readl(pll->pcw_addr) & (~dds_mask);
 129         con_pcw_tmp = (con_pcw_tmp | (readl(regs->reg_mon) & dds_mask) |
 130                        data->pcwchg);
 131
 132         writel(con_pcw_tmp, pll->pcw_addr);
 133         writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id), regs->reg_hp_en);
 134
 135         if (state->ssc_rate)
 136                 fhctl_set_ssc_regs(pll, regs, data, state->ssc_rate);
 137
 138         return ret;
 139 }
 140
 141 static unsigned int __get_postdiv(struct mtk_clk_pll *pll)
 142 {
 143         unsigned int regval;
 144
 145         regval = readl(pll->pd_addr) >> pll->data->pd_shift;
 146         regval &= POSTDIV_MASK;
 147
 148         return BIT(regval);
 149 }
 150
 151 static void __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv)
 152 {
 153         unsigned int regval;
 154
 155         regval = readl(pll->pd_addr);
 156         regval &= ~(POSTDIV_MASK << pll->data->pd_shift);
 157         regval |= (ffs(postdiv) - 1) << pll->data->pd_shift;
 158         writel(regval, pll->pd_addr);
 159 }
 160
 161 static int fhctl_hopping(struct mtk_fh *fh, unsigned int new_dds,
 162                          unsigned int postdiv)
 163 {
 164         const struct fh_pll_data *data = &fh->pllfh_data->data;
 165         struct fh_pll_state *state = &fh->pllfh_data->state;
 166         struct fh_pll_regs *regs = &fh->regs;
 167         struct mtk_clk_pll *pll = &fh->clk_pll;
 168         spinlock_t *lock = fh->lock;
 169         unsigned int pll_postdiv;
 170         unsigned long flags = 0;
 171         int ret;
 172
 173         if (postdiv) {
 174                 pll_postdiv = __get_postdiv(pll);
 175
 176                 if (postdiv > pll_postdiv)
 177                         __set_postdiv(pll, postdiv);
 178         }
 179
 180         spin_lock_irqsave(lock, flags);
 181
 182         ret = hopping_hw_flow(pll, regs, data, state, new_dds);
 183
 184         spin_unlock_irqrestore(lock, flags);
 185
 186         if (postdiv && postdiv < pll_postdiv)
 187                 __set_postdiv(pll, postdiv);
 188
 189         return ret;
 190 }
 191
 192 static int fhctl_ssc_enable(struct mtk_fh *fh, u32 rate)
 193 {
 194         const struct fh_pll_data *data = &fh->pllfh_data->data;
 195         struct fh_pll_state *state = &fh->pllfh_data->state;
 196         struct fh_pll_regs *regs = &fh->regs;
 197         struct mtk_clk_pll *pll = &fh->clk_pll;
 198         spinlock_t *lock = fh->lock;
 199         unsigned long flags = 0;
 200
 201         spin_lock_irqsave(lock, flags);
 202
 203         fhctl_set_ssc_regs(pll, regs, data, rate);
 204         state->ssc_rate = rate;
 205
 206         spin_unlock_irqrestore(lock, flags);
 207
 208         return 0;
 209 }
 210
 211 static const struct fh_operation fhctl_ops = {
 212         .hopping = fhctl_hopping,
 213         .ssc_enable = fhctl_ssc_enable,
 214 };
 215
 216 const struct fh_operation *fhctl_get_ops(void)
 217 {
 218         return &fhctl_ops;
 219 }
 220
 221 void fhctl_hw_init(struct mtk_fh *fh)
 222 {
 223         const struct fh_pll_data data = fh->pllfh_data->data;
 224         struct fh_pll_state state = fh->pllfh_data->state;
 225         struct fh_pll_regs regs = fh->regs;
 226         u32 val;
 227
 228         /* initial hw register */
 229         val = readl(regs.reg_clk_con) | BIT(data.fh_id);
 230         writel(val, regs.reg_clk_con);
 231
 232         val = readl(regs.reg_rst_con) & ~BIT(data.fh_id);
 233         writel(val, regs.reg_rst_con);
 234         val = readl(regs.reg_rst_con) | BIT(data.fh_id);
 235         writel(val, regs.reg_rst_con);
 236
 237         writel(0x0, regs.reg_cfg);
 238         writel(0x0, regs.reg_updnlmt);
 239         writel(0x0, regs.reg_dds);
 240
 241         /* enable ssc if needed */
 242         if (state.ssc_rate)
 243                 fh->ops->ssc_enable(fh, state.ssc_rate);
 244 }