1 // SPDX-License-Identifier: GPL-2.0
3 * Clock driver for TI Davinci PSC controllers
5 * Copyright (C) 2017 David Lechner <david@lechnology.com>
7 * Based on: drivers/clk/keystone/gate.c
8 * Copyright (C) 2013 Texas Instruments.
9 * Murali Karicheri <m-karicheri2@ti.com>
10 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * And: arch/arm/mach-davinci/psc.c
13 * Copyright (C) 2006 Texas Instruments.
16 #include <linux/clk-provider.h>
17 #include <linux/clk.h>
18 #include <linux/clkdev.h>
19 #include <linux/err.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_clock.h>
25 #include <linux/pm_domain.h>
26 #include <linux/regmap.h>
27 #include <linux/reset-controller.h>
28 #include <linux/slab.h>
29 #include <linux/types.h>
33 /* PSC register offsets */
37 #define PDSTAT(n) (0x200 + 4 * (n))
38 #define PDCTL(n) (0x300 + 4 * (n))
39 #define MDSTAT(n) (0x800 + 4 * (n))
40 #define MDCTL(n) (0xa00 + 4 * (n))
42 /* PSC module states */
43 enum davinci_lpsc_state {
44 LPSC_STATE_SWRSTDISABLE = 0,
45 LPSC_STATE_SYNCRST = 1,
46 LPSC_STATE_DISABLE = 2,
47 LPSC_STATE_ENABLE = 3,
50 #define MDSTAT_STATE_MASK GENMASK(5, 0)
51 #define MDSTAT_MCKOUT BIT(12)
52 #define PDSTAT_STATE_MASK GENMASK(4, 0)
53 #define MDCTL_FORCE BIT(31)
54 #define MDCTL_LRESET BIT(8)
55 #define PDCTL_EPCGOOD BIT(8)
56 #define PDCTL_NEXT BIT(0)
58 struct davinci_psc_data {
59 struct clk_onecell_data clk_data;
60 struct genpd_onecell_data pm_data;
61 struct reset_controller_dev rcdev;
65 * struct davinci_lpsc_clk - LPSC clock structure
66 * @dev: the device that provides this LPSC
67 * @hw: clk_hw for the LPSC
68 * @pm_domain: power domain for the LPSC
69 * @genpd_clk: clock reference owned by @pm_domain
70 * @regmap: PSC MMIO region
71 * @md: Module domain (LPSC module id)
73 * @flags: LPSC_* quirk flags
75 struct davinci_lpsc_clk {
78 struct generic_pm_domain pm_domain;
79 struct clk *genpd_clk;
80 struct regmap *regmap;
86 #define to_davinci_psc_data(x) container_of(x, struct davinci_psc_data, x)
87 #define to_davinci_lpsc_clk(x) container_of(x, struct davinci_lpsc_clk, x)
90 * best_dev_name - get the "best" device name.
93 * Returns the device tree compatible name if the device has a DT node,
94 * otherwise return the device name. This is mainly needed because clkdev
95 * lookups are limited to 20 chars for dev_id and when using device tree,
96 * dev_name(dev) is much longer than that.
98 static inline const char *best_dev_name(struct device *dev)
100 const char *compatible;
102 if (!of_property_read_string(dev->of_node, "compatible", &compatible))
105 return dev_name(dev);
108 static void davinci_lpsc_config(struct davinci_lpsc_clk *lpsc,
109 enum davinci_lpsc_state next_state)
111 u32 epcpr, pdstat, mdstat, ptstat;
113 regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDSTAT_STATE_MASK,
116 if (lpsc->flags & LPSC_FORCE)
117 regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_FORCE,
120 regmap_read(lpsc->regmap, PDSTAT(lpsc->pd), &pdstat);
121 if ((pdstat & PDSTAT_STATE_MASK) == 0) {
122 regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_NEXT,
125 regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd));
127 regmap_read_poll_timeout(lpsc->regmap, EPCPR, epcpr,
128 epcpr & BIT(lpsc->pd), 0, 0);
130 regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_EPCGOOD,
133 regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd));
136 regmap_read_poll_timeout(lpsc->regmap, PTSTAT, ptstat,
137 !(ptstat & BIT(lpsc->pd)), 0, 0);
139 regmap_read_poll_timeout(lpsc->regmap, MDSTAT(lpsc->md), mdstat,
140 (mdstat & MDSTAT_STATE_MASK) == next_state,
144 static int davinci_lpsc_clk_enable(struct clk_hw *hw)
146 struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
148 davinci_lpsc_config(lpsc, LPSC_STATE_ENABLE);
153 static void davinci_lpsc_clk_disable(struct clk_hw *hw)
155 struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
157 davinci_lpsc_config(lpsc, LPSC_STATE_DISABLE);
160 static int davinci_lpsc_clk_is_enabled(struct clk_hw *hw)
162 struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
165 regmap_read(lpsc->regmap, MDSTAT(lpsc->md), &mdstat);
167 return (mdstat & MDSTAT_MCKOUT) ? 1 : 0;
170 static const struct clk_ops davinci_lpsc_clk_ops = {
171 .enable = davinci_lpsc_clk_enable,
172 .disable = davinci_lpsc_clk_disable,
173 .is_enabled = davinci_lpsc_clk_is_enabled,
176 static int davinci_psc_genpd_attach_dev(struct generic_pm_domain *pm_domain,
179 struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain);
184 * pm_clk_remove_clk() will call clk_put(), so we have to use clk_get()
185 * to get the clock instead of using lpsc->hw.clk directly.
187 clk = clk_get_sys(best_dev_name(lpsc->dev), clk_hw_get_name(&lpsc->hw));
189 return (PTR_ERR(clk));
191 ret = pm_clk_create(dev);
195 ret = pm_clk_add_clk(dev, clk);
197 goto fail_pm_clk_destroy;
199 lpsc->genpd_clk = clk;
211 static void davinci_psc_genpd_detach_dev(struct generic_pm_domain *pm_domain,
214 struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain);
216 pm_clk_remove_clk(dev, lpsc->genpd_clk);
219 lpsc->genpd_clk = NULL;
223 * davinci_lpsc_clk_register - register LPSC clock
224 * @name: name of this clock
225 * @parent_name: name of clock's parent
226 * @regmap: PSC MMIO region
227 * @md: local PSC number
229 * @flags: LPSC_* flags
231 static struct davinci_lpsc_clk *
232 davinci_lpsc_clk_register(struct device *dev, const char *name,
233 const char *parent_name, struct regmap *regmap,
234 u32 md, u32 pd, u32 flags)
236 struct clk_init_data init;
237 struct davinci_lpsc_clk *lpsc;
241 lpsc = devm_kzalloc(dev, sizeof(*lpsc), GFP_KERNEL);
243 return ERR_PTR(-ENOMEM);
246 init.ops = &davinci_lpsc_clk_ops;
247 init.parent_names = (parent_name ? &parent_name : NULL);
248 init.num_parents = (parent_name ? 1 : 0);
251 if (flags & LPSC_ALWAYS_ENABLED)
252 init.flags |= CLK_IS_CRITICAL;
254 if (flags & LPSC_SET_RATE_PARENT)
255 init.flags |= CLK_SET_RATE_PARENT;
258 lpsc->regmap = regmap;
259 lpsc->hw.init = &init;
264 ret = devm_clk_hw_register(dev, &lpsc->hw);
268 /* genpd attach needs a way to look up this clock */
269 ret = clk_hw_register_clkdev(&lpsc->hw, name, best_dev_name(dev));
271 lpsc->pm_domain.name = devm_kasprintf(dev, GFP_KERNEL, "%s: %s",
272 best_dev_name(dev), name);
273 lpsc->pm_domain.attach_dev = davinci_psc_genpd_attach_dev;
274 lpsc->pm_domain.detach_dev = davinci_psc_genpd_detach_dev;
275 lpsc->pm_domain.flags = GENPD_FLAG_PM_CLK;
277 is_on = davinci_lpsc_clk_is_enabled(&lpsc->hw);
278 pm_genpd_init(&lpsc->pm_domain, NULL, is_on);
283 static int davinci_lpsc_clk_reset(struct clk *clk, bool reset)
285 struct clk_hw *hw = __clk_get_hw(clk);
286 struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
289 if (IS_ERR_OR_NULL(lpsc))
292 mdctl = reset ? 0 : MDCTL_LRESET;
293 regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_LRESET, mdctl);
299 * REVISIT: These exported functions can be removed after a non-DT lookup is
300 * added to the reset controller framework and the davinci-rproc driver is
301 * updated to use the generic reset controller framework.
304 int davinci_clk_reset_assert(struct clk *clk)
306 return davinci_lpsc_clk_reset(clk, true);
308 EXPORT_SYMBOL(davinci_clk_reset_assert);
310 int davinci_clk_reset_deassert(struct clk *clk)
312 return davinci_lpsc_clk_reset(clk, false);
314 EXPORT_SYMBOL(davinci_clk_reset_deassert);
316 static int davinci_psc_reset_assert(struct reset_controller_dev *rcdev,
319 struct davinci_psc_data *psc = to_davinci_psc_data(rcdev);
320 struct clk *clk = psc->clk_data.clks[id];
322 return davinci_lpsc_clk_reset(clk, true);
325 static int davinci_psc_reset_deassert(struct reset_controller_dev *rcdev,
328 struct davinci_psc_data *psc = to_davinci_psc_data(rcdev);
329 struct clk *clk = psc->clk_data.clks[id];
331 return davinci_lpsc_clk_reset(clk, false);
334 static const struct reset_control_ops davinci_psc_reset_ops = {
335 .assert = davinci_psc_reset_assert,
336 .deassert = davinci_psc_reset_deassert,
339 static int davinci_psc_reset_of_xlate(struct reset_controller_dev *rcdev,
340 const struct of_phandle_args *reset_spec)
342 struct of_phandle_args clkspec = *reset_spec; /* discard const qualifier */
345 struct davinci_lpsc_clk *lpsc;
347 /* the clock node is the same as the reset node */
348 clk = of_clk_get_from_provider(&clkspec);
352 hw = __clk_get_hw(clk);
353 lpsc = to_davinci_lpsc_clk(hw);
356 /* not all modules support local reset */
357 if (!(lpsc->flags & LPSC_LOCAL_RESET))
363 static const struct regmap_config davinci_psc_regmap_config = {
369 static struct davinci_psc_data *
370 __davinci_psc_register_clocks(struct device *dev,
371 const struct davinci_lpsc_clk_info *info,
375 struct davinci_psc_data *psc;
377 struct generic_pm_domain **pm_domains;
378 struct regmap *regmap;
381 psc = devm_kzalloc(dev, sizeof(*psc), GFP_KERNEL);
383 return ERR_PTR(-ENOMEM);
385 clks = devm_kmalloc_array(dev, num_clks, sizeof(*clks), GFP_KERNEL);
387 return ERR_PTR(-ENOMEM);
389 psc->clk_data.clks = clks;
390 psc->clk_data.clk_num = num_clks;
393 * init array with error so that of_clk_src_onecell_get() doesn't
394 * return NULL for gaps in the sparse array
396 for (i = 0; i < num_clks; i++)
397 clks[i] = ERR_PTR(-ENOENT);
399 pm_domains = devm_kcalloc(dev, num_clks, sizeof(*pm_domains), GFP_KERNEL);
401 return ERR_PTR(-ENOMEM);
403 psc->pm_data.domains = pm_domains;
404 psc->pm_data.num_domains = num_clks;
406 regmap = devm_regmap_init_mmio(dev, base, &davinci_psc_regmap_config);
408 return ERR_CAST(regmap);
410 for (; info->name; info++) {
411 struct davinci_lpsc_clk *lpsc;
413 lpsc = davinci_lpsc_clk_register(dev, info->name, info->parent,
414 regmap, info->md, info->pd,
417 dev_warn(dev, "Failed to register %s (%ld)\n",
418 info->name, PTR_ERR(lpsc));
422 clks[info->md] = lpsc->hw.clk;
423 pm_domains[info->md] = &lpsc->pm_domain;
426 psc->rcdev.ops = &davinci_psc_reset_ops;
427 psc->rcdev.owner = THIS_MODULE;
428 psc->rcdev.dev = dev;
429 psc->rcdev.of_node = dev->of_node;
430 psc->rcdev.of_reset_n_cells = 1;
431 psc->rcdev.of_xlate = davinci_psc_reset_of_xlate;
432 psc->rcdev.nr_resets = num_clks;
434 ret = devm_reset_controller_register(dev, &psc->rcdev);
436 dev_warn(dev, "Failed to register reset controller (%d)\n", ret);
441 int davinci_psc_register_clocks(struct device *dev,
442 const struct davinci_lpsc_clk_info *info,
446 struct davinci_psc_data *psc;
448 psc = __davinci_psc_register_clocks(dev, info, num_clks, base);
452 for (; info->name; info++) {
453 const struct davinci_lpsc_clkdev_info *cdevs = info->cdevs;
454 struct clk *clk = psc->clk_data.clks[info->md];
456 if (!cdevs || IS_ERR_OR_NULL(clk))
459 for (; cdevs->con_id || cdevs->dev_id; cdevs++)
460 clk_register_clkdev(clk, cdevs->con_id, cdevs->dev_id);
466 int of_davinci_psc_clk_init(struct device *dev,
467 const struct davinci_lpsc_clk_info *info,
471 struct device_node *node = dev->of_node;
472 struct davinci_psc_data *psc;
474 psc = __davinci_psc_register_clocks(dev, info, num_clks, base);
478 of_genpd_add_provider_onecell(node, &psc->pm_data);
480 of_clk_add_provider(node, of_clk_src_onecell_get, &psc->clk_data);
485 static const struct of_device_id davinci_psc_of_match[] = {
486 { .compatible = "ti,da850-psc0", .data = &of_da850_psc0_init_data },
487 { .compatible = "ti,da850-psc1", .data = &of_da850_psc1_init_data },
491 static const struct platform_device_id davinci_psc_id_table[] = {
492 { .name = "da830-psc0", .driver_data = (kernel_ulong_t)&da830_psc0_init_data },
493 { .name = "da830-psc1", .driver_data = (kernel_ulong_t)&da830_psc1_init_data },
494 { .name = "da850-psc0", .driver_data = (kernel_ulong_t)&da850_psc0_init_data },
495 { .name = "da850-psc1", .driver_data = (kernel_ulong_t)&da850_psc1_init_data },
496 { .name = "dm355-psc", .driver_data = (kernel_ulong_t)&dm355_psc_init_data },
497 { .name = "dm365-psc", .driver_data = (kernel_ulong_t)&dm365_psc_init_data },
498 { .name = "dm644x-psc", .driver_data = (kernel_ulong_t)&dm644x_psc_init_data },
499 { .name = "dm646x-psc", .driver_data = (kernel_ulong_t)&dm646x_psc_init_data },
503 static int davinci_psc_probe(struct platform_device *pdev)
505 struct device *dev = &pdev->dev;
506 const struct of_device_id *of_id;
507 const struct davinci_psc_init_data *init_data = NULL;
508 struct resource *res;
512 of_id = of_match_device(davinci_psc_of_match, dev);
514 init_data = of_id->data;
515 else if (pdev->id_entry)
516 init_data = (void *)pdev->id_entry->driver_data;
519 dev_err(dev, "unable to find driver init data\n");
523 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
524 base = devm_ioremap_resource(dev, res);
526 return PTR_ERR(base);
528 ret = devm_clk_bulk_get(dev, init_data->num_parent_clks,
529 init_data->parent_clks);
533 return init_data->psc_init(dev, base);
536 static struct platform_driver davinci_psc_driver = {
537 .probe = davinci_psc_probe,
539 .name = "davinci-psc-clk",
540 .of_match_table = davinci_psc_of_match,
542 .id_table = davinci_psc_id_table,
545 static int __init davinci_psc_driver_init(void)
547 return platform_driver_register(&davinci_psc_driver);
550 /* has to be postcore_initcall because davinci_gpio depend on PSC clocks */
551 postcore_initcall(davinci_psc_driver_init);