drivers/clk/davinci/pll-dm355.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * PLL clock descriptions for TI DM355
   4  *
   5  * Copyright (C) 2018 David Lechner <david@lechnology.com>
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/clkdev.h>
  10 #include <linux/init.h>
  11 #include <linux/types.h>
  12
  13 #include "pll.h"
  14
  15 static const struct davinci_pll_clk_info dm355_pll1_info = {
  16         .name = "pll1",
  17         .pllm_mask = GENMASK(7, 0),
  18         .pllm_min = 92,
  19         .pllm_max = 184,
  20         .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_PREDIV_ALWAYS_ENABLED |
  21                  PLL_PREDIV_FIXED8 | PLL_HAS_POSTDIV |
  22                  PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
  23 };
  24
  25 SYSCLK(1, pll1_sysclk1, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
  26 SYSCLK(2, pll1_sysclk2, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
  27 SYSCLK(3, pll1_sysclk3, pll1, 5, SYSCLK_ALWAYS_ENABLED);
  28 SYSCLK(4, pll1_sysclk4, pll1, 5, SYSCLK_ALWAYS_ENABLED);
  29
  30 int dm355_pll1_init(struct device *dev, void __iomem *base)
  31 {
  32         struct clk *clk;
  33
  34         davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base);
  35
  36         clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
  37         clk_register_clkdev(clk, "pll1_sysclk1", "dm355-psc");
  38
  39         clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
  40         clk_register_clkdev(clk, "pll1_sysclk2", "dm355-psc");
  41
  42         clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
  43         clk_register_clkdev(clk, "pll1_sysclk3", "dm355-psc");
  44
  45         clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);
  46         clk_register_clkdev(clk, "pll1_sysclk4", "dm355-psc");
  47
  48         clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
  49         clk_register_clkdev(clk, "pll1_auxclk", "dm355-psc");
  50
  51         davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
  52
  53         return 0;
  54 }
  55
  56 static const struct davinci_pll_clk_info dm355_pll2_info = {
  57         .name = "pll2",
  58         .pllm_mask = GENMASK(7, 0),
  59         .pllm_min = 92,
  60         .pllm_max = 184,
  61         .flags = PLL_HAS_PREDIV | PLL_PREDIV_ALWAYS_ENABLED | PLL_HAS_POSTDIV |
  62                  PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
  63 };
  64
  65 SYSCLK(1, pll2_sysclk1, pll2, 5, SYSCLK_FIXED_DIV);
  66 SYSCLK(2, pll2_sysclk2, pll2, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
  67
  68 int dm355_pll2_init(struct device *dev, void __iomem *base)
  69 {
  70         davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base);
  71
  72         davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
  73
  74         davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
  75
  76         davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
  77
  78         return 0;
  79 }