4 * Copyright 2011-2 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/slab.h>
19 #include <linux/platform_device.h>
20 #include <linux/mfd/wm831x/core.h>
23 struct wm831x *wm831x;
24 struct clk_hw xtal_hw;
26 struct clk_hw clkout_hw;
33 static int wm831x_xtal_is_prepared(struct clk_hw *hw)
35 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
38 return clkdata->xtal_ena;
41 static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw,
42 unsigned long parent_rate)
44 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
47 if (clkdata->xtal_ena)
53 static const struct clk_ops wm831x_xtal_ops = {
54 .is_prepared = wm831x_xtal_is_prepared,
55 .recalc_rate = wm831x_xtal_recalc_rate,
58 static struct clk_init_data wm831x_xtal_init = {
60 .ops = &wm831x_xtal_ops,
63 static const unsigned long wm831x_fll_auto_rates[] = {
74 static int wm831x_fll_is_prepared(struct clk_hw *hw)
76 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
78 struct wm831x *wm831x = clkdata->wm831x;
81 ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1);
83 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n",
88 return (ret & WM831X_FLL_ENA) != 0;
91 static int wm831x_fll_prepare(struct clk_hw *hw)
93 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
95 struct wm831x *wm831x = clkdata->wm831x;
98 ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1,
99 WM831X_FLL_ENA, WM831X_FLL_ENA);
101 dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
103 usleep_range(2000, 2000);
108 static void wm831x_fll_unprepare(struct clk_hw *hw)
110 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
112 struct wm831x *wm831x = clkdata->wm831x;
115 ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, WM831X_FLL_ENA, 0);
117 dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret);
120 static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
121 unsigned long parent_rate)
123 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
125 struct wm831x *wm831x = clkdata->wm831x;
128 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
130 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
135 if (ret & WM831X_FLL_AUTO)
136 return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK];
138 dev_err(wm831x->dev, "FLL only supported in AUTO mode\n");
143 static long wm831x_fll_round_rate(struct clk_hw *hw, unsigned long rate,
144 unsigned long *unused)
149 for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
150 if (abs(wm831x_fll_auto_rates[i] - rate) <
151 abs(wm831x_fll_auto_rates[best] - rate))
154 return wm831x_fll_auto_rates[best];
157 static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate,
158 unsigned long parent_rate)
160 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
162 struct wm831x *wm831x = clkdata->wm831x;
165 for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
166 if (wm831x_fll_auto_rates[i] == rate)
168 if (i == ARRAY_SIZE(wm831x_fll_auto_rates))
171 if (wm831x_fll_is_prepared(hw))
174 return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2,
175 WM831X_FLL_AUTO_FREQ_MASK, i);
178 static const char *wm831x_fll_parents[] = {
183 static u8 wm831x_fll_get_parent(struct clk_hw *hw)
185 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
187 struct wm831x *wm831x = clkdata->wm831x;
190 /* AUTO mode is always clocked from the crystal */
191 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
193 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
198 if (ret & WM831X_FLL_AUTO)
201 ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5);
203 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n",
208 switch (ret & WM831X_FLL_CLK_SRC_MASK) {
214 dev_err(wm831x->dev, "Unsupported FLL clock source %d\n",
215 ret & WM831X_FLL_CLK_SRC_MASK);
220 static const struct clk_ops wm831x_fll_ops = {
221 .is_prepared = wm831x_fll_is_prepared,
222 .prepare = wm831x_fll_prepare,
223 .unprepare = wm831x_fll_unprepare,
224 .round_rate = wm831x_fll_round_rate,
225 .recalc_rate = wm831x_fll_recalc_rate,
226 .set_rate = wm831x_fll_set_rate,
227 .get_parent = wm831x_fll_get_parent,
230 static struct clk_init_data wm831x_fll_init = {
232 .ops = &wm831x_fll_ops,
233 .parent_names = wm831x_fll_parents,
234 .num_parents = ARRAY_SIZE(wm831x_fll_parents),
235 .flags = CLK_SET_RATE_GATE,
238 static int wm831x_clkout_is_prepared(struct clk_hw *hw)
240 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
242 struct wm831x *wm831x = clkdata->wm831x;
245 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
247 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
252 return (ret & WM831X_CLKOUT_ENA) != 0;
255 static int wm831x_clkout_prepare(struct clk_hw *hw)
257 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
259 struct wm831x *wm831x = clkdata->wm831x;
262 ret = wm831x_reg_unlock(wm831x);
264 dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
268 ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
269 WM831X_CLKOUT_ENA, WM831X_CLKOUT_ENA);
271 dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret);
273 wm831x_reg_lock(wm831x);
278 static void wm831x_clkout_unprepare(struct clk_hw *hw)
280 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
282 struct wm831x *wm831x = clkdata->wm831x;
285 ret = wm831x_reg_unlock(wm831x);
287 dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
291 ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
292 WM831X_CLKOUT_ENA, 0);
294 dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret);
296 wm831x_reg_lock(wm831x);
299 static const char *wm831x_clkout_parents[] = {
304 static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
306 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
308 struct wm831x *wm831x = clkdata->wm831x;
311 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
313 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
318 if (ret & WM831X_CLKOUT_SRC)
324 static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
326 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
328 struct wm831x *wm831x = clkdata->wm831x;
330 return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
332 parent << WM831X_CLKOUT_SRC_SHIFT);
335 static const struct clk_ops wm831x_clkout_ops = {
336 .is_prepared = wm831x_clkout_is_prepared,
337 .prepare = wm831x_clkout_prepare,
338 .unprepare = wm831x_clkout_unprepare,
339 .get_parent = wm831x_clkout_get_parent,
340 .set_parent = wm831x_clkout_set_parent,
343 static struct clk_init_data wm831x_clkout_init = {
345 .ops = &wm831x_clkout_ops,
346 .parent_names = wm831x_clkout_parents,
347 .num_parents = ARRAY_SIZE(wm831x_clkout_parents),
348 .flags = CLK_SET_RATE_PARENT,
351 static int wm831x_clk_probe(struct platform_device *pdev)
353 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
354 struct wm831x_clk *clkdata;
357 clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
361 clkdata->wm831x = wm831x;
363 /* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
364 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
366 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
370 clkdata->xtal_ena = ret & WM831X_XTAL_ENA;
372 clkdata->xtal_hw.init = &wm831x_xtal_init;
373 clkdata->xtal = devm_clk_register(&pdev->dev, &clkdata->xtal_hw);
374 if (IS_ERR(clkdata->xtal))
375 return PTR_ERR(clkdata->xtal);
377 clkdata->fll_hw.init = &wm831x_fll_init;
378 clkdata->fll = devm_clk_register(&pdev->dev, &clkdata->fll_hw);
379 if (IS_ERR(clkdata->fll))
380 return PTR_ERR(clkdata->fll);
382 clkdata->clkout_hw.init = &wm831x_clkout_init;
383 clkdata->clkout = devm_clk_register(&pdev->dev, &clkdata->clkout_hw);
384 if (IS_ERR(clkdata->clkout))
385 return PTR_ERR(clkdata->clkout);
387 platform_set_drvdata(pdev, clkdata);
392 static struct platform_driver wm831x_clk_driver = {
393 .probe = wm831x_clk_probe,
395 .name = "wm831x-clk",
399 module_platform_driver(wm831x_clk_driver);
401 /* Module information */
402 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
403 MODULE_DESCRIPTION("WM831x clock driver");
404 MODULE_LICENSE("GPL");
405 MODULE_ALIAS("platform:wm831x-clk");