1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for IDT Versaclock 5
5 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
9 * Possible optimizations:
10 * - Use spread spectrum
11 * - Use integer divider in FOD if applicable
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/interrupt.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
22 #include <linux/of_platform.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
26 #include <dt-bindings/clock/versaclock.h>
28 /* VersaClock5 registers */
29 #define VC5_OTP_CONTROL 0x00
31 /* Factory-reserved register block */
32 #define VC5_RSVD_DEVICE_ID 0x01
33 #define VC5_RSVD_ADC_GAIN_7_0 0x02
34 #define VC5_RSVD_ADC_GAIN_15_8 0x03
35 #define VC5_RSVD_ADC_OFFSET_7_0 0x04
36 #define VC5_RSVD_ADC_OFFSET_15_8 0x05
37 #define VC5_RSVD_TEMPY 0x06
38 #define VC5_RSVD_OFFSET_TBIN 0x07
39 #define VC5_RSVD_GAIN 0x08
40 #define VC5_RSVD_TEST_NP 0x09
41 #define VC5_RSVD_UNUSED 0x0a
42 #define VC5_RSVD_BANDGAP_TRIM_UP 0x0b
43 #define VC5_RSVD_BANDGAP_TRIM_DN 0x0c
44 #define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d
45 #define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e
46 #define VC5_RSVD_CLK_AMP_123 0x0f
48 /* Configuration register block */
49 #define VC5_PRIM_SRC_SHDN 0x10
50 #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7)
51 #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6)
52 #define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3)
53 #define VC5_PRIM_SRC_SHDN_SP BIT(1)
54 #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0)
56 #define VC5_VCO_BAND 0x11
57 #define VC5_XTAL_X1_LOAD_CAP 0x12
58 #define VC5_XTAL_X2_LOAD_CAP 0x13
59 #define VC5_REF_DIVIDER 0x15
60 #define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7)
61 #define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f)
63 #define VC5_VCO_CTRL_AND_PREDIV 0x16
64 #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7)
66 #define VC5_FEEDBACK_INT_DIV 0x17
67 #define VC5_FEEDBACK_INT_DIV_BITS 0x18
68 #define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n))
69 #define VC5_RC_CONTROL0 0x1e
70 #define VC5_RC_CONTROL1 0x1f
72 /* These registers are named "Unused Factory Reserved Registers" */
73 #define VC5_RESERVED_X0(idx) (0x20 + ((idx) * 0x10))
74 #define VC5_RESERVED_X0_BYPASS_SYNC BIT(7) /* bypass_sync<idx> bit */
76 /* Output divider control for divider 1,2,3,4 */
77 #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10))
78 #define VC5_OUT_DIV_CONTROL_RESET BIT(7)
79 #define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3)
80 #define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2)
81 #define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1)
82 #define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0)
84 #define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n))
85 #define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1)
87 #define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n))
88 #define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n))
89 #define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n))
90 #define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n))
91 #define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10))
93 /* Clock control register for clock 1,2 */
94 #define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n))
95 #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5
96 #define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT)
98 #define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL (VC5_LVPECL)
99 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS)
100 #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33 (VC5_HCSL33)
101 #define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS)
102 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2)
103 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD)
104 #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25 (VC5_HCSL25)
106 #define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3
107 #define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
108 #define VC5_CLK_OUTPUT_CFG0_PWR_18 (0<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
109 #define VC5_CLK_OUTPUT_CFG0_PWR_25 (2<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
110 #define VC5_CLK_OUTPUT_CFG0_PWR_33 (3<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
111 #define VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT 0
112 #define VC5_CLK_OUTPUT_CFG0_SLEW_MASK GENMASK(1, VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
113 #define VC5_CLK_OUTPUT_CFG0_SLEW_80 (0<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
114 #define VC5_CLK_OUTPUT_CFG0_SLEW_85 (1<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
115 #define VC5_CLK_OUTPUT_CFG0_SLEW_90 (2<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
116 #define VC5_CLK_OUTPUT_CFG0_SLEW_100 (3<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
117 #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0)
119 #define VC5_CLK_OE_SHDN 0x68
120 #define VC5_CLK_OS_SHDN 0x69
122 #define VC5_GLOBAL_REGISTER 0x76
123 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
125 /* The minimum VCO frequency is 2.5 GHz. The maximum is variant specific. */
126 #define VC5_PLL_VCO_MIN 2500000000UL
128 /* VC5 Input mux settings */
129 #define VC5_MUX_IN_XIN BIT(0)
130 #define VC5_MUX_IN_CLKIN BIT(1)
132 /* Maximum number of clk_out supported by this driver */
133 #define VC5_MAX_CLK_OUT_NUM 5
135 /* Maximum number of FODs supported by this driver */
136 #define VC5_MAX_FOD_NUM 4
138 /* flags to describe chip features */
139 /* chip has built-in oscilator */
140 #define VC5_HAS_INTERNAL_XTAL BIT(0)
141 /* chip has PFD requency doubler */
142 #define VC5_HAS_PFD_FREQ_DBL BIT(1)
143 /* chip has bits to disable FOD sync */
144 #define VC5_HAS_BYPASS_SYNC_BIT BIT(2)
146 /* Supported IDT VC5 models. */
158 /* Structure to describe features of a particular VC5 model */
159 struct vc5_chip_info {
160 const enum vc5_model model;
161 const unsigned int clk_fod_cnt;
162 const unsigned int clk_out_cnt;
164 const unsigned long vco_max;
167 struct vc5_driver_data;
171 struct vc5_driver_data *vc5;
177 struct vc5_out_data {
179 struct vc5_driver_data *vc5;
181 unsigned int clk_output_cfg0;
182 unsigned int clk_output_cfg0_mask;
185 struct vc5_driver_data {
186 struct i2c_client *client;
187 struct regmap *regmap;
188 const struct vc5_chip_info *chip_info;
191 struct clk *pin_clkin;
192 unsigned char clk_mux_ins;
193 struct clk_hw clk_mux;
194 struct clk_hw clk_mul;
195 struct clk_hw clk_pfd;
196 struct vc5_hw_data clk_pll;
197 struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM];
198 struct vc5_out_data clk_out[VC5_MAX_CLK_OUT_NUM];
202 * VersaClock5 i2c regmap
204 static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg)
206 /* Factory reserved regs, make them read-only */
210 /* Factory reserved regs, make them read-only */
211 if (reg == 0x14 || reg == 0x1c || reg == 0x1d)
217 static const struct regmap_config vc5_regmap_config = {
220 .cache_type = REGCACHE_RBTREE,
221 .max_register = 0x76,
222 .writeable_reg = vc5_regmap_is_writeable,
226 * VersaClock5 input multiplexer between XTAL and CLKIN divider
228 static unsigned char vc5_mux_get_parent(struct clk_hw *hw)
230 struct vc5_driver_data *vc5 =
231 container_of(hw, struct vc5_driver_data, clk_mux);
232 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
236 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src);
242 if (src == VC5_PRIM_SRC_SHDN_EN_XTAL)
245 if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN)
248 dev_warn(&vc5->client->dev,
249 "Invalid clock input configuration (%02x)\n", src);
253 static int vc5_mux_set_parent(struct clk_hw *hw, u8 index)
255 struct vc5_driver_data *vc5 =
256 container_of(hw, struct vc5_driver_data, clk_mux);
257 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
260 if ((index > 1) || !vc5->clk_mux_ins)
263 if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) {
265 src = VC5_PRIM_SRC_SHDN_EN_XTAL;
267 src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
272 if (vc5->clk_mux_ins == VC5_MUX_IN_XIN)
273 src = VC5_PRIM_SRC_SHDN_EN_XTAL;
274 else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN)
275 src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
276 else /* Invalid; should have been caught by vc5_probe() */
280 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src);
283 static const struct clk_ops vc5_mux_ops = {
284 .set_parent = vc5_mux_set_parent,
285 .get_parent = vc5_mux_get_parent,
288 static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw,
289 unsigned long parent_rate)
291 struct vc5_driver_data *vc5 =
292 container_of(hw, struct vc5_driver_data, clk_mul);
296 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul);
300 if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ)
306 static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
307 unsigned long *parent_rate)
309 if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))
315 static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
316 unsigned long parent_rate)
318 struct vc5_driver_data *vc5 =
319 container_of(hw, struct vc5_driver_data, clk_mul);
322 if ((parent_rate * 2) == rate)
323 mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ;
327 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN,
328 VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ,
332 static const struct clk_ops vc5_dbl_ops = {
333 .recalc_rate = vc5_dbl_recalc_rate,
334 .round_rate = vc5_dbl_round_rate,
335 .set_rate = vc5_dbl_set_rate,
338 static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw,
339 unsigned long parent_rate)
341 struct vc5_driver_data *vc5 =
342 container_of(hw, struct vc5_driver_data, clk_pfd);
343 unsigned int prediv, div;
346 ret = regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
350 /* The bypass_prediv is set, PLL fed from Ref_in directly. */
351 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV)
354 ret = regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div);
358 /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */
359 if (div & VC5_REF_DIVIDER_SEL_PREDIV2)
360 return parent_rate / 2;
362 return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);
365 static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
366 unsigned long *parent_rate)
370 /* PLL cannot operate with input clock above 50 MHz. */
374 /* CLKIN within range of PLL input, feed directly to PLL. */
375 if (*parent_rate <= 50000000)
378 idiv = DIV_ROUND_UP(*parent_rate, rate);
382 return *parent_rate / idiv;
385 static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
386 unsigned long parent_rate)
388 struct vc5_driver_data *vc5 =
389 container_of(hw, struct vc5_driver_data, clk_pfd);
394 /* CLKIN within range of PLL input, feed directly to PLL. */
395 if (parent_rate <= 50000000) {
396 ret = regmap_set_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
397 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
401 return regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00);
404 idiv = DIV_ROUND_UP(parent_rate, rate);
406 /* We have dedicated div-2 predivider. */
408 div = VC5_REF_DIVIDER_SEL_PREDIV2;
410 div = VC5_REF_DIVIDER_REF_DIV(idiv);
412 ret = regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div);
416 return regmap_clear_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
417 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
420 static const struct clk_ops vc5_pfd_ops = {
421 .recalc_rate = vc5_pfd_recalc_rate,
422 .round_rate = vc5_pfd_round_rate,
423 .set_rate = vc5_pfd_set_rate,
427 * VersaClock5 PLL/VCO
429 static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw,
430 unsigned long parent_rate)
432 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
433 struct vc5_driver_data *vc5 = hwdata->vc5;
434 u32 div_int, div_frc;
437 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
439 div_int = (fb[0] << 4) | (fb[1] >> 4);
440 div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4];
442 /* The PLL divider has 12 integer bits and 24 fractional bits */
443 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);
446 static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
447 unsigned long *parent_rate)
449 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
450 struct vc5_driver_data *vc5 = hwdata->vc5;
454 rate = clamp(rate, VC5_PLL_VCO_MIN, vc5->chip_info->vco_max);
456 /* Determine integer part, which is 12 bit wide */
457 div_int = rate / *parent_rate;
459 rate = *parent_rate * 0xfff;
461 /* Determine best fractional part, which is 24 bit wide */
462 div_frc = rate % *parent_rate;
463 div_frc *= BIT(24) - 1;
464 do_div(div_frc, *parent_rate);
466 hwdata->div_int = div_int;
467 hwdata->div_frc = (u32)div_frc;
469 return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24);
472 static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate,
473 unsigned long parent_rate)
475 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
476 struct vc5_driver_data *vc5 = hwdata->vc5;
479 fb[0] = hwdata->div_int >> 4;
480 fb[1] = hwdata->div_int << 4;
481 fb[2] = hwdata->div_frc >> 16;
482 fb[3] = hwdata->div_frc >> 8;
483 fb[4] = hwdata->div_frc;
485 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
488 static const struct clk_ops vc5_pll_ops = {
489 .recalc_rate = vc5_pll_recalc_rate,
490 .round_rate = vc5_pll_round_rate,
491 .set_rate = vc5_pll_set_rate,
494 static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw,
495 unsigned long parent_rate)
497 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
498 struct vc5_driver_data *vc5 = hwdata->vc5;
499 /* VCO frequency is divided by two before entering FOD */
500 u32 f_in = parent_rate / 2;
501 u32 div_int, div_frc;
505 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0),
507 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
510 div_int = (od_int[0] << 4) | (od_int[1] >> 4);
511 div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) |
512 (od_frc[2] << 6) | (od_frc[3] >> 2);
514 /* Avoid division by zero if the output is not configured. */
515 if (div_int == 0 && div_frc == 0)
518 /* The PLL divider has 12 integer bits and 30 fractional bits */
519 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
522 static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate,
523 unsigned long *parent_rate)
525 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
526 /* VCO frequency is divided by two before entering FOD */
527 u32 f_in = *parent_rate / 2;
531 /* Determine integer part, which is 12 bit wide */
532 div_int = f_in / rate;
534 * WARNING: The clock chip does not output signal if the integer part
535 * of the divider is 0xfff and fractional part is non-zero.
536 * Clamp the divider at 0xffe to keep the code simple.
538 if (div_int > 0xffe) {
540 rate = f_in / div_int;
543 /* Determine best fractional part, which is 30 bit wide */
544 div_frc = f_in % rate;
546 do_div(div_frc, rate);
548 hwdata->div_int = div_int;
549 hwdata->div_frc = (u32)div_frc;
551 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
554 static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate,
555 unsigned long parent_rate)
557 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
558 struct vc5_driver_data *vc5 = hwdata->vc5;
560 hwdata->div_frc >> 22, hwdata->div_frc >> 14,
561 hwdata->div_frc >> 6, hwdata->div_frc << 2,
564 hwdata->div_int >> 4, hwdata->div_int << 4,
569 ret = regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
575 * Toggle magic bit in undocumented register for unknown reason.
576 * This is what the IDT timing commander tool does and the chip
577 * datasheet somewhat implies this is needed, but the register
578 * and the bit is not documented.
580 ret = regmap_clear_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
581 VC5_GLOBAL_REGISTER_GLOBAL_RESET);
585 return regmap_set_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
586 VC5_GLOBAL_REGISTER_GLOBAL_RESET);
589 static const struct clk_ops vc5_fod_ops = {
590 .recalc_rate = vc5_fod_recalc_rate,
591 .round_rate = vc5_fod_round_rate,
592 .set_rate = vc5_fod_set_rate,
595 static int vc5_clk_out_prepare(struct clk_hw *hw)
597 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
598 struct vc5_driver_data *vc5 = hwdata->vc5;
599 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
600 VC5_OUT_DIV_CONTROL_SEL_EXT |
601 VC5_OUT_DIV_CONTROL_EN_FOD;
606 * When enabling a FOD, all currently enabled FODs are briefly
607 * stopped in order to synchronize all of them. This causes a clock
608 * disruption to any unrelated chips that might be already using
609 * other clock outputs. Bypass the sync feature to avoid the issue,
610 * which is possible on the VersaClock 6E family via reserved
613 if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) {
614 ret = regmap_set_bits(vc5->regmap,
615 VC5_RESERVED_X0(hwdata->num),
616 VC5_RESERVED_X0_BYPASS_SYNC);
622 * If the input mux is disabled, enable it first and
623 * select source from matching FOD.
625 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
629 if ((src & mask) == 0) {
630 src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD;
631 ret = regmap_update_bits(vc5->regmap,
632 VC5_OUT_DIV_CONTROL(hwdata->num),
633 mask | VC5_OUT_DIV_CONTROL_RESET, src);
638 /* Enable the clock buffer */
639 ret = regmap_set_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
640 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
644 if (hwdata->clk_output_cfg0_mask) {
645 dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n",
646 hwdata->num, hwdata->clk_output_cfg0_mask,
647 hwdata->clk_output_cfg0);
649 ret = regmap_update_bits(vc5->regmap,
650 VC5_CLK_OUTPUT_CFG(hwdata->num, 0),
651 hwdata->clk_output_cfg0_mask,
652 hwdata->clk_output_cfg0);
660 static void vc5_clk_out_unprepare(struct clk_hw *hw)
662 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
663 struct vc5_driver_data *vc5 = hwdata->vc5;
665 /* Disable the clock buffer */
666 regmap_clear_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
667 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
670 static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
672 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
673 struct vc5_driver_data *vc5 = hwdata->vc5;
674 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
675 VC5_OUT_DIV_CONTROL_SEL_EXT |
676 VC5_OUT_DIV_CONTROL_EN_FOD;
677 const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM |
678 VC5_OUT_DIV_CONTROL_EN_FOD;
679 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
680 VC5_OUT_DIV_CONTROL_SEL_EXT;
684 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
690 if (src == 0) /* Input mux set to DISABLED */
693 if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD)
699 dev_warn(&vc5->client->dev,
700 "Invalid clock output configuration (%02x)\n", src);
704 static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index)
706 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
707 struct vc5_driver_data *vc5 = hwdata->vc5;
708 const u8 mask = VC5_OUT_DIV_CONTROL_RESET |
709 VC5_OUT_DIV_CONTROL_SELB_NORM |
710 VC5_OUT_DIV_CONTROL_SEL_EXT |
711 VC5_OUT_DIV_CONTROL_EN_FOD;
712 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
713 VC5_OUT_DIV_CONTROL_SEL_EXT;
714 u8 src = VC5_OUT_DIV_CONTROL_RESET;
717 src |= VC5_OUT_DIV_CONTROL_EN_FOD;
721 return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num),
725 static const struct clk_ops vc5_clk_out_ops = {
726 .prepare = vc5_clk_out_prepare,
727 .unprepare = vc5_clk_out_unprepare,
728 .set_parent = vc5_clk_out_set_parent,
729 .get_parent = vc5_clk_out_get_parent,
732 static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec,
735 struct vc5_driver_data *vc5 = data;
736 unsigned int idx = clkspec->args[0];
738 if (idx >= vc5->chip_info->clk_out_cnt)
739 return ERR_PTR(-EINVAL);
741 return &vc5->clk_out[idx].hw;
744 static int vc5_map_index_to_output(const enum vc5_model model,
745 const unsigned int n)
748 case IDT_VC5_5P49V5933:
749 return (n == 0) ? 0 : 3;
750 case IDT_VC5_5P49V5923:
751 case IDT_VC5_5P49V5925:
752 case IDT_VC5_5P49V5935:
753 case IDT_VC6_5P49V6901:
754 case IDT_VC6_5P49V6965:
755 case IDT_VC6_5P49V6975:
761 static int vc5_update_mode(struct device_node *np_output,
762 struct vc5_out_data *clk_out)
766 if (!of_property_read_u32(np_output, "idt,mode", &value)) {
767 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_CFG_MASK;
769 case VC5_CLK_OUTPUT_CFG0_CFG_LVPECL:
770 case VC5_CLK_OUTPUT_CFG0_CFG_CMOS:
771 case VC5_CLK_OUTPUT_CFG0_CFG_HCSL33:
772 case VC5_CLK_OUTPUT_CFG0_CFG_LVDS:
773 case VC5_CLK_OUTPUT_CFG0_CFG_CMOS2:
774 case VC5_CLK_OUTPUT_CFG0_CFG_CMOSD:
775 case VC5_CLK_OUTPUT_CFG0_CFG_HCSL25:
776 clk_out->clk_output_cfg0 |=
777 value << VC5_CLK_OUTPUT_CFG0_CFG_SHIFT;
786 static int vc5_update_power(struct device_node *np_output,
787 struct vc5_out_data *clk_out)
791 if (!of_property_read_u32(np_output, "idt,voltage-microvolt",
793 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_PWR_MASK;
796 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_18;
799 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_25;
802 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_33;
811 static int vc5_map_cap_value(u32 femtofarads)
816 * The datasheet explicitly states 9000 - 25000 with 0.5pF
817 * steps, but the Programmer's guide shows the steps are 0.430pF.
818 * After getting feedback from Renesas, the .5pF steps were the
819 * goal, but 430nF was the actual values.
820 * Because of this, the actual range goes to 22760 instead of 25000
822 if (femtofarads < 9000 || femtofarads > 22760)
826 * The Programmer's guide shows XTAL[5:0] but in reality,
827 * XTAL[0] and XTAL[1] are both LSB which makes the math
828 * strange. With clarfication from Renesas, setting the
829 * values should be simpler by ignoring XTAL[0]
831 mapped_value = DIV_ROUND_CLOSEST(femtofarads - 9000, 430);
834 * Since the calculation ignores XTAL[0], there is one
835 * special case where mapped_value = 32. In reality, this means
836 * the real mapped value should be 111111b. In other cases,
837 * the mapped_value needs to be shifted 1 to the left.
839 if (mapped_value > 31)
846 static int vc5_update_cap_load(struct device_node *node, struct vc5_driver_data *vc5)
852 if (of_property_read_u32(node, "idt,xtal-load-femtofarads", &value))
855 mapped_value = vc5_map_cap_value(value);
856 if (mapped_value < 0)
860 * The mapped_value is really the high 6 bits of
861 * VC5_XTAL_X1_LOAD_CAP and VC5_XTAL_X2_LOAD_CAP, so
862 * shift the value 2 places.
864 ret = regmap_update_bits(vc5->regmap, VC5_XTAL_X1_LOAD_CAP, ~0x03,
869 return regmap_update_bits(vc5->regmap, VC5_XTAL_X2_LOAD_CAP, ~0x03,
873 static int vc5_update_slew(struct device_node *np_output,
874 struct vc5_out_data *clk_out)
878 if (!of_property_read_u32(np_output, "idt,slew-percent", &value)) {
879 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_SLEW_MASK;
882 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_80;
885 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_85;
888 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_90;
891 clk_out->clk_output_cfg0 |=
892 VC5_CLK_OUTPUT_CFG0_SLEW_100;
901 static int vc5_get_output_config(struct i2c_client *client,
902 struct vc5_out_data *clk_out)
904 struct device_node *np_output;
908 child_name = kasprintf(GFP_KERNEL, "OUT%d", clk_out->num + 1);
912 np_output = of_get_child_by_name(client->dev.of_node, child_name);
917 ret = vc5_update_mode(np_output, clk_out);
921 ret = vc5_update_power(np_output, clk_out);
925 ret = vc5_update_slew(np_output, clk_out);
929 dev_err(&client->dev,
930 "Invalid clock output configuration OUT%d\n",
934 of_node_put(np_output);
939 static const struct of_device_id clk_vc5_of_match[];
941 static int vc5_probe(struct i2c_client *client)
943 unsigned int oe, sd, src_mask = 0, src_val = 0;
944 struct vc5_driver_data *vc5;
945 struct clk_init_data init;
946 const char *parent_names[2];
947 unsigned int n, idx = 0;
950 vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
954 i2c_set_clientdata(client, vc5);
955 vc5->client = client;
956 vc5->chip_info = of_device_get_match_data(&client->dev);
958 vc5->pin_xin = devm_clk_get(&client->dev, "xin");
959 if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
960 return -EPROBE_DEFER;
962 vc5->pin_clkin = devm_clk_get(&client->dev, "clkin");
963 if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER)
964 return -EPROBE_DEFER;
966 vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config);
967 if (IS_ERR(vc5->regmap))
968 return dev_err_probe(&client->dev, PTR_ERR(vc5->regmap),
969 "failed to allocate register map\n");
971 ret = of_property_read_u32(client->dev.of_node, "idt,shutdown", &sd);
973 src_mask |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN;
975 src_val |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN;
976 } else if (ret != -EINVAL) {
977 return dev_err_probe(&client->dev, ret,
978 "could not read idt,shutdown\n");
981 ret = of_property_read_u32(client->dev.of_node,
982 "idt,output-enable-active", &oe);
984 src_mask |= VC5_PRIM_SRC_SHDN_SP;
986 src_val |= VC5_PRIM_SRC_SHDN_SP;
987 } else if (ret != -EINVAL) {
988 return dev_err_probe(&client->dev, ret,
989 "could not read idt,output-enable-active\n");
992 ret = regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, src_mask,
997 /* Register clock input mux */
998 memset(&init, 0, sizeof(init));
1000 if (!IS_ERR(vc5->pin_xin)) {
1001 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
1002 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
1003 } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) {
1004 vc5->pin_xin = clk_register_fixed_rate(&client->dev,
1005 "internal-xtal", NULL,
1007 if (IS_ERR(vc5->pin_xin))
1008 return PTR_ERR(vc5->pin_xin);
1009 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
1010 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
1013 if (!IS_ERR(vc5->pin_clkin)) {
1014 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN;
1015 parent_names[init.num_parents++] =
1016 __clk_get_name(vc5->pin_clkin);
1019 if (!init.num_parents)
1020 return dev_err_probe(&client->dev, -EINVAL,
1021 "no input clock specified!\n");
1023 /* Configure Optional Loading Capacitance for external XTAL */
1024 if (!(vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)) {
1025 ret = vc5_update_cap_load(client->dev.of_node, vc5);
1027 goto err_clk_register;
1030 init.name = kasprintf(GFP_KERNEL, "%pOFn.mux", client->dev.of_node);
1031 init.ops = &vc5_mux_ops;
1033 init.parent_names = parent_names;
1034 vc5->clk_mux.init = &init;
1035 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux);
1037 goto err_clk_register;
1038 kfree(init.name); /* clock framework made a copy of the name */
1040 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) {
1041 /* Register frequency doubler */
1042 memset(&init, 0, sizeof(init));
1043 init.name = kasprintf(GFP_KERNEL, "%pOFn.dbl",
1044 client->dev.of_node);
1045 init.ops = &vc5_dbl_ops;
1046 init.flags = CLK_SET_RATE_PARENT;
1047 init.parent_names = parent_names;
1048 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
1049 init.num_parents = 1;
1050 vc5->clk_mul.init = &init;
1051 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul);
1053 goto err_clk_register;
1054 kfree(init.name); /* clock framework made a copy of the name */
1058 memset(&init, 0, sizeof(init));
1059 init.name = kasprintf(GFP_KERNEL, "%pOFn.pfd", client->dev.of_node);
1060 init.ops = &vc5_pfd_ops;
1061 init.flags = CLK_SET_RATE_PARENT;
1062 init.parent_names = parent_names;
1063 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL)
1064 parent_names[0] = clk_hw_get_name(&vc5->clk_mul);
1066 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
1067 init.num_parents = 1;
1068 vc5->clk_pfd.init = &init;
1069 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd);
1071 goto err_clk_register;
1072 kfree(init.name); /* clock framework made a copy of the name */
1075 memset(&init, 0, sizeof(init));
1076 init.name = kasprintf(GFP_KERNEL, "%pOFn.pll", client->dev.of_node);
1077 init.ops = &vc5_pll_ops;
1078 init.flags = CLK_SET_RATE_PARENT;
1079 init.parent_names = parent_names;
1080 parent_names[0] = clk_hw_get_name(&vc5->clk_pfd);
1081 init.num_parents = 1;
1082 vc5->clk_pll.num = 0;
1083 vc5->clk_pll.vc5 = vc5;
1084 vc5->clk_pll.hw.init = &init;
1085 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw);
1087 goto err_clk_register;
1088 kfree(init.name); /* clock framework made a copy of the name */
1091 for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
1092 idx = vc5_map_index_to_output(vc5->chip_info->model, n);
1093 memset(&init, 0, sizeof(init));
1094 init.name = kasprintf(GFP_KERNEL, "%pOFn.fod%d",
1095 client->dev.of_node, idx);
1096 init.ops = &vc5_fod_ops;
1097 init.flags = CLK_SET_RATE_PARENT;
1098 init.parent_names = parent_names;
1099 parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw);
1100 init.num_parents = 1;
1101 vc5->clk_fod[n].num = idx;
1102 vc5->clk_fod[n].vc5 = vc5;
1103 vc5->clk_fod[n].hw.init = &init;
1104 ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw);
1106 goto err_clk_register;
1107 kfree(init.name); /* clock framework made a copy of the name */
1110 /* Register MUX-connected OUT0_I2C_SELB output */
1111 memset(&init, 0, sizeof(init));
1112 init.name = kasprintf(GFP_KERNEL, "%pOFn.out0_sel_i2cb",
1113 client->dev.of_node);
1114 init.ops = &vc5_clk_out_ops;
1115 init.flags = CLK_SET_RATE_PARENT;
1116 init.parent_names = parent_names;
1117 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
1118 init.num_parents = 1;
1119 vc5->clk_out[0].num = idx;
1120 vc5->clk_out[0].vc5 = vc5;
1121 vc5->clk_out[0].hw.init = &init;
1122 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw);
1124 goto err_clk_register;
1125 kfree(init.name); /* clock framework made a copy of the name */
1127 /* Register FOD-connected OUTx outputs */
1128 for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
1129 idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1);
1130 parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw);
1132 parent_names[1] = clk_hw_get_name(&vc5->clk_mux);
1135 clk_hw_get_name(&vc5->clk_out[n - 1].hw);
1137 memset(&init, 0, sizeof(init));
1138 init.name = kasprintf(GFP_KERNEL, "%pOFn.out%d",
1139 client->dev.of_node, idx + 1);
1140 init.ops = &vc5_clk_out_ops;
1141 init.flags = CLK_SET_RATE_PARENT;
1142 init.parent_names = parent_names;
1143 init.num_parents = 2;
1144 vc5->clk_out[n].num = idx;
1145 vc5->clk_out[n].vc5 = vc5;
1146 vc5->clk_out[n].hw.init = &init;
1147 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[n].hw);
1149 goto err_clk_register;
1150 kfree(init.name); /* clock framework made a copy of the name */
1152 /* Fetch Clock Output configuration from DT (if specified) */
1153 ret = vc5_get_output_config(client, &vc5->clk_out[n]);
1158 ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5);
1160 dev_err_probe(&client->dev, ret,
1161 "unable to add clk provider\n");
1168 dev_err_probe(&client->dev, ret,
1169 "unable to register %s\n", init.name);
1170 kfree(init.name); /* clock framework made a copy of the name */
1172 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
1173 clk_unregister_fixed_rate(vc5->pin_xin);
1177 static void vc5_remove(struct i2c_client *client)
1179 struct vc5_driver_data *vc5 = i2c_get_clientdata(client);
1181 of_clk_del_provider(client->dev.of_node);
1183 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
1184 clk_unregister_fixed_rate(vc5->pin_xin);
1187 static int __maybe_unused vc5_suspend(struct device *dev)
1189 struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
1191 regcache_cache_only(vc5->regmap, true);
1192 regcache_mark_dirty(vc5->regmap);
1197 static int __maybe_unused vc5_resume(struct device *dev)
1199 struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
1202 regcache_cache_only(vc5->regmap, false);
1203 ret = regcache_sync(vc5->regmap);
1205 dev_err(dev, "Failed to restore register map: %d\n", ret);
1209 static const struct vc5_chip_info idt_5p49v5923_info = {
1210 .model = IDT_VC5_5P49V5923,
1214 .vco_max = 3000000000UL,
1217 static const struct vc5_chip_info idt_5p49v5925_info = {
1218 .model = IDT_VC5_5P49V5925,
1222 .vco_max = 3000000000UL,
1225 static const struct vc5_chip_info idt_5p49v5933_info = {
1226 .model = IDT_VC5_5P49V5933,
1229 .flags = VC5_HAS_INTERNAL_XTAL,
1230 .vco_max = 3000000000UL,
1233 static const struct vc5_chip_info idt_5p49v5935_info = {
1234 .model = IDT_VC5_5P49V5935,
1237 .flags = VC5_HAS_INTERNAL_XTAL,
1238 .vco_max = 3000000000UL,
1241 static const struct vc5_chip_info idt_5p49v60_info = {
1242 .model = IDT_VC6_5P49V60,
1245 .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT,
1246 .vco_max = 2700000000UL,
1249 static const struct vc5_chip_info idt_5p49v6901_info = {
1250 .model = IDT_VC6_5P49V6901,
1253 .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT,
1254 .vco_max = 3000000000UL,
1257 static const struct vc5_chip_info idt_5p49v6965_info = {
1258 .model = IDT_VC6_5P49V6965,
1261 .flags = VC5_HAS_BYPASS_SYNC_BIT,
1262 .vco_max = 3000000000UL,
1265 static const struct vc5_chip_info idt_5p49v6975_info = {
1266 .model = IDT_VC6_5P49V6975,
1269 .flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_INTERNAL_XTAL,
1270 .vco_max = 3000000000UL,
1273 static const struct i2c_device_id vc5_id[] = {
1274 { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
1275 { "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
1276 { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
1277 { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
1278 { "5p49v60", .driver_data = IDT_VC6_5P49V60 },
1279 { "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
1280 { "5p49v6965", .driver_data = IDT_VC6_5P49V6965 },
1281 { "5p49v6975", .driver_data = IDT_VC6_5P49V6975 },
1284 MODULE_DEVICE_TABLE(i2c, vc5_id);
1286 static const struct of_device_id clk_vc5_of_match[] = {
1287 { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
1288 { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
1289 { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
1290 { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
1291 { .compatible = "idt,5p49v60", .data = &idt_5p49v60_info },
1292 { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
1293 { .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info },
1294 { .compatible = "idt,5p49v6975", .data = &idt_5p49v6975_info },
1297 MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
1299 static SIMPLE_DEV_PM_OPS(vc5_pm_ops, vc5_suspend, vc5_resume);
1301 static struct i2c_driver vc5_driver = {
1305 .of_match_table = clk_vc5_of_match,
1307 .probe_new = vc5_probe,
1308 .remove = vc5_remove,
1311 module_i2c_driver(vc5_driver);
1313 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
1314 MODULE_DESCRIPTION("IDT VersaClock 5 driver");
1315 MODULE_LICENSE("GPL");