1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for IDT Versaclock 5
5 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
9 * Possible optimizations:
10 * - Use spread spectrum
11 * - Use integer divider in FOD if applicable
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/interrupt.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
22 #include <linux/of_platform.h>
23 #include <linux/rational.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
27 #include <dt-bindings/clk/versaclock.h>
29 /* VersaClock5 registers */
30 #define VC5_OTP_CONTROL 0x00
32 /* Factory-reserved register block */
33 #define VC5_RSVD_DEVICE_ID 0x01
34 #define VC5_RSVD_ADC_GAIN_7_0 0x02
35 #define VC5_RSVD_ADC_GAIN_15_8 0x03
36 #define VC5_RSVD_ADC_OFFSET_7_0 0x04
37 #define VC5_RSVD_ADC_OFFSET_15_8 0x05
38 #define VC5_RSVD_TEMPY 0x06
39 #define VC5_RSVD_OFFSET_TBIN 0x07
40 #define VC5_RSVD_GAIN 0x08
41 #define VC5_RSVD_TEST_NP 0x09
42 #define VC5_RSVD_UNUSED 0x0a
43 #define VC5_RSVD_BANDGAP_TRIM_UP 0x0b
44 #define VC5_RSVD_BANDGAP_TRIM_DN 0x0c
45 #define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d
46 #define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e
47 #define VC5_RSVD_CLK_AMP_123 0x0f
49 /* Configuration register block */
50 #define VC5_PRIM_SRC_SHDN 0x10
51 #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7)
52 #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6)
53 #define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3)
54 #define VC5_PRIM_SRC_SHDN_SP BIT(1)
55 #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0)
57 #define VC5_VCO_BAND 0x11
58 #define VC5_XTAL_X1_LOAD_CAP 0x12
59 #define VC5_XTAL_X2_LOAD_CAP 0x13
60 #define VC5_REF_DIVIDER 0x15
61 #define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7)
62 #define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f)
64 #define VC5_VCO_CTRL_AND_PREDIV 0x16
65 #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7)
67 #define VC5_FEEDBACK_INT_DIV 0x17
68 #define VC5_FEEDBACK_INT_DIV_BITS 0x18
69 #define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n))
70 #define VC5_RC_CONTROL0 0x1e
71 #define VC5_RC_CONTROL1 0x1f
72 /* Register 0x20 is factory reserved */
74 /* Output divider control for divider 1,2,3,4 */
75 #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10))
76 #define VC5_OUT_DIV_CONTROL_RESET BIT(7)
77 #define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3)
78 #define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2)
79 #define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1)
80 #define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0)
82 #define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n))
83 #define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1)
85 #define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n))
86 #define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n))
87 #define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n))
88 #define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n))
89 #define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10))
90 /* Registers 0x30, 0x40, 0x50 are factory reserved */
92 /* Clock control register for clock 1,2 */
93 #define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n))
94 #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5
95 #define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT)
97 #define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL (VC5_LVPECL)
98 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS)
99 #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33 (VC5_HCSL33)
100 #define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS)
101 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2)
102 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD)
103 #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25 (VC5_HCSL25)
105 #define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3
106 #define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
107 #define VC5_CLK_OUTPUT_CFG0_PWR_18 (0<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
108 #define VC5_CLK_OUTPUT_CFG0_PWR_25 (2<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
109 #define VC5_CLK_OUTPUT_CFG0_PWR_33 (3<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
110 #define VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT 0
111 #define VC5_CLK_OUTPUT_CFG0_SLEW_MASK GENMASK(1, VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
112 #define VC5_CLK_OUTPUT_CFG0_SLEW_80 (0<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
113 #define VC5_CLK_OUTPUT_CFG0_SLEW_85 (1<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
114 #define VC5_CLK_OUTPUT_CFG0_SLEW_90 (2<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
115 #define VC5_CLK_OUTPUT_CFG0_SLEW_100 (3<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
116 #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0)
118 #define VC5_CLK_OE_SHDN 0x68
119 #define VC5_CLK_OS_SHDN 0x69
121 #define VC5_GLOBAL_REGISTER 0x76
122 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
124 /* PLL/VCO runs between 2.5 GHz and 3.0 GHz */
125 #define VC5_PLL_VCO_MIN 2500000000UL
126 #define VC5_PLL_VCO_MAX 3000000000UL
128 /* VC5 Input mux settings */
129 #define VC5_MUX_IN_XIN BIT(0)
130 #define VC5_MUX_IN_CLKIN BIT(1)
132 /* Maximum number of clk_out supported by this driver */
133 #define VC5_MAX_CLK_OUT_NUM 5
135 /* Maximum number of FODs supported by this driver */
136 #define VC5_MAX_FOD_NUM 4
138 /* flags to describe chip features */
139 /* chip has built-in oscilator */
140 #define VC5_HAS_INTERNAL_XTAL BIT(0)
141 /* chip has PFD requency doubler */
142 #define VC5_HAS_PFD_FREQ_DBL BIT(1)
144 /* Supported IDT VC5 models. */
154 /* Structure to describe features of a particular VC5 model */
155 struct vc5_chip_info {
156 const enum vc5_model model;
157 const unsigned int clk_fod_cnt;
158 const unsigned int clk_out_cnt;
162 struct vc5_driver_data;
166 struct vc5_driver_data *vc5;
172 struct vc5_out_data {
174 struct vc5_driver_data *vc5;
176 unsigned int clk_output_cfg0;
177 unsigned int clk_output_cfg0_mask;
180 struct vc5_driver_data {
181 struct i2c_client *client;
182 struct regmap *regmap;
183 const struct vc5_chip_info *chip_info;
186 struct clk *pin_clkin;
187 unsigned char clk_mux_ins;
188 struct clk_hw clk_mux;
189 struct clk_hw clk_mul;
190 struct clk_hw clk_pfd;
191 struct vc5_hw_data clk_pll;
192 struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM];
193 struct vc5_out_data clk_out[VC5_MAX_CLK_OUT_NUM];
197 * VersaClock5 i2c regmap
199 static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg)
201 /* Factory reserved regs, make them read-only */
205 /* Factory reserved regs, make them read-only */
206 if (reg == 0x14 || reg == 0x1c || reg == 0x1d)
212 static const struct regmap_config vc5_regmap_config = {
215 .cache_type = REGCACHE_RBTREE,
216 .max_register = 0x76,
217 .writeable_reg = vc5_regmap_is_writeable,
221 * VersaClock5 input multiplexer between XTAL and CLKIN divider
223 static unsigned char vc5_mux_get_parent(struct clk_hw *hw)
225 struct vc5_driver_data *vc5 =
226 container_of(hw, struct vc5_driver_data, clk_mux);
227 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
230 regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src);
233 if (src == VC5_PRIM_SRC_SHDN_EN_XTAL)
236 if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN)
239 dev_warn(&vc5->client->dev,
240 "Invalid clock input configuration (%02x)\n", src);
244 static int vc5_mux_set_parent(struct clk_hw *hw, u8 index)
246 struct vc5_driver_data *vc5 =
247 container_of(hw, struct vc5_driver_data, clk_mux);
248 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
251 if ((index > 1) || !vc5->clk_mux_ins)
254 if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) {
256 src = VC5_PRIM_SRC_SHDN_EN_XTAL;
258 src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
263 if (vc5->clk_mux_ins == VC5_MUX_IN_XIN)
264 src = VC5_PRIM_SRC_SHDN_EN_XTAL;
265 else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN)
266 src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
267 else /* Invalid; should have been caught by vc5_probe() */
271 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src);
274 static const struct clk_ops vc5_mux_ops = {
275 .set_parent = vc5_mux_set_parent,
276 .get_parent = vc5_mux_get_parent,
279 static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw,
280 unsigned long parent_rate)
282 struct vc5_driver_data *vc5 =
283 container_of(hw, struct vc5_driver_data, clk_mul);
286 regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul);
287 if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ)
293 static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
294 unsigned long *parent_rate)
296 if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))
302 static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
303 unsigned long parent_rate)
305 struct vc5_driver_data *vc5 =
306 container_of(hw, struct vc5_driver_data, clk_mul);
309 if ((parent_rate * 2) == rate)
310 mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ;
314 regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN,
315 VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ,
321 static const struct clk_ops vc5_dbl_ops = {
322 .recalc_rate = vc5_dbl_recalc_rate,
323 .round_rate = vc5_dbl_round_rate,
324 .set_rate = vc5_dbl_set_rate,
327 static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw,
328 unsigned long parent_rate)
330 struct vc5_driver_data *vc5 =
331 container_of(hw, struct vc5_driver_data, clk_pfd);
332 unsigned int prediv, div;
334 regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
336 /* The bypass_prediv is set, PLL fed from Ref_in directly. */
337 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV)
340 regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div);
342 /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */
343 if (div & VC5_REF_DIVIDER_SEL_PREDIV2)
344 return parent_rate / 2;
346 return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);
349 static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
350 unsigned long *parent_rate)
354 /* PLL cannot operate with input clock above 50 MHz. */
358 /* CLKIN within range of PLL input, feed directly to PLL. */
359 if (*parent_rate <= 50000000)
362 idiv = DIV_ROUND_UP(*parent_rate, rate);
366 return *parent_rate / idiv;
369 static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
370 unsigned long parent_rate)
372 struct vc5_driver_data *vc5 =
373 container_of(hw, struct vc5_driver_data, clk_pfd);
377 /* CLKIN within range of PLL input, feed directly to PLL. */
378 if (parent_rate <= 50000000) {
379 regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
380 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV,
381 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
382 regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00);
386 idiv = DIV_ROUND_UP(parent_rate, rate);
388 /* We have dedicated div-2 predivider. */
390 div = VC5_REF_DIVIDER_SEL_PREDIV2;
392 div = VC5_REF_DIVIDER_REF_DIV(idiv);
394 regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div);
395 regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
396 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV, 0);
401 static const struct clk_ops vc5_pfd_ops = {
402 .recalc_rate = vc5_pfd_recalc_rate,
403 .round_rate = vc5_pfd_round_rate,
404 .set_rate = vc5_pfd_set_rate,
408 * VersaClock5 PLL/VCO
410 static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw,
411 unsigned long parent_rate)
413 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
414 struct vc5_driver_data *vc5 = hwdata->vc5;
415 u32 div_int, div_frc;
418 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
420 div_int = (fb[0] << 4) | (fb[1] >> 4);
421 div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4];
423 /* The PLL divider has 12 integer bits and 24 fractional bits */
424 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);
427 static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
428 unsigned long *parent_rate)
430 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
434 if (rate < VC5_PLL_VCO_MIN)
435 rate = VC5_PLL_VCO_MIN;
436 if (rate > VC5_PLL_VCO_MAX)
437 rate = VC5_PLL_VCO_MAX;
439 /* Determine integer part, which is 12 bit wide */
440 div_int = rate / *parent_rate;
442 rate = *parent_rate * 0xfff;
444 /* Determine best fractional part, which is 24 bit wide */
445 div_frc = rate % *parent_rate;
446 div_frc *= BIT(24) - 1;
447 do_div(div_frc, *parent_rate);
449 hwdata->div_int = div_int;
450 hwdata->div_frc = (u32)div_frc;
452 return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24);
455 static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate,
456 unsigned long parent_rate)
458 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
459 struct vc5_driver_data *vc5 = hwdata->vc5;
462 fb[0] = hwdata->div_int >> 4;
463 fb[1] = hwdata->div_int << 4;
464 fb[2] = hwdata->div_frc >> 16;
465 fb[3] = hwdata->div_frc >> 8;
466 fb[4] = hwdata->div_frc;
468 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
471 static const struct clk_ops vc5_pll_ops = {
472 .recalc_rate = vc5_pll_recalc_rate,
473 .round_rate = vc5_pll_round_rate,
474 .set_rate = vc5_pll_set_rate,
477 static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw,
478 unsigned long parent_rate)
480 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
481 struct vc5_driver_data *vc5 = hwdata->vc5;
482 /* VCO frequency is divided by two before entering FOD */
483 u32 f_in = parent_rate / 2;
484 u32 div_int, div_frc;
488 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0),
490 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
493 div_int = (od_int[0] << 4) | (od_int[1] >> 4);
494 div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) |
495 (od_frc[2] << 6) | (od_frc[3] >> 2);
497 /* Avoid division by zero if the output is not configured. */
498 if (div_int == 0 && div_frc == 0)
501 /* The PLL divider has 12 integer bits and 30 fractional bits */
502 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
505 static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate,
506 unsigned long *parent_rate)
508 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
509 /* VCO frequency is divided by two before entering FOD */
510 u32 f_in = *parent_rate / 2;
514 /* Determine integer part, which is 12 bit wide */
515 div_int = f_in / rate;
517 * WARNING: The clock chip does not output signal if the integer part
518 * of the divider is 0xfff and fractional part is non-zero.
519 * Clamp the divider at 0xffe to keep the code simple.
521 if (div_int > 0xffe) {
523 rate = f_in / div_int;
526 /* Determine best fractional part, which is 30 bit wide */
527 div_frc = f_in % rate;
529 do_div(div_frc, rate);
531 hwdata->div_int = div_int;
532 hwdata->div_frc = (u32)div_frc;
534 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
537 static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate,
538 unsigned long parent_rate)
540 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
541 struct vc5_driver_data *vc5 = hwdata->vc5;
543 hwdata->div_frc >> 22, hwdata->div_frc >> 14,
544 hwdata->div_frc >> 6, hwdata->div_frc << 2,
547 hwdata->div_int >> 4, hwdata->div_int << 4,
551 regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
555 * Toggle magic bit in undocumented register for unknown reason.
556 * This is what the IDT timing commander tool does and the chip
557 * datasheet somewhat implies this is needed, but the register
558 * and the bit is not documented.
560 regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
561 VC5_GLOBAL_REGISTER_GLOBAL_RESET, 0);
562 regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
563 VC5_GLOBAL_REGISTER_GLOBAL_RESET,
564 VC5_GLOBAL_REGISTER_GLOBAL_RESET);
568 static const struct clk_ops vc5_fod_ops = {
569 .recalc_rate = vc5_fod_recalc_rate,
570 .round_rate = vc5_fod_round_rate,
571 .set_rate = vc5_fod_set_rate,
574 static int vc5_clk_out_prepare(struct clk_hw *hw)
576 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
577 struct vc5_driver_data *vc5 = hwdata->vc5;
578 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
579 VC5_OUT_DIV_CONTROL_SEL_EXT |
580 VC5_OUT_DIV_CONTROL_EN_FOD;
585 * If the input mux is disabled, enable it first and
586 * select source from matching FOD.
588 regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
589 if ((src & mask) == 0) {
590 src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD;
591 ret = regmap_update_bits(vc5->regmap,
592 VC5_OUT_DIV_CONTROL(hwdata->num),
593 mask | VC5_OUT_DIV_CONTROL_RESET, src);
598 /* Enable the clock buffer */
599 regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
600 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF,
601 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
602 if (hwdata->clk_output_cfg0_mask) {
603 dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n",
604 hwdata->num, hwdata->clk_output_cfg0_mask,
605 hwdata->clk_output_cfg0);
607 regmap_update_bits(vc5->regmap,
608 VC5_CLK_OUTPUT_CFG(hwdata->num, 0),
609 hwdata->clk_output_cfg0_mask,
610 hwdata->clk_output_cfg0);
616 static void vc5_clk_out_unprepare(struct clk_hw *hw)
618 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
619 struct vc5_driver_data *vc5 = hwdata->vc5;
621 /* Disable the clock buffer */
622 regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
623 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 0);
626 static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
628 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
629 struct vc5_driver_data *vc5 = hwdata->vc5;
630 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
631 VC5_OUT_DIV_CONTROL_SEL_EXT |
632 VC5_OUT_DIV_CONTROL_EN_FOD;
633 const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM |
634 VC5_OUT_DIV_CONTROL_EN_FOD;
635 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
636 VC5_OUT_DIV_CONTROL_SEL_EXT;
639 regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
642 if (src == 0) /* Input mux set to DISABLED */
645 if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD)
651 dev_warn(&vc5->client->dev,
652 "Invalid clock output configuration (%02x)\n", src);
656 static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index)
658 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
659 struct vc5_driver_data *vc5 = hwdata->vc5;
660 const u8 mask = VC5_OUT_DIV_CONTROL_RESET |
661 VC5_OUT_DIV_CONTROL_SELB_NORM |
662 VC5_OUT_DIV_CONTROL_SEL_EXT |
663 VC5_OUT_DIV_CONTROL_EN_FOD;
664 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
665 VC5_OUT_DIV_CONTROL_SEL_EXT;
666 u8 src = VC5_OUT_DIV_CONTROL_RESET;
669 src |= VC5_OUT_DIV_CONTROL_EN_FOD;
673 return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num),
677 static const struct clk_ops vc5_clk_out_ops = {
678 .prepare = vc5_clk_out_prepare,
679 .unprepare = vc5_clk_out_unprepare,
680 .set_parent = vc5_clk_out_set_parent,
681 .get_parent = vc5_clk_out_get_parent,
684 static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec,
687 struct vc5_driver_data *vc5 = data;
688 unsigned int idx = clkspec->args[0];
690 if (idx >= vc5->chip_info->clk_out_cnt)
691 return ERR_PTR(-EINVAL);
693 return &vc5->clk_out[idx].hw;
696 static int vc5_map_index_to_output(const enum vc5_model model,
697 const unsigned int n)
700 case IDT_VC5_5P49V5933:
701 return (n == 0) ? 0 : 3;
702 case IDT_VC5_5P49V5923:
703 case IDT_VC5_5P49V5925:
704 case IDT_VC5_5P49V5935:
705 case IDT_VC6_5P49V6901:
706 case IDT_VC6_5P49V6965:
712 static int vc5_update_mode(struct device_node *np_output,
713 struct vc5_out_data *clk_out)
717 if (!of_property_read_u32(np_output, "idt,mode", &value)) {
718 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_CFG_MASK;
720 case VC5_CLK_OUTPUT_CFG0_CFG_LVPECL:
721 case VC5_CLK_OUTPUT_CFG0_CFG_CMOS:
722 case VC5_CLK_OUTPUT_CFG0_CFG_HCSL33:
723 case VC5_CLK_OUTPUT_CFG0_CFG_LVDS:
724 case VC5_CLK_OUTPUT_CFG0_CFG_CMOS2:
725 case VC5_CLK_OUTPUT_CFG0_CFG_CMOSD:
726 case VC5_CLK_OUTPUT_CFG0_CFG_HCSL25:
727 clk_out->clk_output_cfg0 |=
728 value << VC5_CLK_OUTPUT_CFG0_CFG_SHIFT;
737 static int vc5_update_power(struct device_node *np_output,
738 struct vc5_out_data *clk_out)
742 if (!of_property_read_u32(np_output, "idt,voltage-microvolt",
744 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_PWR_MASK;
747 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_18;
750 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_25;
753 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_33;
762 static int vc5_map_cap_value(u32 femtofarads)
767 * The datasheet explicitly states 9000 - 25000 with 0.5pF
768 * steps, but the Programmer's guide shows the steps are 0.430pF.
769 * After getting feedback from Renesas, the .5pF steps were the
770 * goal, but 430nF was the actual values.
771 * Because of this, the actual range goes to 22760 instead of 25000
773 if (femtofarads < 9000 || femtofarads > 22760)
777 * The Programmer's guide shows XTAL[5:0] but in reality,
778 * XTAL[0] and XTAL[1] are both LSB which makes the math
779 * strange. With clarfication from Renesas, setting the
780 * values should be simpler by ignoring XTAL[0]
782 mapped_value = DIV_ROUND_CLOSEST(femtofarads - 9000, 430);
785 * Since the calculation ignores XTAL[0], there is one
786 * special case where mapped_value = 32. In reality, this means
787 * the real mapped value should be 111111b. In other cases,
788 * the mapped_value needs to be shifted 1 to the left.
790 if (mapped_value > 31)
797 static int vc5_update_cap_load(struct device_node *node, struct vc5_driver_data *vc5)
802 if (!of_property_read_u32(node, "idt,xtal-load-femtofarads", &value)) {
803 mapped_value = vc5_map_cap_value(value);
804 if (mapped_value < 0)
808 * The mapped_value is really the high 6 bits of
809 * VC5_XTAL_X1_LOAD_CAP and VC5_XTAL_X2_LOAD_CAP, so
810 * shift the value 2 places.
812 regmap_update_bits(vc5->regmap, VC5_XTAL_X1_LOAD_CAP, ~0x03, mapped_value << 2);
813 regmap_update_bits(vc5->regmap, VC5_XTAL_X2_LOAD_CAP, ~0x03, mapped_value << 2);
819 static int vc5_update_slew(struct device_node *np_output,
820 struct vc5_out_data *clk_out)
824 if (!of_property_read_u32(np_output, "idt,slew-percent", &value)) {
825 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_SLEW_MASK;
828 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_80;
831 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_85;
834 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_90;
837 clk_out->clk_output_cfg0 |=
838 VC5_CLK_OUTPUT_CFG0_SLEW_100;
847 static int vc5_get_output_config(struct i2c_client *client,
848 struct vc5_out_data *clk_out)
850 struct device_node *np_output;
854 child_name = kasprintf(GFP_KERNEL, "OUT%d", clk_out->num + 1);
858 np_output = of_get_child_by_name(client->dev.of_node, child_name);
863 ret = vc5_update_mode(np_output, clk_out);
867 ret = vc5_update_power(np_output, clk_out);
871 ret = vc5_update_slew(np_output, clk_out);
875 dev_err(&client->dev,
876 "Invalid clock output configuration OUT%d\n",
880 of_node_put(np_output);
885 static const struct of_device_id clk_vc5_of_match[];
887 static int vc5_probe(struct i2c_client *client, const struct i2c_device_id *id)
889 struct vc5_driver_data *vc5;
890 struct clk_init_data init;
891 const char *parent_names[2];
892 unsigned int n, idx = 0;
895 vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
899 i2c_set_clientdata(client, vc5);
900 vc5->client = client;
901 vc5->chip_info = of_device_get_match_data(&client->dev);
903 vc5->pin_xin = devm_clk_get(&client->dev, "xin");
904 if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
905 return -EPROBE_DEFER;
907 vc5->pin_clkin = devm_clk_get(&client->dev, "clkin");
908 if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER)
909 return -EPROBE_DEFER;
911 vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config);
912 if (IS_ERR(vc5->regmap)) {
913 dev_err(&client->dev, "failed to allocate register map\n");
914 return PTR_ERR(vc5->regmap);
917 /* Register clock input mux */
918 memset(&init, 0, sizeof(init));
920 if (!IS_ERR(vc5->pin_xin)) {
921 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
922 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
923 } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) {
924 vc5->pin_xin = clk_register_fixed_rate(&client->dev,
925 "internal-xtal", NULL,
927 if (IS_ERR(vc5->pin_xin))
928 return PTR_ERR(vc5->pin_xin);
929 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
930 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
933 if (!IS_ERR(vc5->pin_clkin)) {
934 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN;
935 parent_names[init.num_parents++] =
936 __clk_get_name(vc5->pin_clkin);
939 if (!init.num_parents) {
940 dev_err(&client->dev, "no input clock specified!\n");
944 /* Configure Optional Loading Capacitance for external XTAL */
945 if (!(vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)) {
946 ret = vc5_update_cap_load(client->dev.of_node, vc5);
948 goto err_clk_register;
951 init.name = kasprintf(GFP_KERNEL, "%pOFn.mux", client->dev.of_node);
952 init.ops = &vc5_mux_ops;
954 init.parent_names = parent_names;
955 vc5->clk_mux.init = &init;
956 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux);
958 goto err_clk_register;
959 kfree(init.name); /* clock framework made a copy of the name */
961 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) {
962 /* Register frequency doubler */
963 memset(&init, 0, sizeof(init));
964 init.name = kasprintf(GFP_KERNEL, "%pOFn.dbl",
965 client->dev.of_node);
966 init.ops = &vc5_dbl_ops;
967 init.flags = CLK_SET_RATE_PARENT;
968 init.parent_names = parent_names;
969 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
970 init.num_parents = 1;
971 vc5->clk_mul.init = &init;
972 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul);
974 goto err_clk_register;
975 kfree(init.name); /* clock framework made a copy of the name */
979 memset(&init, 0, sizeof(init));
980 init.name = kasprintf(GFP_KERNEL, "%pOFn.pfd", client->dev.of_node);
981 init.ops = &vc5_pfd_ops;
982 init.flags = CLK_SET_RATE_PARENT;
983 init.parent_names = parent_names;
984 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL)
985 parent_names[0] = clk_hw_get_name(&vc5->clk_mul);
987 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
988 init.num_parents = 1;
989 vc5->clk_pfd.init = &init;
990 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd);
992 goto err_clk_register;
993 kfree(init.name); /* clock framework made a copy of the name */
996 memset(&init, 0, sizeof(init));
997 init.name = kasprintf(GFP_KERNEL, "%pOFn.pll", client->dev.of_node);
998 init.ops = &vc5_pll_ops;
999 init.flags = CLK_SET_RATE_PARENT;
1000 init.parent_names = parent_names;
1001 parent_names[0] = clk_hw_get_name(&vc5->clk_pfd);
1002 init.num_parents = 1;
1003 vc5->clk_pll.num = 0;
1004 vc5->clk_pll.vc5 = vc5;
1005 vc5->clk_pll.hw.init = &init;
1006 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw);
1008 goto err_clk_register;
1009 kfree(init.name); /* clock framework made a copy of the name */
1012 for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
1013 idx = vc5_map_index_to_output(vc5->chip_info->model, n);
1014 memset(&init, 0, sizeof(init));
1015 init.name = kasprintf(GFP_KERNEL, "%pOFn.fod%d",
1016 client->dev.of_node, idx);
1017 init.ops = &vc5_fod_ops;
1018 init.flags = CLK_SET_RATE_PARENT;
1019 init.parent_names = parent_names;
1020 parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw);
1021 init.num_parents = 1;
1022 vc5->clk_fod[n].num = idx;
1023 vc5->clk_fod[n].vc5 = vc5;
1024 vc5->clk_fod[n].hw.init = &init;
1025 ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw);
1027 goto err_clk_register;
1028 kfree(init.name); /* clock framework made a copy of the name */
1031 /* Register MUX-connected OUT0_I2C_SELB output */
1032 memset(&init, 0, sizeof(init));
1033 init.name = kasprintf(GFP_KERNEL, "%pOFn.out0_sel_i2cb",
1034 client->dev.of_node);
1035 init.ops = &vc5_clk_out_ops;
1036 init.flags = CLK_SET_RATE_PARENT;
1037 init.parent_names = parent_names;
1038 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
1039 init.num_parents = 1;
1040 vc5->clk_out[0].num = idx;
1041 vc5->clk_out[0].vc5 = vc5;
1042 vc5->clk_out[0].hw.init = &init;
1043 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw);
1045 goto err_clk_register;
1046 kfree(init.name); /* clock framework made a copy of the name */
1048 /* Register FOD-connected OUTx outputs */
1049 for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
1050 idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1);
1051 parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw);
1053 parent_names[1] = clk_hw_get_name(&vc5->clk_mux);
1056 clk_hw_get_name(&vc5->clk_out[n - 1].hw);
1058 memset(&init, 0, sizeof(init));
1059 init.name = kasprintf(GFP_KERNEL, "%pOFn.out%d",
1060 client->dev.of_node, idx + 1);
1061 init.ops = &vc5_clk_out_ops;
1062 init.flags = CLK_SET_RATE_PARENT;
1063 init.parent_names = parent_names;
1064 init.num_parents = 2;
1065 vc5->clk_out[n].num = idx;
1066 vc5->clk_out[n].vc5 = vc5;
1067 vc5->clk_out[n].hw.init = &init;
1068 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[n].hw);
1070 goto err_clk_register;
1071 kfree(init.name); /* clock framework made a copy of the name */
1073 /* Fetch Clock Output configuration from DT (if specified) */
1074 ret = vc5_get_output_config(client, &vc5->clk_out[n]);
1079 ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5);
1081 dev_err(&client->dev, "unable to add clk provider\n");
1088 dev_err(&client->dev, "unable to register %s\n", init.name);
1089 kfree(init.name); /* clock framework made a copy of the name */
1091 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
1092 clk_unregister_fixed_rate(vc5->pin_xin);
1096 static int vc5_remove(struct i2c_client *client)
1098 struct vc5_driver_data *vc5 = i2c_get_clientdata(client);
1100 of_clk_del_provider(client->dev.of_node);
1102 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
1103 clk_unregister_fixed_rate(vc5->pin_xin);
1108 static int __maybe_unused vc5_suspend(struct device *dev)
1110 struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
1112 regcache_cache_only(vc5->regmap, true);
1113 regcache_mark_dirty(vc5->regmap);
1118 static int __maybe_unused vc5_resume(struct device *dev)
1120 struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
1123 regcache_cache_only(vc5->regmap, false);
1124 ret = regcache_sync(vc5->regmap);
1126 dev_err(dev, "Failed to restore register map: %d\n", ret);
1130 static const struct vc5_chip_info idt_5p49v5923_info = {
1131 .model = IDT_VC5_5P49V5923,
1137 static const struct vc5_chip_info idt_5p49v5925_info = {
1138 .model = IDT_VC5_5P49V5925,
1144 static const struct vc5_chip_info idt_5p49v5933_info = {
1145 .model = IDT_VC5_5P49V5933,
1148 .flags = VC5_HAS_INTERNAL_XTAL,
1151 static const struct vc5_chip_info idt_5p49v5935_info = {
1152 .model = IDT_VC5_5P49V5935,
1155 .flags = VC5_HAS_INTERNAL_XTAL,
1158 static const struct vc5_chip_info idt_5p49v6901_info = {
1159 .model = IDT_VC6_5P49V6901,
1162 .flags = VC5_HAS_PFD_FREQ_DBL,
1165 static const struct vc5_chip_info idt_5p49v6965_info = {
1166 .model = IDT_VC6_5P49V6965,
1172 static const struct i2c_device_id vc5_id[] = {
1173 { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
1174 { "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
1175 { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
1176 { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
1177 { "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
1178 { "5p49v6965", .driver_data = IDT_VC6_5P49V6965 },
1181 MODULE_DEVICE_TABLE(i2c, vc5_id);
1183 static const struct of_device_id clk_vc5_of_match[] = {
1184 { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
1185 { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
1186 { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
1187 { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
1188 { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
1189 { .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info },
1192 MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
1194 static SIMPLE_DEV_PM_OPS(vc5_pm_ops, vc5_suspend, vc5_resume);
1196 static struct i2c_driver vc5_driver = {
1200 .of_match_table = clk_vc5_of_match,
1203 .remove = vc5_remove,
1206 module_i2c_driver(vc5_driver);
1208 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
1209 MODULE_DESCRIPTION("IDT VersaClock 5 driver");
1210 MODULE_LICENSE("GPL");