1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-si5351.c: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator
5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 * Rabeeh Khoury <rabeeh@solid-run.com>
9 * [1] "Si5351A/B/C Data Sheet"
10 * https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
11 * [2] "AN619: Manually Generating an Si5351 Register Map"
12 * https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/AN619.pdf
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
22 #include <linux/rational.h>
23 #include <linux/i2c.h>
25 #include <linux/platform_data/si5351.h>
26 #include <linux/regmap.h>
27 #include <linux/slab.h>
28 #include <linux/string.h>
29 #include <asm/div64.h>
31 #include "clk-si5351.h"
33 struct si5351_driver_data;
35 struct si5351_parameters {
42 struct si5351_hw_data {
44 struct si5351_driver_data *drvdata;
45 struct si5351_parameters params;
49 struct si5351_driver_data {
50 enum si5351_variant variant;
51 struct i2c_client *client;
52 struct regmap *regmap;
55 const char *pxtal_name;
58 const char *pclkin_name;
61 struct si5351_hw_data pll[2];
62 struct si5351_hw_data *msynth;
63 struct si5351_hw_data *clkout;
67 static const char * const si5351_input_names[] = {
70 static const char * const si5351_pll_names[] = {
71 "si5351_plla", "si5351_pllb", "si5351_vxco"
73 static const char * const si5351_msynth_names[] = {
74 "ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7"
76 static const char * const si5351_clkout_names[] = {
77 "clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7"
83 static inline u8 si5351_reg_read(struct si5351_driver_data *drvdata, u8 reg)
88 ret = regmap_read(drvdata->regmap, reg, &val);
90 dev_err(&drvdata->client->dev,
91 "unable to read from reg%02x\n", reg);
98 static inline int si5351_bulk_read(struct si5351_driver_data *drvdata,
99 u8 reg, u8 count, u8 *buf)
101 return regmap_bulk_read(drvdata->regmap, reg, buf, count);
104 static inline int si5351_reg_write(struct si5351_driver_data *drvdata,
107 return regmap_write(drvdata->regmap, reg, val);
110 static inline int si5351_bulk_write(struct si5351_driver_data *drvdata,
111 u8 reg, u8 count, const u8 *buf)
113 return regmap_raw_write(drvdata->regmap, reg, buf, count);
116 static inline int si5351_set_bits(struct si5351_driver_data *drvdata,
117 u8 reg, u8 mask, u8 val)
119 return regmap_update_bits(drvdata->regmap, reg, mask, val);
122 static inline u8 si5351_msynth_params_address(int num)
125 return SI5351_CLK6_PARAMETERS + (num - 6);
126 return SI5351_CLK0_PARAMETERS + (SI5351_PARAMETERS_LENGTH * num);
129 static void si5351_read_parameters(struct si5351_driver_data *drvdata,
130 u8 reg, struct si5351_parameters *params)
132 u8 buf[SI5351_PARAMETERS_LENGTH];
135 case SI5351_CLK6_PARAMETERS:
136 case SI5351_CLK7_PARAMETERS:
137 buf[0] = si5351_reg_read(drvdata, reg);
143 si5351_bulk_read(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
144 params->p1 = ((buf[2] & 0x03) << 16) | (buf[3] << 8) | buf[4];
145 params->p2 = ((buf[5] & 0x0f) << 16) | (buf[6] << 8) | buf[7];
146 params->p3 = ((buf[5] & 0xf0) << 12) | (buf[0] << 8) | buf[1];
151 static void si5351_write_parameters(struct si5351_driver_data *drvdata,
152 u8 reg, struct si5351_parameters *params)
154 u8 buf[SI5351_PARAMETERS_LENGTH];
157 case SI5351_CLK6_PARAMETERS:
158 case SI5351_CLK7_PARAMETERS:
159 buf[0] = params->p1 & 0xff;
160 si5351_reg_write(drvdata, reg, buf[0]);
163 buf[0] = ((params->p3 & 0x0ff00) >> 8) & 0xff;
164 buf[1] = params->p3 & 0xff;
165 /* save rdiv and divby4 */
166 buf[2] = si5351_reg_read(drvdata, reg + 2) & ~0x03;
167 buf[2] |= ((params->p1 & 0x30000) >> 16) & 0x03;
168 buf[3] = ((params->p1 & 0x0ff00) >> 8) & 0xff;
169 buf[4] = params->p1 & 0xff;
170 buf[5] = ((params->p3 & 0xf0000) >> 12) |
171 ((params->p2 & 0xf0000) >> 16);
172 buf[6] = ((params->p2 & 0x0ff00) >> 8) & 0xff;
173 buf[7] = params->p2 & 0xff;
174 si5351_bulk_write(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
178 static bool si5351_regmap_is_volatile(struct device *dev, unsigned int reg)
181 case SI5351_DEVICE_STATUS:
182 case SI5351_INTERRUPT_STATUS:
183 case SI5351_PLL_RESET:
189 static bool si5351_regmap_is_writeable(struct device *dev, unsigned int reg)
191 /* reserved registers */
192 if (reg >= 4 && reg <= 8)
194 if (reg >= 10 && reg <= 14)
196 if (reg >= 173 && reg <= 176)
198 if (reg >= 178 && reg <= 182)
201 if (reg == SI5351_DEVICE_STATUS)
206 static const struct regmap_config si5351_regmap_config = {
209 .cache_type = REGCACHE_MAPLE,
211 .writeable_reg = si5351_regmap_is_writeable,
212 .volatile_reg = si5351_regmap_is_volatile,
216 * Si5351 xtal clock input
218 static int si5351_xtal_prepare(struct clk_hw *hw)
220 struct si5351_driver_data *drvdata =
221 container_of(hw, struct si5351_driver_data, xtal);
222 si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
223 SI5351_XTAL_ENABLE, SI5351_XTAL_ENABLE);
227 static void si5351_xtal_unprepare(struct clk_hw *hw)
229 struct si5351_driver_data *drvdata =
230 container_of(hw, struct si5351_driver_data, xtal);
231 si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
232 SI5351_XTAL_ENABLE, 0);
235 static const struct clk_ops si5351_xtal_ops = {
236 .prepare = si5351_xtal_prepare,
237 .unprepare = si5351_xtal_unprepare,
241 * Si5351 clkin clock input (Si5351C only)
243 static int si5351_clkin_prepare(struct clk_hw *hw)
245 struct si5351_driver_data *drvdata =
246 container_of(hw, struct si5351_driver_data, clkin);
247 si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
248 SI5351_CLKIN_ENABLE, SI5351_CLKIN_ENABLE);
252 static void si5351_clkin_unprepare(struct clk_hw *hw)
254 struct si5351_driver_data *drvdata =
255 container_of(hw, struct si5351_driver_data, clkin);
256 si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
257 SI5351_CLKIN_ENABLE, 0);
261 * CMOS clock source constraints:
262 * The input frequency range of the PLL is 10Mhz to 40MHz.
263 * If CLKIN is >40MHz, the input divider must be used.
265 static unsigned long si5351_clkin_recalc_rate(struct clk_hw *hw,
266 unsigned long parent_rate)
268 struct si5351_driver_data *drvdata =
269 container_of(hw, struct si5351_driver_data, clkin);
274 if (parent_rate > 160000000) {
275 idiv = SI5351_CLKIN_DIV_8;
277 } else if (parent_rate > 80000000) {
278 idiv = SI5351_CLKIN_DIV_4;
280 } else if (parent_rate > 40000000) {
281 idiv = SI5351_CLKIN_DIV_2;
284 idiv = SI5351_CLKIN_DIV_1;
287 si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
288 SI5351_CLKIN_DIV_MASK, idiv);
290 dev_dbg(&drvdata->client->dev, "%s - clkin div = %d, rate = %lu\n",
291 __func__, (1 << (idiv >> 6)), rate);
296 static const struct clk_ops si5351_clkin_ops = {
297 .prepare = si5351_clkin_prepare,
298 .unprepare = si5351_clkin_unprepare,
299 .recalc_rate = si5351_clkin_recalc_rate,
303 * Si5351 vxco clock input (Si5351B only)
306 static int si5351_vxco_prepare(struct clk_hw *hw)
308 struct si5351_hw_data *hwdata =
309 container_of(hw, struct si5351_hw_data, hw);
311 dev_warn(&hwdata->drvdata->client->dev, "VXCO currently unsupported\n");
316 static void si5351_vxco_unprepare(struct clk_hw *hw)
320 static unsigned long si5351_vxco_recalc_rate(struct clk_hw *hw,
321 unsigned long parent_rate)
326 static int si5351_vxco_set_rate(struct clk_hw *hw, unsigned long rate,
327 unsigned long parent)
332 static const struct clk_ops si5351_vxco_ops = {
333 .prepare = si5351_vxco_prepare,
334 .unprepare = si5351_vxco_unprepare,
335 .recalc_rate = si5351_vxco_recalc_rate,
336 .set_rate = si5351_vxco_set_rate,
342 * Feedback Multisynth Divider Equations [2]
344 * fVCO = fIN * (a + b/c)
346 * with 15 + 0/1048575 <= (a + b/c) <= 90 + 0/1048575 and
347 * fIN = fXTAL or fIN = fCLKIN/CLKIN_DIV
349 * Feedback Multisynth Register Equations
351 * (1) MSNx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
352 * (2) MSNx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
353 * (3) MSNx_P3[19:0] = c
355 * Transposing (2) yields: (4) floor(128 * b/c) = (128 * b / MSNx_P2)/c
357 * Using (4) on (1) yields:
358 * MSNx_P1 = 128 * a + (128 * b/MSNx_P2)/c - 512
359 * MSNx_P1 + 512 + MSNx_P2/c = 128 * a + 128 * b/c
361 * a + b/c = (MSNx_P1 + MSNx_P2/MSNx_P3 + 512)/128
362 * = (MSNx_P1*MSNx_P3 + MSNx_P2 + 512*MSNx_P3)/(128*MSNx_P3)
365 static int _si5351_pll_reparent(struct si5351_driver_data *drvdata,
366 int num, enum si5351_pll_src parent)
368 u8 mask = (num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
370 if (parent == SI5351_PLL_SRC_DEFAULT)
376 if (drvdata->variant != SI5351_VARIANT_C &&
377 parent != SI5351_PLL_SRC_XTAL)
380 si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, mask,
381 (parent == SI5351_PLL_SRC_XTAL) ? 0 : mask);
385 static unsigned char si5351_pll_get_parent(struct clk_hw *hw)
387 struct si5351_hw_data *hwdata =
388 container_of(hw, struct si5351_hw_data, hw);
389 u8 mask = (hwdata->num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
392 val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE);
394 return (val & mask) ? 1 : 0;
397 static int si5351_pll_set_parent(struct clk_hw *hw, u8 index)
399 struct si5351_hw_data *hwdata =
400 container_of(hw, struct si5351_hw_data, hw);
402 if (hwdata->drvdata->variant != SI5351_VARIANT_C &&
409 return _si5351_pll_reparent(hwdata->drvdata, hwdata->num,
410 (index == 0) ? SI5351_PLL_SRC_XTAL :
411 SI5351_PLL_SRC_CLKIN);
414 static unsigned long si5351_pll_recalc_rate(struct clk_hw *hw,
415 unsigned long parent_rate)
417 struct si5351_hw_data *hwdata =
418 container_of(hw, struct si5351_hw_data, hw);
419 u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
420 SI5351_PLLB_PARAMETERS;
421 unsigned long long rate;
423 if (!hwdata->params.valid)
424 si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
426 if (hwdata->params.p3 == 0)
429 /* fVCO = fIN * (P1*P3 + 512*P3 + P2)/(128*P3) */
430 rate = hwdata->params.p1 * hwdata->params.p3;
431 rate += 512 * hwdata->params.p3;
432 rate += hwdata->params.p2;
434 do_div(rate, 128 * hwdata->params.p3);
436 dev_dbg(&hwdata->drvdata->client->dev,
437 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
438 __func__, clk_hw_get_name(hw),
439 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
440 parent_rate, (unsigned long)rate);
442 return (unsigned long)rate;
445 static int si5351_pll_determine_rate(struct clk_hw *hw,
446 struct clk_rate_request *req)
448 struct si5351_hw_data *hwdata =
449 container_of(hw, struct si5351_hw_data, hw);
450 unsigned long rate = req->rate;
451 unsigned long rfrac, denom, a, b, c;
452 unsigned long long lltmp;
454 if (rate < SI5351_PLL_VCO_MIN)
455 rate = SI5351_PLL_VCO_MIN;
456 if (rate > SI5351_PLL_VCO_MAX)
457 rate = SI5351_PLL_VCO_MAX;
459 /* determine integer part of feedback equation */
460 a = rate / req->best_parent_rate;
462 if (a < SI5351_PLL_A_MIN)
463 rate = req->best_parent_rate * SI5351_PLL_A_MIN;
464 if (a > SI5351_PLL_A_MAX)
465 rate = req->best_parent_rate * SI5351_PLL_A_MAX;
467 /* find best approximation for b/c = fVCO mod fIN */
469 lltmp = rate % (req->best_parent_rate);
471 do_div(lltmp, req->best_parent_rate);
472 rfrac = (unsigned long)lltmp;
477 rational_best_approximation(rfrac, denom,
478 SI5351_PLL_B_MAX, SI5351_PLL_C_MAX, &b, &c);
480 /* calculate parameters */
481 hwdata->params.p3 = c;
482 hwdata->params.p2 = (128 * b) % c;
483 hwdata->params.p1 = 128 * a;
484 hwdata->params.p1 += (128 * b / c);
485 hwdata->params.p1 -= 512;
487 /* recalculate rate by fIN * (a + b/c) */
488 lltmp = req->best_parent_rate;
492 rate = (unsigned long)lltmp;
493 rate += req->best_parent_rate * a;
495 dev_dbg(&hwdata->drvdata->client->dev,
496 "%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n",
497 __func__, clk_hw_get_name(hw), a, b, c,
498 req->best_parent_rate, rate);
504 static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate,
505 unsigned long parent_rate)
507 struct si5351_hw_data *hwdata =
508 container_of(hw, struct si5351_hw_data, hw);
509 u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
510 SI5351_PLLB_PARAMETERS;
512 /* write multisynth parameters */
513 si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
515 /* plla/pllb ctrl is in clk6/clk7 ctrl registers */
516 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_CTRL + hwdata->num,
517 SI5351_CLK_INTEGER_MODE,
518 (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
520 /* Do a pll soft reset on the affected pll */
521 si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
522 hwdata->num == 0 ? SI5351_PLL_RESET_A :
525 dev_dbg(&hwdata->drvdata->client->dev,
526 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
527 __func__, clk_hw_get_name(hw),
528 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
534 static const struct clk_ops si5351_pll_ops = {
535 .set_parent = si5351_pll_set_parent,
536 .get_parent = si5351_pll_get_parent,
537 .recalc_rate = si5351_pll_recalc_rate,
538 .determine_rate = si5351_pll_determine_rate,
539 .set_rate = si5351_pll_set_rate,
543 * Si5351 multisync divider
545 * for fOUT <= 150 MHz:
547 * fOUT = (fIN * (a + b/c)) / CLKOUTDIV
549 * with 6 + 0/1048575 <= (a + b/c) <= 1800 + 0/1048575 and
552 * Output Clock Multisynth Register Equations
554 * MSx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
555 * MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
558 * MS[6,7] are integer (P1) divide only, P1 = divide value,
559 * P2 and P3 are not applicable
561 * for 150MHz < fOUT <= 160MHz:
563 * MSx_P1 = 0, MSx_P2 = 0, MSx_P3 = 1, MSx_INT = 1, MSx_DIVBY4 = 11b
565 static int _si5351_msynth_reparent(struct si5351_driver_data *drvdata,
566 int num, enum si5351_multisynth_src parent)
568 if (parent == SI5351_MULTISYNTH_SRC_DEFAULT)
574 si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, SI5351_CLK_PLL_SELECT,
575 (parent == SI5351_MULTISYNTH_SRC_VCO0) ? 0 :
576 SI5351_CLK_PLL_SELECT);
580 static unsigned char si5351_msynth_get_parent(struct clk_hw *hw)
582 struct si5351_hw_data *hwdata =
583 container_of(hw, struct si5351_hw_data, hw);
586 val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
588 return (val & SI5351_CLK_PLL_SELECT) ? 1 : 0;
591 static int si5351_msynth_set_parent(struct clk_hw *hw, u8 index)
593 struct si5351_hw_data *hwdata =
594 container_of(hw, struct si5351_hw_data, hw);
596 return _si5351_msynth_reparent(hwdata->drvdata, hwdata->num,
597 (index == 0) ? SI5351_MULTISYNTH_SRC_VCO0 :
598 SI5351_MULTISYNTH_SRC_VCO1);
601 static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw,
602 unsigned long parent_rate)
604 struct si5351_hw_data *hwdata =
605 container_of(hw, struct si5351_hw_data, hw);
606 u8 reg = si5351_msynth_params_address(hwdata->num);
607 unsigned long long rate;
610 if (!hwdata->params.valid)
611 si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
614 * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3)
615 * multisync6-7: fOUT = fIN / P1
618 if (hwdata->num > 5) {
619 m = hwdata->params.p1;
620 } else if (hwdata->params.p3 == 0) {
622 } else if ((si5351_reg_read(hwdata->drvdata, reg + 2) &
623 SI5351_OUTPUT_CLK_DIVBY4) == SI5351_OUTPUT_CLK_DIVBY4) {
626 rate *= 128 * hwdata->params.p3;
627 m = hwdata->params.p1 * hwdata->params.p3;
628 m += hwdata->params.p2;
629 m += 512 * hwdata->params.p3;
636 dev_dbg(&hwdata->drvdata->client->dev,
637 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n",
638 __func__, clk_hw_get_name(hw),
639 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
640 m, parent_rate, (unsigned long)rate);
642 return (unsigned long)rate;
645 static int si5351_msynth_determine_rate(struct clk_hw *hw,
646 struct clk_rate_request *req)
648 struct si5351_hw_data *hwdata =
649 container_of(hw, struct si5351_hw_data, hw);
650 unsigned long rate = req->rate;
651 unsigned long long lltmp;
652 unsigned long a, b, c;
655 /* multisync6-7 can only handle freqencies < 150MHz */
656 if (hwdata->num >= 6 && rate > SI5351_MULTISYNTH67_MAX_FREQ)
657 rate = SI5351_MULTISYNTH67_MAX_FREQ;
659 /* multisync frequency is 1MHz .. 160MHz */
660 if (rate > SI5351_MULTISYNTH_MAX_FREQ)
661 rate = SI5351_MULTISYNTH_MAX_FREQ;
662 if (rate < SI5351_MULTISYNTH_MIN_FREQ)
663 rate = SI5351_MULTISYNTH_MIN_FREQ;
666 if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
669 /* multisync can set pll */
670 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
672 * find largest integer divider for max
673 * vco frequency and given target rate
676 lltmp = SI5351_PLL_VCO_MAX;
678 a = (unsigned long)lltmp;
685 req->best_parent_rate = a * rate;
686 } else if (hwdata->num >= 6) {
687 /* determine the closest integer divider */
688 a = DIV_ROUND_CLOSEST(req->best_parent_rate, rate);
689 if (a < SI5351_MULTISYNTH_A_MIN)
690 a = SI5351_MULTISYNTH_A_MIN;
691 if (a > SI5351_MULTISYNTH67_A_MAX)
692 a = SI5351_MULTISYNTH67_A_MAX;
697 unsigned long rfrac, denom;
701 rate = SI5351_MULTISYNTH_DIVBY4_FREQ;
705 /* determine integer part of divider equation */
706 a = req->best_parent_rate / rate;
707 if (a < SI5351_MULTISYNTH_A_MIN)
708 a = SI5351_MULTISYNTH_A_MIN;
709 if (a > SI5351_MULTISYNTH_A_MAX)
710 a = SI5351_MULTISYNTH_A_MAX;
712 /* find best approximation for b/c = fVCO mod fOUT */
714 lltmp = req->best_parent_rate % rate;
717 rfrac = (unsigned long)lltmp;
722 rational_best_approximation(rfrac, denom,
723 SI5351_MULTISYNTH_B_MAX, SI5351_MULTISYNTH_C_MAX,
727 /* recalculate rate by fOUT = fIN / (a + b/c) */
728 lltmp = req->best_parent_rate;
730 do_div(lltmp, a * c + b);
731 rate = (unsigned long)lltmp;
733 /* calculate parameters */
735 hwdata->params.p3 = 1;
736 hwdata->params.p2 = 0;
737 hwdata->params.p1 = 0;
738 } else if (hwdata->num >= 6) {
739 hwdata->params.p3 = 0;
740 hwdata->params.p2 = 0;
741 hwdata->params.p1 = a;
743 hwdata->params.p3 = c;
744 hwdata->params.p2 = (128 * b) % c;
745 hwdata->params.p1 = 128 * a;
746 hwdata->params.p1 += (128 * b / c);
747 hwdata->params.p1 -= 512;
750 dev_dbg(&hwdata->drvdata->client->dev,
751 "%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
752 __func__, clk_hw_get_name(hw), a, b, c, divby4,
753 req->best_parent_rate, rate);
760 static int si5351_msynth_set_rate(struct clk_hw *hw, unsigned long rate,
761 unsigned long parent_rate)
763 struct si5351_hw_data *hwdata =
764 container_of(hw, struct si5351_hw_data, hw);
765 u8 reg = si5351_msynth_params_address(hwdata->num);
768 /* write multisynth parameters */
769 si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
771 if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
774 /* enable/disable integer mode and divby4 on multisynth0-5 */
775 if (hwdata->num < 6) {
776 si5351_set_bits(hwdata->drvdata, reg + 2,
777 SI5351_OUTPUT_CLK_DIVBY4,
778 (divby4) ? SI5351_OUTPUT_CLK_DIVBY4 : 0);
779 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
780 SI5351_CLK_INTEGER_MODE,
781 (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
784 dev_dbg(&hwdata->drvdata->client->dev,
785 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
786 __func__, clk_hw_get_name(hw),
787 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
788 divby4, parent_rate, rate);
793 static const struct clk_ops si5351_msynth_ops = {
794 .set_parent = si5351_msynth_set_parent,
795 .get_parent = si5351_msynth_get_parent,
796 .recalc_rate = si5351_msynth_recalc_rate,
797 .determine_rate = si5351_msynth_determine_rate,
798 .set_rate = si5351_msynth_set_rate,
802 * Si5351 clkout divider
804 static int _si5351_clkout_reparent(struct si5351_driver_data *drvdata,
805 int num, enum si5351_clkout_src parent)
813 case SI5351_CLKOUT_SRC_MSYNTH_N:
814 val = SI5351_CLK_INPUT_MULTISYNTH_N;
816 case SI5351_CLKOUT_SRC_MSYNTH_0_4:
817 /* clk0/clk4 can only connect to its own multisync */
818 if (num == 0 || num == 4)
819 val = SI5351_CLK_INPUT_MULTISYNTH_N;
821 val = SI5351_CLK_INPUT_MULTISYNTH_0_4;
823 case SI5351_CLKOUT_SRC_XTAL:
824 val = SI5351_CLK_INPUT_XTAL;
826 case SI5351_CLKOUT_SRC_CLKIN:
827 if (drvdata->variant != SI5351_VARIANT_C)
830 val = SI5351_CLK_INPUT_CLKIN;
836 si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
837 SI5351_CLK_INPUT_MASK, val);
841 static int _si5351_clkout_set_drive_strength(
842 struct si5351_driver_data *drvdata, int num,
843 enum si5351_drive_strength drive)
851 case SI5351_DRIVE_2MA:
852 mask = SI5351_CLK_DRIVE_STRENGTH_2MA;
854 case SI5351_DRIVE_4MA:
855 mask = SI5351_CLK_DRIVE_STRENGTH_4MA;
857 case SI5351_DRIVE_6MA:
858 mask = SI5351_CLK_DRIVE_STRENGTH_6MA;
860 case SI5351_DRIVE_8MA:
861 mask = SI5351_CLK_DRIVE_STRENGTH_8MA;
867 si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
868 SI5351_CLK_DRIVE_STRENGTH_MASK, mask);
872 static int _si5351_clkout_set_disable_state(
873 struct si5351_driver_data *drvdata, int num,
874 enum si5351_disable_state state)
876 u8 reg = (num < 4) ? SI5351_CLK3_0_DISABLE_STATE :
877 SI5351_CLK7_4_DISABLE_STATE;
878 u8 shift = (num < 4) ? (2 * num) : (2 * (num-4));
879 u8 mask = SI5351_CLK_DISABLE_STATE_MASK << shift;
886 case SI5351_DISABLE_LOW:
887 val = SI5351_CLK_DISABLE_STATE_LOW;
889 case SI5351_DISABLE_HIGH:
890 val = SI5351_CLK_DISABLE_STATE_HIGH;
892 case SI5351_DISABLE_FLOATING:
893 val = SI5351_CLK_DISABLE_STATE_FLOAT;
895 case SI5351_DISABLE_NEVER:
896 val = SI5351_CLK_DISABLE_STATE_NEVER;
902 si5351_set_bits(drvdata, reg, mask, val << shift);
907 static void _si5351_clkout_reset_pll(struct si5351_driver_data *drvdata, int num)
909 u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num);
910 u8 mask = val & SI5351_CLK_PLL_SELECT ? SI5351_PLL_RESET_B :
915 switch (val & SI5351_CLK_INPUT_MASK) {
916 case SI5351_CLK_INPUT_XTAL:
917 case SI5351_CLK_INPUT_CLKIN:
918 return; /* pll not used, no need to reset */
921 si5351_reg_write(drvdata, SI5351_PLL_RESET, mask);
923 err = regmap_read_poll_timeout(drvdata->regmap, SI5351_PLL_RESET, v,
924 !(v & mask), 0, 20000);
926 dev_err(&drvdata->client->dev, "Reset bit didn't clear\n");
928 dev_dbg(&drvdata->client->dev, "%s - %s: pll = %d\n",
929 __func__, clk_hw_get_name(&drvdata->clkout[num].hw),
930 (val & SI5351_CLK_PLL_SELECT) ? 1 : 0);
933 static int si5351_clkout_prepare(struct clk_hw *hw)
935 struct si5351_hw_data *hwdata =
936 container_of(hw, struct si5351_hw_data, hw);
937 struct si5351_platform_data *pdata =
938 hwdata->drvdata->client->dev.platform_data;
940 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
941 SI5351_CLK_POWERDOWN, 0);
944 * Do a pll soft reset on the parent pll -- needed to get a
945 * deterministic phase relationship between the output clocks.
947 if (pdata->clkout[hwdata->num].pll_reset)
948 _si5351_clkout_reset_pll(hwdata->drvdata, hwdata->num);
950 si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
951 (1 << hwdata->num), 0);
955 static void si5351_clkout_unprepare(struct clk_hw *hw)
957 struct si5351_hw_data *hwdata =
958 container_of(hw, struct si5351_hw_data, hw);
960 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
961 SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN);
962 si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
963 (1 << hwdata->num), (1 << hwdata->num));
966 static u8 si5351_clkout_get_parent(struct clk_hw *hw)
968 struct si5351_hw_data *hwdata =
969 container_of(hw, struct si5351_hw_data, hw);
973 val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
974 switch (val & SI5351_CLK_INPUT_MASK) {
975 case SI5351_CLK_INPUT_MULTISYNTH_N:
978 case SI5351_CLK_INPUT_MULTISYNTH_0_4:
981 case SI5351_CLK_INPUT_XTAL:
984 case SI5351_CLK_INPUT_CLKIN:
992 static int si5351_clkout_set_parent(struct clk_hw *hw, u8 index)
994 struct si5351_hw_data *hwdata =
995 container_of(hw, struct si5351_hw_data, hw);
996 enum si5351_clkout_src parent = SI5351_CLKOUT_SRC_DEFAULT;
1000 parent = SI5351_CLKOUT_SRC_MSYNTH_N;
1003 parent = SI5351_CLKOUT_SRC_MSYNTH_0_4;
1006 parent = SI5351_CLKOUT_SRC_XTAL;
1009 parent = SI5351_CLKOUT_SRC_CLKIN;
1013 return _si5351_clkout_reparent(hwdata->drvdata, hwdata->num, parent);
1016 static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
1017 unsigned long parent_rate)
1019 struct si5351_hw_data *hwdata =
1020 container_of(hw, struct si5351_hw_data, hw);
1024 if (hwdata->num <= 5)
1025 reg = si5351_msynth_params_address(hwdata->num) + 2;
1027 reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
1029 rdiv = si5351_reg_read(hwdata->drvdata, reg);
1030 if (hwdata->num == 6) {
1031 rdiv &= SI5351_OUTPUT_CLK6_DIV_MASK;
1033 rdiv &= SI5351_OUTPUT_CLK_DIV_MASK;
1034 rdiv >>= SI5351_OUTPUT_CLK_DIV_SHIFT;
1037 return parent_rate >> rdiv;
1040 static int si5351_clkout_determine_rate(struct clk_hw *hw,
1041 struct clk_rate_request *req)
1043 struct si5351_hw_data *hwdata =
1044 container_of(hw, struct si5351_hw_data, hw);
1045 unsigned long rate = req->rate;
1048 /* clkout6/7 can only handle output freqencies < 150MHz */
1049 if (hwdata->num >= 6 && rate > SI5351_CLKOUT67_MAX_FREQ)
1050 rate = SI5351_CLKOUT67_MAX_FREQ;
1052 /* clkout freqency is 8kHz - 160MHz */
1053 if (rate > SI5351_CLKOUT_MAX_FREQ)
1054 rate = SI5351_CLKOUT_MAX_FREQ;
1055 if (rate < SI5351_CLKOUT_MIN_FREQ)
1056 rate = SI5351_CLKOUT_MIN_FREQ;
1058 /* request frequency if multisync master */
1059 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
1060 /* use r divider for frequencies below 1MHz */
1061 rdiv = SI5351_OUTPUT_CLK_DIV_1;
1062 while (rate < SI5351_MULTISYNTH_MIN_FREQ &&
1063 rdiv < SI5351_OUTPUT_CLK_DIV_128) {
1067 req->best_parent_rate = rate;
1069 unsigned long new_rate, new_err, err;
1071 /* round to closed rdiv */
1072 rdiv = SI5351_OUTPUT_CLK_DIV_1;
1073 new_rate = req->best_parent_rate;
1074 err = abs(new_rate - rate);
1077 new_err = abs(new_rate - rate);
1078 if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
1084 rate = req->best_parent_rate >> rdiv;
1086 dev_dbg(&hwdata->drvdata->client->dev,
1087 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1088 __func__, clk_hw_get_name(hw), (1 << rdiv),
1089 req->best_parent_rate, rate);
1095 static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
1096 unsigned long parent_rate)
1098 struct si5351_hw_data *hwdata =
1099 container_of(hw, struct si5351_hw_data, hw);
1100 unsigned long new_rate, new_err, err;
1103 /* round to closed rdiv */
1104 rdiv = SI5351_OUTPUT_CLK_DIV_1;
1105 new_rate = parent_rate;
1106 err = abs(new_rate - rate);
1109 new_err = abs(new_rate - rate);
1110 if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
1116 /* write output divider */
1117 switch (hwdata->num) {
1119 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
1120 SI5351_OUTPUT_CLK6_DIV_MASK, rdiv);
1123 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
1124 SI5351_OUTPUT_CLK_DIV_MASK,
1125 rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
1128 si5351_set_bits(hwdata->drvdata,
1129 si5351_msynth_params_address(hwdata->num) + 2,
1130 SI5351_OUTPUT_CLK_DIV_MASK,
1131 rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
1134 /* powerup clkout */
1135 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
1136 SI5351_CLK_POWERDOWN, 0);
1138 dev_dbg(&hwdata->drvdata->client->dev,
1139 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1140 __func__, clk_hw_get_name(hw), (1 << rdiv),
1146 static const struct clk_ops si5351_clkout_ops = {
1147 .prepare = si5351_clkout_prepare,
1148 .unprepare = si5351_clkout_unprepare,
1149 .set_parent = si5351_clkout_set_parent,
1150 .get_parent = si5351_clkout_get_parent,
1151 .recalc_rate = si5351_clkout_recalc_rate,
1152 .determine_rate = si5351_clkout_determine_rate,
1153 .set_rate = si5351_clkout_set_rate,
1157 * Si5351 i2c probe and DT
1160 static const struct of_device_id si5351_dt_ids[] = {
1161 { .compatible = "silabs,si5351a", .data = (void *)SI5351_VARIANT_A, },
1162 { .compatible = "silabs,si5351a-msop",
1163 .data = (void *)SI5351_VARIANT_A3, },
1164 { .compatible = "silabs,si5351b", .data = (void *)SI5351_VARIANT_B, },
1165 { .compatible = "silabs,si5351c", .data = (void *)SI5351_VARIANT_C, },
1168 MODULE_DEVICE_TABLE(of, si5351_dt_ids);
1170 static int si5351_dt_parse(struct i2c_client *client,
1171 enum si5351_variant variant)
1173 struct device_node *child, *np = client->dev.of_node;
1174 struct si5351_platform_data *pdata;
1175 struct property *prop;
1183 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1188 * property silabs,pll-source : <num src>, [<..>]
1189 * allow to selectively set pll source
1191 of_property_for_each_u32(np, "silabs,pll-source", prop, p, num) {
1193 dev_err(&client->dev,
1194 "invalid pll %d on pll-source prop\n", num);
1198 p = of_prop_next_u32(prop, p, &val);
1200 dev_err(&client->dev,
1201 "missing pll-source for pll %d\n", num);
1207 pdata->pll_src[num] = SI5351_PLL_SRC_XTAL;
1210 if (variant != SI5351_VARIANT_C) {
1211 dev_err(&client->dev,
1212 "invalid parent %d for pll %d\n",
1216 pdata->pll_src[num] = SI5351_PLL_SRC_CLKIN;
1219 dev_err(&client->dev,
1220 "invalid parent %d for pll %d\n", val, num);
1225 /* per clkout properties */
1226 for_each_child_of_node(np, child) {
1227 if (of_property_read_u32(child, "reg", &num)) {
1228 dev_err(&client->dev, "missing reg property of %pOFn\n",
1234 (variant == SI5351_VARIANT_A3 && num >= 3)) {
1235 dev_err(&client->dev, "invalid clkout %d\n", num);
1239 if (!of_property_read_u32(child, "silabs,multisynth-source",
1243 pdata->clkout[num].multisynth_src =
1244 SI5351_MULTISYNTH_SRC_VCO0;
1247 pdata->clkout[num].multisynth_src =
1248 SI5351_MULTISYNTH_SRC_VCO1;
1251 dev_err(&client->dev,
1252 "invalid parent %d for multisynth %d\n",
1258 if (!of_property_read_u32(child, "silabs,clock-source", &val)) {
1261 pdata->clkout[num].clkout_src =
1262 SI5351_CLKOUT_SRC_MSYNTH_N;
1265 pdata->clkout[num].clkout_src =
1266 SI5351_CLKOUT_SRC_MSYNTH_0_4;
1269 pdata->clkout[num].clkout_src =
1270 SI5351_CLKOUT_SRC_XTAL;
1273 if (variant != SI5351_VARIANT_C) {
1274 dev_err(&client->dev,
1275 "invalid parent %d for clkout %d\n",
1279 pdata->clkout[num].clkout_src =
1280 SI5351_CLKOUT_SRC_CLKIN;
1283 dev_err(&client->dev,
1284 "invalid parent %d for clkout %d\n",
1290 if (!of_property_read_u32(child, "silabs,drive-strength",
1293 case SI5351_DRIVE_2MA:
1294 case SI5351_DRIVE_4MA:
1295 case SI5351_DRIVE_6MA:
1296 case SI5351_DRIVE_8MA:
1297 pdata->clkout[num].drive = val;
1300 dev_err(&client->dev,
1301 "invalid drive strength %d for clkout %d\n",
1307 if (!of_property_read_u32(child, "silabs,disable-state",
1311 pdata->clkout[num].disable_state =
1315 pdata->clkout[num].disable_state =
1316 SI5351_DISABLE_HIGH;
1319 pdata->clkout[num].disable_state =
1320 SI5351_DISABLE_FLOATING;
1323 pdata->clkout[num].disable_state =
1324 SI5351_DISABLE_NEVER;
1327 dev_err(&client->dev,
1328 "invalid disable state %d for clkout %d\n",
1334 if (!of_property_read_u32(child, "clock-frequency", &val))
1335 pdata->clkout[num].rate = val;
1337 pdata->clkout[num].pll_master =
1338 of_property_read_bool(child, "silabs,pll-master");
1340 pdata->clkout[num].pll_reset =
1341 of_property_read_bool(child, "silabs,pll-reset");
1343 client->dev.platform_data = pdata;
1351 static struct clk_hw *
1352 si53351_of_clk_get(struct of_phandle_args *clkspec, void *data)
1354 struct si5351_driver_data *drvdata = data;
1355 unsigned int idx = clkspec->args[0];
1357 if (idx >= drvdata->num_clkout) {
1358 pr_err("%s: invalid index %u\n", __func__, idx);
1359 return ERR_PTR(-EINVAL);
1362 return &drvdata->clkout[idx].hw;
1365 static int si5351_dt_parse(struct i2c_client *client, enum si5351_variant variant)
1370 static struct clk_hw *
1371 si53351_of_clk_get(struct of_phandle_args *clkspec, void *data)
1375 #endif /* CONFIG_OF */
1377 static const struct i2c_device_id si5351_i2c_ids[] = {
1378 { "si5351a", SI5351_VARIANT_A },
1379 { "si5351a-msop", SI5351_VARIANT_A3 },
1380 { "si5351b", SI5351_VARIANT_B },
1381 { "si5351c", SI5351_VARIANT_C },
1384 MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids);
1386 static int si5351_i2c_probe(struct i2c_client *client)
1388 enum si5351_variant variant;
1389 struct si5351_platform_data *pdata;
1390 struct si5351_driver_data *drvdata;
1391 struct clk_init_data init;
1392 const char *parent_names[4];
1393 u8 num_parents, num_clocks;
1396 variant = (enum si5351_variant)(uintptr_t)i2c_get_match_data(client);
1397 ret = si5351_dt_parse(client, variant);
1401 pdata = client->dev.platform_data;
1405 drvdata = devm_kzalloc(&client->dev, sizeof(*drvdata), GFP_KERNEL);
1409 i2c_set_clientdata(client, drvdata);
1410 drvdata->client = client;
1411 drvdata->variant = variant;
1412 drvdata->pxtal = devm_clk_get(&client->dev, "xtal");
1413 drvdata->pclkin = devm_clk_get(&client->dev, "clkin");
1415 if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER ||
1416 PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER)
1417 return -EPROBE_DEFER;
1420 * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL,
1421 * VARIANT_C can have CLKIN instead.
1423 if (IS_ERR(drvdata->pxtal) &&
1424 (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) {
1425 dev_err(&client->dev, "missing parent clock\n");
1429 drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config);
1430 if (IS_ERR(drvdata->regmap)) {
1431 dev_err(&client->dev, "failed to allocate register map\n");
1432 return PTR_ERR(drvdata->regmap);
1435 /* Disable interrupts */
1436 si5351_reg_write(drvdata, SI5351_INTERRUPT_MASK, 0xf0);
1437 /* Ensure pll select is on XTAL for Si5351A/B */
1438 if (drvdata->variant != SI5351_VARIANT_C)
1439 si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
1440 SI5351_PLLA_SOURCE | SI5351_PLLB_SOURCE, 0);
1442 /* setup clock configuration */
1443 for (n = 0; n < 2; n++) {
1444 ret = _si5351_pll_reparent(drvdata, n, pdata->pll_src[n]);
1446 dev_err(&client->dev,
1447 "failed to reparent pll %d to %d\n",
1448 n, pdata->pll_src[n]);
1453 for (n = 0; n < 8; n++) {
1454 ret = _si5351_msynth_reparent(drvdata, n,
1455 pdata->clkout[n].multisynth_src);
1457 dev_err(&client->dev,
1458 "failed to reparent multisynth %d to %d\n",
1459 n, pdata->clkout[n].multisynth_src);
1463 ret = _si5351_clkout_reparent(drvdata, n,
1464 pdata->clkout[n].clkout_src);
1466 dev_err(&client->dev,
1467 "failed to reparent clkout %d to %d\n",
1468 n, pdata->clkout[n].clkout_src);
1472 ret = _si5351_clkout_set_drive_strength(drvdata, n,
1473 pdata->clkout[n].drive);
1475 dev_err(&client->dev,
1476 "failed set drive strength of clkout%d to %d\n",
1477 n, pdata->clkout[n].drive);
1481 ret = _si5351_clkout_set_disable_state(drvdata, n,
1482 pdata->clkout[n].disable_state);
1484 dev_err(&client->dev,
1485 "failed set disable state of clkout%d to %d\n",
1486 n, pdata->clkout[n].disable_state);
1491 /* register xtal input clock gate */
1492 memset(&init, 0, sizeof(init));
1493 init.name = si5351_input_names[0];
1494 init.ops = &si5351_xtal_ops;
1496 if (!IS_ERR(drvdata->pxtal)) {
1497 drvdata->pxtal_name = __clk_get_name(drvdata->pxtal);
1498 init.parent_names = &drvdata->pxtal_name;
1499 init.num_parents = 1;
1501 drvdata->xtal.init = &init;
1502 ret = devm_clk_hw_register(&client->dev, &drvdata->xtal);
1504 dev_err(&client->dev, "unable to register %s\n", init.name);
1508 /* register clkin input clock gate */
1509 if (drvdata->variant == SI5351_VARIANT_C) {
1510 memset(&init, 0, sizeof(init));
1511 init.name = si5351_input_names[1];
1512 init.ops = &si5351_clkin_ops;
1513 if (!IS_ERR(drvdata->pclkin)) {
1514 drvdata->pclkin_name = __clk_get_name(drvdata->pclkin);
1515 init.parent_names = &drvdata->pclkin_name;
1516 init.num_parents = 1;
1518 drvdata->clkin.init = &init;
1519 ret = devm_clk_hw_register(&client->dev, &drvdata->clkin);
1521 dev_err(&client->dev, "unable to register %s\n",
1527 /* Si5351C allows to mux either xtal or clkin to PLL input */
1528 num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 2 : 1;
1529 parent_names[0] = si5351_input_names[0];
1530 parent_names[1] = si5351_input_names[1];
1533 drvdata->pll[0].num = 0;
1534 drvdata->pll[0].drvdata = drvdata;
1535 drvdata->pll[0].hw.init = &init;
1536 memset(&init, 0, sizeof(init));
1537 init.name = si5351_pll_names[0];
1538 init.ops = &si5351_pll_ops;
1540 init.parent_names = parent_names;
1541 init.num_parents = num_parents;
1542 ret = devm_clk_hw_register(&client->dev, &drvdata->pll[0].hw);
1544 dev_err(&client->dev, "unable to register %s\n", init.name);
1548 /* register PLLB or VXCO (Si5351B) */
1549 drvdata->pll[1].num = 1;
1550 drvdata->pll[1].drvdata = drvdata;
1551 drvdata->pll[1].hw.init = &init;
1552 memset(&init, 0, sizeof(init));
1553 if (drvdata->variant == SI5351_VARIANT_B) {
1554 init.name = si5351_pll_names[2];
1555 init.ops = &si5351_vxco_ops;
1557 init.parent_names = NULL;
1558 init.num_parents = 0;
1560 init.name = si5351_pll_names[1];
1561 init.ops = &si5351_pll_ops;
1563 init.parent_names = parent_names;
1564 init.num_parents = num_parents;
1566 ret = devm_clk_hw_register(&client->dev, &drvdata->pll[1].hw);
1568 dev_err(&client->dev, "unable to register %s\n", init.name);
1572 /* register clk multisync and clk out divider */
1573 num_clocks = (drvdata->variant == SI5351_VARIANT_A3) ? 3 : 8;
1574 parent_names[0] = si5351_pll_names[0];
1575 if (drvdata->variant == SI5351_VARIANT_B)
1576 parent_names[1] = si5351_pll_names[2];
1578 parent_names[1] = si5351_pll_names[1];
1580 drvdata->msynth = devm_kcalloc(&client->dev, num_clocks,
1581 sizeof(*drvdata->msynth), GFP_KERNEL);
1582 drvdata->clkout = devm_kcalloc(&client->dev, num_clocks,
1583 sizeof(*drvdata->clkout), GFP_KERNEL);
1584 drvdata->num_clkout = num_clocks;
1586 if (WARN_ON(!drvdata->msynth || !drvdata->clkout)) {
1591 for (n = 0; n < num_clocks; n++) {
1592 drvdata->msynth[n].num = n;
1593 drvdata->msynth[n].drvdata = drvdata;
1594 drvdata->msynth[n].hw.init = &init;
1595 memset(&init, 0, sizeof(init));
1596 init.name = si5351_msynth_names[n];
1597 init.ops = &si5351_msynth_ops;
1599 if (pdata->clkout[n].pll_master)
1600 init.flags |= CLK_SET_RATE_PARENT;
1601 init.parent_names = parent_names;
1602 init.num_parents = 2;
1603 ret = devm_clk_hw_register(&client->dev,
1604 &drvdata->msynth[n].hw);
1606 dev_err(&client->dev, "unable to register %s\n",
1612 num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 4 : 3;
1613 parent_names[2] = si5351_input_names[0];
1614 parent_names[3] = si5351_input_names[1];
1615 for (n = 0; n < num_clocks; n++) {
1616 parent_names[0] = si5351_msynth_names[n];
1617 parent_names[1] = (n < 4) ? si5351_msynth_names[0] :
1618 si5351_msynth_names[4];
1620 drvdata->clkout[n].num = n;
1621 drvdata->clkout[n].drvdata = drvdata;
1622 drvdata->clkout[n].hw.init = &init;
1623 memset(&init, 0, sizeof(init));
1624 init.name = si5351_clkout_names[n];
1625 init.ops = &si5351_clkout_ops;
1627 if (pdata->clkout[n].clkout_src == SI5351_CLKOUT_SRC_MSYNTH_N)
1628 init.flags |= CLK_SET_RATE_PARENT;
1629 init.parent_names = parent_names;
1630 init.num_parents = num_parents;
1631 ret = devm_clk_hw_register(&client->dev,
1632 &drvdata->clkout[n].hw);
1634 dev_err(&client->dev, "unable to register %s\n",
1639 /* set initial clkout rate */
1640 if (pdata->clkout[n].rate != 0) {
1642 ret = clk_set_rate(drvdata->clkout[n].hw.clk,
1643 pdata->clkout[n].rate);
1645 dev_err(&client->dev, "Cannot set rate : %d\n",
1651 ret = devm_of_clk_add_hw_provider(&client->dev, si53351_of_clk_get,
1654 dev_err(&client->dev, "unable to add clk provider\n");
1661 static struct i2c_driver si5351_driver = {
1664 .of_match_table = of_match_ptr(si5351_dt_ids),
1666 .probe = si5351_i2c_probe,
1667 .id_table = si5351_i2c_ids,
1669 module_i2c_driver(si5351_driver);
1671 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com");
1672 MODULE_DESCRIPTION("Silicon Labs Si5351A/B/C clock generator driver");
1673 MODULE_LICENSE("GPL");