1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Renesas 9-series PCIe clock generator driver
5 * The following series can be supported:
6 * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ
10 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
13 #include <linux/clk-provider.h>
14 #include <linux/i2c.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/module.h>
18 #include <linux/regmap.h>
20 #define RS9_REG_OE 0x0
21 #define RS9_REG_OE_DIF_OE(n) BIT((n) + 1)
22 #define RS9_REG_SS 0x1
23 #define RS9_REG_SS_AMP_0V6 0x0
24 #define RS9_REG_SS_AMP_0V7 0x1
25 #define RS9_REG_SS_AMP_0V8 0x2
26 #define RS9_REG_SS_AMP_0V9 0x3
27 #define RS9_REG_SS_AMP_MASK 0x3
28 #define RS9_REG_SS_SSC_100 0
29 #define RS9_REG_SS_SSC_M025 (1 << 3)
30 #define RS9_REG_SS_SSC_M050 (3 << 3)
31 #define RS9_REG_SS_SSC_MASK (3 << 3)
32 #define RS9_REG_SS_SSC_LOCK BIT(5)
33 #define RS9_REG_SR 0x2
34 #define RS9_REG_SR_2V0_DIF(n) 0
35 #define RS9_REG_SR_3V0_DIF(n) BIT((n) + 1)
36 #define RS9_REG_SR_DIF_MASK(n) BIT((n) + 1)
37 #define RS9_REG_REF 0x3
38 #define RS9_REG_REF_OE BIT(4)
39 #define RS9_REG_REF_OD BIT(5)
40 #define RS9_REG_REF_SR_SLOWEST 0
41 #define RS9_REG_REF_SR_SLOW (1 << 6)
42 #define RS9_REG_REF_SR_FAST (2 << 6)
43 #define RS9_REG_REF_SR_FASTER (3 << 6)
44 #define RS9_REG_VID 0x5
45 #define RS9_REG_DID 0x6
46 #define RS9_REG_BCP 0x7
48 /* Supported Renesas 9-series models. */
53 /* Structure to describe features of a particular 9-series model */
54 struct rs9_chip_info {
55 const enum rs9_model model;
56 unsigned int num_clks;
59 struct rs9_driver_data {
60 struct i2c_client *client;
61 struct regmap *regmap;
62 const struct rs9_chip_info *chip_info;
63 struct clk_hw *clk_dif[2];
70 * Renesas 9-series i2c regmap
72 static const struct regmap_range rs9_readable_ranges[] = {
73 regmap_reg_range(RS9_REG_OE, RS9_REG_REF),
74 regmap_reg_range(RS9_REG_VID, RS9_REG_BCP),
77 static const struct regmap_access_table rs9_readable_table = {
78 .yes_ranges = rs9_readable_ranges,
79 .n_yes_ranges = ARRAY_SIZE(rs9_readable_ranges),
82 static const struct regmap_range rs9_writeable_ranges[] = {
83 regmap_reg_range(RS9_REG_OE, RS9_REG_REF),
84 regmap_reg_range(RS9_REG_BCP, RS9_REG_BCP),
87 static const struct regmap_access_table rs9_writeable_table = {
88 .yes_ranges = rs9_writeable_ranges,
89 .n_yes_ranges = ARRAY_SIZE(rs9_writeable_ranges),
92 static int rs9_regmap_i2c_write(void *context,
93 unsigned int reg, unsigned int val)
95 struct i2c_client *i2c = context;
96 const u8 data[3] = { reg, 1, val };
97 const int count = ARRAY_SIZE(data);
100 ret = i2c_master_send(i2c, data, count);
109 static int rs9_regmap_i2c_read(void *context,
110 unsigned int reg, unsigned int *val)
112 struct i2c_client *i2c = context;
113 struct i2c_msg xfer[2];
118 xfer[0].addr = i2c->addr;
121 xfer[0].buf = (void *)&txdata;
123 xfer[1].addr = i2c->addr;
124 xfer[1].flags = I2C_M_RD;
126 xfer[1].buf = (void *)rxdata;
128 ret = i2c_transfer(i2c->adapter, xfer, 2);
135 * Byte 0 is transfer length, which is always 1 due
136 * to BCP register programming to 1 in rs9_probe(),
137 * ignore it and use data from Byte 1.
143 static const struct regmap_config rs9_regmap_config = {
146 .cache_type = REGCACHE_NONE,
147 .max_register = RS9_REG_BCP,
148 .rd_table = &rs9_readable_table,
149 .wr_table = &rs9_writeable_table,
150 .reg_write = rs9_regmap_i2c_write,
151 .reg_read = rs9_regmap_i2c_read,
154 static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx)
156 struct i2c_client *client = rs9->client;
157 unsigned char name[5] = "DIF0";
158 struct device_node *np;
163 rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx);
164 rs9->clk_dif_sr |= RS9_REG_SR_3V0_DIF(idx);
166 snprintf(name, 5, "DIF%d", idx);
167 np = of_get_child_by_name(client->dev.of_node, name);
171 /* Output clock slew rate */
172 ret = of_property_read_u32(np, "renesas,slew-rate", &sr);
175 if (sr == 2000000) { /* 2V/ns */
176 rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx);
177 rs9->clk_dif_sr |= RS9_REG_SR_2V0_DIF(idx);
178 } else if (sr == 3000000) { /* 3V/ns (default) */
179 rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx);
180 rs9->clk_dif_sr |= RS9_REG_SR_3V0_DIF(idx);
182 ret = dev_err_probe(&client->dev, -EINVAL,
183 "Invalid renesas,slew-rate value\n");
189 static int rs9_get_common_config(struct rs9_driver_data *rs9)
191 struct i2c_client *client = rs9->client;
192 struct device_node *np = client->dev.of_node;
193 unsigned int amp, ssc;
197 rs9->pll_amplitude = RS9_REG_SS_AMP_0V7;
198 rs9->pll_ssc = RS9_REG_SS_SSC_100;
200 /* Output clock amplitude */
201 ret = of_property_read_u32(np, "renesas,out-amplitude-microvolt",
204 if (amp == 600000) /* 0.6V */
205 rs9->pll_amplitude = RS9_REG_SS_AMP_0V6;
206 else if (amp == 700000) /* 0.7V (default) */
207 rs9->pll_amplitude = RS9_REG_SS_AMP_0V7;
208 else if (amp == 800000) /* 0.8V */
209 rs9->pll_amplitude = RS9_REG_SS_AMP_0V8;
210 else if (amp == 900000) /* 0.9V */
211 rs9->pll_amplitude = RS9_REG_SS_AMP_0V9;
213 return dev_err_probe(&client->dev, -EINVAL,
214 "Invalid renesas,out-amplitude-microvolt value\n");
217 /* Output clock spread spectrum */
218 ret = of_property_read_u32(np, "renesas,out-spread-spectrum", &ssc);
220 if (ssc == 100000) /* 100% ... no spread (default) */
221 rs9->pll_ssc = RS9_REG_SS_SSC_100;
222 else if (ssc == 99750) /* -0.25% ... down spread */
223 rs9->pll_ssc = RS9_REG_SS_SSC_M025;
224 else if (ssc == 99500) /* -0.50% ... down spread */
225 rs9->pll_ssc = RS9_REG_SS_SSC_M050;
227 return dev_err_probe(&client->dev, -EINVAL,
228 "Invalid renesas,out-spread-spectrum value\n");
234 static void rs9_update_config(struct rs9_driver_data *rs9)
238 /* If amplitude is non-default, update it. */
239 if (rs9->pll_amplitude != RS9_REG_SS_AMP_0V7) {
240 regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_AMP_MASK,
244 /* If SSC is non-default, update it. */
245 if (rs9->pll_ssc != RS9_REG_SS_SSC_100) {
246 regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_SSC_MASK,
250 for (i = 0; i < rs9->chip_info->num_clks; i++) {
251 if (rs9->clk_dif_sr & RS9_REG_SR_3V0_DIF(i))
254 regmap_update_bits(rs9->regmap, RS9_REG_SR, RS9_REG_SR_3V0_DIF(i),
255 rs9->clk_dif_sr & RS9_REG_SR_3V0_DIF(i));
259 static struct clk_hw *
260 rs9_of_clk_get(struct of_phandle_args *clkspec, void *data)
262 struct rs9_driver_data *rs9 = data;
263 unsigned int idx = clkspec->args[0];
265 return rs9->clk_dif[idx];
268 static int rs9_probe(struct i2c_client *client)
270 unsigned char name[5] = "DIF0";
271 struct rs9_driver_data *rs9;
275 rs9 = devm_kzalloc(&client->dev, sizeof(*rs9), GFP_KERNEL);
279 i2c_set_clientdata(client, rs9);
280 rs9->client = client;
281 rs9->chip_info = device_get_match_data(&client->dev);
285 /* Fetch common configuration from DT (if specified) */
286 ret = rs9_get_common_config(rs9);
290 /* Fetch DIFx output configuration from DT (if specified) */
291 for (i = 0; i < rs9->chip_info->num_clks; i++) {
292 ret = rs9_get_output_config(rs9, i);
297 rs9->regmap = devm_regmap_init(&client->dev, NULL,
298 client, &rs9_regmap_config);
299 if (IS_ERR(rs9->regmap))
300 return dev_err_probe(&client->dev, PTR_ERR(rs9->regmap),
301 "Failed to allocate register map\n");
303 /* Always read back 1 Byte via I2C */
304 ret = regmap_write(rs9->regmap, RS9_REG_BCP, 1);
309 for (i = 0; i < rs9->chip_info->num_clks; i++) {
310 snprintf(name, 5, "DIF%d", i);
311 hw = devm_clk_hw_register_fixed_factor_index(&client->dev, name,
316 rs9->clk_dif[i] = hw;
319 ret = devm_of_clk_add_hw_provider(&client->dev, rs9_of_clk_get, rs9);
321 rs9_update_config(rs9);
326 static int __maybe_unused rs9_suspend(struct device *dev)
328 struct rs9_driver_data *rs9 = dev_get_drvdata(dev);
330 regcache_cache_only(rs9->regmap, true);
331 regcache_mark_dirty(rs9->regmap);
336 static int __maybe_unused rs9_resume(struct device *dev)
338 struct rs9_driver_data *rs9 = dev_get_drvdata(dev);
341 regcache_cache_only(rs9->regmap, false);
342 ret = regcache_sync(rs9->regmap);
344 dev_err(dev, "Failed to restore register map: %d\n", ret);
348 static const struct rs9_chip_info renesas_9fgv0241_info = {
349 .model = RENESAS_9FGV0241,
353 static const struct i2c_device_id rs9_id[] = {
354 { "9fgv0241", .driver_data = RENESAS_9FGV0241 },
357 MODULE_DEVICE_TABLE(i2c, rs9_id);
359 static const struct of_device_id clk_rs9_of_match[] = {
360 { .compatible = "renesas,9fgv0241", .data = &renesas_9fgv0241_info },
363 MODULE_DEVICE_TABLE(of, clk_rs9_of_match);
365 static SIMPLE_DEV_PM_OPS(rs9_pm_ops, rs9_suspend, rs9_resume);
367 static struct i2c_driver rs9_driver = {
369 .name = "clk-renesas-pcie-9series",
371 .of_match_table = clk_rs9_of_match,
373 .probe_new = rs9_probe,
376 module_i2c_driver(rs9_driver);
378 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
379 MODULE_DESCRIPTION("Renesas 9-series PCIe clock generator driver");
380 MODULE_LICENSE("GPL");