1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Intel Corporation
5 * Adjustable fractional divider clock implementation.
6 * Output rate = (m / n) * parent_rate.
7 * Uses rational best approximation algorithm.
10 #include <linux/clk-provider.h>
11 #include <linux/module.h>
12 #include <linux/device.h>
13 #include <linux/slab.h>
14 #include <linux/rational.h>
16 static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
17 unsigned long parent_rate)
19 struct clk_fractional_divider *fd = to_clk_fd(hw);
20 unsigned long flags = 0;
26 spin_lock_irqsave(fd->lock, flags);
30 val = clk_readl(fd->reg);
33 spin_unlock_irqrestore(fd->lock, flags);
37 m = (val & fd->mmask) >> fd->mshift;
38 n = (val & fd->nmask) >> fd->nshift;
40 if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
48 ret = (u64)parent_rate * m;
54 static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
55 unsigned long *parent_rate,
56 unsigned long *m, unsigned long *n)
58 struct clk_fractional_divider *fd = to_clk_fd(hw);
62 * Get rate closer to *parent_rate to guarantee there is no overflow
63 * for m and n. In the result it will be the nearest rate left shifted
64 * by (scale - fd->nwidth) bits.
66 scale = fls_long(*parent_rate / rate - 1);
67 if (scale > fd->nwidth)
68 rate <<= scale - fd->nwidth;
70 rational_best_approximation(rate, *parent_rate,
71 GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
75 static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
76 unsigned long *parent_rate)
78 struct clk_fractional_divider *fd = to_clk_fd(hw);
82 if (!rate || (!clk_hw_can_set_rate_parent(hw) && rate >= *parent_rate))
85 if (fd->approximation)
86 fd->approximation(hw, rate, parent_rate, &m, &n);
88 clk_fd_general_approximation(hw, rate, parent_rate, &m, &n);
90 ret = (u64)*parent_rate * m;
96 static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
97 unsigned long parent_rate)
99 struct clk_fractional_divider *fd = to_clk_fd(hw);
100 unsigned long flags = 0;
104 rational_best_approximation(rate, parent_rate,
105 GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
108 if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
114 spin_lock_irqsave(fd->lock, flags);
118 val = clk_readl(fd->reg);
119 val &= ~(fd->mmask | fd->nmask);
120 val |= (m << fd->mshift) | (n << fd->nshift);
121 clk_writel(val, fd->reg);
124 spin_unlock_irqrestore(fd->lock, flags);
131 const struct clk_ops clk_fractional_divider_ops = {
132 .recalc_rate = clk_fd_recalc_rate,
133 .round_rate = clk_fd_round_rate,
134 .set_rate = clk_fd_set_rate,
136 EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);
138 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
139 const char *name, const char *parent_name, unsigned long flags,
140 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
141 u8 clk_divider_flags, spinlock_t *lock)
143 struct clk_fractional_divider *fd;
144 struct clk_init_data init;
148 fd = kzalloc(sizeof(*fd), GFP_KERNEL);
150 return ERR_PTR(-ENOMEM);
153 init.ops = &clk_fractional_divider_ops;
154 init.flags = flags | CLK_IS_BASIC;
155 init.parent_names = parent_name ? &parent_name : NULL;
156 init.num_parents = parent_name ? 1 : 0;
161 fd->mmask = GENMASK(mwidth - 1, 0) << mshift;
164 fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
165 fd->flags = clk_divider_flags;
170 ret = clk_hw_register(dev, hw);
178 EXPORT_SYMBOL_GPL(clk_hw_register_fractional_divider);
180 struct clk *clk_register_fractional_divider(struct device *dev,
181 const char *name, const char *parent_name, unsigned long flags,
182 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
183 u8 clk_divider_flags, spinlock_t *lock)
187 hw = clk_hw_register_fractional_divider(dev, name, parent_name, flags,
188 reg, mshift, mwidth, nshift, nwidth, clk_divider_flags,
194 EXPORT_SYMBOL_GPL(clk_register_fractional_divider);
196 void clk_hw_unregister_fractional_divider(struct clk_hw *hw)
198 struct clk_fractional_divider *fd;
202 clk_hw_unregister(hw);