1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/clk/at91_pmc.h>
5 #include <linux/mfd/syscon.h>
6 #include <linux/regmap.h>
7 #include <linux/slab.h>
11 #define MASTER_SOURCE_MAX 4
13 #define PERIPHERAL_AT91RM9200 0
14 #define PERIPHERAL_AT91SAM9X5 1
16 #define PERIPHERAL_MAX 64
18 #define PERIPHERAL_ID_MIN 2
20 #define PROG_SOURCE_MAX 5
23 #define SYSTEM_MAX_ID 31
25 #ifdef CONFIG_HAVE_AT91_AUDIO_PLL
26 static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
29 const char *name = np->name;
30 const char *parent_name;
31 struct regmap *regmap;
33 regmap = syscon_node_to_regmap(of_get_parent(np));
37 parent_name = of_clk_get_parent_name(np, 0);
39 hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name);
43 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
45 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup,
46 "atmel,sama5d2-clk-audio-pll-frac",
47 of_sama5d2_clk_audio_pll_frac_setup);
49 static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
52 const char *name = np->name;
53 const char *parent_name;
54 struct regmap *regmap;
56 regmap = syscon_node_to_regmap(of_get_parent(np));
60 parent_name = of_clk_get_parent_name(np, 0);
62 hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name);
66 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
68 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup,
69 "atmel,sama5d2-clk-audio-pll-pad",
70 of_sama5d2_clk_audio_pll_pad_setup);
72 static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
75 const char *name = np->name;
76 const char *parent_name;
77 struct regmap *regmap;
79 regmap = syscon_node_to_regmap(of_get_parent(np));
83 parent_name = of_clk_get_parent_name(np, 0);
85 hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name);
89 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
91 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup,
92 "atmel,sama5d2-clk-audio-pll-pmc",
93 of_sama5d2_clk_audio_pll_pmc_setup);
94 #endif /* CONFIG_HAVE_AT91_AUDIO_PLL */
96 #ifdef CONFIG_HAVE_AT91_GENERATED_CLK
97 #define GENERATED_SOURCE_MAX 6
99 #define GCK_ID_I2S0 54
100 #define GCK_ID_I2S1 55
101 #define GCK_ID_CLASSD 59
103 static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
109 unsigned int num_parents;
110 const char *parent_names[GENERATED_SOURCE_MAX];
111 struct device_node *gcknp;
112 struct clk_range range = CLK_RANGE(0, 0);
113 struct regmap *regmap;
115 num_parents = of_clk_get_parent_count(np);
116 if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
119 of_clk_parent_fill(np, parent_names, num_parents);
121 num = of_get_child_count(np);
122 if (!num || num > PERIPHERAL_MAX)
125 regmap = syscon_node_to_regmap(of_get_parent(np));
129 for_each_child_of_node(np, gcknp) {
130 bool pll_audio = false;
132 if (of_property_read_u32(gcknp, "reg", &id))
135 if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
138 if (of_property_read_string(np, "clock-output-names", &name))
141 of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
144 if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
145 (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
146 id == GCK_ID_CLASSD))
149 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, name,
150 parent_names, num_parents,
151 id, pll_audio, &range);
155 of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw);
158 CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated",
159 of_sama5d2_clk_generated_setup);
160 #endif /* CONFIG_HAVE_AT91_GENERATED_CLK */
162 #ifdef CONFIG_HAVE_AT91_H32MX
163 static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
166 const char *name = np->name;
167 const char *parent_name;
168 struct regmap *regmap;
170 regmap = syscon_node_to_regmap(of_get_parent(np));
174 parent_name = of_clk_get_parent_name(np, 0);
176 hw = at91_clk_register_h32mx(regmap, name, parent_name);
180 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
182 CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
183 of_sama5d4_clk_h32mx_setup);
184 #endif /* CONFIG_HAVE_AT91_H32MX */
186 #ifdef CONFIG_HAVE_AT91_I2S_MUX_CLK
189 static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)
191 struct regmap *regmap_sfr;
193 const char *parent_names[2];
194 struct device_node *i2s_mux_np;
198 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
199 if (IS_ERR(regmap_sfr))
202 for_each_child_of_node(np, i2s_mux_np) {
203 if (of_property_read_u8(i2s_mux_np, "reg", &bus_id))
206 if (bus_id > I2S_BUS_NR)
209 ret = of_clk_parent_fill(i2s_mux_np, parent_names, 2);
213 hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name,
214 parent_names, 2, bus_id);
218 of_clk_add_hw_provider(i2s_mux_np, of_clk_hw_simple_get, hw);
221 CLK_OF_DECLARE(sama5d2_clk_i2s_mux, "atmel,sama5d2-clk-i2s-mux",
222 of_sama5d2_clk_i2s_mux_setup);
223 #endif /* CONFIG_HAVE_AT91_I2S_MUX_CLK */
225 static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
228 const char *name = np->name;
229 const char *parent_name;
230 struct regmap *regmap;
233 of_property_read_string(np, "clock-output-names", &name);
234 bypass = of_property_read_bool(np, "atmel,osc-bypass");
235 parent_name = of_clk_get_parent_name(np, 0);
237 regmap = syscon_node_to_regmap(of_get_parent(np));
241 hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass);
245 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
247 CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc",
248 of_at91rm9200_clk_main_osc_setup);
250 static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
255 const char *name = np->name;
256 struct regmap *regmap;
258 of_property_read_string(np, "clock-output-names", &name);
259 of_property_read_u32(np, "clock-frequency", &frequency);
260 of_property_read_u32(np, "clock-accuracy", &accuracy);
262 regmap = syscon_node_to_regmap(of_get_parent(np));
266 hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy);
270 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
272 CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc",
273 of_at91sam9x5_clk_main_rc_osc_setup);
275 static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
278 const char *parent_name;
279 const char *name = np->name;
280 struct regmap *regmap;
282 parent_name = of_clk_get_parent_name(np, 0);
283 of_property_read_string(np, "clock-output-names", &name);
285 regmap = syscon_node_to_regmap(of_get_parent(np));
289 hw = at91_clk_register_rm9200_main(regmap, name, parent_name);
293 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
295 CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
296 of_at91rm9200_clk_main_setup);
298 static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
301 const char *parent_names[2];
302 unsigned int num_parents;
303 const char *name = np->name;
304 struct regmap *regmap;
306 num_parents = of_clk_get_parent_count(np);
307 if (num_parents == 0 || num_parents > 2)
310 of_clk_parent_fill(np, parent_names, num_parents);
311 regmap = syscon_node_to_regmap(of_get_parent(np));
315 of_property_read_string(np, "clock-output-names", &name);
317 hw = at91_clk_register_sam9x5_main(regmap, name, parent_names,
322 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
324 CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main",
325 of_at91sam9x5_clk_main_setup);
327 static struct clk_master_characteristics * __init
328 of_at91_clk_master_get_characteristics(struct device_node *np)
330 struct clk_master_characteristics *characteristics;
332 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
333 if (!characteristics)
336 if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))
337 goto out_free_characteristics;
339 of_property_read_u32_array(np, "atmel,clk-divisors",
340 characteristics->divisors, 4);
342 characteristics->have_div3_pres =
343 of_property_read_bool(np, "atmel,master-clk-have-div3-pres");
345 return characteristics;
347 out_free_characteristics:
348 kfree(characteristics);
353 of_at91_clk_master_setup(struct device_node *np,
354 const struct clk_master_layout *layout)
357 unsigned int num_parents;
358 const char *parent_names[MASTER_SOURCE_MAX];
359 const char *name = np->name;
360 struct clk_master_characteristics *characteristics;
361 struct regmap *regmap;
363 num_parents = of_clk_get_parent_count(np);
364 if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX)
367 of_clk_parent_fill(np, parent_names, num_parents);
369 of_property_read_string(np, "clock-output-names", &name);
371 characteristics = of_at91_clk_master_get_characteristics(np);
372 if (!characteristics)
375 regmap = syscon_node_to_regmap(of_get_parent(np));
379 hw = at91_clk_register_master(regmap, name, num_parents,
380 parent_names, layout,
383 goto out_free_characteristics;
385 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
388 out_free_characteristics:
389 kfree(characteristics);
392 static void __init of_at91rm9200_clk_master_setup(struct device_node *np)
394 of_at91_clk_master_setup(np, &at91rm9200_master_layout);
396 CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master",
397 of_at91rm9200_clk_master_setup);
399 static void __init of_at91sam9x5_clk_master_setup(struct device_node *np)
401 of_at91_clk_master_setup(np, &at91sam9x5_master_layout);
403 CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master",
404 of_at91sam9x5_clk_master_setup);
407 of_at91_clk_periph_setup(struct device_node *np, u8 type)
412 const char *parent_name;
414 struct device_node *periphclknp;
415 struct regmap *regmap;
417 parent_name = of_clk_get_parent_name(np, 0);
421 num = of_get_child_count(np);
422 if (!num || num > PERIPHERAL_MAX)
425 regmap = syscon_node_to_regmap(of_get_parent(np));
429 for_each_child_of_node(np, periphclknp) {
430 if (of_property_read_u32(periphclknp, "reg", &id))
433 if (id >= PERIPHERAL_MAX)
436 if (of_property_read_string(np, "clock-output-names", &name))
437 name = periphclknp->name;
439 if (type == PERIPHERAL_AT91RM9200) {
440 hw = at91_clk_register_peripheral(regmap, name,
443 struct clk_range range = CLK_RANGE(0, 0);
445 of_at91_get_clk_range(periphclknp,
446 "atmel,clk-output-range",
449 hw = at91_clk_register_sam9x5_peripheral(regmap,
459 of_clk_add_hw_provider(periphclknp, of_clk_hw_simple_get, hw);
463 static void __init of_at91rm9200_clk_periph_setup(struct device_node *np)
465 of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200);
467 CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral",
468 of_at91rm9200_clk_periph_setup);
470 static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np)
472 of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5);
474 CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral",
475 of_at91sam9x5_clk_periph_setup);
477 static struct clk_pll_characteristics * __init
478 of_at91_clk_pll_get_characteristics(struct device_node *np)
485 struct clk_range input;
486 struct clk_range *output;
489 struct clk_pll_characteristics *characteristics;
491 if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
494 if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
498 if (num_cells < 2 || num_cells > 4)
501 if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
503 num_output = tmp / (sizeof(u32) * num_cells);
505 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
506 if (!characteristics)
509 output = kcalloc(num_output, sizeof(*output), GFP_KERNEL);
511 goto out_free_characteristics;
514 out = kcalloc(num_output, sizeof(*out), GFP_KERNEL);
516 goto out_free_output;
520 icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL);
522 goto out_free_output;
525 for (i = 0; i < num_output; i++) {
526 offset = i * num_cells;
527 if (of_property_read_u32_index(np,
528 "atmel,pll-clk-output-ranges",
530 goto out_free_output;
532 if (of_property_read_u32_index(np,
533 "atmel,pll-clk-output-ranges",
535 goto out_free_output;
541 if (of_property_read_u32_index(np,
542 "atmel,pll-clk-output-ranges",
544 goto out_free_output;
550 if (of_property_read_u32_index(np,
551 "atmel,pll-clk-output-ranges",
553 goto out_free_output;
557 characteristics->input = input;
558 characteristics->num_output = num_output;
559 characteristics->output = output;
560 characteristics->out = out;
561 characteristics->icpll = icpll;
562 return characteristics;
568 out_free_characteristics:
569 kfree(characteristics);
574 of_at91_clk_pll_setup(struct device_node *np,
575 const struct clk_pll_layout *layout)
579 struct regmap *regmap;
580 const char *parent_name;
581 const char *name = np->name;
582 struct clk_pll_characteristics *characteristics;
584 if (of_property_read_u32(np, "reg", &id))
587 parent_name = of_clk_get_parent_name(np, 0);
589 of_property_read_string(np, "clock-output-names", &name);
591 regmap = syscon_node_to_regmap(of_get_parent(np));
595 characteristics = of_at91_clk_pll_get_characteristics(np);
596 if (!characteristics)
599 hw = at91_clk_register_pll(regmap, name, parent_name, id, layout,
602 goto out_free_characteristics;
604 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
607 out_free_characteristics:
608 kfree(characteristics);
611 static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
613 of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
615 CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
616 of_at91rm9200_clk_pll_setup);
618 static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
620 of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
622 CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
623 of_at91sam9g45_clk_pll_setup);
625 static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
627 of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
629 CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
630 of_at91sam9g20_clk_pllb_setup);
632 static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
634 of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
636 CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
637 of_sama5d3_clk_pll_setup);
640 of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
643 const char *parent_name;
644 const char *name = np->name;
645 struct regmap *regmap;
647 parent_name = of_clk_get_parent_name(np, 0);
649 of_property_read_string(np, "clock-output-names", &name);
651 regmap = syscon_node_to_regmap(of_get_parent(np));
655 hw = at91_clk_register_plldiv(regmap, name, parent_name);
659 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
661 CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
662 of_at91sam9x5_clk_plldiv_setup);
665 of_at91_clk_prog_setup(struct device_node *np,
666 const struct clk_programmable_layout *layout)
671 unsigned int num_parents;
672 const char *parent_names[PROG_SOURCE_MAX];
674 struct device_node *progclknp;
675 struct regmap *regmap;
677 num_parents = of_clk_get_parent_count(np);
678 if (num_parents == 0 || num_parents > PROG_SOURCE_MAX)
681 of_clk_parent_fill(np, parent_names, num_parents);
683 num = of_get_child_count(np);
684 if (!num || num > (PROG_ID_MAX + 1))
687 regmap = syscon_node_to_regmap(of_get_parent(np));
691 for_each_child_of_node(np, progclknp) {
692 if (of_property_read_u32(progclknp, "reg", &id))
695 if (of_property_read_string(np, "clock-output-names", &name))
696 name = progclknp->name;
698 hw = at91_clk_register_programmable(regmap, name,
699 parent_names, num_parents,
704 of_clk_add_hw_provider(progclknp, of_clk_hw_simple_get, hw);
708 static void __init of_at91rm9200_clk_prog_setup(struct device_node *np)
710 of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout);
712 CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable",
713 of_at91rm9200_clk_prog_setup);
715 static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np)
717 of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout);
719 CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable",
720 of_at91sam9g45_clk_prog_setup);
722 static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np)
724 of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout);
726 CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable",
727 of_at91sam9x5_clk_prog_setup);
729 static void __init of_at91sam9260_clk_slow_setup(struct device_node *np)
732 const char *parent_names[2];
733 unsigned int num_parents;
734 const char *name = np->name;
735 struct regmap *regmap;
737 num_parents = of_clk_get_parent_count(np);
738 if (num_parents != 2)
741 of_clk_parent_fill(np, parent_names, num_parents);
742 regmap = syscon_node_to_regmap(of_get_parent(np));
746 of_property_read_string(np, "clock-output-names", &name);
748 hw = at91_clk_register_sam9260_slow(regmap, name, parent_names,
753 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
755 CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow",
756 of_at91sam9260_clk_slow_setup);
758 #ifdef CONFIG_HAVE_AT91_SMD
759 #define SMD_SOURCE_MAX 2
761 static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
764 unsigned int num_parents;
765 const char *parent_names[SMD_SOURCE_MAX];
766 const char *name = np->name;
767 struct regmap *regmap;
769 num_parents = of_clk_get_parent_count(np);
770 if (num_parents == 0 || num_parents > SMD_SOURCE_MAX)
773 of_clk_parent_fill(np, parent_names, num_parents);
775 of_property_read_string(np, "clock-output-names", &name);
777 regmap = syscon_node_to_regmap(of_get_parent(np));
781 hw = at91sam9x5_clk_register_smd(regmap, name, parent_names,
786 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
788 CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd",
789 of_at91sam9x5_clk_smd_setup);
790 #endif /* CONFIG_HAVE_AT91_SMD */
792 static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
798 struct device_node *sysclknp;
799 const char *parent_name;
800 struct regmap *regmap;
802 num = of_get_child_count(np);
803 if (num > (SYSTEM_MAX_ID + 1))
806 regmap = syscon_node_to_regmap(of_get_parent(np));
810 for_each_child_of_node(np, sysclknp) {
811 if (of_property_read_u32(sysclknp, "reg", &id))
814 if (of_property_read_string(np, "clock-output-names", &name))
815 name = sysclknp->name;
817 parent_name = of_clk_get_parent_name(sysclknp, 0);
819 hw = at91_clk_register_system(regmap, name, parent_name, id);
823 of_clk_add_hw_provider(sysclknp, of_clk_hw_simple_get, hw);
826 CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system",
827 of_at91rm9200_clk_sys_setup);
829 #ifdef CONFIG_HAVE_AT91_USB_CLK
830 #define USB_SOURCE_MAX 2
832 static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
835 unsigned int num_parents;
836 const char *parent_names[USB_SOURCE_MAX];
837 const char *name = np->name;
838 struct regmap *regmap;
840 num_parents = of_clk_get_parent_count(np);
841 if (num_parents == 0 || num_parents > USB_SOURCE_MAX)
844 of_clk_parent_fill(np, parent_names, num_parents);
846 of_property_read_string(np, "clock-output-names", &name);
848 regmap = syscon_node_to_regmap(of_get_parent(np));
852 hw = at91sam9x5_clk_register_usb(regmap, name, parent_names,
857 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
859 CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb",
860 of_at91sam9x5_clk_usb_setup);
862 static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)
865 const char *parent_name;
866 const char *name = np->name;
867 struct regmap *regmap;
869 parent_name = of_clk_get_parent_name(np, 0);
873 of_property_read_string(np, "clock-output-names", &name);
875 regmap = syscon_node_to_regmap(of_get_parent(np));
879 hw = at91sam9n12_clk_register_usb(regmap, name, parent_name);
883 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
885 CLK_OF_DECLARE(at91sam9n12_clk_usb, "atmel,at91sam9n12-clk-usb",
886 of_at91sam9n12_clk_usb_setup);
888 static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
891 const char *parent_name;
892 const char *name = np->name;
893 u32 divisors[4] = {0, 0, 0, 0};
894 struct regmap *regmap;
896 parent_name = of_clk_get_parent_name(np, 0);
900 of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4);
904 of_property_read_string(np, "clock-output-names", &name);
906 regmap = syscon_node_to_regmap(of_get_parent(np));
909 hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors);
913 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
915 CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb",
916 of_at91rm9200_clk_usb_setup);
917 #endif /* CONFIG_HAVE_AT91_USB_CLK */
919 #ifdef CONFIG_HAVE_AT91_UTMI
920 static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
923 const char *parent_name;
924 const char *name = np->name;
925 struct regmap *regmap_pmc, *regmap_sfr;
927 parent_name = of_clk_get_parent_name(np, 0);
929 of_property_read_string(np, "clock-output-names", &name);
931 regmap_pmc = syscon_node_to_regmap(of_get_parent(np));
932 if (IS_ERR(regmap_pmc))
936 * If the device supports different mainck rates, this value has to be
937 * set in the UTMI Clock Trimming register.
938 * - 9x5: mainck supports several rates but it is indicated that a
939 * 12 MHz is needed in case of USB.
940 * - sama5d3 and sama5d2: mainck supports several rates. Configuring
941 * the FREQ field of the UTMI Clock Trimming register is mandatory.
942 * - sama5d4: mainck is at 12 MHz.
944 * We only need to retrieve sama5d3 or sama5d2 sfr regmap.
946 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr");
947 if (IS_ERR(regmap_sfr)) {
948 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
949 if (IS_ERR(regmap_sfr))
953 hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name);
957 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
959 CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi",
960 of_at91sam9x5_clk_utmi_setup);
961 #endif /* CONFIG_HAVE_AT91_UTMI */