1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
7 thus are a key power management tool on many systems.
9 config HAVE_CLK_PREPARE
12 config HAVE_LEGACY_CLK # TODO: Remove once all legacy users are migrated
16 Select this option when the clock API in <linux/clk.h> is implemented
17 by platform/architecture code. This method is deprecated. Modern
18 code should select COMMON_CLK instead and not define a custom
22 bool "Common Clock Framework"
23 depends on !HAVE_LEGACY_CLK
24 select HAVE_CLK_PREPARE
29 The common clock framework is a single definition of struct
30 clk, useful across many platforms, as well as an
31 implementation of the clock API in include/linux/clk.h.
32 Architectures utilizing the common struct clk should select
37 config COMMON_CLK_WM831X
38 tristate "Clock driver for WM831x/2x PMICs"
41 Supports the clocking subsystem of the WM831x/2x series of
42 PMICs from Wolfson Microelectronics.
44 source "drivers/clk/versatile/Kconfig"
47 bool "PLL Driver for HSDK platform"
48 depends on ARC_SOC_HSDK || COMPILE_TEST
51 This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
55 tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
59 Say yes here to build support for Texas Instruments' LMK04832 Ultra
60 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
62 config COMMON_CLK_MAX77686
63 tristate "Clock driver for Maxim 77620/77686/77802 MFD"
64 depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
66 This driver supports Maxim 77620/77686/77802 crystal oscillator
69 config COMMON_CLK_MAX9485
70 tristate "Maxim 9485 Programmable Clock Generator"
73 This driver supports Maxim 9485 Programmable Audio Clock Generator
75 config COMMON_CLK_RK808
76 tristate "Clock driver for RK805/RK808/RK809/RK817/RK818"
79 This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock.
80 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
81 Clkout1 is always on, Clkout2 can off by control register.
83 config COMMON_CLK_HI655X
84 tristate "Clock driver for Hi655x" if EXPERT
85 depends on (MFD_HI655X_PMIC || COMPILE_TEST)
87 default MFD_HI655X_PMIC
89 This driver supports the hi655x PMIC clock. This
90 multi-function device has one fixed-rate oscillator, clocked
93 config COMMON_CLK_SCMI
94 tristate "Clock driver controlled via SCMI interface"
95 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
97 This driver provides support for clocks that are controlled
98 by firmware that implements the SCMI interface.
100 This driver uses SCMI Message Protocol to interact with the
101 firmware providing all the clock controls.
103 config COMMON_CLK_SCPI
104 tristate "Clock driver controlled via SCPI interface"
105 depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
107 This driver provides support for clocks that are controlled
108 by firmware that implements the SCPI interface.
110 This driver uses SCPI Message Protocol to interact with the
111 firmware providing all the clock controls.
113 config COMMON_CLK_SI5341
114 tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices"
118 This driver supports Silicon Labs Si5341 and Si5340 programmable clock
119 generators. Not all features of these chips are currently supported
120 by the driver, in particular it only supports XTAL input. The chip can
121 be pre-programmed to support other configurations and features not yet
122 implemented in the driver.
124 config COMMON_CLK_SI5351
125 tristate "Clock driver for SiLabs 5351A/B/C"
129 This driver supports Silicon Labs 5351A/B/C programmable clock
132 config COMMON_CLK_SI514
133 tristate "Clock driver for SiLabs 514 devices"
138 This driver supports the Silicon Labs 514 programmable clock
141 config COMMON_CLK_SI544
142 tristate "Clock driver for SiLabs 544 devices"
146 This driver supports the Silicon Labs 544 programmable clock
149 config COMMON_CLK_SI570
150 tristate "Clock driver for SiLabs 570 and compatible devices"
155 This driver supports Silicon Labs 570/571/598/599 programmable
158 config COMMON_CLK_BM1880
159 bool "Clock driver for Bitmain BM1880 SoC"
160 depends on ARCH_BITMAIN || COMPILE_TEST
163 This driver supports the clocks on Bitmain BM1880 SoC.
165 config COMMON_CLK_CDCE706
166 tristate "Clock driver for TI CDCE706 clock synthesizer"
170 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
172 config COMMON_CLK_TPS68470
173 tristate "Clock Driver for TI TPS68470 PMIC"
175 depends on INTEL_SKL_INT3472 || COMPILE_TEST
178 This driver supports the clocks provided by the TPS68470 PMIC.
180 config COMMON_CLK_CDCE925
181 tristate "Clock driver for TI CDCE913/925/937/949 devices"
186 This driver supports the TI CDCE913/925/937/949 programmable clock
187 synthesizer. Each chip has different number of PLLs and outputs.
188 For example, the CDCE925 contains two PLLs with spread-spectrum
189 clocking support and five output dividers. The driver only supports
190 the following setup, and uses a fixed setting for the output muxes.
191 Y1 is derived from the input clock
192 Y2 and Y3 derive from PLL1
193 Y4 and Y5 derive from PLL2
194 Given a target output frequency, the driver will set the PLL and
195 divider to best approximate the desired output.
197 config COMMON_CLK_CS2000_CP
198 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
202 If you say yes here you get support for the CS2000 clock multiplier.
204 config COMMON_CLK_FSL_FLEXSPI
205 tristate "Clock driver for FlexSPI on Layerscape SoCs"
206 depends on ARCH_LAYERSCAPE || COMPILE_TEST
207 default ARCH_LAYERSCAPE && SPI_NXP_FLEXSPI
209 On Layerscape SoCs there is a special clock for the FlexSPI
212 config COMMON_CLK_FSL_SAI
213 bool "Clock driver for BCLK of Freescale SAI cores"
214 depends on ARCH_LAYERSCAPE || COMPILE_TEST
216 This driver supports the Freescale SAI (Synchronous Audio Interface)
217 to be used as a generic clock output. Some SoCs have restrictions
218 regarding the possible pin multiplexer settings. Eg. on some SoCs
219 two SAI interfaces can only be enabled together. If just one is
220 needed, the BCLK pin of the second one can be used as general
221 purpose clock output. Ideally, it can be used to drive an audio
222 codec (sometimes known as MCLK).
224 config COMMON_CLK_GEMINI
225 bool "Clock driver for Cortina Systems Gemini SoC"
226 depends on ARCH_GEMINI || COMPILE_TEST
228 select RESET_CONTROLLER
230 This driver supports the SoC clocks on the Cortina Systems Gemini
231 platform, also known as SL3516 or CS3516.
233 config COMMON_CLK_LAN966X
234 bool "Generic Clock Controller driver for LAN966X SoC"
236 This driver provides support for Generic Clock Controller(GCK) on
237 LAN966X SoC. GCK generates and supplies clock to various peripherals
240 config COMMON_CLK_ASPEED
241 bool "Clock driver for Aspeed BMC SoCs"
242 depends on ARCH_ASPEED || COMPILE_TEST
245 select RESET_CONTROLLER
247 This driver supports the SoC clocks on the Aspeed BMC platforms.
249 The G4 and G5 series, including the ast2400 and ast2500, are supported
252 config COMMON_CLK_S2MPS11
253 tristate "Clock driver for S2MPS1X/S5M8767 MFD"
254 depends on MFD_SEC_CORE || COMPILE_TEST
256 This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator
257 clock. These multi-function devices have two (S2MPS14) or three
258 (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
261 tristate "External McPDM functional clock from twl6040"
262 depends on TWL6040_CORE
264 Enable the external functional clock support on OMAP4+ platforms for
265 McPDM. McPDM module is using the external bit clock on the McPDM bus
268 config COMMON_CLK_AXI_CLKGEN
269 tristate "AXI clkgen driver"
270 depends on HAS_IOMEM || COMPILE_TEST
273 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
274 FPGAs. It is commonly used in Analog Devices' reference designs.
277 bool "Clock driver for Freescale QorIQ platforms"
279 depends on PPC_E500MC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
281 This adds the clock driver support for Freescale QorIQ platforms
282 using common clock framework.
284 config CLK_LS1028A_PLLDIG
285 tristate "Clock driver for LS1028A Display output"
286 depends on ARCH_LAYERSCAPE || COMPILE_TEST
287 default ARCH_LAYERSCAPE
289 This driver support the Display output interfaces(LCD, DPHY) pixel clocks
290 of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
291 features of the PLL are currently supported by the driver. By default,
292 configured bypass mode with this PLL.
294 config COMMON_CLK_XGENE
295 bool "Clock driver for APM XGene SoC"
297 depends on ARM64 || COMPILE_TEST
299 Support for the APM X-Gene SoC reference, PLL, and device clocks.
301 config COMMON_CLK_LOCHNAGAR
302 tristate "Cirrus Logic Lochnagar clock driver"
303 depends on MFD_LOCHNAGAR
305 This driver supports the clocking features of the Cirrus Logic
306 Lochnagar audio development board.
308 config COMMON_CLK_NXP
309 def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)
310 select REGMAP_MMIO if ARCH_LPC32XX
311 select MFD_SYSCON if ARCH_LPC18XX
313 Support for clock providers on NXP platforms.
315 config COMMON_CLK_PALMAS
316 tristate "Clock driver for TI Palmas devices"
317 depends on MFD_PALMAS
319 This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
320 using common clock framework.
322 config COMMON_CLK_PWM
323 tristate "Clock driver for PWMs used as clock outputs"
326 Adapter driver so that any PWM output can be (mis)used as clock signal
329 config COMMON_CLK_PXA
330 def_bool COMMON_CLK && ARCH_PXA
332 Support for the Marvell PXA SoC.
334 config COMMON_CLK_OXNAS
335 bool "Clock driver for the OXNAS SoC Family"
336 depends on ARCH_OXNAS || COMPILE_TEST
339 Support for the OXNAS SoC Family clocks.
341 config COMMON_CLK_RS9_PCIE
342 tristate "Clock driver for Renesas 9-series PCIe clock generators"
347 This driver supports the Renesas 9-series PCIe clock generator
348 models 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ.
350 config COMMON_CLK_VC5
351 tristate "Clock driver for IDT VersaClock 5,6 devices"
356 This driver supports the IDT VersaClock 5 and VersaClock 6
357 programmable clock generators.
359 config COMMON_CLK_STM32MP157
360 def_bool COMMON_CLK && MACH_STM32MP157
362 Support for stm32mp157 SoC family clocks
364 config COMMON_CLK_STM32F
365 def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
367 Support for stm32f4 and stm32f7 SoC families clocks
369 config COMMON_CLK_STM32H7
370 def_bool COMMON_CLK && MACH_STM32H743
372 Support for stm32h7 SoC family clocks
374 config COMMON_CLK_MMP2
375 def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)
377 Support for Marvell MMP2 and MMP3 SoC clocks
379 config COMMON_CLK_MMP2_AUDIO
380 tristate "Clock driver for MMP2 Audio subsystem"
381 depends on COMMON_CLK_MMP2 || COMPILE_TEST
383 This driver supports clocks for Audio subsystem on MMP2 SoC.
385 config COMMON_CLK_BD718XX
386 tristate "Clock driver for 32K clk gates on ROHM PMICs"
387 depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828
389 This driver supports ROHM BD71837, BD71847, BD71850, BD71815
390 and BD71828 PMICs clock gates.
392 config COMMON_CLK_FIXED_MMIO
393 bool "Clock driver for Memory Mapped Fixed values"
394 depends on COMMON_CLK && OF
396 Support for Memory Mapped IO Fixed clocks
398 config COMMON_CLK_K210
399 bool "Clock driver for the Canaan Kendryte K210 SoC"
400 depends on OF && RISCV && SOC_CANAAN
403 Support for the Canaan Kendryte K210 RISC-V SoC clocks.
405 source "drivers/clk/actions/Kconfig"
406 source "drivers/clk/analogbits/Kconfig"
407 source "drivers/clk/baikal-t1/Kconfig"
408 source "drivers/clk/bcm/Kconfig"
409 source "drivers/clk/hisilicon/Kconfig"
410 source "drivers/clk/imgtec/Kconfig"
411 source "drivers/clk/imx/Kconfig"
412 source "drivers/clk/ingenic/Kconfig"
413 source "drivers/clk/keystone/Kconfig"
414 source "drivers/clk/mediatek/Kconfig"
415 source "drivers/clk/meson/Kconfig"
416 source "drivers/clk/mstar/Kconfig"
417 source "drivers/clk/microchip/Kconfig"
418 source "drivers/clk/mvebu/Kconfig"
419 source "drivers/clk/pistachio/Kconfig"
420 source "drivers/clk/qcom/Kconfig"
421 source "drivers/clk/ralink/Kconfig"
422 source "drivers/clk/renesas/Kconfig"
423 source "drivers/clk/rockchip/Kconfig"
424 source "drivers/clk/samsung/Kconfig"
425 source "drivers/clk/sifive/Kconfig"
426 source "drivers/clk/socfpga/Kconfig"
427 source "drivers/clk/sprd/Kconfig"
428 source "drivers/clk/starfive/Kconfig"
429 source "drivers/clk/sunxi/Kconfig"
430 source "drivers/clk/sunxi-ng/Kconfig"
431 source "drivers/clk/tegra/Kconfig"
432 source "drivers/clk/ti/Kconfig"
433 source "drivers/clk/uniphier/Kconfig"
434 source "drivers/clk/visconti/Kconfig"
435 source "drivers/clk/x86/Kconfig"
436 source "drivers/clk/xilinx/Kconfig"
437 source "drivers/clk/zynqmp/Kconfig"
440 config CLK_GATE_KUNIT_TEST
441 tristate "Basic gate type Kunit test" if !KUNIT_ALL_TESTS
443 default KUNIT_ALL_TESTS
445 Kunit test for the basic clk gate type.