1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2021 Nuvoton Technology corporation
4 * Copyright (C) 2019-2022 Infineon Technologies AG
6 * This device driver implements the TPM interface as defined in the TCG PC
7 * Client Platform TPM Profile (PTP) Specification for TPM 2.0 v1.04
10 * It is based on the tpm_tis_spi device driver.
13 #include <linux/i2c.h>
14 #include <linux/crc-ccitt.h>
15 #include "tpm_tis_core.h"
18 #define TPM_I2C_LOC_SEL 0x00
19 #define TPM_I2C_ACCESS 0x04
20 #define TPM_I2C_INTERFACE_CAPABILITY 0x30
21 #define TPM_I2C_DEVICE_ADDRESS 0x38
22 #define TPM_I2C_DATA_CSUM_ENABLE 0x40
23 #define TPM_DATA_CSUM 0x44
24 #define TPM_I2C_DID_VID 0x48
25 #define TPM_I2C_RID 0x4C
27 /* TIS-compatible register address to avoid clash with TPM_ACCESS (0x00) */
28 #define TPM_LOC_SEL 0x0FFF
30 /* Mask to extract the I2C register from TIS register addresses */
31 #define TPM_TIS_REGISTER_MASK 0x0FFF
33 /* Default Guard Time of 250µs until interface capability register is read */
34 #define GUARD_TIME_DEFAULT_MIN 250
35 #define GUARD_TIME_DEFAULT_MAX 300
37 /* Guard Time of 250µs after I2C slave NACK */
38 #define GUARD_TIME_ERR_MIN 250
39 #define GUARD_TIME_ERR_MAX 300
41 /* Guard Time bit masks; SR is repeated start, RW is read then write, etc. */
42 #define TPM_GUARD_TIME_SR_MASK 0x40000000
43 #define TPM_GUARD_TIME_RR_MASK 0x00100000
44 #define TPM_GUARD_TIME_RW_MASK 0x00080000
45 #define TPM_GUARD_TIME_WR_MASK 0x00040000
46 #define TPM_GUARD_TIME_WW_MASK 0x00020000
47 #define TPM_GUARD_TIME_MIN_MASK 0x0001FE00
48 #define TPM_GUARD_TIME_MIN_SHIFT 9
50 /* Masks with bits that must be read zero */
51 #define TPM_ACCESS_READ_ZERO 0x48
52 #define TPM_INT_ENABLE_ZERO 0x7FFFFF60
53 #define TPM_STS_READ_ZERO 0x23
54 #define TPM_INTF_CAPABILITY_ZERO 0x0FFFF000
55 #define TPM_I2C_INTERFACE_CAPABILITY_ZERO 0x80000000
57 struct tpm_tis_i2c_phy {
58 struct tpm_tis_data priv;
59 struct i2c_client *i2c_client;
61 bool guard_time_write;
67 static inline struct tpm_tis_i2c_phy *
68 to_tpm_tis_i2c_phy(struct tpm_tis_data *data)
70 return container_of(data, struct tpm_tis_i2c_phy, priv);
74 * tpm_tis_core uses the register addresses as defined in Table 19 "Allocation
75 * of Register Space for FIFO TPM Access" of the TCG PC Client PTP
76 * Specification. In order for this code to work together with tpm_tis_core,
77 * those addresses need to mapped to the registers defined for I2C TPMs in
78 * Table 51 "I2C-TPM Register Overview".
80 * For most addresses this can be done by simply stripping off the locality
81 * information from the address. A few addresses need to be mapped explicitly,
82 * since the corresponding I2C registers have been moved around. TPM_LOC_SEL is
83 * only defined for I2C TPMs and is also mapped explicitly here to distinguish
84 * it from TPM_ACCESS(0).
86 * Locality information is ignored, since this driver assumes exclusive access
87 * to the TPM and always uses locality 0.
89 static u8 tpm_tis_i2c_address_to_register(u32 addr)
91 addr &= TPM_TIS_REGISTER_MASK;
95 return TPM_I2C_ACCESS;
97 return TPM_I2C_LOC_SEL;
99 return TPM_I2C_DID_VID;
107 static int tpm_tis_i2c_retry_transfer_until_ack(struct tpm_tis_data *data,
110 struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
115 if (msg->flags & I2C_M_RD)
116 guard_time = phy->guard_time_read;
118 guard_time = phy->guard_time_write;
121 ret = i2c_transfer(phy->i2c_client->adapter, msg, 1);
123 usleep_range(GUARD_TIME_ERR_MIN, GUARD_TIME_ERR_MAX);
125 usleep_range(phy->guard_time_min, phy->guard_time_max);
126 /* retry on TPM NACK */
127 } while (ret < 0 && i++ < TPM_RETRY);
132 /* Check that bits which must be read zero are not set */
133 static int tpm_tis_i2c_sanity_check_read(u8 reg, u16 len, u8 *buf)
143 value = le16_to_cpup((__le16 *)buf);
146 value = le32_to_cpup((__le32 *)buf);
149 /* unknown length, skip check */
155 zero_mask = TPM_ACCESS_READ_ZERO;
157 case TPM_INT_ENABLE(0) & TPM_TIS_REGISTER_MASK:
158 zero_mask = TPM_INT_ENABLE_ZERO;
160 case TPM_STS(0) & TPM_TIS_REGISTER_MASK:
161 zero_mask = TPM_STS_READ_ZERO;
163 case TPM_INTF_CAPS(0) & TPM_TIS_REGISTER_MASK:
164 zero_mask = TPM_INTF_CAPABILITY_ZERO;
166 case TPM_I2C_INTERFACE_CAPABILITY:
167 zero_mask = TPM_I2C_INTERFACE_CAPABILITY_ZERO;
170 /* unknown register, skip check */
174 if (unlikely((value & zero_mask) != 0x00)) {
175 pr_debug("TPM I2C read of register 0x%02x failed sanity check: 0x%x\n", reg, value);
182 static int tpm_tis_i2c_read_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
183 u8 *result, enum tpm_tis_io_mode io_mode)
185 struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
186 struct i2c_msg msg = { .addr = phy->i2c_client->addr };
187 u8 reg = tpm_tis_i2c_address_to_register(addr);
191 for (i = 0; i < TPM_RETRY; i++) {
193 msg.len = sizeof(reg);
196 ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
203 msg.flags = I2C_M_RD;
204 ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
208 ret = tpm_tis_i2c_sanity_check_read(reg, len, result);
212 usleep_range(GUARD_TIME_ERR_MIN, GUARD_TIME_ERR_MAX);
218 static int tpm_tis_i2c_write_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
220 enum tpm_tis_io_mode io_mode)
222 struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
223 struct i2c_msg msg = { .addr = phy->i2c_client->addr };
224 u8 reg = tpm_tis_i2c_address_to_register(addr);
227 if (len > TPM_BUFSIZE - 1)
230 /* write register and data in one go */
231 phy->io_buf[0] = reg;
232 memcpy(phy->io_buf + sizeof(reg), value, len);
234 msg.len = sizeof(reg) + len;
235 msg.buf = phy->io_buf;
236 ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
243 static int tpm_tis_i2c_verify_crc(struct tpm_tis_data *data, size_t len,
246 u16 crc_tpm, crc_host;
249 rc = tpm_tis_read16(data, TPM_DATA_CSUM, &crc_tpm);
253 /* reflect crc result, regardless of host endianness */
254 crc_host = swab16(crc_ccitt(0, value, len));
255 if (crc_tpm != crc_host)
263 * After each I2C operation, the TPM might require the master to wait.
264 * The time period is vendor-specific and must be read from the
265 * TPM_I2C_INTERFACE_CAPABILITY register.
267 * Before the Guard Time is read (or after the TPM failed to send an I2C NACK),
268 * a Guard Time of 250µs applies.
270 * Various flags in the same register indicate if a guard time is needed:
271 * - SR: <I2C read with repeated start> <guard time> <I2C read>
272 * - RR: <I2C read> <guard time> <I2C read>
273 * - RW: <I2C read> <guard time> <I2C write>
274 * - WR: <I2C write> <guard time> <I2C read>
275 * - WW: <I2C write> <guard time> <I2C write>
277 * See TCG PC Client PTP Specification v1.04, 8.1.10 GUARD_TIME
279 static int tpm_tis_i2c_init_guard_time(struct tpm_tis_i2c_phy *phy)
284 phy->guard_time_read = true;
285 phy->guard_time_write = true;
286 phy->guard_time_min = GUARD_TIME_DEFAULT_MIN;
287 phy->guard_time_max = GUARD_TIME_DEFAULT_MAX;
289 ret = tpm_tis_i2c_read_bytes(&phy->priv, TPM_I2C_INTERFACE_CAPABILITY,
290 sizeof(i2c_caps), (u8 *)&i2c_caps,
295 phy->guard_time_read = (i2c_caps & TPM_GUARD_TIME_RR_MASK) ||
296 (i2c_caps & TPM_GUARD_TIME_RW_MASK);
297 phy->guard_time_write = (i2c_caps & TPM_GUARD_TIME_WR_MASK) ||
298 (i2c_caps & TPM_GUARD_TIME_WW_MASK);
299 phy->guard_time_min = (i2c_caps & TPM_GUARD_TIME_MIN_MASK) >>
300 TPM_GUARD_TIME_MIN_SHIFT;
301 /* guard_time_max = guard_time_min * 1.2 */
302 phy->guard_time_max = phy->guard_time_min + phy->guard_time_min / 5;
307 static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume);
309 static const struct tpm_tis_phy_ops tpm_i2c_phy_ops = {
310 .read_bytes = tpm_tis_i2c_read_bytes,
311 .write_bytes = tpm_tis_i2c_write_bytes,
312 .verify_crc = tpm_tis_i2c_verify_crc,
315 static int tpm_tis_i2c_probe(struct i2c_client *dev)
317 struct tpm_tis_i2c_phy *phy;
318 const u8 crc_enable = 1;
319 const u8 locality = 0;
322 phy = devm_kzalloc(&dev->dev, sizeof(struct tpm_tis_i2c_phy),
327 phy->io_buf = devm_kzalloc(&dev->dev, TPM_BUFSIZE, GFP_KERNEL);
331 set_bit(TPM_TIS_DEFAULT_CANCELLATION, &phy->priv.flags);
332 phy->i2c_client = dev;
334 /* must precede all communication with the tpm */
335 ret = tpm_tis_i2c_init_guard_time(phy);
339 ret = tpm_tis_i2c_write_bytes(&phy->priv, TPM_LOC_SEL, sizeof(locality),
340 &locality, TPM_TIS_PHYS_8);
344 ret = tpm_tis_i2c_write_bytes(&phy->priv, TPM_I2C_DATA_CSUM_ENABLE,
345 sizeof(crc_enable), &crc_enable,
350 return tpm_tis_core_init(&dev->dev, &phy->priv, -1, &tpm_i2c_phy_ops,
354 static void tpm_tis_i2c_remove(struct i2c_client *client)
356 struct tpm_chip *chip = i2c_get_clientdata(client);
358 tpm_chip_unregister(chip);
359 tpm_tis_remove(chip);
362 static const struct i2c_device_id tpm_tis_i2c_id[] = {
363 { "tpm_tis_i2c", 0 },
366 MODULE_DEVICE_TABLE(i2c, tpm_tis_i2c_id);
369 static const struct of_device_id of_tis_i2c_match[] = {
370 { .compatible = "infineon,slb9673", },
373 MODULE_DEVICE_TABLE(of, of_tis_i2c_match);
376 static struct i2c_driver tpm_tis_i2c_driver = {
378 .name = "tpm_tis_i2c",
380 .of_match_table = of_match_ptr(of_tis_i2c_match),
382 .probe_new = tpm_tis_i2c_probe,
383 .remove = tpm_tis_i2c_remove,
384 .id_table = tpm_tis_i2c_id,
386 module_i2c_driver(tpm_tis_i2c_driver);
388 MODULE_DESCRIPTION("TPM Driver for native I2C access");
389 MODULE_LICENSE("GPL");