drivers/char/agp/intel-gtt.c

   1 /*
   2  * Intel GTT (Graphics Translation Table) routines
   3  *
   4  * Caveat: This driver implements the linux agp interface, but this is far from
   5  * a agp driver! GTT support ended up here for purely historical reasons: The
   6  * old userspace intel graphics drivers needed an interface to map memory into
   7  * the GTT. And the drm provides a default interface for graphic devices sitting
   8  * on an agp port. So it made sense to fake the GTT support as an agp port to
   9  * avoid having to create a new api.
  10  *
  11  * With gem this does not make much sense anymore, just needlessly complicates
  12  * the code. But as long as the old graphics stack is still support, it's stuck
  13  * here.
  14  *
  15  * /fairy-tale-mode off
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/pagemap.h>
  23 #include <linux/agp_backend.h>
  24 #include <asm/smp.h>
  25 #include "agp.h"
  26 #include "intel-agp.h"
  27 #include <linux/intel-gtt.h>
  28 #include <drm/intel-gtt.h>
  29
  30 /*
  31  * If we have Intel graphics, we're not going to have anything other than
  32  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  33  * on the Intel IOMMU support (CONFIG_DMAR).
  34  * Only newer chipsets need to bother with this, of course.
  35  */
  36 #ifdef CONFIG_DMAR
  37 #define USE_PCI_DMA_API 1
  38 #endif
  39
  40 /* Max amount of stolen space, anything above will be returned to Linux */
  41 int intel_max_stolen = 32 * 1024 * 1024;
  42 EXPORT_SYMBOL(intel_max_stolen);
  43
  44 static const struct aper_size_info_fixed intel_i810_sizes[] =
  45 {
  46         {64, 16384, 4},
  47         /* The 32M mode still requires a 64k gatt */
  48         {32, 8192, 4}
  49 };
  50
  51 #define AGP_DCACHE_MEMORY       1
  52 #define AGP_PHYS_MEMORY         2
  53 #define INTEL_AGP_CACHED_MEMORY 3
  54
  55 static struct gatt_mask intel_i810_masks[] =
  56 {
  57         {.mask = I810_PTE_VALID, .type = 0},
  58         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
  59         {.mask = I810_PTE_VALID, .type = 0},
  60         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
  61          .type = INTEL_AGP_CACHED_MEMORY}
  62 };
  63
  64 #define INTEL_AGP_UNCACHED_MEMORY              0
  65 #define INTEL_AGP_CACHED_MEMORY_LLC            1
  66 #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT       2
  67 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC        3
  68 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT   4
  69
  70 static struct gatt_mask intel_gen6_masks[] =
  71 {
  72         {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED,
  73          .type = INTEL_AGP_UNCACHED_MEMORY },
  74         {.mask = I810_PTE_VALID | GEN6_PTE_LLC,
  75          .type = INTEL_AGP_CACHED_MEMORY_LLC },
  76         {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT,
  77          .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT },
  78         {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC,
  79          .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC },
  80         {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT,
  81          .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT },
  82 };
  83
  84 static struct _intel_private {
  85         struct intel_gtt base;
  86         struct pci_dev *pcidev; /* device one */
  87         u8 __iomem *registers;
  88         u32 __iomem *gtt;               /* I915G */
  89         int num_dcache_entries;
  90         union {
  91                 void __iomem *i9xx_flush_page;
  92                 void *i8xx_flush_page;
  93         };
  94         struct page *i8xx_page;
  95         struct resource ifp_resource;
  96         int resource_valid;
  97 } intel_private;
  98
  99 #ifdef USE_PCI_DMA_API
 100 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
 101 {
 102         *ret = pci_map_page(intel_private.pcidev, page, 0,
 103                             PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 104         if (pci_dma_mapping_error(intel_private.pcidev, *ret))
 105                 return -EINVAL;
 106         return 0;
 107 }
 108
 109 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
 110 {
 111         pci_unmap_page(intel_private.pcidev, dma,
 112                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 113 }
 114
 115 static void intel_agp_free_sglist(struct agp_memory *mem)
 116 {
 117         struct sg_table st;
 118
 119         st.sgl = mem->sg_list;
 120         st.orig_nents = st.nents = mem->page_count;
 121
 122         sg_free_table(&st);
 123
 124         mem->sg_list = NULL;
 125         mem->num_sg = 0;
 126 }
 127
 128 static int intel_agp_map_memory(struct agp_memory *mem)
 129 {
 130         struct sg_table st;
 131         struct scatterlist *sg;
 132         int i;
 133
 134         DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
 135
 136         if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
 137                 goto err;
 138
 139         mem->sg_list = sg = st.sgl;
 140
 141         for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
 142                 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
 143
 144         mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
 145                                  mem->page_count, PCI_DMA_BIDIRECTIONAL);
 146         if (unlikely(!mem->num_sg))
 147                 goto err;
 148
 149         return 0;
 150
 151 err:
 152         sg_free_table(&st);
 153         return -ENOMEM;
 154 }
 155
 156 static void intel_agp_unmap_memory(struct agp_memory *mem)
 157 {
 158         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 159
 160         pci_unmap_sg(intel_private.pcidev, mem->sg_list,
 161                      mem->page_count, PCI_DMA_BIDIRECTIONAL);
 162         intel_agp_free_sglist(mem);
 163 }
 164
 165 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 166                                         off_t pg_start, int mask_type)
 167 {
 168         struct scatterlist *sg;
 169         int i, j;
 170
 171         j = pg_start;
 172
 173         WARN_ON(!mem->num_sg);
 174
 175         if (mem->num_sg == mem->page_count) {
 176                 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
 177                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 178                                         sg_dma_address(sg), mask_type),
 179                                         intel_private.gtt+j);
 180                         j++;
 181                 }
 182         } else {
 183                 /* sg may merge pages, but we have to separate
 184                  * per-page addr for GTT */
 185                 unsigned int len, m;
 186
 187                 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
 188                         len = sg_dma_len(sg) / PAGE_SIZE;
 189                         for (m = 0; m < len; m++) {
 190                                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 191                                                                        sg_dma_address(sg) + m * PAGE_SIZE,
 192                                                                        mask_type),
 193                                        intel_private.gtt+j);
 194                                 j++;
 195                         }
 196                 }
 197         }
 198         readl(intel_private.gtt+j-1);
 199 }
 200
 201 #else
 202
 203 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 204                                         off_t pg_start, int mask_type)
 205 {
 206         int i, j;
 207
 208         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 209                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 210                                 page_to_phys(mem->pages[i]), mask_type),
 211                        intel_private.gtt+j);
 212         }
 213
 214         readl(intel_private.gtt+j-1);
 215 }
 216
 217 #endif
 218
 219 static int intel_i810_fetch_size(void)
 220 {
 221         u32 smram_miscc;
 222         struct aper_size_info_fixed *values;
 223
 224         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 225         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 226
 227         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 228                 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
 229                 return 0;
 230         }
 231         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 232                 agp_bridge->current_size = (void *) (values + 1);
 233                 agp_bridge->aperture_size_idx = 1;
 234                 return values[1].size;
 235         } else {
 236                 agp_bridge->current_size = (void *) (values);
 237                 agp_bridge->aperture_size_idx = 0;
 238                 return values[0].size;
 239         }
 240
 241         return 0;
 242 }
 243
 244 static int intel_i810_configure(void)
 245 {
 246         struct aper_size_info_fixed *current_size;
 247         u32 temp;
 248         int i;
 249
 250         current_size = A_SIZE_FIX(agp_bridge->current_size);
 251
 252         if (!intel_private.registers) {
 253                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 254                 temp &= 0xfff80000;
 255
 256                 intel_private.registers = ioremap(temp, 128 * 4096);
 257                 if (!intel_private.registers) {
 258                         dev_err(&intel_private.pcidev->dev,
 259                                 "can't remap memory\n");
 260                         return -ENOMEM;
 261                 }
 262         }
 263
 264         if ((readl(intel_private.registers+I810_DRAM_CTL)
 265                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 266                 /* This will need to be dynamically assigned */
 267                 dev_info(&intel_private.pcidev->dev,
 268                          "detected 4MB dedicated video ram\n");
 269                 intel_private.num_dcache_entries = 1024;
 270         }
 271         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 272         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 273         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 274         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 275
 276         if (agp_bridge->driver->needs_scratch_page) {
 277                 for (i = 0; i < current_size->num_entries; i++) {
 278                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 279                 }
 280                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
 281         }
 282         global_cache_flush();
 283         return 0;
 284 }
 285
 286 static void intel_i810_cleanup(void)
 287 {
 288         writel(0, intel_private.registers+I810_PGETBL_CTL);
 289         readl(intel_private.registers); /* PCI Posting. */
 290         iounmap(intel_private.registers);
 291 }
 292
 293 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 294 {
 295         return;
 296 }
 297
 298 /* Exists to support ARGB cursors */
 299 static struct page *i8xx_alloc_pages(void)
 300 {
 301         struct page *page;
 302
 303         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 304         if (page == NULL)
 305                 return NULL;
 306
 307         if (set_pages_uc(page, 4) < 0) {
 308                 set_pages_wb(page, 4);
 309                 __free_pages(page, 2);
 310                 return NULL;
 311         }
 312         get_page(page);
 313         atomic_inc(&agp_bridge->current_memory_agp);
 314         return page;
 315 }
 316
 317 static void i8xx_destroy_pages(struct page *page)
 318 {
 319         if (page == NULL)
 320                 return;
 321
 322         set_pages_wb(page, 4);
 323         put_page(page);
 324         __free_pages(page, 2);
 325         atomic_dec(&agp_bridge->current_memory_agp);
 326 }
 327
 328 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 329                                         int type)
 330 {
 331         if (type < AGP_USER_TYPES)
 332                 return type;
 333         else if (type == AGP_USER_CACHED_MEMORY)
 334                 return INTEL_AGP_CACHED_MEMORY;
 335         else
 336                 return 0;
 337 }
 338
 339 static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge,
 340                                         int type)
 341 {
 342         unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT;
 343         unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT;
 344
 345         if (type_mask == AGP_USER_UNCACHED_MEMORY)
 346                 return INTEL_AGP_UNCACHED_MEMORY;
 347         else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
 348                 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT :
 349                               INTEL_AGP_CACHED_MEMORY_LLC_MLC;
 350         else /* set 'normal'/'cached' to LLC by default */
 351                 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT :
 352                               INTEL_AGP_CACHED_MEMORY_LLC;
 353 }
 354
 355
 356 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 357                                 int type)
 358 {
 359         int i, j, num_entries;
 360         void *temp;
 361         int ret = -EINVAL;
 362         int mask_type;
 363
 364         if (mem->page_count == 0)
 365                 goto out;
 366
 367         temp = agp_bridge->current_size;
 368         num_entries = A_SIZE_FIX(temp)->num_entries;
 369
 370         if ((pg_start + mem->page_count) > num_entries)
 371                 goto out_err;
 372
 373
 374         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 375                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 376                         ret = -EBUSY;
 377                         goto out_err;
 378                 }
 379         }
 380
 381         if (type != mem->type)
 382                 goto out_err;
 383
 384         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 385
 386         switch (mask_type) {
 387         case AGP_DCACHE_MEMORY:
 388                 if (!mem->is_flushed)
 389                         global_cache_flush();
 390                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 391                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 392                                intel_private.registers+I810_PTE_BASE+(i*4));
 393                 }
 394                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 395                 break;
 396         case AGP_PHYS_MEMORY:
 397         case AGP_NORMAL_MEMORY:
 398                 if (!mem->is_flushed)
 399                         global_cache_flush();
 400                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 401                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 402                                         page_to_phys(mem->pages[i]), mask_type),
 403                                intel_private.registers+I810_PTE_BASE+(j*4));
 404                 }
 405                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 406                 break;
 407         default:
 408                 goto out_err;
 409         }
 410
 411 out:
 412         ret = 0;
 413 out_err:
 414         mem->is_flushed = true;
 415         return ret;
 416 }
 417
 418 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 419                                 int type)
 420 {
 421         int i;
 422
 423         if (mem->page_count == 0)
 424                 return 0;
 425
 426         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 427                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 428         }
 429         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 430
 431         return 0;
 432 }
 433
 434 /*
 435  * The i810/i830 requires a physical address to program its mouse
 436  * pointer into hardware.
 437  * However the Xserver still writes to it through the agp aperture.
 438  */
 439 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 440 {
 441         struct agp_memory *new;
 442         struct page *page;
 443
 444         switch (pg_count) {
 445         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 446                 break;
 447         case 4:
 448                 /* kludge to get 4 physical pages for ARGB cursor */
 449                 page = i8xx_alloc_pages();
 450                 break;
 451         default:
 452                 return NULL;
 453         }
 454
 455         if (page == NULL)
 456                 return NULL;
 457
 458         new = agp_create_memory(pg_count);
 459         if (new == NULL)
 460                 return NULL;
 461
 462         new->pages[0] = page;
 463         if (pg_count == 4) {
 464                 /* kludge to get 4 physical pages for ARGB cursor */
 465                 new->pages[1] = new->pages[0] + 1;
 466                 new->pages[2] = new->pages[1] + 1;
 467                 new->pages[3] = new->pages[2] + 1;
 468         }
 469         new->page_count = pg_count;
 470         new->num_scratch_pages = pg_count;
 471         new->type = AGP_PHYS_MEMORY;
 472         new->physical = page_to_phys(new->pages[0]);
 473         return new;
 474 }
 475
 476 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 477 {
 478         struct agp_memory *new;
 479
 480         if (type == AGP_DCACHE_MEMORY) {
 481                 if (pg_count != intel_private.num_dcache_entries)
 482                         return NULL;
 483
 484                 new = agp_create_memory(1);
 485                 if (new == NULL)
 486                         return NULL;
 487
 488                 new->type = AGP_DCACHE_MEMORY;
 489                 new->page_count = pg_count;
 490                 new->num_scratch_pages = 0;
 491                 agp_free_page_array(new);
 492                 return new;
 493         }
 494         if (type == AGP_PHYS_MEMORY)
 495                 return alloc_agpphysmem_i8xx(pg_count, type);
 496         return NULL;
 497 }
 498
 499 static void intel_i810_free_by_type(struct agp_memory *curr)
 500 {
 501         agp_free_key(curr->key);
 502         if (curr->type == AGP_PHYS_MEMORY) {
 503                 if (curr->page_count == 4)
 504                         i8xx_destroy_pages(curr->pages[0]);
 505                 else {
 506                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 507                                                              AGP_PAGE_DESTROY_UNMAP);
 508                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 509                                                              AGP_PAGE_DESTROY_FREE);
 510                 }
 511                 agp_free_page_array(curr);
 512         }
 513         kfree(curr);
 514 }
 515
 516 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 517                                             dma_addr_t addr, int type)
 518 {
 519         /* Type checking must be done elsewhere */
 520         return addr | bridge->driver->masks[type].mask;
 521 }
 522
 523 static struct aper_size_info_fixed intel_i830_sizes[] =
 524 {
 525         {128, 32768, 5},
 526         /* The 64M mode still requires a 128k gatt */
 527         {64, 16384, 5},
 528         {256, 65536, 6},
 529         {512, 131072, 7},
 530 };
 531
 532 static void intel_i830_init_gtt_entries(void)
 533 {
 534         u16 gmch_ctrl;
 535         int gtt_entries = 0;
 536         u8 rdct;
 537         int local = 0;
 538         static const int ddt[4] = { 0, 16, 32, 64 };
 539         int size; /* reserved space (in kb) at the top of stolen memory */
 540
 541         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 542
 543         if (IS_I965) {
 544                 u32 pgetbl_ctl;
 545                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 546
 547                 /* The 965 has a field telling us the size of the GTT,
 548                  * which may be larger than what is necessary to map the
 549                  * aperture.
 550                  */
 551                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 552                 case I965_PGETBL_SIZE_128KB:
 553                         size = 128;
 554                         break;
 555                 case I965_PGETBL_SIZE_256KB:
 556                         size = 256;
 557                         break;
 558                 case I965_PGETBL_SIZE_512KB:
 559                         size = 512;
 560                         break;
 561                 case I965_PGETBL_SIZE_1MB:
 562                         size = 1024;
 563                         break;
 564                 case I965_PGETBL_SIZE_2MB:
 565                         size = 2048;
 566                         break;
 567                 case I965_PGETBL_SIZE_1_5MB:
 568                         size = 1024 + 512;
 569                         break;
 570                 default:
 571                         dev_info(&intel_private.pcidev->dev,
 572                                  "unknown page table size, assuming 512KB\n");
 573                         size = 512;
 574                 }
 575                 size += 4; /* add in BIOS popup space */
 576         } else if (IS_G33 && !IS_PINEVIEW) {
 577         /* G33's GTT size defined in gmch_ctrl */
 578                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 579                 case G33_PGETBL_SIZE_1M:
 580                         size = 1024;
 581                         break;
 582                 case G33_PGETBL_SIZE_2M:
 583                         size = 2048;
 584                         break;
 585                 default:
 586                         dev_info(&agp_bridge->dev->dev,
 587                                  "unknown page table size 0x%x, assuming 512KB\n",
 588                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 589                         size = 512;
 590                 }
 591                 size += 4;
 592         } else if (IS_G4X || IS_PINEVIEW) {
 593                 /* On 4 series hardware, GTT stolen is separate from graphics
 594                  * stolen, ignore it in stolen gtt entries counting.  However,
 595                  * 4KB of the stolen memory doesn't get mapped to the GTT.
 596                  */
 597                 size = 4;
 598         } else {
 599                 /* On previous hardware, the GTT size was just what was
 600                  * required to map the aperture.
 601                  */
 602                 size = agp_bridge->driver->fetch_size() + 4;
 603         }
 604
 605         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 606             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 607                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 608                 case I830_GMCH_GMS_STOLEN_512:
 609                         gtt_entries = KB(512) - KB(size);
 610                         break;
 611                 case I830_GMCH_GMS_STOLEN_1024:
 612                         gtt_entries = MB(1) - KB(size);
 613                         break;
 614                 case I830_GMCH_GMS_STOLEN_8192:
 615                         gtt_entries = MB(8) - KB(size);
 616                         break;
 617                 case I830_GMCH_GMS_LOCAL:
 618                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 619                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 620                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 621                         local = 1;
 622                         break;
 623                 default:
 624                         gtt_entries = 0;
 625                         break;
 626                 }
 627         } else if (IS_SNB) {
 628                 /*
 629                  * SandyBridge has new memory control reg at 0x50.w
 630                  */
 631                 u16 snb_gmch_ctl;
 632                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 633                 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
 634                 case SNB_GMCH_GMS_STOLEN_32M:
 635                         gtt_entries = MB(32) - KB(size);
 636                         break;
 637                 case SNB_GMCH_GMS_STOLEN_64M:
 638                         gtt_entries = MB(64) - KB(size);
 639                         break;
 640                 case SNB_GMCH_GMS_STOLEN_96M:
 641                         gtt_entries = MB(96) - KB(size);
 642                         break;
 643                 case SNB_GMCH_GMS_STOLEN_128M:
 644                         gtt_entries = MB(128) - KB(size);
 645                         break;
 646                 case SNB_GMCH_GMS_STOLEN_160M:
 647                         gtt_entries = MB(160) - KB(size);
 648                         break;
 649                 case SNB_GMCH_GMS_STOLEN_192M:
 650                         gtt_entries = MB(192) - KB(size);
 651                         break;
 652                 case SNB_GMCH_GMS_STOLEN_224M:
 653                         gtt_entries = MB(224) - KB(size);
 654                         break;
 655                 case SNB_GMCH_GMS_STOLEN_256M:
 656                         gtt_entries = MB(256) - KB(size);
 657                         break;
 658                 case SNB_GMCH_GMS_STOLEN_288M:
 659                         gtt_entries = MB(288) - KB(size);
 660                         break;
 661                 case SNB_GMCH_GMS_STOLEN_320M:
 662                         gtt_entries = MB(320) - KB(size);
 663                         break;
 664                 case SNB_GMCH_GMS_STOLEN_352M:
 665                         gtt_entries = MB(352) - KB(size);
 666                         break;
 667                 case SNB_GMCH_GMS_STOLEN_384M:
 668                         gtt_entries = MB(384) - KB(size);
 669                         break;
 670                 case SNB_GMCH_GMS_STOLEN_416M:
 671                         gtt_entries = MB(416) - KB(size);
 672                         break;
 673                 case SNB_GMCH_GMS_STOLEN_448M:
 674                         gtt_entries = MB(448) - KB(size);
 675                         break;
 676                 case SNB_GMCH_GMS_STOLEN_480M:
 677                         gtt_entries = MB(480) - KB(size);
 678                         break;
 679                 case SNB_GMCH_GMS_STOLEN_512M:
 680                         gtt_entries = MB(512) - KB(size);
 681                         break;
 682                 }
 683         } else {
 684                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 685                 case I855_GMCH_GMS_STOLEN_1M:
 686                         gtt_entries = MB(1) - KB(size);
 687                         break;
 688                 case I855_GMCH_GMS_STOLEN_4M:
 689                         gtt_entries = MB(4) - KB(size);
 690                         break;
 691                 case I855_GMCH_GMS_STOLEN_8M:
 692                         gtt_entries = MB(8) - KB(size);
 693                         break;
 694                 case I855_GMCH_GMS_STOLEN_16M:
 695                         gtt_entries = MB(16) - KB(size);
 696                         break;
 697                 case I855_GMCH_GMS_STOLEN_32M:
 698                         gtt_entries = MB(32) - KB(size);
 699                         break;
 700                 case I915_GMCH_GMS_STOLEN_48M:
 701                         /* Check it's really I915G */
 702                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 703                                 gtt_entries = MB(48) - KB(size);
 704                         else
 705                                 gtt_entries = 0;
 706                         break;
 707                 case I915_GMCH_GMS_STOLEN_64M:
 708                         /* Check it's really I915G */
 709                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 710                                 gtt_entries = MB(64) - KB(size);
 711                         else
 712                                 gtt_entries = 0;
 713                         break;
 714                 case G33_GMCH_GMS_STOLEN_128M:
 715                         if (IS_G33 || IS_I965 || IS_G4X)
 716                                 gtt_entries = MB(128) - KB(size);
 717                         else
 718                                 gtt_entries = 0;
 719                         break;
 720                 case G33_GMCH_GMS_STOLEN_256M:
 721                         if (IS_G33 || IS_I965 || IS_G4X)
 722                                 gtt_entries = MB(256) - KB(size);
 723                         else
 724                                 gtt_entries = 0;
 725                         break;
 726                 case INTEL_GMCH_GMS_STOLEN_96M:
 727                         if (IS_I965 || IS_G4X)
 728                                 gtt_entries = MB(96) - KB(size);
 729                         else
 730                                 gtt_entries = 0;
 731                         break;
 732                 case INTEL_GMCH_GMS_STOLEN_160M:
 733                         if (IS_I965 || IS_G4X)
 734                                 gtt_entries = MB(160) - KB(size);
 735                         else
 736                                 gtt_entries = 0;
 737                         break;
 738                 case INTEL_GMCH_GMS_STOLEN_224M:
 739                         if (IS_I965 || IS_G4X)
 740                                 gtt_entries = MB(224) - KB(size);
 741                         else
 742                                 gtt_entries = 0;
 743                         break;
 744                 case INTEL_GMCH_GMS_STOLEN_352M:
 745                         if (IS_I965 || IS_G4X)
 746                                 gtt_entries = MB(352) - KB(size);
 747                         else
 748                                 gtt_entries = 0;
 749                         break;
 750                 default:
 751                         gtt_entries = 0;
 752                         break;
 753                 }
 754         }
 755         if (!local && gtt_entries > intel_max_stolen) {
 756                 dev_info(&agp_bridge->dev->dev,
 757                          "detected %dK stolen memory, trimming to %dK\n",
 758                          gtt_entries / KB(1), intel_max_stolen / KB(1));
 759                 gtt_entries = intel_max_stolen / KB(4);
 760         } else if (gtt_entries > 0) {
 761                 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
 762                        gtt_entries / KB(1), local ? "local" : "stolen");
 763                 gtt_entries /= KB(4);
 764         } else {
 765                 dev_info(&agp_bridge->dev->dev,
 766                        "no pre-allocated video memory detected\n");
 767                 gtt_entries = 0;
 768         }
 769
 770         intel_private.base.gtt_stolen_entries = gtt_entries;
 771 }
 772
 773 static void intel_i830_fini_flush(void)
 774 {
 775         kunmap(intel_private.i8xx_page);
 776         intel_private.i8xx_flush_page = NULL;
 777         unmap_page_from_agp(intel_private.i8xx_page);
 778
 779         __free_page(intel_private.i8xx_page);
 780         intel_private.i8xx_page = NULL;
 781 }
 782
 783 static void intel_i830_setup_flush(void)
 784 {
 785         /* return if we've already set the flush mechanism up */
 786         if (intel_private.i8xx_page)
 787                 return;
 788
 789         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 790         if (!intel_private.i8xx_page)
 791                 return;
 792
 793         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 794         if (!intel_private.i8xx_flush_page)
 795                 intel_i830_fini_flush();
 796 }
 797
 798 /* The chipset_flush interface needs to get data that has already been
 799  * flushed out of the CPU all the way out to main memory, because the GPU
 800  * doesn't snoop those buffers.
 801  *
 802  * The 8xx series doesn't have the same lovely interface for flushing the
 803  * chipset write buffers that the later chips do. According to the 865
 804  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 805  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 806  * that it'll push whatever was in there out.  It appears to work.
 807  */
 808 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 809 {
 810         unsigned int *pg = intel_private.i8xx_flush_page;
 811
 812         memset(pg, 0, 1024);
 813
 814         if (cpu_has_clflush)
 815                 clflush_cache_range(pg, 1024);
 816         else if (wbinvd_on_all_cpus() != 0)
 817                 printk(KERN_ERR "Timed out waiting for cache flush.\n");
 818 }
 819
 820 /* The intel i830 automatically initializes the agp aperture during POST.
 821  * Use the memory already set aside for in the GTT.
 822  */
 823 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 824 {
 825         int page_order;
 826         struct aper_size_info_fixed *size;
 827         int num_entries;
 828         u32 temp;
 829
 830         size = agp_bridge->current_size;
 831         page_order = size->page_order;
 832         num_entries = size->num_entries;
 833         agp_bridge->gatt_table_real = NULL;
 834
 835         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 836         temp &= 0xfff80000;
 837
 838         intel_private.registers = ioremap(temp, 128 * 4096);
 839         if (!intel_private.registers)
 840                 return -ENOMEM;
 841
 842         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 843         global_cache_flush();   /* FIXME: ?? */
 844
 845         /* we have to call this as early as possible after the MMIO base address is known */
 846         intel_i830_init_gtt_entries();
 847         if (intel_private.base.gtt_stolen_entries == 0) {
 848                 iounmap(intel_private.registers);
 849                 return -ENOMEM;
 850         }
 851
 852         agp_bridge->gatt_table = NULL;
 853
 854         agp_bridge->gatt_bus_addr = temp;
 855
 856         return 0;
 857 }
 858
 859 /* Return the gatt table to a sane state. Use the top of stolen
 860  * memory for the GTT.
 861  */
 862 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 863 {
 864         return 0;
 865 }
 866
 867 static int intel_i830_fetch_size(void)
 868 {
 869         u16 gmch_ctrl;
 870         struct aper_size_info_fixed *values;
 871
 872         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 873
 874         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 875             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 876                 /* 855GM/852GM/865G has 128MB aperture size */
 877                 agp_bridge->current_size = (void *) values;
 878                 agp_bridge->aperture_size_idx = 0;
 879                 return values[0].size;
 880         }
 881
 882         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 883
 884         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 885                 agp_bridge->current_size = (void *) values;
 886                 agp_bridge->aperture_size_idx = 0;
 887                 return values[0].size;
 888         } else {
 889                 agp_bridge->current_size = (void *) (values + 1);
 890                 agp_bridge->aperture_size_idx = 1;
 891                 return values[1].size;
 892         }
 893
 894         return 0;
 895 }
 896
 897 static int intel_i830_configure(void)
 898 {
 899         struct aper_size_info_fixed *current_size;
 900         u32 temp;
 901         u16 gmch_ctrl;
 902         int i;
 903
 904         current_size = A_SIZE_FIX(agp_bridge->current_size);
 905
 906         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 907         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 908
 909         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 910         gmch_ctrl |= I830_GMCH_ENABLED;
 911         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
 912
 913         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 914         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 915
 916         if (agp_bridge->driver->needs_scratch_page) {
 917                 for (i = intel_private.base.gtt_stolen_entries; i < current_size->num_entries; i++) {
 918                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 919                 }
 920                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
 921         }
 922
 923         global_cache_flush();
 924
 925         intel_i830_setup_flush();
 926         return 0;
 927 }
 928
 929 static void intel_i830_cleanup(void)
 930 {
 931         iounmap(intel_private.registers);
 932 }
 933
 934 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
 935                                      int type)
 936 {
 937         int i, j, num_entries;
 938         void *temp;
 939         int ret = -EINVAL;
 940         int mask_type;
 941
 942         if (mem->page_count == 0)
 943                 goto out;
 944
 945         temp = agp_bridge->current_size;
 946         num_entries = A_SIZE_FIX(temp)->num_entries;
 947
 948         if (pg_start < intel_private.base.gtt_stolen_entries) {
 949                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
 950                            "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
 951                            pg_start, intel_private.base.gtt_stolen_entries);
 952
 953                 dev_info(&intel_private.pcidev->dev,
 954                          "trying to insert into local/stolen memory\n");
 955                 goto out_err;
 956         }
 957
 958         if ((pg_start + mem->page_count) > num_entries)
 959                 goto out_err;
 960
 961         /* The i830 can't check the GTT for entries since its read only,
 962          * depend on the caller to make the correct offset decisions.
 963          */
 964
 965         if (type != mem->type)
 966                 goto out_err;
 967
 968         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 969
 970         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 971             mask_type != INTEL_AGP_CACHED_MEMORY)
 972                 goto out_err;
 973
 974         if (!mem->is_flushed)
 975                 global_cache_flush();
 976
 977         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 978                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 979                                 page_to_phys(mem->pages[i]), mask_type),
 980                        intel_private.registers+I810_PTE_BASE+(j*4));
 981         }
 982         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 983
 984 out:
 985         ret = 0;
 986 out_err:
 987         mem->is_flushed = true;
 988         return ret;
 989 }
 990
 991 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
 992                                      int type)
 993 {
 994         int i;
 995
 996         if (mem->page_count == 0)
 997                 return 0;
 998
 999         if (pg_start < intel_private.base.gtt_stolen_entries) {
1000                 dev_info(&intel_private.pcidev->dev,
1001                          "trying to disable local/stolen memory\n");
1002                 return -EINVAL;
1003         }
1004
1005         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1006                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1007         }
1008         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1009
1010         return 0;
1011 }
1012
1013 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1014 {
1015         if (type == AGP_PHYS_MEMORY)
1016                 return alloc_agpphysmem_i8xx(pg_count, type);
1017         /* always return NULL for other allocation types for now */
1018         return NULL;
1019 }
1020
1021 static int intel_alloc_chipset_flush_resource(void)
1022 {
1023         int ret;
1024         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1025                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1026                                      pcibios_align_resource, agp_bridge->dev);
1027
1028         return ret;
1029 }
1030
1031 static void intel_i915_setup_chipset_flush(void)
1032 {
1033         int ret;
1034         u32 temp;
1035
1036         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
1037         if (!(temp & 0x1)) {
1038                 intel_alloc_chipset_flush_resource();
1039                 intel_private.resource_valid = 1;
1040                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1041         } else {
1042                 temp &= ~1;
1043
1044                 intel_private.resource_valid = 1;
1045                 intel_private.ifp_resource.start = temp;
1046                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1047                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1048                 /* some BIOSes reserve this area in a pnp some don't */
1049                 if (ret)
1050                         intel_private.resource_valid = 0;
1051         }
1052 }
1053
1054 static void intel_i965_g33_setup_chipset_flush(void)
1055 {
1056         u32 temp_hi, temp_lo;
1057         int ret;
1058
1059         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
1060         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
1061
1062         if (!(temp_lo & 0x1)) {
1063
1064                 intel_alloc_chipset_flush_resource();
1065
1066                 intel_private.resource_valid = 1;
1067                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
1068                         upper_32_bits(intel_private.ifp_resource.start));
1069                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1070         } else {
1071                 u64 l64;
1072
1073                 temp_lo &= ~0x1;
1074                 l64 = ((u64)temp_hi << 32) | temp_lo;
1075
1076                 intel_private.resource_valid = 1;
1077                 intel_private.ifp_resource.start = l64;
1078                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1079                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1080                 /* some BIOSes reserve this area in a pnp some don't */
1081                 if (ret)
1082                         intel_private.resource_valid = 0;
1083         }
1084 }
1085
1086 static void intel_i9xx_setup_flush(void)
1087 {
1088         /* return if already configured */
1089         if (intel_private.ifp_resource.start)
1090                 return;
1091
1092         if (IS_SNB)
1093                 return;
1094
1095         /* setup a resource for this object */
1096         intel_private.ifp_resource.name = "Intel Flush Page";
1097         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1098
1099         /* Setup chipset flush for 915 */
1100         if (IS_I965 || IS_G33 || IS_G4X) {
1101                 intel_i965_g33_setup_chipset_flush();
1102         } else {
1103                 intel_i915_setup_chipset_flush();
1104         }
1105
1106         if (intel_private.ifp_resource.start)
1107                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1108         if (!intel_private.i9xx_flush_page)
1109                 dev_err(&intel_private.pcidev->dev,
1110                         "can't ioremap flush page - no chipset flushing\n");
1111 }
1112
1113 static int intel_i9xx_configure(void)
1114 {
1115         struct aper_size_info_fixed *current_size;
1116         u32 temp;
1117         u16 gmch_ctrl;
1118         int i;
1119
1120         current_size = A_SIZE_FIX(agp_bridge->current_size);
1121
1122         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1123
1124         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1125
1126         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1127         gmch_ctrl |= I830_GMCH_ENABLED;
1128         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1129
1130         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1131         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1132
1133         if (agp_bridge->driver->needs_scratch_page) {
1134                 for (i = intel_private.base.gtt_stolen_entries; i <
1135                                 intel_private.base.gtt_total_entries; i++) {
1136                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
1137                 }
1138                 readl(intel_private.gtt+i-1);   /* PCI Posting. */
1139         }
1140
1141         global_cache_flush();
1142
1143         intel_i9xx_setup_flush();
1144
1145         return 0;
1146 }
1147
1148 static void intel_i915_cleanup(void)
1149 {
1150         if (intel_private.i9xx_flush_page)
1151                 iounmap(intel_private.i9xx_flush_page);
1152         if (intel_private.resource_valid)
1153                 release_resource(&intel_private.ifp_resource);
1154         intel_private.ifp_resource.start = 0;
1155         intel_private.resource_valid = 0;
1156         iounmap(intel_private.gtt);
1157         iounmap(intel_private.registers);
1158 }
1159
1160 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1161 {
1162         if (intel_private.i9xx_flush_page)
1163                 writel(1, intel_private.i9xx_flush_page);
1164 }
1165
1166 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1167                                      int type)
1168 {
1169         int num_entries;
1170         void *temp;
1171         int ret = -EINVAL;
1172         int mask_type;
1173
1174         if (mem->page_count == 0)
1175                 goto out;
1176
1177         temp = agp_bridge->current_size;
1178         num_entries = A_SIZE_FIX(temp)->num_entries;
1179
1180         if (pg_start < intel_private.base.gtt_stolen_entries) {
1181                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1182                            "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1183                            pg_start, intel_private.base.gtt_stolen_entries);
1184
1185                 dev_info(&intel_private.pcidev->dev,
1186                          "trying to insert into local/stolen memory\n");
1187                 goto out_err;
1188         }
1189
1190         if ((pg_start + mem->page_count) > num_entries)
1191                 goto out_err;
1192
1193         /* The i915 can't check the GTT for entries since it's read only;
1194          * depend on the caller to make the correct offset decisions.
1195          */
1196
1197         if (type != mem->type)
1198                 goto out_err;
1199
1200         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1201
1202         if (!IS_SNB && mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1203             mask_type != INTEL_AGP_CACHED_MEMORY)
1204                 goto out_err;
1205
1206         if (!mem->is_flushed)
1207                 global_cache_flush();
1208
1209         intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1210
1211  out:
1212         ret = 0;
1213  out_err:
1214         mem->is_flushed = true;
1215         return ret;
1216 }
1217
1218 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1219                                      int type)
1220 {
1221         int i;
1222
1223         if (mem->page_count == 0)
1224                 return 0;
1225
1226         if (pg_start < intel_private.base.gtt_stolen_entries) {
1227                 dev_info(&intel_private.pcidev->dev,
1228                          "trying to disable local/stolen memory\n");
1229                 return -EINVAL;
1230         }
1231
1232         for (i = pg_start; i < (mem->page_count + pg_start); i++)
1233                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1234
1235         readl(intel_private.gtt+i-1);
1236
1237         return 0;
1238 }
1239
1240 /* Return the aperture size by just checking the resource length.  The effect
1241  * described in the spec of the MSAC registers is just changing of the
1242  * resource size.
1243  */
1244 static int intel_i9xx_fetch_size(void)
1245 {
1246         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1247         int aper_size; /* size in megabytes */
1248         int i;
1249
1250         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1251
1252         for (i = 0; i < num_sizes; i++) {
1253                 if (aper_size == intel_i830_sizes[i].size) {
1254                         agp_bridge->current_size = intel_i830_sizes + i;
1255                         return aper_size;
1256                 }
1257         }
1258
1259         return 0;
1260 }
1261
1262 static int intel_i915_get_gtt_size(void)
1263 {
1264         int size;
1265
1266         if (IS_G33) {
1267                 u16 gmch_ctrl;
1268
1269                 /* G33's GTT size defined in gmch_ctrl */
1270                 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1271                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
1272                 case I830_GMCH_GMS_STOLEN_512:
1273                         size = 512;
1274                         break;
1275                 case I830_GMCH_GMS_STOLEN_1024:
1276                         size = 1024;
1277                         break;
1278                 case I830_GMCH_GMS_STOLEN_8192:
1279                         size = 8*1024;
1280                         break;
1281                 default:
1282                         dev_info(&agp_bridge->dev->dev,
1283                                  "unknown page table size 0x%x, assuming 512KB\n",
1284                                 (gmch_ctrl & I830_GMCH_GMS_MASK));
1285                         size = 512;
1286                 }
1287         } else {
1288                 /* On previous hardware, the GTT size was just what was
1289                  * required to map the aperture.
1290                  */
1291                 size = agp_bridge->driver->fetch_size();
1292         }
1293
1294         return KB(size);
1295 }
1296
1297 /* The intel i915 automatically initializes the agp aperture during POST.
1298  * Use the memory already set aside for in the GTT.
1299  */
1300 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1301 {
1302         int page_order;
1303         struct aper_size_info_fixed *size;
1304         int num_entries;
1305         u32 temp, temp2;
1306         int gtt_map_size;
1307
1308         size = agp_bridge->current_size;
1309         page_order = size->page_order;
1310         num_entries = size->num_entries;
1311         agp_bridge->gatt_table_real = NULL;
1312
1313         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1314         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1315
1316         gtt_map_size = intel_i915_get_gtt_size();
1317
1318         intel_private.gtt = ioremap(temp2, gtt_map_size);
1319         if (!intel_private.gtt)
1320                 return -ENOMEM;
1321
1322         intel_private.base.gtt_total_entries = gtt_map_size / 4;
1323
1324         temp &= 0xfff80000;
1325
1326         intel_private.registers = ioremap(temp, 128 * 4096);
1327         if (!intel_private.registers) {
1328                 iounmap(intel_private.gtt);
1329                 return -ENOMEM;
1330         }
1331
1332         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1333         global_cache_flush();   /* FIXME: ? */
1334
1335         /* we have to call this as early as possible after the MMIO base address is known */
1336         intel_i830_init_gtt_entries();
1337         if (intel_private.base.gtt_stolen_entries == 0) {
1338                 iounmap(intel_private.gtt);
1339                 iounmap(intel_private.registers);
1340                 return -ENOMEM;
1341         }
1342
1343         agp_bridge->gatt_table = NULL;
1344
1345         agp_bridge->gatt_bus_addr = temp;
1346
1347         return 0;
1348 }
1349
1350 /*
1351  * The i965 supports 36-bit physical addresses, but to keep
1352  * the format of the GTT the same, the bits that don't fit
1353  * in a 32-bit word are shifted down to bits 4..7.
1354  *
1355  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1356  * is always zero on 32-bit architectures, so no need to make
1357  * this conditional.
1358  */
1359 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1360                                             dma_addr_t addr, int type)
1361 {
1362         /* Shift high bits down */
1363         addr |= (addr >> 28) & 0xf0;
1364
1365         /* Type checking must be done elsewhere */
1366         return addr | bridge->driver->masks[type].mask;
1367 }
1368
1369 static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
1370                                             dma_addr_t addr, int type)
1371 {
1372         /* gen6 has bit11-4 for physical addr bit39-32 */
1373         addr |= (addr >> 28) & 0xff0;
1374
1375         /* Type checking must be done elsewhere */
1376         return addr | bridge->driver->masks[type].mask;
1377 }
1378
1379 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1380 {
1381         u16 snb_gmch_ctl;
1382
1383         switch (agp_bridge->dev->device) {
1384         case PCI_DEVICE_ID_INTEL_GM45_HB:
1385         case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
1386         case PCI_DEVICE_ID_INTEL_Q45_HB:
1387         case PCI_DEVICE_ID_INTEL_G45_HB:
1388         case PCI_DEVICE_ID_INTEL_G41_HB:
1389         case PCI_DEVICE_ID_INTEL_B43_HB:
1390         case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB:
1391         case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
1392         case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
1393         case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
1394                 *gtt_offset = *gtt_size = MB(2);
1395                 break;
1396         case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
1397         case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
1398         case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB:
1399                 *gtt_offset = MB(2);
1400
1401                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1402                 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
1403                 default:
1404                 case SNB_GTT_SIZE_0M:
1405                         printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
1406                         *gtt_size = MB(0);
1407                         break;
1408                 case SNB_GTT_SIZE_1M:
1409                         *gtt_size = MB(1);
1410                         break;
1411                 case SNB_GTT_SIZE_2M:
1412                         *gtt_size = MB(2);
1413                         break;
1414                 }
1415                 break;
1416         default:
1417                 *gtt_offset = *gtt_size = KB(512);
1418         }
1419 }
1420
1421 /* The intel i965 automatically initializes the agp aperture during POST.
1422  * Use the memory already set aside for in the GTT.
1423  */
1424 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1425 {
1426         int page_order;
1427         struct aper_size_info_fixed *size;
1428         int num_entries;
1429         u32 temp;
1430         int gtt_offset, gtt_size;
1431
1432         size = agp_bridge->current_size;
1433         page_order = size->page_order;
1434         num_entries = size->num_entries;
1435         agp_bridge->gatt_table_real = NULL;
1436
1437         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1438
1439         temp &= 0xfff00000;
1440
1441         intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1442
1443         intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1444
1445         if (!intel_private.gtt)
1446                 return -ENOMEM;
1447
1448         intel_private.base.gtt_total_entries = gtt_size / 4;
1449
1450         intel_private.registers = ioremap(temp, 128 * 4096);
1451         if (!intel_private.registers) {
1452                 iounmap(intel_private.gtt);
1453                 return -ENOMEM;
1454         }
1455
1456         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1457         global_cache_flush();   /* FIXME: ? */
1458
1459         /* we have to call this as early as possible after the MMIO base address is known */
1460         intel_i830_init_gtt_entries();
1461         if (intel_private.base.gtt_stolen_entries == 0) {
1462                 iounmap(intel_private.gtt);
1463                 iounmap(intel_private.registers);
1464                 return -ENOMEM;
1465         }
1466
1467         agp_bridge->gatt_table = NULL;
1468
1469         agp_bridge->gatt_bus_addr = temp;
1470
1471         return 0;
1472 }
1473
1474 static const struct agp_bridge_driver intel_810_driver = {
1475         .owner                  = THIS_MODULE,
1476         .aperture_sizes         = intel_i810_sizes,
1477         .size_type              = FIXED_APER_SIZE,
1478         .num_aperture_sizes     = 2,
1479         .needs_scratch_page     = true,
1480         .configure              = intel_i810_configure,
1481         .fetch_size             = intel_i810_fetch_size,
1482         .cleanup                = intel_i810_cleanup,
1483         .mask_memory            = intel_i810_mask_memory,
1484         .masks                  = intel_i810_masks,
1485         .agp_enable             = intel_i810_agp_enable,
1486         .cache_flush            = global_cache_flush,
1487         .create_gatt_table      = agp_generic_create_gatt_table,
1488         .free_gatt_table        = agp_generic_free_gatt_table,
1489         .insert_memory          = intel_i810_insert_entries,
1490         .remove_memory          = intel_i810_remove_entries,
1491         .alloc_by_type          = intel_i810_alloc_by_type,
1492         .free_by_type           = intel_i810_free_by_type,
1493         .agp_alloc_page         = agp_generic_alloc_page,
1494         .agp_alloc_pages        = agp_generic_alloc_pages,
1495         .agp_destroy_page       = agp_generic_destroy_page,
1496         .agp_destroy_pages      = agp_generic_destroy_pages,
1497         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1498 };
1499
1500 static const struct agp_bridge_driver intel_830_driver = {
1501         .owner                  = THIS_MODULE,
1502         .aperture_sizes         = intel_i830_sizes,
1503         .size_type              = FIXED_APER_SIZE,
1504         .num_aperture_sizes     = 4,
1505         .needs_scratch_page     = true,
1506         .configure              = intel_i830_configure,
1507         .fetch_size             = intel_i830_fetch_size,
1508         .cleanup                = intel_i830_cleanup,
1509         .mask_memory            = intel_i810_mask_memory,
1510         .masks                  = intel_i810_masks,
1511         .agp_enable             = intel_i810_agp_enable,
1512         .cache_flush            = global_cache_flush,
1513         .create_gatt_table      = intel_i830_create_gatt_table,
1514         .free_gatt_table        = intel_i830_free_gatt_table,
1515         .insert_memory          = intel_i830_insert_entries,
1516         .remove_memory          = intel_i830_remove_entries,
1517         .alloc_by_type          = intel_i830_alloc_by_type,
1518         .free_by_type           = intel_i810_free_by_type,
1519         .agp_alloc_page         = agp_generic_alloc_page,
1520         .agp_alloc_pages        = agp_generic_alloc_pages,
1521         .agp_destroy_page       = agp_generic_destroy_page,
1522         .agp_destroy_pages      = agp_generic_destroy_pages,
1523         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1524         .chipset_flush          = intel_i830_chipset_flush,
1525 };
1526
1527 static const struct agp_bridge_driver intel_915_driver = {
1528         .owner                  = THIS_MODULE,
1529         .aperture_sizes         = intel_i830_sizes,
1530         .size_type              = FIXED_APER_SIZE,
1531         .num_aperture_sizes     = 4,
1532         .needs_scratch_page     = true,
1533         .configure              = intel_i9xx_configure,
1534         .fetch_size             = intel_i9xx_fetch_size,
1535         .cleanup                = intel_i915_cleanup,
1536         .mask_memory            = intel_i810_mask_memory,
1537         .masks                  = intel_i810_masks,
1538         .agp_enable             = intel_i810_agp_enable,
1539         .cache_flush            = global_cache_flush,
1540         .create_gatt_table      = intel_i915_create_gatt_table,
1541         .free_gatt_table        = intel_i830_free_gatt_table,
1542         .insert_memory          = intel_i915_insert_entries,
1543         .remove_memory          = intel_i915_remove_entries,
1544         .alloc_by_type          = intel_i830_alloc_by_type,
1545         .free_by_type           = intel_i810_free_by_type,
1546         .agp_alloc_page         = agp_generic_alloc_page,
1547         .agp_alloc_pages        = agp_generic_alloc_pages,
1548         .agp_destroy_page       = agp_generic_destroy_page,
1549         .agp_destroy_pages      = agp_generic_destroy_pages,
1550         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1551         .chipset_flush          = intel_i915_chipset_flush,
1552 #ifdef USE_PCI_DMA_API
1553         .agp_map_page           = intel_agp_map_page,
1554         .agp_unmap_page         = intel_agp_unmap_page,
1555         .agp_map_memory         = intel_agp_map_memory,
1556         .agp_unmap_memory       = intel_agp_unmap_memory,
1557 #endif
1558 };
1559
1560 static const struct agp_bridge_driver intel_i965_driver = {
1561         .owner                  = THIS_MODULE,
1562         .aperture_sizes         = intel_i830_sizes,
1563         .size_type              = FIXED_APER_SIZE,
1564         .num_aperture_sizes     = 4,
1565         .needs_scratch_page     = true,
1566         .configure              = intel_i9xx_configure,
1567         .fetch_size             = intel_i9xx_fetch_size,
1568         .cleanup                = intel_i915_cleanup,
1569         .mask_memory            = intel_i965_mask_memory,
1570         .masks                  = intel_i810_masks,
1571         .agp_enable             = intel_i810_agp_enable,
1572         .cache_flush            = global_cache_flush,
1573         .create_gatt_table      = intel_i965_create_gatt_table,
1574         .free_gatt_table        = intel_i830_free_gatt_table,
1575         .insert_memory          = intel_i915_insert_entries,
1576         .remove_memory          = intel_i915_remove_entries,
1577         .alloc_by_type          = intel_i830_alloc_by_type,
1578         .free_by_type           = intel_i810_free_by_type,
1579         .agp_alloc_page         = agp_generic_alloc_page,
1580         .agp_alloc_pages        = agp_generic_alloc_pages,
1581         .agp_destroy_page       = agp_generic_destroy_page,
1582         .agp_destroy_pages      = agp_generic_destroy_pages,
1583         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1584         .chipset_flush          = intel_i915_chipset_flush,
1585 #ifdef USE_PCI_DMA_API
1586         .agp_map_page           = intel_agp_map_page,
1587         .agp_unmap_page         = intel_agp_unmap_page,
1588         .agp_map_memory         = intel_agp_map_memory,
1589         .agp_unmap_memory       = intel_agp_unmap_memory,
1590 #endif
1591 };
1592
1593 static const struct agp_bridge_driver intel_gen6_driver = {
1594         .owner                  = THIS_MODULE,
1595         .aperture_sizes         = intel_i830_sizes,
1596         .size_type              = FIXED_APER_SIZE,
1597         .num_aperture_sizes     = 4,
1598         .needs_scratch_page     = true,
1599         .configure              = intel_i9xx_configure,
1600         .fetch_size             = intel_i9xx_fetch_size,
1601         .cleanup                = intel_i915_cleanup,
1602         .mask_memory            = intel_gen6_mask_memory,
1603         .masks                  = intel_gen6_masks,
1604         .agp_enable             = intel_i810_agp_enable,
1605         .cache_flush            = global_cache_flush,
1606         .create_gatt_table      = intel_i965_create_gatt_table,
1607         .free_gatt_table        = intel_i830_free_gatt_table,
1608         .insert_memory          = intel_i915_insert_entries,
1609         .remove_memory          = intel_i915_remove_entries,
1610         .alloc_by_type          = intel_i830_alloc_by_type,
1611         .free_by_type           = intel_i810_free_by_type,
1612         .agp_alloc_page         = agp_generic_alloc_page,
1613         .agp_alloc_pages        = agp_generic_alloc_pages,
1614         .agp_destroy_page       = agp_generic_destroy_page,
1615         .agp_destroy_pages      = agp_generic_destroy_pages,
1616         .agp_type_to_mask_type  = intel_gen6_type_to_mask_type,
1617         .chipset_flush          = intel_i915_chipset_flush,
1618 #ifdef USE_PCI_DMA_API
1619         .agp_map_page           = intel_agp_map_page,
1620         .agp_unmap_page         = intel_agp_unmap_page,
1621         .agp_map_memory         = intel_agp_map_memory,
1622         .agp_unmap_memory       = intel_agp_unmap_memory,
1623 #endif
1624 };
1625
1626 static const struct agp_bridge_driver intel_g33_driver = {
1627         .owner                  = THIS_MODULE,
1628         .aperture_sizes         = intel_i830_sizes,
1629         .size_type              = FIXED_APER_SIZE,
1630         .num_aperture_sizes     = 4,
1631         .needs_scratch_page     = true,
1632         .configure              = intel_i9xx_configure,
1633         .fetch_size             = intel_i9xx_fetch_size,
1634         .cleanup                = intel_i915_cleanup,
1635         .mask_memory            = intel_i965_mask_memory,
1636         .masks                  = intel_i810_masks,
1637         .agp_enable             = intel_i810_agp_enable,
1638         .cache_flush            = global_cache_flush,
1639         .create_gatt_table      = intel_i915_create_gatt_table,
1640         .free_gatt_table        = intel_i830_free_gatt_table,
1641         .insert_memory          = intel_i915_insert_entries,
1642         .remove_memory          = intel_i915_remove_entries,
1643         .alloc_by_type          = intel_i830_alloc_by_type,
1644         .free_by_type           = intel_i810_free_by_type,
1645         .agp_alloc_page         = agp_generic_alloc_page,
1646         .agp_alloc_pages        = agp_generic_alloc_pages,
1647         .agp_destroy_page       = agp_generic_destroy_page,
1648         .agp_destroy_pages      = agp_generic_destroy_pages,
1649         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1650         .chipset_flush          = intel_i915_chipset_flush,
1651 #ifdef USE_PCI_DMA_API
1652         .agp_map_page           = intel_agp_map_page,
1653         .agp_unmap_page         = intel_agp_unmap_page,
1654         .agp_map_memory         = intel_agp_map_memory,
1655         .agp_unmap_memory       = intel_agp_unmap_memory,
1656 #endif
1657 };
1658
1659 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1660  * driver and gmch_driver must be non-null, and find_gmch will determine
1661  * which one should be used if a gmch_chip_id is present.
1662  */
1663 static const struct intel_gtt_driver_description {
1664         unsigned int gmch_chip_id;
1665         char *name;
1666         const struct agp_bridge_driver *gmch_driver;
1667 } intel_gtt_chipsets[] = {
1668         { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver },
1669         { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver },
1670         { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver },
1671         { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver },
1672         { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", &intel_830_driver },
1673         { PCI_DEVICE_ID_INTEL_82845G_IG, "830M", &intel_830_driver },
1674         { PCI_DEVICE_ID_INTEL_82854_IG, "854", &intel_830_driver },
1675         { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", &intel_830_driver },
1676         { PCI_DEVICE_ID_INTEL_82865_IG, "865", &intel_830_driver },
1677         { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", &intel_915_driver },
1678         { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", &intel_915_driver },
1679         { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", &intel_915_driver },
1680         { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", &intel_915_driver },
1681         { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", &intel_915_driver },
1682         { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", &intel_915_driver },
1683         { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", &intel_i965_driver },
1684         { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", &intel_i965_driver },
1685         { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", &intel_i965_driver },
1686         { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", &intel_i965_driver },
1687         { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", &intel_i965_driver },
1688         { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", &intel_i965_driver },
1689         { PCI_DEVICE_ID_INTEL_G33_IG, "G33", &intel_g33_driver },
1690         { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", &intel_g33_driver },
1691         { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", &intel_g33_driver },
1692         { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", &intel_g33_driver },
1693         { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", &intel_g33_driver },
1694         { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", &intel_i965_driver },
1695         { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", &intel_i965_driver },
1696         { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", &intel_i965_driver },
1697         { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", &intel_i965_driver },
1698         { PCI_DEVICE_ID_INTEL_B43_IG, "B43", &intel_i965_driver },
1699         { PCI_DEVICE_ID_INTEL_G41_IG, "G41", &intel_i965_driver },
1700         { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1701             "HD Graphics", &intel_i965_driver },
1702         { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1703             "HD Graphics", &intel_i965_driver },
1704         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1705             "Sandybridge", &intel_gen6_driver },
1706         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1707             "Sandybridge", &intel_gen6_driver },
1708         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1709             "Sandybridge", &intel_gen6_driver },
1710         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1711             "Sandybridge", &intel_gen6_driver },
1712         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1713             "Sandybridge", &intel_gen6_driver },
1714         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1715             "Sandybridge", &intel_gen6_driver },
1716         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1717             "Sandybridge", &intel_gen6_driver },
1718         { 0, NULL, NULL }
1719 };
1720
1721 static int find_gmch(u16 device)
1722 {
1723         struct pci_dev *gmch_device;
1724
1725         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1726         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1727                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1728                                              device, gmch_device);
1729         }
1730
1731         if (!gmch_device)
1732                 return 0;
1733
1734         intel_private.pcidev = gmch_device;
1735         return 1;
1736 }
1737
1738 int intel_gmch_probe(struct pci_dev *pdev,
1739                                       struct agp_bridge_data *bridge)
1740 {
1741         int i, mask;
1742         bridge->driver = NULL;
1743
1744         for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1745                 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1746                         bridge->driver =
1747                                 intel_gtt_chipsets[i].gmch_driver;
1748                         break;
1749                 }
1750         }
1751
1752         if (!bridge->driver)
1753                 return 0;
1754
1755         bridge->dev_private_data = &intel_private;
1756         bridge->dev = pdev;
1757
1758         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1759
1760         if (bridge->driver->mask_memory == intel_gen6_mask_memory)
1761                 mask = 40;
1762         else if (bridge->driver->mask_memory == intel_i965_mask_memory)
1763                 mask = 36;
1764         else
1765                 mask = 32;
1766
1767         if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1768                 dev_err(&intel_private.pcidev->dev,
1769                         "set gfx device dma mask %d-bit failed!\n", mask);
1770         else
1771                 pci_set_consistent_dma_mask(intel_private.pcidev,
1772                                             DMA_BIT_MASK(mask));
1773
1774         return 1;
1775 }
1776 EXPORT_SYMBOL(intel_gmch_probe);
1777
1778 void intel_gmch_remove(struct pci_dev *pdev)
1779 {
1780         if (intel_private.pcidev)
1781                 pci_dev_put(intel_private.pcidev);
1782 }
1783 EXPORT_SYMBOL(intel_gmch_remove);
1784
1785 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1786 MODULE_LICENSE("GPL and additional rights");