2 * Intel AGPGART routines.
5 #include <linux/module.h>
7 #include <linux/slab.h>
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/pagemap.h>
11 #include <linux/agp_backend.h>
15 int intel_agp_enabled;
16 EXPORT_SYMBOL(intel_agp_enabled);
19 * If we have Intel graphics, we're not going to have anything other than
20 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
21 * on the Intel IOMMU support (CONFIG_DMAR).
22 * Only newer chipsets need to bother with this, of course.
25 #define USE_PCI_DMA_API 1
28 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
29 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
30 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
31 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
32 #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
33 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
34 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
35 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
36 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
37 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
38 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
39 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
40 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
41 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
42 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
43 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
44 #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010
45 #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011
46 #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000
47 #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001
48 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
49 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
50 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
51 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
52 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
53 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
54 #define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40
55 #define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42
56 #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
57 #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
58 #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00
59 #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02
60 #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
61 #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
62 #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
63 #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
64 #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
65 #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
66 #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040
67 #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042
68 #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044
69 #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
70 #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a
71 #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046
72 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100
73 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG 0x0102
74 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104
75 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG 0x0106
77 /* cover 915 and 945 variants */
78 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
79 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
80 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
81 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
82 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
83 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
85 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
86 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
87 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
88 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
89 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
90 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
92 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
93 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
94 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
95 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
96 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
98 #define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
99 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
101 #define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
102 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
104 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
105 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
106 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
107 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
108 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
109 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
110 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \
111 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
112 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
113 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \
116 extern int agp_memory_reserved;
119 /* Intel 815 register */
120 #define INTEL_815_APCONT 0x51
121 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
123 /* Intel i820 registers */
124 #define INTEL_I820_RDCR 0x51
125 #define INTEL_I820_ERRSTS 0xc8
127 /* Intel i840 registers */
128 #define INTEL_I840_MCHCFG 0x50
129 #define INTEL_I840_ERRSTS 0xc8
131 /* Intel i850 registers */
132 #define INTEL_I850_MCHCFG 0x50
133 #define INTEL_I850_ERRSTS 0xc8
135 /* intel 915G registers */
136 #define I915_GMADDR 0x18
137 #define I915_MMADDR 0x10
138 #define I915_PTEADDR 0x1C
139 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
140 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
141 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
142 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
143 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
144 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
145 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
146 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
148 #define I915_IFPADDR 0x60
150 /* Intel 965G registers */
151 #define I965_MSAC 0x62
152 #define I965_IFPADDR 0x70
154 /* Intel 7505 registers */
155 #define INTEL_I7505_APSIZE 0x74
156 #define INTEL_I7505_NCAPID 0x60
157 #define INTEL_I7505_NISTAT 0x6c
158 #define INTEL_I7505_ATTBASE 0x78
159 #define INTEL_I7505_ERRSTS 0x42
160 #define INTEL_I7505_AGPCTRL 0x70
161 #define INTEL_I7505_MCHCFG 0x50
163 #define SNB_GMCH_CTRL 0x50
164 #define SNB_GMCH_GMS_STOLEN_MASK 0xF8
165 #define SNB_GMCH_GMS_STOLEN_32M (1 << 3)
166 #define SNB_GMCH_GMS_STOLEN_64M (2 << 3)
167 #define SNB_GMCH_GMS_STOLEN_96M (3 << 3)
168 #define SNB_GMCH_GMS_STOLEN_128M (4 << 3)
169 #define SNB_GMCH_GMS_STOLEN_160M (5 << 3)
170 #define SNB_GMCH_GMS_STOLEN_192M (6 << 3)
171 #define SNB_GMCH_GMS_STOLEN_224M (7 << 3)
172 #define SNB_GMCH_GMS_STOLEN_256M (8 << 3)
173 #define SNB_GMCH_GMS_STOLEN_288M (9 << 3)
174 #define SNB_GMCH_GMS_STOLEN_320M (0xa << 3)
175 #define SNB_GMCH_GMS_STOLEN_352M (0xb << 3)
176 #define SNB_GMCH_GMS_STOLEN_384M (0xc << 3)
177 #define SNB_GMCH_GMS_STOLEN_416M (0xd << 3)
178 #define SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
179 #define SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
180 #define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
181 #define SNB_GTT_SIZE_0M (0 << 8)
182 #define SNB_GTT_SIZE_1M (1 << 8)
183 #define SNB_GTT_SIZE_2M (2 << 8)
184 #define SNB_GTT_SIZE_MASK (3 << 8)
186 static const struct aper_size_info_fixed intel_i810_sizes[] =
189 /* The 32M mode still requires a 64k gatt */
193 #define AGP_DCACHE_MEMORY 1
194 #define AGP_PHYS_MEMORY 2
195 #define INTEL_AGP_CACHED_MEMORY 3
197 static struct gatt_mask intel_i810_masks[] =
199 {.mask = I810_PTE_VALID, .type = 0},
200 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
201 {.mask = I810_PTE_VALID, .type = 0},
202 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
203 .type = INTEL_AGP_CACHED_MEMORY}
206 static struct _intel_private {
207 struct pci_dev *pcidev; /* device one */
208 u8 __iomem *registers;
209 u32 __iomem *gtt; /* I915G */
210 int num_dcache_entries;
211 /* gtt_entries is the number of gtt entries that are already mapped
212 * to stolen memory. Stolen memory is larger than the memory mapped
213 * through gtt_entries, as it includes some reserved space for the BIOS
214 * popup and for the GTT.
216 int gtt_entries; /* i830+ */
219 void __iomem *i9xx_flush_page;
220 void *i8xx_flush_page;
222 struct page *i8xx_page;
223 struct resource ifp_resource;
227 #ifdef USE_PCI_DMA_API
228 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
230 *ret = pci_map_page(intel_private.pcidev, page, 0,
231 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
232 if (pci_dma_mapping_error(intel_private.pcidev, *ret))
237 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
239 pci_unmap_page(intel_private.pcidev, dma,
240 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
243 static void intel_agp_free_sglist(struct agp_memory *mem)
247 st.sgl = mem->sg_list;
248 st.orig_nents = st.nents = mem->page_count;
256 static int intel_agp_map_memory(struct agp_memory *mem)
259 struct scatterlist *sg;
262 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
264 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
267 mem->sg_list = sg = st.sgl;
269 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
270 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
272 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
273 mem->page_count, PCI_DMA_BIDIRECTIONAL);
274 if (unlikely(!mem->num_sg)) {
275 intel_agp_free_sglist(mem);
281 static void intel_agp_unmap_memory(struct agp_memory *mem)
283 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
285 pci_unmap_sg(intel_private.pcidev, mem->sg_list,
286 mem->page_count, PCI_DMA_BIDIRECTIONAL);
287 intel_agp_free_sglist(mem);
290 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
291 off_t pg_start, int mask_type)
293 struct scatterlist *sg;
298 WARN_ON(!mem->num_sg);
300 if (mem->num_sg == mem->page_count) {
301 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
302 writel(agp_bridge->driver->mask_memory(agp_bridge,
303 sg_dma_address(sg), mask_type),
304 intel_private.gtt+j);
308 /* sg may merge pages, but we have to separate
309 * per-page addr for GTT */
312 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
313 len = sg_dma_len(sg) / PAGE_SIZE;
314 for (m = 0; m < len; m++) {
315 writel(agp_bridge->driver->mask_memory(agp_bridge,
316 sg_dma_address(sg) + m * PAGE_SIZE,
318 intel_private.gtt+j);
323 readl(intel_private.gtt+j-1);
328 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
329 off_t pg_start, int mask_type)
334 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
335 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
337 cache_bits = I830_PTE_SYSTEM_CACHED;
340 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
341 writel(agp_bridge->driver->mask_memory(agp_bridge,
342 page_to_phys(mem->pages[i]), mask_type),
343 intel_private.gtt+j);
346 readl(intel_private.gtt+j-1);
351 static int intel_i810_fetch_size(void)
354 struct aper_size_info_fixed *values;
356 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
357 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
359 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
360 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
363 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
364 agp_bridge->previous_size =
365 agp_bridge->current_size = (void *) (values + 1);
366 agp_bridge->aperture_size_idx = 1;
367 return values[1].size;
369 agp_bridge->previous_size =
370 agp_bridge->current_size = (void *) (values);
371 agp_bridge->aperture_size_idx = 0;
372 return values[0].size;
378 static int intel_i810_configure(void)
380 struct aper_size_info_fixed *current_size;
384 current_size = A_SIZE_FIX(agp_bridge->current_size);
386 if (!intel_private.registers) {
387 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
390 intel_private.registers = ioremap(temp, 128 * 4096);
391 if (!intel_private.registers) {
392 dev_err(&intel_private.pcidev->dev,
393 "can't remap memory\n");
398 if ((readl(intel_private.registers+I810_DRAM_CTL)
399 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
400 /* This will need to be dynamically assigned */
401 dev_info(&intel_private.pcidev->dev,
402 "detected 4MB dedicated video ram\n");
403 intel_private.num_dcache_entries = 1024;
405 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
406 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
407 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
408 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
410 if (agp_bridge->driver->needs_scratch_page) {
411 for (i = 0; i < current_size->num_entries; i++) {
412 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
414 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
416 global_cache_flush();
420 static void intel_i810_cleanup(void)
422 writel(0, intel_private.registers+I810_PGETBL_CTL);
423 readl(intel_private.registers); /* PCI Posting. */
424 iounmap(intel_private.registers);
427 static void intel_i810_tlbflush(struct agp_memory *mem)
432 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
437 /* Exists to support ARGB cursors */
438 static struct page *i8xx_alloc_pages(void)
442 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
446 if (set_pages_uc(page, 4) < 0) {
447 set_pages_wb(page, 4);
448 __free_pages(page, 2);
452 atomic_inc(&agp_bridge->current_memory_agp);
456 static void i8xx_destroy_pages(struct page *page)
461 set_pages_wb(page, 4);
463 __free_pages(page, 2);
464 atomic_dec(&agp_bridge->current_memory_agp);
467 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
470 if (type < AGP_USER_TYPES)
472 else if (type == AGP_USER_CACHED_MEMORY)
473 return INTEL_AGP_CACHED_MEMORY;
478 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
481 int i, j, num_entries;
486 if (mem->page_count == 0)
489 temp = agp_bridge->current_size;
490 num_entries = A_SIZE_FIX(temp)->num_entries;
492 if ((pg_start + mem->page_count) > num_entries)
496 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
497 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
503 if (type != mem->type)
506 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
509 case AGP_DCACHE_MEMORY:
510 if (!mem->is_flushed)
511 global_cache_flush();
512 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
513 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
514 intel_private.registers+I810_PTE_BASE+(i*4));
516 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
518 case AGP_PHYS_MEMORY:
519 case AGP_NORMAL_MEMORY:
520 if (!mem->is_flushed)
521 global_cache_flush();
522 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
523 writel(agp_bridge->driver->mask_memory(agp_bridge,
524 page_to_phys(mem->pages[i]), mask_type),
525 intel_private.registers+I810_PTE_BASE+(j*4));
527 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
533 agp_bridge->driver->tlb_flush(mem);
537 mem->is_flushed = true;
541 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
546 if (mem->page_count == 0)
549 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
550 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
552 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
554 agp_bridge->driver->tlb_flush(mem);
559 * The i810/i830 requires a physical address to program its mouse
560 * pointer into hardware.
561 * However the Xserver still writes to it through the agp aperture.
563 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
565 struct agp_memory *new;
569 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
572 /* kludge to get 4 physical pages for ARGB cursor */
573 page = i8xx_alloc_pages();
582 new = agp_create_memory(pg_count);
586 new->pages[0] = page;
588 /* kludge to get 4 physical pages for ARGB cursor */
589 new->pages[1] = new->pages[0] + 1;
590 new->pages[2] = new->pages[1] + 1;
591 new->pages[3] = new->pages[2] + 1;
593 new->page_count = pg_count;
594 new->num_scratch_pages = pg_count;
595 new->type = AGP_PHYS_MEMORY;
596 new->physical = page_to_phys(new->pages[0]);
600 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
602 struct agp_memory *new;
604 if (type == AGP_DCACHE_MEMORY) {
605 if (pg_count != intel_private.num_dcache_entries)
608 new = agp_create_memory(1);
612 new->type = AGP_DCACHE_MEMORY;
613 new->page_count = pg_count;
614 new->num_scratch_pages = 0;
615 agp_free_page_array(new);
618 if (type == AGP_PHYS_MEMORY)
619 return alloc_agpphysmem_i8xx(pg_count, type);
623 static void intel_i810_free_by_type(struct agp_memory *curr)
625 agp_free_key(curr->key);
626 if (curr->type == AGP_PHYS_MEMORY) {
627 if (curr->page_count == 4)
628 i8xx_destroy_pages(curr->pages[0]);
630 agp_bridge->driver->agp_destroy_page(curr->pages[0],
631 AGP_PAGE_DESTROY_UNMAP);
632 agp_bridge->driver->agp_destroy_page(curr->pages[0],
633 AGP_PAGE_DESTROY_FREE);
635 agp_free_page_array(curr);
640 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
641 dma_addr_t addr, int type)
643 /* Type checking must be done elsewhere */
644 return addr | bridge->driver->masks[type].mask;
647 static struct aper_size_info_fixed intel_i830_sizes[] =
650 /* The 64M mode still requires a 128k gatt */
656 static void intel_i830_init_gtt_entries(void)
662 static const int ddt[4] = { 0, 16, 32, 64 };
663 int size; /* reserved space (in kb) at the top of stolen memory */
665 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
669 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
671 /* The 965 has a field telling us the size of the GTT,
672 * which may be larger than what is necessary to map the
675 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
676 case I965_PGETBL_SIZE_128KB:
679 case I965_PGETBL_SIZE_256KB:
682 case I965_PGETBL_SIZE_512KB:
685 case I965_PGETBL_SIZE_1MB:
688 case I965_PGETBL_SIZE_2MB:
691 case I965_PGETBL_SIZE_1_5MB:
695 dev_info(&intel_private.pcidev->dev,
696 "unknown page table size, assuming 512KB\n");
699 size += 4; /* add in BIOS popup space */
700 } else if (IS_G33 && !IS_PINEVIEW) {
701 /* G33's GTT size defined in gmch_ctrl */
702 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
703 case G33_PGETBL_SIZE_1M:
706 case G33_PGETBL_SIZE_2M:
710 dev_info(&agp_bridge->dev->dev,
711 "unknown page table size 0x%x, assuming 512KB\n",
712 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
716 } else if (IS_G4X || IS_PINEVIEW) {
717 /* On 4 series hardware, GTT stolen is separate from graphics
718 * stolen, ignore it in stolen gtt entries counting. However,
719 * 4KB of the stolen memory doesn't get mapped to the GTT.
723 /* On previous hardware, the GTT size was just what was
724 * required to map the aperture.
726 size = agp_bridge->driver->fetch_size() + 4;
729 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
730 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
731 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
732 case I830_GMCH_GMS_STOLEN_512:
733 gtt_entries = KB(512) - KB(size);
735 case I830_GMCH_GMS_STOLEN_1024:
736 gtt_entries = MB(1) - KB(size);
738 case I830_GMCH_GMS_STOLEN_8192:
739 gtt_entries = MB(8) - KB(size);
741 case I830_GMCH_GMS_LOCAL:
742 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
743 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
744 MB(ddt[I830_RDRAM_DDT(rdct)]);
751 } else if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
752 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) {
754 * SandyBridge has new memory control reg at 0x50.w
757 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
758 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
759 case SNB_GMCH_GMS_STOLEN_32M:
760 gtt_entries = MB(32) - KB(size);
762 case SNB_GMCH_GMS_STOLEN_64M:
763 gtt_entries = MB(64) - KB(size);
765 case SNB_GMCH_GMS_STOLEN_96M:
766 gtt_entries = MB(96) - KB(size);
768 case SNB_GMCH_GMS_STOLEN_128M:
769 gtt_entries = MB(128) - KB(size);
771 case SNB_GMCH_GMS_STOLEN_160M:
772 gtt_entries = MB(160) - KB(size);
774 case SNB_GMCH_GMS_STOLEN_192M:
775 gtt_entries = MB(192) - KB(size);
777 case SNB_GMCH_GMS_STOLEN_224M:
778 gtt_entries = MB(224) - KB(size);
780 case SNB_GMCH_GMS_STOLEN_256M:
781 gtt_entries = MB(256) - KB(size);
783 case SNB_GMCH_GMS_STOLEN_288M:
784 gtt_entries = MB(288) - KB(size);
786 case SNB_GMCH_GMS_STOLEN_320M:
787 gtt_entries = MB(320) - KB(size);
789 case SNB_GMCH_GMS_STOLEN_352M:
790 gtt_entries = MB(352) - KB(size);
792 case SNB_GMCH_GMS_STOLEN_384M:
793 gtt_entries = MB(384) - KB(size);
795 case SNB_GMCH_GMS_STOLEN_416M:
796 gtt_entries = MB(416) - KB(size);
798 case SNB_GMCH_GMS_STOLEN_448M:
799 gtt_entries = MB(448) - KB(size);
801 case SNB_GMCH_GMS_STOLEN_480M:
802 gtt_entries = MB(480) - KB(size);
804 case SNB_GMCH_GMS_STOLEN_512M:
805 gtt_entries = MB(512) - KB(size);
809 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
810 case I855_GMCH_GMS_STOLEN_1M:
811 gtt_entries = MB(1) - KB(size);
813 case I855_GMCH_GMS_STOLEN_4M:
814 gtt_entries = MB(4) - KB(size);
816 case I855_GMCH_GMS_STOLEN_8M:
817 gtt_entries = MB(8) - KB(size);
819 case I855_GMCH_GMS_STOLEN_16M:
820 gtt_entries = MB(16) - KB(size);
822 case I855_GMCH_GMS_STOLEN_32M:
823 gtt_entries = MB(32) - KB(size);
825 case I915_GMCH_GMS_STOLEN_48M:
826 /* Check it's really I915G */
827 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
828 gtt_entries = MB(48) - KB(size);
832 case I915_GMCH_GMS_STOLEN_64M:
833 /* Check it's really I915G */
834 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
835 gtt_entries = MB(64) - KB(size);
839 case G33_GMCH_GMS_STOLEN_128M:
840 if (IS_G33 || IS_I965 || IS_G4X)
841 gtt_entries = MB(128) - KB(size);
845 case G33_GMCH_GMS_STOLEN_256M:
846 if (IS_G33 || IS_I965 || IS_G4X)
847 gtt_entries = MB(256) - KB(size);
851 case INTEL_GMCH_GMS_STOLEN_96M:
852 if (IS_I965 || IS_G4X)
853 gtt_entries = MB(96) - KB(size);
857 case INTEL_GMCH_GMS_STOLEN_160M:
858 if (IS_I965 || IS_G4X)
859 gtt_entries = MB(160) - KB(size);
863 case INTEL_GMCH_GMS_STOLEN_224M:
864 if (IS_I965 || IS_G4X)
865 gtt_entries = MB(224) - KB(size);
869 case INTEL_GMCH_GMS_STOLEN_352M:
870 if (IS_I965 || IS_G4X)
871 gtt_entries = MB(352) - KB(size);
880 if (gtt_entries > 0) {
881 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
882 gtt_entries / KB(1), local ? "local" : "stolen");
883 gtt_entries /= KB(4);
885 dev_info(&agp_bridge->dev->dev,
886 "no pre-allocated video memory detected\n");
890 intel_private.gtt_entries = gtt_entries;
893 static void intel_i830_fini_flush(void)
895 kunmap(intel_private.i8xx_page);
896 intel_private.i8xx_flush_page = NULL;
897 unmap_page_from_agp(intel_private.i8xx_page);
899 __free_page(intel_private.i8xx_page);
900 intel_private.i8xx_page = NULL;
903 static void intel_i830_setup_flush(void)
905 /* return if we've already set the flush mechanism up */
906 if (intel_private.i8xx_page)
909 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
910 if (!intel_private.i8xx_page)
913 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
914 if (!intel_private.i8xx_flush_page)
915 intel_i830_fini_flush();
918 /* The chipset_flush interface needs to get data that has already been
919 * flushed out of the CPU all the way out to main memory, because the GPU
920 * doesn't snoop those buffers.
922 * The 8xx series doesn't have the same lovely interface for flushing the
923 * chipset write buffers that the later chips do. According to the 865
924 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
925 * that buffer out, we just fill 1KB and clflush it out, on the assumption
926 * that it'll push whatever was in there out. It appears to work.
928 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
930 unsigned int *pg = intel_private.i8xx_flush_page;
935 clflush_cache_range(pg, 1024);
936 else if (wbinvd_on_all_cpus() != 0)
937 printk(KERN_ERR "Timed out waiting for cache flush.\n");
940 /* The intel i830 automatically initializes the agp aperture during POST.
941 * Use the memory already set aside for in the GTT.
943 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
946 struct aper_size_info_fixed *size;
950 size = agp_bridge->current_size;
951 page_order = size->page_order;
952 num_entries = size->num_entries;
953 agp_bridge->gatt_table_real = NULL;
955 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
958 intel_private.registers = ioremap(temp, 128 * 4096);
959 if (!intel_private.registers)
962 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
963 global_cache_flush(); /* FIXME: ?? */
965 /* we have to call this as early as possible after the MMIO base address is known */
966 intel_i830_init_gtt_entries();
968 agp_bridge->gatt_table = NULL;
970 agp_bridge->gatt_bus_addr = temp;
975 /* Return the gatt table to a sane state. Use the top of stolen
976 * memory for the GTT.
978 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
983 static int intel_i830_fetch_size(void)
986 struct aper_size_info_fixed *values;
988 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
990 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
991 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
992 /* 855GM/852GM/865G has 128MB aperture size */
993 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
994 agp_bridge->aperture_size_idx = 0;
995 return values[0].size;
998 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1000 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
1001 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
1002 agp_bridge->aperture_size_idx = 0;
1003 return values[0].size;
1005 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
1006 agp_bridge->aperture_size_idx = 1;
1007 return values[1].size;
1013 static int intel_i830_configure(void)
1015 struct aper_size_info_fixed *current_size;
1020 current_size = A_SIZE_FIX(agp_bridge->current_size);
1022 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
1023 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1025 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1026 gmch_ctrl |= I830_GMCH_ENABLED;
1027 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1029 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1030 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1032 if (agp_bridge->driver->needs_scratch_page) {
1033 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
1034 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1036 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
1039 global_cache_flush();
1041 intel_i830_setup_flush();
1045 static void intel_i830_cleanup(void)
1047 iounmap(intel_private.registers);
1050 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
1053 int i, j, num_entries;
1058 if (mem->page_count == 0)
1061 temp = agp_bridge->current_size;
1062 num_entries = A_SIZE_FIX(temp)->num_entries;
1064 if (pg_start < intel_private.gtt_entries) {
1065 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1066 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1067 pg_start, intel_private.gtt_entries);
1069 dev_info(&intel_private.pcidev->dev,
1070 "trying to insert into local/stolen memory\n");
1074 if ((pg_start + mem->page_count) > num_entries)
1077 /* The i830 can't check the GTT for entries since its read only,
1078 * depend on the caller to make the correct offset decisions.
1081 if (type != mem->type)
1084 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1086 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1087 mask_type != INTEL_AGP_CACHED_MEMORY)
1090 if (!mem->is_flushed)
1091 global_cache_flush();
1093 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1094 writel(agp_bridge->driver->mask_memory(agp_bridge,
1095 page_to_phys(mem->pages[i]), mask_type),
1096 intel_private.registers+I810_PTE_BASE+(j*4));
1098 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
1099 agp_bridge->driver->tlb_flush(mem);
1104 mem->is_flushed = true;
1108 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
1113 if (mem->page_count == 0)
1116 if (pg_start < intel_private.gtt_entries) {
1117 dev_info(&intel_private.pcidev->dev,
1118 "trying to disable local/stolen memory\n");
1122 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1123 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1125 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1127 agp_bridge->driver->tlb_flush(mem);
1131 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1133 if (type == AGP_PHYS_MEMORY)
1134 return alloc_agpphysmem_i8xx(pg_count, type);
1135 /* always return NULL for other allocation types for now */
1139 static int intel_alloc_chipset_flush_resource(void)
1142 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1143 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1144 pcibios_align_resource, agp_bridge->dev);
1149 static void intel_i915_setup_chipset_flush(void)
1154 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
1155 if (!(temp & 0x1)) {
1156 intel_alloc_chipset_flush_resource();
1157 intel_private.resource_valid = 1;
1158 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1162 intel_private.resource_valid = 1;
1163 intel_private.ifp_resource.start = temp;
1164 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1165 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1166 /* some BIOSes reserve this area in a pnp some don't */
1168 intel_private.resource_valid = 0;
1172 static void intel_i965_g33_setup_chipset_flush(void)
1174 u32 temp_hi, temp_lo;
1177 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
1178 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
1180 if (!(temp_lo & 0x1)) {
1182 intel_alloc_chipset_flush_resource();
1184 intel_private.resource_valid = 1;
1185 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
1186 upper_32_bits(intel_private.ifp_resource.start));
1187 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1192 l64 = ((u64)temp_hi << 32) | temp_lo;
1194 intel_private.resource_valid = 1;
1195 intel_private.ifp_resource.start = l64;
1196 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1197 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1198 /* some BIOSes reserve this area in a pnp some don't */
1200 intel_private.resource_valid = 0;
1204 static void intel_i9xx_setup_flush(void)
1206 /* return if already configured */
1207 if (intel_private.ifp_resource.start)
1213 /* setup a resource for this object */
1214 intel_private.ifp_resource.name = "Intel Flush Page";
1215 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1217 /* Setup chipset flush for 915 */
1218 if (IS_I965 || IS_G33 || IS_G4X) {
1219 intel_i965_g33_setup_chipset_flush();
1221 intel_i915_setup_chipset_flush();
1224 if (intel_private.ifp_resource.start) {
1225 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1226 if (!intel_private.i9xx_flush_page)
1227 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
1231 static int intel_i915_configure(void)
1233 struct aper_size_info_fixed *current_size;
1238 current_size = A_SIZE_FIX(agp_bridge->current_size);
1240 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1242 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1244 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1245 gmch_ctrl |= I830_GMCH_ENABLED;
1246 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1248 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1249 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1251 if (agp_bridge->driver->needs_scratch_page) {
1252 for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) {
1253 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1255 readl(intel_private.gtt+i-1); /* PCI Posting. */
1258 global_cache_flush();
1260 intel_i9xx_setup_flush();
1265 static void intel_i915_cleanup(void)
1267 if (intel_private.i9xx_flush_page)
1268 iounmap(intel_private.i9xx_flush_page);
1269 if (intel_private.resource_valid)
1270 release_resource(&intel_private.ifp_resource);
1271 intel_private.ifp_resource.start = 0;
1272 intel_private.resource_valid = 0;
1273 iounmap(intel_private.gtt);
1274 iounmap(intel_private.registers);
1277 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1279 if (intel_private.i9xx_flush_page)
1280 writel(1, intel_private.i9xx_flush_page);
1283 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1291 if (mem->page_count == 0)
1294 temp = agp_bridge->current_size;
1295 num_entries = A_SIZE_FIX(temp)->num_entries;
1297 if (pg_start < intel_private.gtt_entries) {
1298 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1299 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1300 pg_start, intel_private.gtt_entries);
1302 dev_info(&intel_private.pcidev->dev,
1303 "trying to insert into local/stolen memory\n");
1307 if ((pg_start + mem->page_count) > num_entries)
1310 /* The i915 can't check the GTT for entries since it's read only;
1311 * depend on the caller to make the correct offset decisions.
1314 if (type != mem->type)
1317 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1319 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1320 mask_type != INTEL_AGP_CACHED_MEMORY)
1323 if (!mem->is_flushed)
1324 global_cache_flush();
1326 intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1327 agp_bridge->driver->tlb_flush(mem);
1332 mem->is_flushed = true;
1336 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1341 if (mem->page_count == 0)
1344 if (pg_start < intel_private.gtt_entries) {
1345 dev_info(&intel_private.pcidev->dev,
1346 "trying to disable local/stolen memory\n");
1350 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1351 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1353 readl(intel_private.gtt+i-1);
1355 agp_bridge->driver->tlb_flush(mem);
1359 /* Return the aperture size by just checking the resource length. The effect
1360 * described in the spec of the MSAC registers is just changing of the
1363 static int intel_i9xx_fetch_size(void)
1365 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1366 int aper_size; /* size in megabytes */
1369 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1371 for (i = 0; i < num_sizes; i++) {
1372 if (aper_size == intel_i830_sizes[i].size) {
1373 agp_bridge->current_size = intel_i830_sizes + i;
1374 agp_bridge->previous_size = agp_bridge->current_size;
1382 /* The intel i915 automatically initializes the agp aperture during POST.
1383 * Use the memory already set aside for in the GTT.
1385 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1388 struct aper_size_info_fixed *size;
1391 int gtt_map_size = 256 * 1024;
1393 size = agp_bridge->current_size;
1394 page_order = size->page_order;
1395 num_entries = size->num_entries;
1396 agp_bridge->gatt_table_real = NULL;
1398 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1399 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1402 gtt_map_size = 1024 * 1024; /* 1M on G33 */
1403 intel_private.gtt = ioremap(temp2, gtt_map_size);
1404 if (!intel_private.gtt)
1407 intel_private.gtt_total_size = gtt_map_size / 4;
1411 intel_private.registers = ioremap(temp, 128 * 4096);
1412 if (!intel_private.registers) {
1413 iounmap(intel_private.gtt);
1417 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1418 global_cache_flush(); /* FIXME: ? */
1420 /* we have to call this as early as possible after the MMIO base address is known */
1421 intel_i830_init_gtt_entries();
1423 agp_bridge->gatt_table = NULL;
1425 agp_bridge->gatt_bus_addr = temp;
1431 * The i965 supports 36-bit physical addresses, but to keep
1432 * the format of the GTT the same, the bits that don't fit
1433 * in a 32-bit word are shifted down to bits 4..7.
1435 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1436 * is always zero on 32-bit architectures, so no need to make
1439 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1440 dma_addr_t addr, int type)
1442 /* Shift high bits down */
1443 addr |= (addr >> 28) & 0xf0;
1445 /* Type checking must be done elsewhere */
1446 return addr | bridge->driver->masks[type].mask;
1449 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1453 switch (agp_bridge->dev->device) {
1454 case PCI_DEVICE_ID_INTEL_GM45_HB:
1455 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
1456 case PCI_DEVICE_ID_INTEL_Q45_HB:
1457 case PCI_DEVICE_ID_INTEL_G45_HB:
1458 case PCI_DEVICE_ID_INTEL_G41_HB:
1459 case PCI_DEVICE_ID_INTEL_B43_HB:
1460 case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB:
1461 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
1462 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
1463 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
1464 *gtt_offset = *gtt_size = MB(2);
1466 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
1467 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
1468 *gtt_offset = MB(2);
1470 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1471 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
1473 case SNB_GTT_SIZE_0M:
1474 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
1477 case SNB_GTT_SIZE_1M:
1480 case SNB_GTT_SIZE_2M:
1486 *gtt_offset = *gtt_size = KB(512);
1490 /* The intel i965 automatically initializes the agp aperture during POST.
1491 * Use the memory already set aside for in the GTT.
1493 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1496 struct aper_size_info_fixed *size;
1499 int gtt_offset, gtt_size;
1501 size = agp_bridge->current_size;
1502 page_order = size->page_order;
1503 num_entries = size->num_entries;
1504 agp_bridge->gatt_table_real = NULL;
1506 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1510 intel_i965_get_gtt_range(>t_offset, >t_size);
1512 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1514 if (!intel_private.gtt)
1517 intel_private.gtt_total_size = gtt_size / 4;
1519 intel_private.registers = ioremap(temp, 128 * 4096);
1520 if (!intel_private.registers) {
1521 iounmap(intel_private.gtt);
1525 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1526 global_cache_flush(); /* FIXME: ? */
1528 /* we have to call this as early as possible after the MMIO base address is known */
1529 intel_i830_init_gtt_entries();
1531 agp_bridge->gatt_table = NULL;
1533 agp_bridge->gatt_bus_addr = temp;
1539 static int intel_fetch_size(void)
1543 struct aper_size_info_16 *values;
1545 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1546 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1548 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1549 if (temp == values[i].size_value) {
1550 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1551 agp_bridge->aperture_size_idx = i;
1552 return values[i].size;
1559 static int __intel_8xx_fetch_size(u8 temp)
1562 struct aper_size_info_8 *values;
1564 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1566 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1567 if (temp == values[i].size_value) {
1568 agp_bridge->previous_size =
1569 agp_bridge->current_size = (void *) (values + i);
1570 agp_bridge->aperture_size_idx = i;
1571 return values[i].size;
1577 static int intel_8xx_fetch_size(void)
1581 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1582 return __intel_8xx_fetch_size(temp);
1585 static int intel_815_fetch_size(void)
1589 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1590 * one non-reserved bit, so mask the others out ... */
1591 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1594 return __intel_8xx_fetch_size(temp);
1597 static void intel_tlbflush(struct agp_memory *mem)
1599 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1600 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1604 static void intel_8xx_tlbflush(struct agp_memory *mem)
1607 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1608 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1609 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1610 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1614 static void intel_cleanup(void)
1617 struct aper_size_info_16 *previous_size;
1619 previous_size = A_SIZE_16(agp_bridge->previous_size);
1620 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1621 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1622 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1626 static void intel_8xx_cleanup(void)
1629 struct aper_size_info_8 *previous_size;
1631 previous_size = A_SIZE_8(agp_bridge->previous_size);
1632 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1633 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1634 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1638 static int intel_configure(void)
1642 struct aper_size_info_16 *current_size;
1644 current_size = A_SIZE_16(agp_bridge->current_size);
1647 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1649 /* address to map to */
1650 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1651 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1653 /* attbase - aperture base */
1654 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1657 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1660 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1661 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1662 (temp2 & ~(1 << 10)) | (1 << 9));
1663 /* clear any possible error conditions */
1664 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1668 static int intel_815_configure(void)
1672 struct aper_size_info_8 *current_size;
1674 /* attbase - aperture base */
1675 /* the Intel 815 chipset spec. says that bits 29-31 in the
1676 * ATTBASE register are reserved -> try not to write them */
1677 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1678 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1682 current_size = A_SIZE_8(agp_bridge->current_size);
1685 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1686 current_size->size_value);
1688 /* address to map to */
1689 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1690 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1692 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1693 addr &= INTEL_815_ATTBASE_MASK;
1694 addr |= agp_bridge->gatt_bus_addr;
1695 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1698 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1701 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1702 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1704 /* clear any possible error conditions */
1705 /* Oddness : this chipset seems to have no ERRSTS register ! */
1709 static void intel_820_tlbflush(struct agp_memory *mem)
1714 static void intel_820_cleanup(void)
1717 struct aper_size_info_8 *previous_size;
1719 previous_size = A_SIZE_8(agp_bridge->previous_size);
1720 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1721 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1723 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1724 previous_size->size_value);
1728 static int intel_820_configure(void)
1732 struct aper_size_info_8 *current_size;
1734 current_size = A_SIZE_8(agp_bridge->current_size);
1737 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1739 /* address to map to */
1740 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1741 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1743 /* attbase - aperture base */
1744 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1747 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1749 /* global enable aperture access */
1750 /* This flag is not accessed through MCHCFG register as in */
1752 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1753 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1754 /* clear any possible AGP-related error conditions */
1755 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1759 static int intel_840_configure(void)
1763 struct aper_size_info_8 *current_size;
1765 current_size = A_SIZE_8(agp_bridge->current_size);
1768 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1770 /* address to map to */
1771 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1772 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1774 /* attbase - aperture base */
1775 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1778 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1781 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1782 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1783 /* clear any possible error conditions */
1784 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1788 static int intel_845_configure(void)
1792 struct aper_size_info_8 *current_size;
1794 current_size = A_SIZE_8(agp_bridge->current_size);
1797 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1799 if (agp_bridge->apbase_config != 0) {
1800 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1801 agp_bridge->apbase_config);
1803 /* address to map to */
1804 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1805 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1806 agp_bridge->apbase_config = temp;
1809 /* attbase - aperture base */
1810 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1813 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1816 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1817 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1818 /* clear any possible error conditions */
1819 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1821 intel_i830_setup_flush();
1825 static int intel_850_configure(void)
1829 struct aper_size_info_8 *current_size;
1831 current_size = A_SIZE_8(agp_bridge->current_size);
1834 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1836 /* address to map to */
1837 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1838 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1840 /* attbase - aperture base */
1841 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1844 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1847 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1848 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1849 /* clear any possible AGP-related error conditions */
1850 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1854 static int intel_860_configure(void)
1858 struct aper_size_info_8 *current_size;
1860 current_size = A_SIZE_8(agp_bridge->current_size);
1863 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1865 /* address to map to */
1866 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1867 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1869 /* attbase - aperture base */
1870 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1873 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1876 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1877 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1878 /* clear any possible AGP-related error conditions */
1879 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1883 static int intel_830mp_configure(void)
1887 struct aper_size_info_8 *current_size;
1889 current_size = A_SIZE_8(agp_bridge->current_size);
1892 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1894 /* address to map to */
1895 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1896 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1898 /* attbase - aperture base */
1899 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1902 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1905 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1906 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1907 /* clear any possible AGP-related error conditions */
1908 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1912 static int intel_7505_configure(void)
1916 struct aper_size_info_8 *current_size;
1918 current_size = A_SIZE_8(agp_bridge->current_size);
1921 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1923 /* address to map to */
1924 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1925 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1927 /* attbase - aperture base */
1928 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1931 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1934 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1935 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1940 /* Setup function */
1941 static const struct gatt_mask intel_generic_masks[] =
1943 {.mask = 0x00000017, .type = 0}
1946 static const struct aper_size_info_8 intel_815_sizes[2] =
1952 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1955 {128, 32768, 5, 32},
1963 static const struct aper_size_info_16 intel_generic_sizes[7] =
1966 {128, 32768, 5, 32},
1974 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1977 {128, 32768, 5, 32},
1982 static const struct agp_bridge_driver intel_generic_driver = {
1983 .owner = THIS_MODULE,
1984 .aperture_sizes = intel_generic_sizes,
1985 .size_type = U16_APER_SIZE,
1986 .num_aperture_sizes = 7,
1987 .configure = intel_configure,
1988 .fetch_size = intel_fetch_size,
1989 .cleanup = intel_cleanup,
1990 .tlb_flush = intel_tlbflush,
1991 .mask_memory = agp_generic_mask_memory,
1992 .masks = intel_generic_masks,
1993 .agp_enable = agp_generic_enable,
1994 .cache_flush = global_cache_flush,
1995 .create_gatt_table = agp_generic_create_gatt_table,
1996 .free_gatt_table = agp_generic_free_gatt_table,
1997 .insert_memory = agp_generic_insert_memory,
1998 .remove_memory = agp_generic_remove_memory,
1999 .alloc_by_type = agp_generic_alloc_by_type,
2000 .free_by_type = agp_generic_free_by_type,
2001 .agp_alloc_page = agp_generic_alloc_page,
2002 .agp_alloc_pages = agp_generic_alloc_pages,
2003 .agp_destroy_page = agp_generic_destroy_page,
2004 .agp_destroy_pages = agp_generic_destroy_pages,
2005 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2008 static const struct agp_bridge_driver intel_810_driver = {
2009 .owner = THIS_MODULE,
2010 .aperture_sizes = intel_i810_sizes,
2011 .size_type = FIXED_APER_SIZE,
2012 .num_aperture_sizes = 2,
2013 .needs_scratch_page = true,
2014 .configure = intel_i810_configure,
2015 .fetch_size = intel_i810_fetch_size,
2016 .cleanup = intel_i810_cleanup,
2017 .tlb_flush = intel_i810_tlbflush,
2018 .mask_memory = intel_i810_mask_memory,
2019 .masks = intel_i810_masks,
2020 .agp_enable = intel_i810_agp_enable,
2021 .cache_flush = global_cache_flush,
2022 .create_gatt_table = agp_generic_create_gatt_table,
2023 .free_gatt_table = agp_generic_free_gatt_table,
2024 .insert_memory = intel_i810_insert_entries,
2025 .remove_memory = intel_i810_remove_entries,
2026 .alloc_by_type = intel_i810_alloc_by_type,
2027 .free_by_type = intel_i810_free_by_type,
2028 .agp_alloc_page = agp_generic_alloc_page,
2029 .agp_alloc_pages = agp_generic_alloc_pages,
2030 .agp_destroy_page = agp_generic_destroy_page,
2031 .agp_destroy_pages = agp_generic_destroy_pages,
2032 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2035 static const struct agp_bridge_driver intel_815_driver = {
2036 .owner = THIS_MODULE,
2037 .aperture_sizes = intel_815_sizes,
2038 .size_type = U8_APER_SIZE,
2039 .num_aperture_sizes = 2,
2040 .configure = intel_815_configure,
2041 .fetch_size = intel_815_fetch_size,
2042 .cleanup = intel_8xx_cleanup,
2043 .tlb_flush = intel_8xx_tlbflush,
2044 .mask_memory = agp_generic_mask_memory,
2045 .masks = intel_generic_masks,
2046 .agp_enable = agp_generic_enable,
2047 .cache_flush = global_cache_flush,
2048 .create_gatt_table = agp_generic_create_gatt_table,
2049 .free_gatt_table = agp_generic_free_gatt_table,
2050 .insert_memory = agp_generic_insert_memory,
2051 .remove_memory = agp_generic_remove_memory,
2052 .alloc_by_type = agp_generic_alloc_by_type,
2053 .free_by_type = agp_generic_free_by_type,
2054 .agp_alloc_page = agp_generic_alloc_page,
2055 .agp_alloc_pages = agp_generic_alloc_pages,
2056 .agp_destroy_page = agp_generic_destroy_page,
2057 .agp_destroy_pages = agp_generic_destroy_pages,
2058 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2061 static const struct agp_bridge_driver intel_830_driver = {
2062 .owner = THIS_MODULE,
2063 .aperture_sizes = intel_i830_sizes,
2064 .size_type = FIXED_APER_SIZE,
2065 .num_aperture_sizes = 4,
2066 .needs_scratch_page = true,
2067 .configure = intel_i830_configure,
2068 .fetch_size = intel_i830_fetch_size,
2069 .cleanup = intel_i830_cleanup,
2070 .tlb_flush = intel_i810_tlbflush,
2071 .mask_memory = intel_i810_mask_memory,
2072 .masks = intel_i810_masks,
2073 .agp_enable = intel_i810_agp_enable,
2074 .cache_flush = global_cache_flush,
2075 .create_gatt_table = intel_i830_create_gatt_table,
2076 .free_gatt_table = intel_i830_free_gatt_table,
2077 .insert_memory = intel_i830_insert_entries,
2078 .remove_memory = intel_i830_remove_entries,
2079 .alloc_by_type = intel_i830_alloc_by_type,
2080 .free_by_type = intel_i810_free_by_type,
2081 .agp_alloc_page = agp_generic_alloc_page,
2082 .agp_alloc_pages = agp_generic_alloc_pages,
2083 .agp_destroy_page = agp_generic_destroy_page,
2084 .agp_destroy_pages = agp_generic_destroy_pages,
2085 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2086 .chipset_flush = intel_i830_chipset_flush,
2089 static const struct agp_bridge_driver intel_820_driver = {
2090 .owner = THIS_MODULE,
2091 .aperture_sizes = intel_8xx_sizes,
2092 .size_type = U8_APER_SIZE,
2093 .num_aperture_sizes = 7,
2094 .configure = intel_820_configure,
2095 .fetch_size = intel_8xx_fetch_size,
2096 .cleanup = intel_820_cleanup,
2097 .tlb_flush = intel_820_tlbflush,
2098 .mask_memory = agp_generic_mask_memory,
2099 .masks = intel_generic_masks,
2100 .agp_enable = agp_generic_enable,
2101 .cache_flush = global_cache_flush,
2102 .create_gatt_table = agp_generic_create_gatt_table,
2103 .free_gatt_table = agp_generic_free_gatt_table,
2104 .insert_memory = agp_generic_insert_memory,
2105 .remove_memory = agp_generic_remove_memory,
2106 .alloc_by_type = agp_generic_alloc_by_type,
2107 .free_by_type = agp_generic_free_by_type,
2108 .agp_alloc_page = agp_generic_alloc_page,
2109 .agp_alloc_pages = agp_generic_alloc_pages,
2110 .agp_destroy_page = agp_generic_destroy_page,
2111 .agp_destroy_pages = agp_generic_destroy_pages,
2112 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2115 static const struct agp_bridge_driver intel_830mp_driver = {
2116 .owner = THIS_MODULE,
2117 .aperture_sizes = intel_830mp_sizes,
2118 .size_type = U8_APER_SIZE,
2119 .num_aperture_sizes = 4,
2120 .configure = intel_830mp_configure,
2121 .fetch_size = intel_8xx_fetch_size,
2122 .cleanup = intel_8xx_cleanup,
2123 .tlb_flush = intel_8xx_tlbflush,
2124 .mask_memory = agp_generic_mask_memory,
2125 .masks = intel_generic_masks,
2126 .agp_enable = agp_generic_enable,
2127 .cache_flush = global_cache_flush,
2128 .create_gatt_table = agp_generic_create_gatt_table,
2129 .free_gatt_table = agp_generic_free_gatt_table,
2130 .insert_memory = agp_generic_insert_memory,
2131 .remove_memory = agp_generic_remove_memory,
2132 .alloc_by_type = agp_generic_alloc_by_type,
2133 .free_by_type = agp_generic_free_by_type,
2134 .agp_alloc_page = agp_generic_alloc_page,
2135 .agp_alloc_pages = agp_generic_alloc_pages,
2136 .agp_destroy_page = agp_generic_destroy_page,
2137 .agp_destroy_pages = agp_generic_destroy_pages,
2138 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2141 static const struct agp_bridge_driver intel_840_driver = {
2142 .owner = THIS_MODULE,
2143 .aperture_sizes = intel_8xx_sizes,
2144 .size_type = U8_APER_SIZE,
2145 .num_aperture_sizes = 7,
2146 .configure = intel_840_configure,
2147 .fetch_size = intel_8xx_fetch_size,
2148 .cleanup = intel_8xx_cleanup,
2149 .tlb_flush = intel_8xx_tlbflush,
2150 .mask_memory = agp_generic_mask_memory,
2151 .masks = intel_generic_masks,
2152 .agp_enable = agp_generic_enable,
2153 .cache_flush = global_cache_flush,
2154 .create_gatt_table = agp_generic_create_gatt_table,
2155 .free_gatt_table = agp_generic_free_gatt_table,
2156 .insert_memory = agp_generic_insert_memory,
2157 .remove_memory = agp_generic_remove_memory,
2158 .alloc_by_type = agp_generic_alloc_by_type,
2159 .free_by_type = agp_generic_free_by_type,
2160 .agp_alloc_page = agp_generic_alloc_page,
2161 .agp_alloc_pages = agp_generic_alloc_pages,
2162 .agp_destroy_page = agp_generic_destroy_page,
2163 .agp_destroy_pages = agp_generic_destroy_pages,
2164 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2167 static const struct agp_bridge_driver intel_845_driver = {
2168 .owner = THIS_MODULE,
2169 .aperture_sizes = intel_8xx_sizes,
2170 .size_type = U8_APER_SIZE,
2171 .num_aperture_sizes = 7,
2172 .configure = intel_845_configure,
2173 .fetch_size = intel_8xx_fetch_size,
2174 .cleanup = intel_8xx_cleanup,
2175 .tlb_flush = intel_8xx_tlbflush,
2176 .mask_memory = agp_generic_mask_memory,
2177 .masks = intel_generic_masks,
2178 .agp_enable = agp_generic_enable,
2179 .cache_flush = global_cache_flush,
2180 .create_gatt_table = agp_generic_create_gatt_table,
2181 .free_gatt_table = agp_generic_free_gatt_table,
2182 .insert_memory = agp_generic_insert_memory,
2183 .remove_memory = agp_generic_remove_memory,
2184 .alloc_by_type = agp_generic_alloc_by_type,
2185 .free_by_type = agp_generic_free_by_type,
2186 .agp_alloc_page = agp_generic_alloc_page,
2187 .agp_alloc_pages = agp_generic_alloc_pages,
2188 .agp_destroy_page = agp_generic_destroy_page,
2189 .agp_destroy_pages = agp_generic_destroy_pages,
2190 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2191 .chipset_flush = intel_i830_chipset_flush,
2194 static const struct agp_bridge_driver intel_850_driver = {
2195 .owner = THIS_MODULE,
2196 .aperture_sizes = intel_8xx_sizes,
2197 .size_type = U8_APER_SIZE,
2198 .num_aperture_sizes = 7,
2199 .configure = intel_850_configure,
2200 .fetch_size = intel_8xx_fetch_size,
2201 .cleanup = intel_8xx_cleanup,
2202 .tlb_flush = intel_8xx_tlbflush,
2203 .mask_memory = agp_generic_mask_memory,
2204 .masks = intel_generic_masks,
2205 .agp_enable = agp_generic_enable,
2206 .cache_flush = global_cache_flush,
2207 .create_gatt_table = agp_generic_create_gatt_table,
2208 .free_gatt_table = agp_generic_free_gatt_table,
2209 .insert_memory = agp_generic_insert_memory,
2210 .remove_memory = agp_generic_remove_memory,
2211 .alloc_by_type = agp_generic_alloc_by_type,
2212 .free_by_type = agp_generic_free_by_type,
2213 .agp_alloc_page = agp_generic_alloc_page,
2214 .agp_alloc_pages = agp_generic_alloc_pages,
2215 .agp_destroy_page = agp_generic_destroy_page,
2216 .agp_destroy_pages = agp_generic_destroy_pages,
2217 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2220 static const struct agp_bridge_driver intel_860_driver = {
2221 .owner = THIS_MODULE,
2222 .aperture_sizes = intel_8xx_sizes,
2223 .size_type = U8_APER_SIZE,
2224 .num_aperture_sizes = 7,
2225 .configure = intel_860_configure,
2226 .fetch_size = intel_8xx_fetch_size,
2227 .cleanup = intel_8xx_cleanup,
2228 .tlb_flush = intel_8xx_tlbflush,
2229 .mask_memory = agp_generic_mask_memory,
2230 .masks = intel_generic_masks,
2231 .agp_enable = agp_generic_enable,
2232 .cache_flush = global_cache_flush,
2233 .create_gatt_table = agp_generic_create_gatt_table,
2234 .free_gatt_table = agp_generic_free_gatt_table,
2235 .insert_memory = agp_generic_insert_memory,
2236 .remove_memory = agp_generic_remove_memory,
2237 .alloc_by_type = agp_generic_alloc_by_type,
2238 .free_by_type = agp_generic_free_by_type,
2239 .agp_alloc_page = agp_generic_alloc_page,
2240 .agp_alloc_pages = agp_generic_alloc_pages,
2241 .agp_destroy_page = agp_generic_destroy_page,
2242 .agp_destroy_pages = agp_generic_destroy_pages,
2243 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2246 static const struct agp_bridge_driver intel_915_driver = {
2247 .owner = THIS_MODULE,
2248 .aperture_sizes = intel_i830_sizes,
2249 .size_type = FIXED_APER_SIZE,
2250 .num_aperture_sizes = 4,
2251 .needs_scratch_page = true,
2252 .configure = intel_i915_configure,
2253 .fetch_size = intel_i9xx_fetch_size,
2254 .cleanup = intel_i915_cleanup,
2255 .tlb_flush = intel_i810_tlbflush,
2256 .mask_memory = intel_i810_mask_memory,
2257 .masks = intel_i810_masks,
2258 .agp_enable = intel_i810_agp_enable,
2259 .cache_flush = global_cache_flush,
2260 .create_gatt_table = intel_i915_create_gatt_table,
2261 .free_gatt_table = intel_i830_free_gatt_table,
2262 .insert_memory = intel_i915_insert_entries,
2263 .remove_memory = intel_i915_remove_entries,
2264 .alloc_by_type = intel_i830_alloc_by_type,
2265 .free_by_type = intel_i810_free_by_type,
2266 .agp_alloc_page = agp_generic_alloc_page,
2267 .agp_alloc_pages = agp_generic_alloc_pages,
2268 .agp_destroy_page = agp_generic_destroy_page,
2269 .agp_destroy_pages = agp_generic_destroy_pages,
2270 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2271 .chipset_flush = intel_i915_chipset_flush,
2272 #ifdef USE_PCI_DMA_API
2273 .agp_map_page = intel_agp_map_page,
2274 .agp_unmap_page = intel_agp_unmap_page,
2275 .agp_map_memory = intel_agp_map_memory,
2276 .agp_unmap_memory = intel_agp_unmap_memory,
2280 static const struct agp_bridge_driver intel_i965_driver = {
2281 .owner = THIS_MODULE,
2282 .aperture_sizes = intel_i830_sizes,
2283 .size_type = FIXED_APER_SIZE,
2284 .num_aperture_sizes = 4,
2285 .needs_scratch_page = true,
2286 .configure = intel_i915_configure,
2287 .fetch_size = intel_i9xx_fetch_size,
2288 .cleanup = intel_i915_cleanup,
2289 .tlb_flush = intel_i810_tlbflush,
2290 .mask_memory = intel_i965_mask_memory,
2291 .masks = intel_i810_masks,
2292 .agp_enable = intel_i810_agp_enable,
2293 .cache_flush = global_cache_flush,
2294 .create_gatt_table = intel_i965_create_gatt_table,
2295 .free_gatt_table = intel_i830_free_gatt_table,
2296 .insert_memory = intel_i915_insert_entries,
2297 .remove_memory = intel_i915_remove_entries,
2298 .alloc_by_type = intel_i830_alloc_by_type,
2299 .free_by_type = intel_i810_free_by_type,
2300 .agp_alloc_page = agp_generic_alloc_page,
2301 .agp_alloc_pages = agp_generic_alloc_pages,
2302 .agp_destroy_page = agp_generic_destroy_page,
2303 .agp_destroy_pages = agp_generic_destroy_pages,
2304 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2305 .chipset_flush = intel_i915_chipset_flush,
2306 #ifdef USE_PCI_DMA_API
2307 .agp_map_page = intel_agp_map_page,
2308 .agp_unmap_page = intel_agp_unmap_page,
2309 .agp_map_memory = intel_agp_map_memory,
2310 .agp_unmap_memory = intel_agp_unmap_memory,
2314 static const struct agp_bridge_driver intel_7505_driver = {
2315 .owner = THIS_MODULE,
2316 .aperture_sizes = intel_8xx_sizes,
2317 .size_type = U8_APER_SIZE,
2318 .num_aperture_sizes = 7,
2319 .configure = intel_7505_configure,
2320 .fetch_size = intel_8xx_fetch_size,
2321 .cleanup = intel_8xx_cleanup,
2322 .tlb_flush = intel_8xx_tlbflush,
2323 .mask_memory = agp_generic_mask_memory,
2324 .masks = intel_generic_masks,
2325 .agp_enable = agp_generic_enable,
2326 .cache_flush = global_cache_flush,
2327 .create_gatt_table = agp_generic_create_gatt_table,
2328 .free_gatt_table = agp_generic_free_gatt_table,
2329 .insert_memory = agp_generic_insert_memory,
2330 .remove_memory = agp_generic_remove_memory,
2331 .alloc_by_type = agp_generic_alloc_by_type,
2332 .free_by_type = agp_generic_free_by_type,
2333 .agp_alloc_page = agp_generic_alloc_page,
2334 .agp_alloc_pages = agp_generic_alloc_pages,
2335 .agp_destroy_page = agp_generic_destroy_page,
2336 .agp_destroy_pages = agp_generic_destroy_pages,
2337 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2340 static const struct agp_bridge_driver intel_g33_driver = {
2341 .owner = THIS_MODULE,
2342 .aperture_sizes = intel_i830_sizes,
2343 .size_type = FIXED_APER_SIZE,
2344 .num_aperture_sizes = 4,
2345 .needs_scratch_page = true,
2346 .configure = intel_i915_configure,
2347 .fetch_size = intel_i9xx_fetch_size,
2348 .cleanup = intel_i915_cleanup,
2349 .tlb_flush = intel_i810_tlbflush,
2350 .mask_memory = intel_i965_mask_memory,
2351 .masks = intel_i810_masks,
2352 .agp_enable = intel_i810_agp_enable,
2353 .cache_flush = global_cache_flush,
2354 .create_gatt_table = intel_i915_create_gatt_table,
2355 .free_gatt_table = intel_i830_free_gatt_table,
2356 .insert_memory = intel_i915_insert_entries,
2357 .remove_memory = intel_i915_remove_entries,
2358 .alloc_by_type = intel_i830_alloc_by_type,
2359 .free_by_type = intel_i810_free_by_type,
2360 .agp_alloc_page = agp_generic_alloc_page,
2361 .agp_alloc_pages = agp_generic_alloc_pages,
2362 .agp_destroy_page = agp_generic_destroy_page,
2363 .agp_destroy_pages = agp_generic_destroy_pages,
2364 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2365 .chipset_flush = intel_i915_chipset_flush,
2366 #ifdef USE_PCI_DMA_API
2367 .agp_map_page = intel_agp_map_page,
2368 .agp_unmap_page = intel_agp_unmap_page,
2369 .agp_map_memory = intel_agp_map_memory,
2370 .agp_unmap_memory = intel_agp_unmap_memory,
2374 static int find_gmch(u16 device)
2376 struct pci_dev *gmch_device;
2378 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2379 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2380 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2381 device, gmch_device);
2387 intel_private.pcidev = gmch_device;
2391 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
2392 * driver and gmch_driver must be non-null, and find_gmch will determine
2393 * which one should be used if a gmch_chip_id is present.
2395 static const struct intel_driver_description {
2396 unsigned int chip_id;
2397 unsigned int gmch_chip_id;
2398 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2400 const struct agp_bridge_driver *driver;
2401 const struct agp_bridge_driver *gmch_driver;
2402 } intel_agp_chipsets[] = {
2403 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2404 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2405 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2406 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2407 NULL, &intel_810_driver },
2408 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2409 NULL, &intel_810_driver },
2410 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2411 NULL, &intel_810_driver },
2412 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2413 &intel_815_driver, &intel_810_driver },
2414 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2415 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2416 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2417 &intel_830mp_driver, &intel_830_driver },
2418 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2419 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2420 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2421 &intel_845_driver, &intel_830_driver },
2422 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2423 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2424 &intel_845_driver, &intel_830_driver },
2425 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2426 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2427 &intel_845_driver, &intel_830_driver },
2428 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2429 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2430 &intel_845_driver, &intel_830_driver },
2431 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2432 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2433 NULL, &intel_915_driver },
2434 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2435 NULL, &intel_915_driver },
2436 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2437 NULL, &intel_915_driver },
2438 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2439 NULL, &intel_915_driver },
2440 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2441 NULL, &intel_915_driver },
2442 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2443 NULL, &intel_915_driver },
2444 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2445 NULL, &intel_i965_driver },
2446 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2447 NULL, &intel_i965_driver },
2448 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2449 NULL, &intel_i965_driver },
2450 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2451 NULL, &intel_i965_driver },
2452 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2453 NULL, &intel_i965_driver },
2454 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2455 NULL, &intel_i965_driver },
2456 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2457 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2458 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2459 NULL, &intel_g33_driver },
2460 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2461 NULL, &intel_g33_driver },
2462 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2463 NULL, &intel_g33_driver },
2464 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, 0, "GMA3150",
2465 NULL, &intel_g33_driver },
2466 { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, 0, "GMA3150",
2467 NULL, &intel_g33_driver },
2468 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2469 "GM45", NULL, &intel_i965_driver },
2470 { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, 0,
2471 "Eaglelake", NULL, &intel_i965_driver },
2472 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2473 "Q45/Q43", NULL, &intel_i965_driver },
2474 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2475 "G45/G43", NULL, &intel_i965_driver },
2476 { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0,
2477 "B43", NULL, &intel_i965_driver },
2478 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2479 "G41", NULL, &intel_i965_driver },
2480 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 0,
2481 "HD Graphics", NULL, &intel_i965_driver },
2482 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2483 "HD Graphics", NULL, &intel_i965_driver },
2484 { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2485 "HD Graphics", NULL, &intel_i965_driver },
2486 { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2487 "HD Graphics", NULL, &intel_i965_driver },
2488 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG, 0,
2489 "Sandybridge", NULL, &intel_i965_driver },
2490 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG, 0,
2491 "Sandybridge", NULL, &intel_i965_driver },
2492 { 0, 0, 0, NULL, NULL, NULL }
2495 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2496 const struct pci_device_id *ent)
2498 struct agp_bridge_data *bridge;
2503 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2505 bridge = agp_alloc_bridge();
2509 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2510 /* In case that multiple models of gfx chip may
2511 stand on same host bridge type, this can be
2512 sure we detect the right IGD. */
2513 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2514 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2515 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2517 intel_agp_chipsets[i].gmch_driver;
2519 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2522 bridge->driver = intel_agp_chipsets[i].driver;
2528 if (intel_agp_chipsets[i].name == NULL) {
2530 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2531 pdev->vendor, pdev->device);
2532 agp_put_bridge(bridge);
2536 if (bridge->driver == NULL) {
2537 /* bridge has no AGP and no IGD detected */
2539 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2540 intel_agp_chipsets[i].gmch_chip_id);
2541 agp_put_bridge(bridge);
2546 bridge->capndx = cap_ptr;
2547 bridge->dev_private_data = &intel_private;
2549 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2552 * The following fixes the case where the BIOS has "forgotten" to
2553 * provide an address range for the GART.
2554 * 20030610 - hamish@zot.org
2556 r = &pdev->resource[0];
2557 if (!r->start && r->end) {
2558 if (pci_assign_resource(pdev, 0)) {
2559 dev_err(&pdev->dev, "can't assign resource 0\n");
2560 agp_put_bridge(bridge);
2566 * If the device has not been properly setup, the following will catch
2567 * the problem and should stop the system from crashing.
2568 * 20030610 - hamish@zot.org
2570 if (pci_enable_device(pdev)) {
2571 dev_err(&pdev->dev, "can't enable PCI device\n");
2572 agp_put_bridge(bridge);
2576 /* Fill in the mode register */
2578 pci_read_config_dword(pdev,
2579 bridge->capndx+PCI_AGP_STATUS,
2583 if (bridge->driver->mask_memory == intel_i965_mask_memory) {
2584 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
2585 dev_err(&intel_private.pcidev->dev,
2586 "set gfx device dma mask 36bit failed!\n");
2588 pci_set_consistent_dma_mask(intel_private.pcidev,
2592 pci_set_drvdata(pdev, bridge);
2593 err = agp_add_bridge(bridge);
2595 intel_agp_enabled = 1;
2599 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2601 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2603 agp_remove_bridge(bridge);
2605 if (intel_private.pcidev)
2606 pci_dev_put(intel_private.pcidev);
2608 agp_put_bridge(bridge);
2612 static int agp_intel_resume(struct pci_dev *pdev)
2614 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2617 if (bridge->driver == &intel_generic_driver)
2619 else if (bridge->driver == &intel_850_driver)
2620 intel_850_configure();
2621 else if (bridge->driver == &intel_845_driver)
2622 intel_845_configure();
2623 else if (bridge->driver == &intel_830mp_driver)
2624 intel_830mp_configure();
2625 else if (bridge->driver == &intel_915_driver)
2626 intel_i915_configure();
2627 else if (bridge->driver == &intel_830_driver)
2628 intel_i830_configure();
2629 else if (bridge->driver == &intel_810_driver)
2630 intel_i810_configure();
2631 else if (bridge->driver == &intel_i965_driver)
2632 intel_i915_configure();
2634 ret_val = agp_rebind_memory();
2642 static struct pci_device_id agp_intel_pci_table[] = {
2645 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2647 .vendor = PCI_VENDOR_ID_INTEL, \
2649 .subvendor = PCI_ANY_ID, \
2650 .subdevice = PCI_ANY_ID, \
2652 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2653 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2654 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2655 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2656 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2657 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2658 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2659 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2660 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2661 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2662 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2663 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2664 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2665 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2666 ID(PCI_DEVICE_ID_INTEL_82854_HB),
2667 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2668 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2669 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2670 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2671 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2672 ID(PCI_DEVICE_ID_INTEL_7505_0),
2673 ID(PCI_DEVICE_ID_INTEL_7205_0),
2674 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2675 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2676 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2677 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2678 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2679 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2680 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB),
2681 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB),
2682 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2683 ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2684 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2685 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2686 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2687 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2688 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2689 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2690 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2691 ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2692 ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB),
2693 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2694 ID(PCI_DEVICE_ID_INTEL_G45_HB),
2695 ID(PCI_DEVICE_ID_INTEL_G41_HB),
2696 ID(PCI_DEVICE_ID_INTEL_B43_HB),
2697 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
2698 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
2699 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
2700 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
2701 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),
2702 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),
2706 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2708 static struct pci_driver agp_intel_pci_driver = {
2709 .name = "agpgart-intel",
2710 .id_table = agp_intel_pci_table,
2711 .probe = agp_intel_probe,
2712 .remove = __devexit_p(agp_intel_remove),
2714 .resume = agp_intel_resume,
2718 static int __init agp_intel_init(void)
2722 return pci_register_driver(&agp_intel_pci_driver);
2725 static void __exit agp_intel_cleanup(void)
2727 pci_unregister_driver(&agp_intel_pci_driver);
2730 module_init(agp_intel_init);
2731 module_exit(agp_intel_cleanup);
2733 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2734 MODULE_LICENSE("GPL and additional rights");