1 // SPDX-License-Identifier: GPL-2.0
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
8 #include <linux/clkdev.h>
9 #include <linux/delay.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_domain.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
15 #include <linux/of_address.h>
16 #include <linux/of_platform.h>
17 #include <linux/slab.h>
18 #include <linux/iopoll.h>
20 #include <linux/platform_data/ti-sysc.h>
22 #include <dt-bindings/bus/ti-sysc.h>
24 #define MAX_MODULE_SOFTRESET_WAIT 10000
26 static const char * const reg_names[] = { "rev", "sysc", "syss", };
42 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
43 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
44 "opt5", "opt6", "opt7",
47 #define SYSC_IDLEMODE_MASK 3
48 #define SYSC_CLOCKACTIVITY_MASK 3
51 * struct sysc - TI sysc interconnect target module registers and capabilities
52 * @dev: struct device pointer
53 * @module_pa: physical address of the interconnect target module
54 * @module_size: size of the interconnect target module
55 * @module_va: virtual address of the interconnect target module
56 * @offsets: register offsets from module base
57 * @mdata: ti-sysc to hwmod translation data for a module
58 * @clocks: clocks used by the interconnect target module
59 * @clock_roles: clock role names for the found clocks
60 * @nr_clocks: number of clocks used by the interconnect target module
61 * @rsts: resets used by the interconnect target module
62 * @legacy_mode: configured for legacy mode if set
63 * @cap: interconnect target module capabilities
64 * @cfg: interconnect target module configuration
65 * @cookie: data used by legacy platform callbacks
66 * @name: name if available
67 * @revision: interconnect target module revision
68 * @enabled: sysc runtime enabled status
69 * @needs_resume: runtime resume needed on resume from suspend
70 * @child_needs_resume: runtime resume needed for child on resume from suspend
71 * @disable_on_idle: status flag used for disabling modules with resets
72 * @idle_work: work structure used to perform delayed idle on a module
73 * @clk_enable_quirk: module specific clock enable quirk
74 * @clk_disable_quirk: module specific clock disable quirk
75 * @reset_done_quirk: module specific reset done quirk
76 * @module_enable_quirk: module specific enable quirk
77 * @module_disable_quirk: module specific disable quirk
83 void __iomem *module_va;
84 int offsets[SYSC_MAX_REGS];
85 struct ti_sysc_module_data *mdata;
87 const char **clock_roles;
89 struct reset_control *rsts;
90 const char *legacy_mode;
91 const struct sysc_capabilities *cap;
92 struct sysc_config cfg;
93 struct ti_sysc_cookie cookie;
96 unsigned int enabled:1;
97 unsigned int needs_resume:1;
98 unsigned int child_needs_resume:1;
99 struct delayed_work idle_work;
100 void (*clk_enable_quirk)(struct sysc *sysc);
101 void (*clk_disable_quirk)(struct sysc *sysc);
102 void (*reset_done_quirk)(struct sysc *sysc);
103 void (*module_enable_quirk)(struct sysc *sysc);
104 void (*module_disable_quirk)(struct sysc *sysc);
107 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
110 static void sysc_write(struct sysc *ddata, int offset, u32 value)
112 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
113 writew_relaxed(value & 0xffff, ddata->module_va + offset);
115 /* Only i2c revision has LO and HI register with stride of 4 */
116 if (ddata->offsets[SYSC_REVISION] >= 0 &&
117 offset == ddata->offsets[SYSC_REVISION]) {
118 u16 hi = value >> 16;
120 writew_relaxed(hi, ddata->module_va + offset + 4);
126 writel_relaxed(value, ddata->module_va + offset);
129 static u32 sysc_read(struct sysc *ddata, int offset)
131 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
134 val = readw_relaxed(ddata->module_va + offset);
136 /* Only i2c revision has LO and HI register with stride of 4 */
137 if (ddata->offsets[SYSC_REVISION] >= 0 &&
138 offset == ddata->offsets[SYSC_REVISION]) {
139 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
147 return readl_relaxed(ddata->module_va + offset);
150 static bool sysc_opt_clks_needed(struct sysc *ddata)
152 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
155 static u32 sysc_read_revision(struct sysc *ddata)
157 int offset = ddata->offsets[SYSC_REVISION];
162 return sysc_read(ddata, offset);
165 static u32 sysc_read_sysconfig(struct sysc *ddata)
167 int offset = ddata->offsets[SYSC_SYSCONFIG];
172 return sysc_read(ddata, offset);
175 static u32 sysc_read_sysstatus(struct sysc *ddata)
177 int offset = ddata->offsets[SYSC_SYSSTATUS];
182 return sysc_read(ddata, offset);
185 static int sysc_add_named_clock_from_child(struct sysc *ddata,
187 const char *optfck_name)
189 struct device_node *np = ddata->dev->of_node;
190 struct device_node *child;
191 struct clk_lookup *cl;
200 /* Does the clock alias already exist? */
201 clock = of_clk_get_by_name(np, n);
202 if (!IS_ERR(clock)) {
208 child = of_get_next_available_child(np, NULL);
212 clock = devm_get_clk_from_child(ddata->dev, child, name);
214 return PTR_ERR(clock);
217 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
218 * limit for clk_get(). If cl ever needs to be freed, it should be done
219 * with clkdev_drop().
221 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
226 cl->dev_id = dev_name(ddata->dev);
235 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
237 const char *optfck_name;
240 if (ddata->nr_clocks < SYSC_OPTFCK0)
241 index = SYSC_OPTFCK0;
243 index = ddata->nr_clocks;
248 optfck_name = clock_names[index];
250 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
254 ddata->clock_roles[index] = optfck_name;
260 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
262 int error, i, index = -ENODEV;
264 if (!strncmp(clock_names[SYSC_FCK], name, 3))
266 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
270 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
271 if (!ddata->clocks[i]) {
279 dev_err(ddata->dev, "clock %s not added\n", name);
283 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
284 if (IS_ERR(ddata->clocks[index])) {
285 dev_err(ddata->dev, "clock get error for %s: %li\n",
286 name, PTR_ERR(ddata->clocks[index]));
288 return PTR_ERR(ddata->clocks[index]);
291 error = clk_prepare(ddata->clocks[index]);
293 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
302 static int sysc_get_clocks(struct sysc *ddata)
304 struct device_node *np = ddata->dev->of_node;
305 struct property *prop;
307 int nr_fck = 0, nr_ick = 0, i, error = 0;
309 ddata->clock_roles = devm_kcalloc(ddata->dev,
311 sizeof(*ddata->clock_roles),
313 if (!ddata->clock_roles)
316 of_property_for_each_string(np, "clock-names", prop, name) {
317 if (!strncmp(clock_names[SYSC_FCK], name, 3))
319 if (!strncmp(clock_names[SYSC_ICK], name, 3))
321 ddata->clock_roles[ddata->nr_clocks] = name;
325 if (ddata->nr_clocks < 1)
328 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
329 error = sysc_init_ext_opt_clock(ddata, NULL);
334 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
335 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
340 if (nr_fck > 1 || nr_ick > 1) {
341 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
346 /* Always add a slot for main clocks fck and ick even if unused */
352 ddata->clocks = devm_kcalloc(ddata->dev,
353 ddata->nr_clocks, sizeof(*ddata->clocks),
358 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
359 const char *name = ddata->clock_roles[i];
364 error = sysc_get_one_clock(ddata, name);
372 static int sysc_enable_main_clocks(struct sysc *ddata)
380 for (i = 0; i < SYSC_OPTFCK0; i++) {
381 clock = ddata->clocks[i];
383 /* Main clocks may not have ick */
384 if (IS_ERR_OR_NULL(clock))
387 error = clk_enable(clock);
395 for (i--; i >= 0; i--) {
396 clock = ddata->clocks[i];
398 /* Main clocks may not have ick */
399 if (IS_ERR_OR_NULL(clock))
408 static void sysc_disable_main_clocks(struct sysc *ddata)
416 for (i = 0; i < SYSC_OPTFCK0; i++) {
417 clock = ddata->clocks[i];
418 if (IS_ERR_OR_NULL(clock))
425 static int sysc_enable_opt_clocks(struct sysc *ddata)
430 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
433 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
434 clock = ddata->clocks[i];
436 /* Assume no holes for opt clocks */
437 if (IS_ERR_OR_NULL(clock))
440 error = clk_enable(clock);
448 for (i--; i >= 0; i--) {
449 clock = ddata->clocks[i];
450 if (IS_ERR_OR_NULL(clock))
459 static void sysc_disable_opt_clocks(struct sysc *ddata)
464 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
467 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
468 clock = ddata->clocks[i];
470 /* Assume no holes for opt clocks */
471 if (IS_ERR_OR_NULL(clock))
478 static void sysc_clkdm_deny_idle(struct sysc *ddata)
480 struct ti_sysc_platform_data *pdata;
482 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
485 pdata = dev_get_platdata(ddata->dev);
486 if (pdata && pdata->clkdm_deny_idle)
487 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
490 static void sysc_clkdm_allow_idle(struct sysc *ddata)
492 struct ti_sysc_platform_data *pdata;
494 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
497 pdata = dev_get_platdata(ddata->dev);
498 if (pdata && pdata->clkdm_allow_idle)
499 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
503 * sysc_init_resets - init rstctrl reset line if configured
504 * @ddata: device driver data
506 * See sysc_rstctrl_reset_deassert().
508 static int sysc_init_resets(struct sysc *ddata)
511 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
513 return PTR_ERR_OR_ZERO(ddata->rsts);
517 * sysc_parse_and_check_child_range - parses module IO region from ranges
518 * @ddata: device driver data
520 * In general we only need rev, syss, and sysc registers and not the whole
521 * module range. But we do want the offsets for these registers from the
522 * module base. This allows us to check them against the legacy hwmod
523 * platform data. Let's also check the ranges are configured properly.
525 static int sysc_parse_and_check_child_range(struct sysc *ddata)
527 struct device_node *np = ddata->dev->of_node;
528 const __be32 *ranges;
529 u32 nr_addr, nr_size;
532 ranges = of_get_property(np, "ranges", &len);
534 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
539 len /= sizeof(*ranges);
542 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
547 error = of_property_read_u32(np, "#address-cells", &nr_addr);
551 error = of_property_read_u32(np, "#size-cells", &nr_size);
555 if (nr_addr != 1 || nr_size != 1) {
556 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
562 ddata->module_pa = of_translate_address(np, ranges++);
563 ddata->module_size = be32_to_cpup(ranges);
568 static struct device_node *stdout_path;
570 static void sysc_init_stdout_path(struct sysc *ddata)
572 struct device_node *np = NULL;
575 if (IS_ERR(stdout_path))
581 np = of_find_node_by_path("/chosen");
585 uart = of_get_property(np, "stdout-path", NULL);
589 np = of_find_node_by_path(uart);
598 stdout_path = ERR_PTR(-ENODEV);
601 static void sysc_check_quirk_stdout(struct sysc *ddata,
602 struct device_node *np)
604 sysc_init_stdout_path(ddata);
605 if (np != stdout_path)
608 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
609 SYSC_QUIRK_NO_RESET_ON_INIT;
613 * sysc_check_one_child - check child configuration
614 * @ddata: device driver data
615 * @np: child device node
617 * Let's avoid messy situations where we have new interconnect target
618 * node but children have "ti,hwmods". These belong to the interconnect
619 * target node and are managed by this driver.
621 static void sysc_check_one_child(struct sysc *ddata,
622 struct device_node *np)
626 name = of_get_property(np, "ti,hwmods", NULL);
628 dev_warn(ddata->dev, "really a child ti,hwmods property?");
630 sysc_check_quirk_stdout(ddata, np);
631 sysc_parse_dts_quirks(ddata, np, true);
634 static void sysc_check_children(struct sysc *ddata)
636 struct device_node *child;
638 for_each_child_of_node(ddata->dev->of_node, child)
639 sysc_check_one_child(ddata, child);
643 * So far only I2C uses 16-bit read access with clockactivity with revision
644 * in two registers with stride of 4. We can detect this based on the rev
645 * register size to configure things far enough to be able to properly read
646 * the revision register.
648 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
650 if (resource_size(res) == 8)
651 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
655 * sysc_parse_one - parses the interconnect target module registers
656 * @ddata: device driver data
657 * @reg: register to parse
659 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
661 struct resource *res;
668 name = reg_names[reg];
674 res = platform_get_resource_byname(to_platform_device(ddata->dev),
675 IORESOURCE_MEM, name);
677 ddata->offsets[reg] = -ENODEV;
682 ddata->offsets[reg] = res->start - ddata->module_pa;
683 if (reg == SYSC_REVISION)
684 sysc_check_quirk_16bit(ddata, res);
689 static int sysc_parse_registers(struct sysc *ddata)
693 for (i = 0; i < SYSC_MAX_REGS; i++) {
694 error = sysc_parse_one(ddata, i);
703 * sysc_check_registers - check for misconfigured register overlaps
704 * @ddata: device driver data
706 static int sysc_check_registers(struct sysc *ddata)
708 int i, j, nr_regs = 0, nr_matches = 0;
710 for (i = 0; i < SYSC_MAX_REGS; i++) {
711 if (ddata->offsets[i] < 0)
714 if (ddata->offsets[i] > (ddata->module_size - 4)) {
715 dev_err(ddata->dev, "register outside module range");
720 for (j = 0; j < SYSC_MAX_REGS; j++) {
721 if (ddata->offsets[j] < 0)
724 if (ddata->offsets[i] == ddata->offsets[j])
730 if (nr_matches > nr_regs) {
731 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
732 nr_regs, nr_matches);
741 * syc_ioremap - ioremap register space for the interconnect target module
742 * @ddata: device driver data
744 * Note that the interconnect target module registers can be anywhere
745 * within the interconnect target module range. For example, SGX has
746 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
747 * has them at offset 0x1200 in the CPSW_WR child. Usually the
748 * the interconnect target module registers are at the beginning of
749 * the module range though.
751 static int sysc_ioremap(struct sysc *ddata)
755 if (ddata->offsets[SYSC_REVISION] < 0 &&
756 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
757 ddata->offsets[SYSC_SYSSTATUS] < 0) {
758 size = ddata->module_size;
760 size = max3(ddata->offsets[SYSC_REVISION],
761 ddata->offsets[SYSC_SYSCONFIG],
762 ddata->offsets[SYSC_SYSSTATUS]);
767 if ((size + sizeof(u32)) > ddata->module_size)
768 size = ddata->module_size;
771 ddata->module_va = devm_ioremap(ddata->dev,
774 if (!ddata->module_va)
781 * sysc_map_and_check_registers - ioremap and check device registers
782 * @ddata: device driver data
784 static int sysc_map_and_check_registers(struct sysc *ddata)
788 error = sysc_parse_and_check_child_range(ddata);
792 sysc_check_children(ddata);
794 error = sysc_parse_registers(ddata);
798 error = sysc_ioremap(ddata);
802 error = sysc_check_registers(ddata);
810 * sysc_show_rev - read and show interconnect target module revision
811 * @bufp: buffer to print the information to
812 * @ddata: device driver data
814 static int sysc_show_rev(char *bufp, struct sysc *ddata)
818 if (ddata->offsets[SYSC_REVISION] < 0)
819 return sprintf(bufp, ":NA");
821 len = sprintf(bufp, ":%08x", ddata->revision);
826 static int sysc_show_reg(struct sysc *ddata,
827 char *bufp, enum sysc_registers reg)
829 if (ddata->offsets[reg] < 0)
830 return sprintf(bufp, ":NA");
832 return sprintf(bufp, ":%x", ddata->offsets[reg]);
835 static int sysc_show_name(char *bufp, struct sysc *ddata)
840 return sprintf(bufp, ":%s", ddata->name);
844 * sysc_show_registers - show information about interconnect target module
845 * @ddata: device driver data
847 static void sysc_show_registers(struct sysc *ddata)
853 for (i = 0; i < SYSC_MAX_REGS; i++)
854 bufp += sysc_show_reg(ddata, bufp, i);
856 bufp += sysc_show_rev(bufp, ddata);
857 bufp += sysc_show_name(bufp, ddata);
859 dev_dbg(ddata->dev, "%llx:%x%s\n",
860 ddata->module_pa, ddata->module_size,
864 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
865 #define SYSC_CLOCACT_ICK 2
867 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
868 static int sysc_enable_module(struct device *dev)
871 const struct sysc_regbits *regbits;
872 u32 reg, idlemodes, best_mode;
874 ddata = dev_get_drvdata(dev);
875 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
878 regbits = ddata->cap->regbits;
879 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
881 /* Set CLOCKACTIVITY, we only use it for ick */
882 if (regbits->clkact_shift >= 0 &&
883 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT ||
884 ddata->cfg.sysc_val & BIT(regbits->clkact_shift)))
885 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
888 idlemodes = ddata->cfg.sidlemodes;
889 if (!idlemodes || regbits->sidle_shift < 0)
892 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
893 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
894 best_mode = SYSC_IDLE_NO;
896 best_mode = fls(ddata->cfg.sidlemodes) - 1;
897 if (best_mode > SYSC_IDLE_MASK) {
898 dev_err(dev, "%s: invalid sidlemode\n", __func__);
903 if (regbits->enwkup_shift >= 0 &&
904 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
905 reg |= BIT(regbits->enwkup_shift);
908 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
909 reg |= best_mode << regbits->sidle_shift;
910 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
914 idlemodes = ddata->cfg.midlemodes;
915 if (!idlemodes || regbits->midle_shift < 0)
918 best_mode = fls(ddata->cfg.midlemodes) - 1;
919 if (best_mode > SYSC_IDLE_MASK) {
920 dev_err(dev, "%s: invalid midlemode\n", __func__);
924 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
925 best_mode = SYSC_IDLE_NO;
927 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
928 reg |= best_mode << regbits->midle_shift;
929 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
932 /* Autoidle bit must enabled separately if available */
933 if (regbits->autoidle_shift >= 0 &&
934 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
935 reg |= 1 << regbits->autoidle_shift;
936 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
939 if (ddata->module_enable_quirk)
940 ddata->module_enable_quirk(ddata);
945 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
947 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
948 *best_mode = SYSC_IDLE_SMART_WKUP;
949 else if (idlemodes & BIT(SYSC_IDLE_SMART))
950 *best_mode = SYSC_IDLE_SMART;
951 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
952 *best_mode = SYSC_IDLE_FORCE;
959 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
960 static int sysc_disable_module(struct device *dev)
963 const struct sysc_regbits *regbits;
964 u32 reg, idlemodes, best_mode;
967 ddata = dev_get_drvdata(dev);
968 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
971 if (ddata->module_disable_quirk)
972 ddata->module_disable_quirk(ddata);
974 regbits = ddata->cap->regbits;
975 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
978 idlemodes = ddata->cfg.midlemodes;
979 if (!idlemodes || regbits->midle_shift < 0)
982 ret = sysc_best_idle_mode(idlemodes, &best_mode);
984 dev_err(dev, "%s: invalid midlemode\n", __func__);
988 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
989 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
990 best_mode = SYSC_IDLE_FORCE;
992 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
993 reg |= best_mode << regbits->midle_shift;
994 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
998 idlemodes = ddata->cfg.sidlemodes;
999 if (!idlemodes || regbits->sidle_shift < 0)
1002 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1003 best_mode = SYSC_IDLE_FORCE;
1005 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1007 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1012 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1013 reg |= best_mode << regbits->sidle_shift;
1014 if (regbits->autoidle_shift >= 0 &&
1015 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1016 reg |= 1 << regbits->autoidle_shift;
1017 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1022 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1025 struct ti_sysc_platform_data *pdata;
1028 pdata = dev_get_platdata(ddata->dev);
1032 if (!pdata->idle_module)
1035 error = pdata->idle_module(dev, &ddata->cookie);
1037 dev_err(dev, "%s: could not idle: %i\n",
1040 reset_control_assert(ddata->rsts);
1045 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1048 struct ti_sysc_platform_data *pdata;
1051 pdata = dev_get_platdata(ddata->dev);
1055 if (!pdata->enable_module)
1058 error = pdata->enable_module(dev, &ddata->cookie);
1060 dev_err(dev, "%s: could not enable: %i\n",
1063 reset_control_deassert(ddata->rsts);
1068 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1073 ddata = dev_get_drvdata(dev);
1075 if (!ddata->enabled)
1078 sysc_clkdm_deny_idle(ddata);
1080 if (ddata->legacy_mode) {
1081 error = sysc_runtime_suspend_legacy(dev, ddata);
1083 goto err_allow_idle;
1085 error = sysc_disable_module(dev);
1087 goto err_allow_idle;
1090 sysc_disable_main_clocks(ddata);
1092 if (sysc_opt_clks_needed(ddata))
1093 sysc_disable_opt_clocks(ddata);
1095 ddata->enabled = false;
1098 reset_control_assert(ddata->rsts);
1100 sysc_clkdm_allow_idle(ddata);
1105 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1110 ddata = dev_get_drvdata(dev);
1116 sysc_clkdm_deny_idle(ddata);
1118 if (sysc_opt_clks_needed(ddata)) {
1119 error = sysc_enable_opt_clocks(ddata);
1121 goto err_allow_idle;
1124 error = sysc_enable_main_clocks(ddata);
1126 goto err_opt_clocks;
1128 reset_control_deassert(ddata->rsts);
1130 if (ddata->legacy_mode) {
1131 error = sysc_runtime_resume_legacy(dev, ddata);
1133 goto err_main_clocks;
1135 error = sysc_enable_module(dev);
1137 goto err_main_clocks;
1140 ddata->enabled = true;
1142 sysc_clkdm_allow_idle(ddata);
1147 sysc_disable_main_clocks(ddata);
1149 if (sysc_opt_clks_needed(ddata))
1150 sysc_disable_opt_clocks(ddata);
1152 sysc_clkdm_allow_idle(ddata);
1157 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1161 ddata = dev_get_drvdata(dev);
1163 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1166 return pm_runtime_force_suspend(dev);
1169 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1173 ddata = dev_get_drvdata(dev);
1175 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1178 return pm_runtime_force_resume(dev);
1181 static const struct dev_pm_ops sysc_pm_ops = {
1182 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1183 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1184 sysc_runtime_resume,
1188 /* Module revision register based quirks */
1189 struct sysc_revision_quirk {
1200 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1201 optrev_val, optrevmask, optquirkmask) \
1203 .name = (optname), \
1204 .base = (optbase), \
1205 .rev_offset = (optrev), \
1206 .sysc_offset = (optsysc), \
1207 .syss_offset = (optsyss), \
1208 .revision = (optrev_val), \
1209 .revision_mask = (optrevmask), \
1210 .quirks = (optquirkmask), \
1213 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1214 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1215 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1216 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1217 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1218 SYSC_QUIRK_LEGACY_IDLE),
1219 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
1220 SYSC_QUIRK_LEGACY_IDLE),
1221 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
1222 SYSC_QUIRK_LEGACY_IDLE),
1223 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
1225 /* Some timers on omap4 and later */
1226 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
1228 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
1230 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1231 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1232 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1233 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1234 /* Uarts on omap4 and later */
1235 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1236 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1237 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1238 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1240 /* Quirks that need to be set based on the module address */
1241 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff,
1242 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1243 SYSC_QUIRK_SWSUP_SIDLE),
1245 /* Quirks that need to be set based on detected module */
1246 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff,
1247 SYSC_MODULE_QUIRK_AESS),
1248 SYSC_QUIRK("dcan", 0x48480000, 0x20, -1, -1, 0xa3170504, 0xffffffff,
1249 SYSC_QUIRK_CLKDM_NOAUTO),
1250 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -1, 0x500a0200, 0xffffffff,
1251 SYSC_QUIRK_CLKDM_NOAUTO),
1252 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -1, 0x500a0200, 0xffffffff,
1253 SYSC_QUIRK_CLKDM_NOAUTO),
1254 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1255 SYSC_MODULE_QUIRK_HDQ1W),
1256 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1257 SYSC_MODULE_QUIRK_HDQ1W),
1258 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1259 SYSC_MODULE_QUIRK_I2C),
1260 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1261 SYSC_MODULE_QUIRK_I2C),
1262 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1263 SYSC_MODULE_QUIRK_I2C),
1264 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1265 SYSC_MODULE_QUIRK_I2C),
1266 SYSC_QUIRK("gpu", 0x50000000, 0x14, -1, -1, 0x00010201, 0xffffffff, 0),
1267 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff,
1268 SYSC_MODULE_QUIRK_SGX),
1269 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff,
1270 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1271 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1272 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1273 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -1, 0x4ea2080d, 0xffffffff,
1274 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1275 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1276 SYSC_MODULE_QUIRK_WDT),
1277 /* Watchdog on am3 and am4 */
1278 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1279 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1282 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
1283 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
1284 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
1285 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1286 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1288 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0xa3170504, 0xffffffff, 0),
1289 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0),
1290 SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
1291 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
1292 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1293 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1294 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
1295 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
1296 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 0),
1297 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1298 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
1299 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
1300 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0),
1301 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
1302 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0),
1303 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1304 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
1305 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0),
1306 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1307 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0),
1308 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0),
1309 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0),
1310 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0),
1311 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0),
1312 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0),
1313 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1314 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0),
1315 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0),
1316 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0),
1317 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0),
1318 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0),
1319 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1320 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1321 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
1322 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
1323 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
1324 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0),
1325 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0),
1326 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0),
1327 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1328 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1329 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
1330 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
1331 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
1336 * Early quirks based on module base and register offsets only that are
1337 * needed before the module revision can be read
1339 static void sysc_init_early_quirks(struct sysc *ddata)
1341 const struct sysc_revision_quirk *q;
1344 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1345 q = &sysc_revision_quirks[i];
1350 if (q->base != ddata->module_pa)
1353 if (q->rev_offset >= 0 &&
1354 q->rev_offset != ddata->offsets[SYSC_REVISION])
1357 if (q->sysc_offset >= 0 &&
1358 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1361 if (q->syss_offset >= 0 &&
1362 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1365 ddata->name = q->name;
1366 ddata->cfg.quirks |= q->quirks;
1370 /* Quirks that also consider the revision register value */
1371 static void sysc_init_revision_quirks(struct sysc *ddata)
1373 const struct sysc_revision_quirk *q;
1376 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1377 q = &sysc_revision_quirks[i];
1379 if (q->base && q->base != ddata->module_pa)
1382 if (q->rev_offset >= 0 &&
1383 q->rev_offset != ddata->offsets[SYSC_REVISION])
1386 if (q->sysc_offset >= 0 &&
1387 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1390 if (q->syss_offset >= 0 &&
1391 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1394 if (q->revision == ddata->revision ||
1395 (q->revision & q->revision_mask) ==
1396 (ddata->revision & q->revision_mask)) {
1397 ddata->name = q->name;
1398 ddata->cfg.quirks |= q->quirks;
1403 /* 1-wire needs module's internal clocks enabled for reset */
1404 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1406 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1409 val = sysc_read(ddata, offset);
1411 sysc_write(ddata, offset, val);
1414 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
1415 static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1417 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1419 sysc_write(ddata, offset, 1);
1422 /* I2C needs extra enable bit toggling for reset */
1423 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1428 /* I2C_CON, omap2/3 is different from omap4 and later */
1429 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1435 val = sysc_read(ddata, offset);
1440 sysc_write(ddata, offset, val);
1443 static void sysc_clk_enable_quirk_i2c(struct sysc *ddata)
1445 sysc_clk_quirk_i2c(ddata, true);
1448 static void sysc_clk_disable_quirk_i2c(struct sysc *ddata)
1450 sysc_clk_quirk_i2c(ddata, false);
1453 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1454 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1456 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1457 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1459 sysc_write(ddata, offset, val);
1462 /* Watchdog timer needs a disable sequence after reset */
1463 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1465 int wps, spr, error;
1471 sysc_write(ddata, spr, 0xaaaa);
1472 error = readl_poll_timeout(ddata->module_va + wps, val,
1474 MAX_MODULE_SOFTRESET_WAIT);
1476 dev_warn(ddata->dev, "wdt disable step1 failed\n");
1478 sysc_write(ddata, spr, 0x5555);
1479 error = readl_poll_timeout(ddata->module_va + wps, val,
1481 MAX_MODULE_SOFTRESET_WAIT);
1483 dev_warn(ddata->dev, "wdt disable step2 failed\n");
1486 static void sysc_init_module_quirks(struct sysc *ddata)
1488 if (ddata->legacy_mode || !ddata->name)
1491 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1492 ddata->clk_disable_quirk = sysc_pre_reset_quirk_hdq1w;
1497 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1498 ddata->clk_enable_quirk = sysc_clk_enable_quirk_i2c;
1499 ddata->clk_disable_quirk = sysc_clk_disable_quirk_i2c;
1504 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
1505 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
1507 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1508 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1510 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
1511 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
1512 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1516 static int sysc_clockdomain_init(struct sysc *ddata)
1518 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1519 struct clk *fck = NULL, *ick = NULL;
1522 if (!pdata || !pdata->init_clockdomain)
1525 switch (ddata->nr_clocks) {
1527 ick = ddata->clocks[SYSC_ICK];
1530 fck = ddata->clocks[SYSC_FCK];
1536 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1537 if (!error || error == -ENODEV)
1544 * Note that pdata->init_module() typically does a reset first. After
1545 * pdata->init_module() is done, PM runtime can be used for the interconnect
1548 static int sysc_legacy_init(struct sysc *ddata)
1550 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1553 if (!pdata || !pdata->init_module)
1556 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1557 if (error == -EEXIST)
1564 * Note that the caller must ensure the interconnect target module is enabled
1565 * before calling reset. Otherwise reset will not complete.
1567 static int sysc_reset(struct sysc *ddata)
1569 int sysc_offset, syss_offset, sysc_val, rstval, error = 0;
1570 u32 sysc_mask, syss_done;
1572 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
1573 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
1575 if (ddata->legacy_mode || sysc_offset < 0 ||
1576 ddata->cap->regbits->srst_shift < 0 ||
1577 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1580 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
1582 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
1585 syss_done = ddata->cfg.syss_mask;
1587 if (ddata->clk_disable_quirk)
1588 ddata->clk_disable_quirk(ddata);
1590 sysc_val = sysc_read_sysconfig(ddata);
1591 sysc_val |= sysc_mask;
1592 sysc_write(ddata, sysc_offset, sysc_val);
1594 if (ddata->cfg.srst_udelay)
1595 usleep_range(ddata->cfg.srst_udelay,
1596 ddata->cfg.srst_udelay * 2);
1598 if (ddata->clk_enable_quirk)
1599 ddata->clk_enable_quirk(ddata);
1601 /* Poll on reset status */
1602 if (syss_offset >= 0) {
1603 error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval,
1604 (rstval & ddata->cfg.syss_mask) ==
1606 100, MAX_MODULE_SOFTRESET_WAIT);
1608 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
1609 error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval,
1610 !(rstval & sysc_mask),
1611 100, MAX_MODULE_SOFTRESET_WAIT);
1614 if (ddata->reset_done_quirk)
1615 ddata->reset_done_quirk(ddata);
1621 * At this point the module is configured enough to read the revision but
1622 * module may not be completely configured yet to use PM runtime. Enable
1623 * all clocks directly during init to configure the quirks needed for PM
1624 * runtime based on the revision register.
1626 static int sysc_init_module(struct sysc *ddata)
1630 error = sysc_clockdomain_init(ddata);
1634 sysc_clkdm_deny_idle(ddata);
1637 * Always enable clocks. The bootloader may or may not have enabled
1638 * the related clocks.
1640 error = sysc_enable_opt_clocks(ddata);
1644 error = sysc_enable_main_clocks(ddata);
1646 goto err_opt_clocks;
1648 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
1649 error = reset_control_deassert(ddata->rsts);
1651 goto err_main_clocks;
1654 ddata->revision = sysc_read_revision(ddata);
1655 sysc_init_revision_quirks(ddata);
1656 sysc_init_module_quirks(ddata);
1658 if (ddata->legacy_mode) {
1659 error = sysc_legacy_init(ddata);
1664 if (!ddata->legacy_mode) {
1665 error = sysc_enable_module(ddata->dev);
1670 error = sysc_reset(ddata);
1672 dev_err(ddata->dev, "Reset failed with %d\n", error);
1674 if (error && !ddata->legacy_mode)
1675 sysc_disable_module(ddata->dev);
1678 if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
1679 reset_control_assert(ddata->rsts);
1683 sysc_disable_main_clocks(ddata);
1685 /* No re-enable of clockdomain autoidle to prevent module autoidle */
1687 sysc_disable_opt_clocks(ddata);
1688 sysc_clkdm_allow_idle(ddata);
1694 static int sysc_init_sysc_mask(struct sysc *ddata)
1696 struct device_node *np = ddata->dev->of_node;
1700 error = of_property_read_u32(np, "ti,sysc-mask", &val);
1704 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
1709 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
1712 struct device_node *np = ddata->dev->of_node;
1713 struct property *prop;
1717 of_property_for_each_u32(np, name, prop, p, val) {
1718 if (val >= SYSC_NR_IDLEMODES) {
1719 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
1722 *idlemodes |= (1 << val);
1728 static int sysc_init_idlemodes(struct sysc *ddata)
1732 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
1737 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1746 * Only some devices on omap4 and later have SYSCONFIG reset done
1747 * bit. We can detect this if there is no SYSSTATUS at all, or the
1748 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1749 * have multiple bits for the child devices like OHCI and EHCI.
1750 * Depends on SYSC being parsed first.
1752 static int sysc_init_syss_mask(struct sysc *ddata)
1754 struct device_node *np = ddata->dev->of_node;
1758 error = of_property_read_u32(np, "ti,syss-mask", &val);
1760 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1761 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1762 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1763 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1768 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1769 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1771 ddata->cfg.syss_mask = val;
1777 * Many child device drivers need to have fck and opt clocks available
1778 * to get the clock rate for device internal configuration etc.
1780 static int sysc_child_add_named_clock(struct sysc *ddata,
1781 struct device *child,
1785 struct clk_lookup *l;
1791 clk = clk_get(child, name);
1797 clk = clk_get(ddata->dev, name);
1801 l = clkdev_create(clk, name, dev_name(child));
1810 static int sysc_child_add_clocks(struct sysc *ddata,
1811 struct device *child)
1815 for (i = 0; i < ddata->nr_clocks; i++) {
1816 error = sysc_child_add_named_clock(ddata,
1818 ddata->clock_roles[i]);
1819 if (error && error != -EEXIST) {
1820 dev_err(ddata->dev, "could not add child clock %s: %i\n",
1821 ddata->clock_roles[i], error);
1830 static struct device_type sysc_device_type = {
1833 static struct sysc *sysc_child_to_parent(struct device *dev)
1835 struct device *parent = dev->parent;
1837 if (!parent || parent->type != &sysc_device_type)
1840 return dev_get_drvdata(parent);
1843 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
1848 ddata = sysc_child_to_parent(dev);
1850 error = pm_generic_runtime_suspend(dev);
1854 if (!ddata->enabled)
1857 return sysc_runtime_suspend(ddata->dev);
1860 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
1865 ddata = sysc_child_to_parent(dev);
1867 if (!ddata->enabled) {
1868 error = sysc_runtime_resume(ddata->dev);
1871 "%s error: %i\n", __func__, error);
1874 return pm_generic_runtime_resume(dev);
1877 #ifdef CONFIG_PM_SLEEP
1878 static int sysc_child_suspend_noirq(struct device *dev)
1883 ddata = sysc_child_to_parent(dev);
1885 dev_dbg(ddata->dev, "%s %s\n", __func__,
1886 ddata->name ? ddata->name : "");
1888 error = pm_generic_suspend_noirq(dev);
1890 dev_err(dev, "%s error at %i: %i\n",
1891 __func__, __LINE__, error);
1896 if (!pm_runtime_status_suspended(dev)) {
1897 error = pm_generic_runtime_suspend(dev);
1899 dev_dbg(dev, "%s busy at %i: %i\n",
1900 __func__, __LINE__, error);
1905 error = sysc_runtime_suspend(ddata->dev);
1907 dev_err(dev, "%s error at %i: %i\n",
1908 __func__, __LINE__, error);
1913 ddata->child_needs_resume = true;
1919 static int sysc_child_resume_noirq(struct device *dev)
1924 ddata = sysc_child_to_parent(dev);
1926 dev_dbg(ddata->dev, "%s %s\n", __func__,
1927 ddata->name ? ddata->name : "");
1929 if (ddata->child_needs_resume) {
1930 ddata->child_needs_resume = false;
1932 error = sysc_runtime_resume(ddata->dev);
1935 "%s runtime resume error: %i\n",
1938 error = pm_generic_runtime_resume(dev);
1941 "%s generic runtime resume: %i\n",
1945 return pm_generic_resume_noirq(dev);
1949 static struct dev_pm_domain sysc_child_pm_domain = {
1951 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1952 sysc_child_runtime_resume,
1954 USE_PLATFORM_PM_SLEEP_OPS
1955 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
1956 sysc_child_resume_noirq)
1961 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
1962 * @ddata: device driver data
1963 * @child: child device driver
1965 * Allow idle for child devices as done with _od_runtime_suspend().
1966 * Otherwise many child devices will not idle because of the permanent
1967 * parent usecount set in pm_runtime_irq_safe().
1969 * Note that the long term solution is to just modify the child device
1970 * drivers to not set pm_runtime_irq_safe() and then this can be just
1973 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
1975 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1976 dev_pm_domain_set(child, &sysc_child_pm_domain);
1979 static int sysc_notifier_call(struct notifier_block *nb,
1980 unsigned long event, void *device)
1982 struct device *dev = device;
1986 ddata = sysc_child_to_parent(dev);
1991 case BUS_NOTIFY_ADD_DEVICE:
1992 error = sysc_child_add_clocks(ddata, dev);
1995 sysc_legacy_idle_quirk(ddata, dev);
2004 static struct notifier_block sysc_nb = {
2005 .notifier_call = sysc_notifier_call,
2008 /* Device tree configured quirks */
2009 struct sysc_dts_quirk {
2014 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2015 { .name = "ti,no-idle-on-init",
2016 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2017 { .name = "ti,no-reset-on-init",
2018 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2019 { .name = "ti,no-idle",
2020 .mask = SYSC_QUIRK_NO_IDLE, },
2023 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2026 const struct property *prop;
2029 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2030 const char *name = sysc_dts_quirks[i].name;
2032 prop = of_get_property(np, name, &len);
2036 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2038 dev_warn(ddata->dev,
2039 "dts flag should be at module level for %s\n",
2045 static int sysc_init_dts_quirks(struct sysc *ddata)
2047 struct device_node *np = ddata->dev->of_node;
2051 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2053 sysc_parse_dts_quirks(ddata, np, false);
2054 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2057 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2061 ddata->cfg.srst_udelay = (u8)val;
2067 static void sysc_unprepare(struct sysc *ddata)
2074 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2075 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2076 clk_unprepare(ddata->clocks[i]);
2081 * Common sysc register bits found on omap2, also known as type1
2083 static const struct sysc_regbits sysc_regbits_omap2 = {
2084 .dmadisable_shift = -ENODEV,
2091 .autoidle_shift = 0,
2094 static const struct sysc_capabilities sysc_omap2 = {
2095 .type = TI_SYSC_OMAP2,
2096 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2097 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2098 SYSC_OMAP2_AUTOIDLE,
2099 .regbits = &sysc_regbits_omap2,
2102 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2103 static const struct sysc_capabilities sysc_omap2_timer = {
2104 .type = TI_SYSC_OMAP2_TIMER,
2105 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2106 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2107 SYSC_OMAP2_AUTOIDLE,
2108 .regbits = &sysc_regbits_omap2,
2109 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2113 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2114 * with different sidle position
2116 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2117 .dmadisable_shift = -ENODEV,
2118 .midle_shift = -ENODEV,
2120 .clkact_shift = -ENODEV,
2121 .enwkup_shift = -ENODEV,
2123 .autoidle_shift = 0,
2124 .emufree_shift = -ENODEV,
2127 static const struct sysc_capabilities sysc_omap3_sham = {
2128 .type = TI_SYSC_OMAP3_SHAM,
2129 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2130 .regbits = &sysc_regbits_omap3_sham,
2134 * AES register bits found on omap3 and later, a variant of
2135 * sysc_regbits_omap2 with different sidle position
2137 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2138 .dmadisable_shift = -ENODEV,
2139 .midle_shift = -ENODEV,
2141 .clkact_shift = -ENODEV,
2142 .enwkup_shift = -ENODEV,
2144 .autoidle_shift = 0,
2145 .emufree_shift = -ENODEV,
2148 static const struct sysc_capabilities sysc_omap3_aes = {
2149 .type = TI_SYSC_OMAP3_AES,
2150 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2151 .regbits = &sysc_regbits_omap3_aes,
2155 * Common sysc register bits found on omap4, also known as type2
2157 static const struct sysc_regbits sysc_regbits_omap4 = {
2158 .dmadisable_shift = 16,
2161 .clkact_shift = -ENODEV,
2162 .enwkup_shift = -ENODEV,
2165 .autoidle_shift = -ENODEV,
2168 static const struct sysc_capabilities sysc_omap4 = {
2169 .type = TI_SYSC_OMAP4,
2170 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2171 SYSC_OMAP4_SOFTRESET,
2172 .regbits = &sysc_regbits_omap4,
2175 static const struct sysc_capabilities sysc_omap4_timer = {
2176 .type = TI_SYSC_OMAP4_TIMER,
2177 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2178 SYSC_OMAP4_SOFTRESET,
2179 .regbits = &sysc_regbits_omap4,
2183 * Common sysc register bits found on omap4, also known as type3
2185 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2186 .dmadisable_shift = -ENODEV,
2189 .clkact_shift = -ENODEV,
2190 .enwkup_shift = -ENODEV,
2191 .srst_shift = -ENODEV,
2192 .emufree_shift = -ENODEV,
2193 .autoidle_shift = -ENODEV,
2196 static const struct sysc_capabilities sysc_omap4_simple = {
2197 .type = TI_SYSC_OMAP4_SIMPLE,
2198 .regbits = &sysc_regbits_omap4_simple,
2202 * SmartReflex sysc found on omap34xx
2204 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2205 .dmadisable_shift = -ENODEV,
2206 .midle_shift = -ENODEV,
2207 .sidle_shift = -ENODEV,
2209 .enwkup_shift = -ENODEV,
2210 .srst_shift = -ENODEV,
2211 .emufree_shift = -ENODEV,
2212 .autoidle_shift = -ENODEV,
2215 static const struct sysc_capabilities sysc_34xx_sr = {
2216 .type = TI_SYSC_OMAP34XX_SR,
2217 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2218 .regbits = &sysc_regbits_omap34xx_sr,
2219 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2220 SYSC_QUIRK_LEGACY_IDLE,
2224 * SmartReflex sysc found on omap36xx and later
2226 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2227 .dmadisable_shift = -ENODEV,
2228 .midle_shift = -ENODEV,
2230 .clkact_shift = -ENODEV,
2232 .srst_shift = -ENODEV,
2233 .emufree_shift = -ENODEV,
2234 .autoidle_shift = -ENODEV,
2237 static const struct sysc_capabilities sysc_36xx_sr = {
2238 .type = TI_SYSC_OMAP36XX_SR,
2239 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2240 .regbits = &sysc_regbits_omap36xx_sr,
2241 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2244 static const struct sysc_capabilities sysc_omap4_sr = {
2245 .type = TI_SYSC_OMAP4_SR,
2246 .regbits = &sysc_regbits_omap36xx_sr,
2247 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2251 * McASP register bits found on omap4 and later
2253 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2254 .dmadisable_shift = -ENODEV,
2255 .midle_shift = -ENODEV,
2257 .clkact_shift = -ENODEV,
2258 .enwkup_shift = -ENODEV,
2259 .srst_shift = -ENODEV,
2260 .emufree_shift = -ENODEV,
2261 .autoidle_shift = -ENODEV,
2264 static const struct sysc_capabilities sysc_omap4_mcasp = {
2265 .type = TI_SYSC_OMAP4_MCASP,
2266 .regbits = &sysc_regbits_omap4_mcasp,
2267 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2271 * McASP found on dra7 and later
2273 static const struct sysc_capabilities sysc_dra7_mcasp = {
2274 .type = TI_SYSC_OMAP4_SIMPLE,
2275 .regbits = &sysc_regbits_omap4_simple,
2276 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2280 * FS USB host found on omap4 and later
2282 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2283 .dmadisable_shift = -ENODEV,
2284 .midle_shift = -ENODEV,
2286 .clkact_shift = -ENODEV,
2288 .srst_shift = -ENODEV,
2289 .emufree_shift = -ENODEV,
2290 .autoidle_shift = -ENODEV,
2293 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2294 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2295 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2296 .regbits = &sysc_regbits_omap4_usb_host_fs,
2299 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2300 .dmadisable_shift = -ENODEV,
2301 .midle_shift = -ENODEV,
2302 .sidle_shift = -ENODEV,
2303 .clkact_shift = -ENODEV,
2306 .emufree_shift = -ENODEV,
2307 .autoidle_shift = -ENODEV,
2310 static const struct sysc_capabilities sysc_dra7_mcan = {
2311 .type = TI_SYSC_DRA7_MCAN,
2312 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2313 .regbits = &sysc_regbits_dra7_mcan,
2314 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2317 static int sysc_init_pdata(struct sysc *ddata)
2319 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2320 struct ti_sysc_module_data *mdata;
2325 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2329 if (ddata->legacy_mode) {
2330 mdata->name = ddata->legacy_mode;
2331 mdata->module_pa = ddata->module_pa;
2332 mdata->module_size = ddata->module_size;
2333 mdata->offsets = ddata->offsets;
2334 mdata->nr_offsets = SYSC_MAX_REGS;
2335 mdata->cap = ddata->cap;
2336 mdata->cfg = &ddata->cfg;
2339 ddata->mdata = mdata;
2344 static int sysc_init_match(struct sysc *ddata)
2346 const struct sysc_capabilities *cap;
2348 cap = of_device_get_match_data(ddata->dev);
2354 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2359 static void ti_sysc_idle(struct work_struct *work)
2363 ddata = container_of(work, struct sysc, idle_work.work);
2366 * One time decrement of clock usage counts if left on from init.
2367 * Note that we disable opt clocks unconditionally in this case
2368 * as they are enabled unconditionally during init without
2369 * considering sysc_opt_clks_needed() at that point.
2371 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2372 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2373 sysc_disable_main_clocks(ddata);
2374 sysc_disable_opt_clocks(ddata);
2375 sysc_clkdm_allow_idle(ddata);
2378 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2379 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2383 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2384 * and SYSC_QUIRK_NO_RESET_ON_INIT
2386 if (pm_runtime_active(ddata->dev))
2387 pm_runtime_put_sync(ddata->dev);
2390 static const struct of_device_id sysc_match_table[] = {
2391 { .compatible = "simple-bus", },
2395 static int sysc_probe(struct platform_device *pdev)
2397 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
2401 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2405 ddata->dev = &pdev->dev;
2406 platform_set_drvdata(pdev, ddata);
2408 error = sysc_init_match(ddata);
2412 error = sysc_init_dts_quirks(ddata);
2416 error = sysc_map_and_check_registers(ddata);
2420 error = sysc_init_sysc_mask(ddata);
2424 error = sysc_init_idlemodes(ddata);
2428 error = sysc_init_syss_mask(ddata);
2432 error = sysc_init_pdata(ddata);
2436 sysc_init_early_quirks(ddata);
2438 error = sysc_get_clocks(ddata);
2442 error = sysc_init_resets(ddata);
2446 error = sysc_init_module(ddata);
2450 pm_runtime_enable(ddata->dev);
2451 error = pm_runtime_get_sync(ddata->dev);
2453 pm_runtime_put_noidle(ddata->dev);
2454 pm_runtime_disable(ddata->dev);
2458 /* Balance use counts as PM runtime should have enabled these all */
2459 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2460 reset_control_assert(ddata->rsts);
2462 if (!(ddata->cfg.quirks &
2463 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
2464 sysc_disable_main_clocks(ddata);
2465 sysc_disable_opt_clocks(ddata);
2466 sysc_clkdm_allow_idle(ddata);
2469 sysc_show_registers(ddata);
2471 ddata->dev->type = &sysc_device_type;
2472 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2473 pdata ? pdata->auxdata : NULL,
2478 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2480 /* At least earlycon won't survive without deferred idle */
2481 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2482 SYSC_QUIRK_NO_IDLE_ON_INIT |
2483 SYSC_QUIRK_NO_RESET_ON_INIT)) {
2484 schedule_delayed_work(&ddata->idle_work, 3000);
2486 pm_runtime_put(&pdev->dev);
2492 pm_runtime_put_sync(&pdev->dev);
2493 pm_runtime_disable(&pdev->dev);
2495 sysc_unprepare(ddata);
2500 static int sysc_remove(struct platform_device *pdev)
2502 struct sysc *ddata = platform_get_drvdata(pdev);
2505 cancel_delayed_work_sync(&ddata->idle_work);
2507 error = pm_runtime_get_sync(ddata->dev);
2509 pm_runtime_put_noidle(ddata->dev);
2510 pm_runtime_disable(ddata->dev);
2514 of_platform_depopulate(&pdev->dev);
2516 pm_runtime_put_sync(&pdev->dev);
2517 pm_runtime_disable(&pdev->dev);
2518 reset_control_assert(ddata->rsts);
2521 sysc_unprepare(ddata);
2526 static const struct of_device_id sysc_match[] = {
2527 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
2528 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
2529 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
2530 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
2531 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
2532 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
2533 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
2534 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
2535 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
2536 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
2537 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2538 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
2539 { .compatible = "ti,sysc-usb-host-fs",
2540 .data = &sysc_omap4_usb_host_fs, },
2541 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
2544 MODULE_DEVICE_TABLE(of, sysc_match);
2546 static struct platform_driver sysc_driver = {
2547 .probe = sysc_probe,
2548 .remove = sysc_remove,
2551 .of_match_table = sysc_match,
2556 static int __init sysc_init(void)
2558 bus_register_notifier(&platform_bus_type, &sysc_nb);
2560 return platform_driver_register(&sysc_driver);
2562 module_init(sysc_init);
2564 static void __exit sysc_exit(void)
2566 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
2567 platform_driver_unregister(&sysc_driver);
2569 module_exit(sysc_exit);
2571 MODULE_DESCRIPTION("TI sysc interconnect target driver");
2572 MODULE_LICENSE("GPL v2");