1 // SPDX-License-Identifier: GPL-2.0
3 * MHI Endpoint bus stack
5 * Copyright (C) 2022 Linaro Ltd.
6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
9 #include <linux/bitfield.h>
10 #include <linux/delay.h>
11 #include <linux/dma-direction.h>
12 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/mhi_ep.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
20 #define M0_WAIT_DELAY_MS 100
21 #define M0_WAIT_COUNT 100
23 static DEFINE_IDA(mhi_ep_cntrl_ida);
25 static int mhi_ep_create_device(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id);
26 static int mhi_ep_destroy_device(struct device *dev, void *data);
28 static int mhi_ep_send_event(struct mhi_ep_cntrl *mhi_cntrl, u32 ring_idx,
29 struct mhi_ring_element *el, bool bei)
31 struct device *dev = &mhi_cntrl->mhi_dev->dev;
32 union mhi_ep_ring_ctx *ctx;
33 struct mhi_ep_ring *ring;
36 mutex_lock(&mhi_cntrl->event_lock);
37 ring = &mhi_cntrl->mhi_event[ring_idx].ring;
38 ctx = (union mhi_ep_ring_ctx *)&mhi_cntrl->ev_ctx_cache[ring_idx];
40 ret = mhi_ep_ring_start(mhi_cntrl, ring, ctx);
42 dev_err(dev, "Error starting event ring (%u)\n", ring_idx);
47 /* Add element to the event ring */
48 ret = mhi_ep_ring_add_element(ring, el);
50 dev_err(dev, "Error adding element to event ring (%u)\n", ring_idx);
54 mutex_unlock(&mhi_cntrl->event_lock);
57 * Raise IRQ to host only if the BEI flag is not set in TRE. Host might
58 * set this flag for interrupt moderation as per MHI protocol.
61 mhi_cntrl->raise_irq(mhi_cntrl, ring->irq_vector);
66 mutex_unlock(&mhi_cntrl->event_lock);
71 static int mhi_ep_send_completion_event(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring,
72 struct mhi_ring_element *tre, u32 len, enum mhi_ev_ccs code)
74 struct mhi_ring_element event = {};
76 event.ptr = cpu_to_le64(ring->rbase + ring->rd_offset * sizeof(*tre));
77 event.dword[0] = MHI_TRE_EV_DWORD0(code, len);
78 event.dword[1] = MHI_TRE_EV_DWORD1(ring->ch_id, MHI_PKT_TYPE_TX_EVENT);
80 return mhi_ep_send_event(mhi_cntrl, ring->er_index, &event, MHI_TRE_DATA_GET_BEI(tre));
83 int mhi_ep_send_state_change_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state state)
85 struct mhi_ring_element event = {};
87 event.dword[0] = MHI_SC_EV_DWORD0(state);
88 event.dword[1] = MHI_SC_EV_DWORD1(MHI_PKT_TYPE_STATE_CHANGE_EVENT);
90 return mhi_ep_send_event(mhi_cntrl, 0, &event, 0);
93 int mhi_ep_send_ee_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_ee_type exec_env)
95 struct mhi_ring_element event = {};
97 event.dword[0] = MHI_EE_EV_DWORD0(exec_env);
98 event.dword[1] = MHI_SC_EV_DWORD1(MHI_PKT_TYPE_EE_EVENT);
100 return mhi_ep_send_event(mhi_cntrl, 0, &event, 0);
103 static int mhi_ep_send_cmd_comp_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_ev_ccs code)
105 struct mhi_ep_ring *ring = &mhi_cntrl->mhi_cmd->ring;
106 struct mhi_ring_element event = {};
108 event.ptr = cpu_to_le64(ring->rbase + ring->rd_offset * sizeof(struct mhi_ring_element));
109 event.dword[0] = MHI_CC_EV_DWORD0(code);
110 event.dword[1] = MHI_CC_EV_DWORD1(MHI_PKT_TYPE_CMD_COMPLETION_EVENT);
112 return mhi_ep_send_event(mhi_cntrl, 0, &event, 0);
115 static int mhi_ep_process_cmd_ring(struct mhi_ep_ring *ring, struct mhi_ring_element *el)
117 struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl;
118 struct device *dev = &mhi_cntrl->mhi_dev->dev;
119 struct mhi_result result = {};
120 struct mhi_ep_chan *mhi_chan;
121 struct mhi_ep_ring *ch_ring;
125 ch_id = MHI_TRE_GET_CMD_CHID(el);
127 /* Check if the channel is supported by the controller */
128 if ((ch_id >= mhi_cntrl->max_chan) || !mhi_cntrl->mhi_chan[ch_id].name) {
129 dev_err(dev, "Channel (%u) not supported!\n", ch_id);
133 mhi_chan = &mhi_cntrl->mhi_chan[ch_id];
134 ch_ring = &mhi_cntrl->mhi_chan[ch_id].ring;
136 switch (MHI_TRE_GET_CMD_TYPE(el)) {
137 case MHI_PKT_TYPE_START_CHAN_CMD:
138 dev_dbg(dev, "Received START command for channel (%u)\n", ch_id);
140 mutex_lock(&mhi_chan->lock);
141 /* Initialize and configure the corresponding channel ring */
142 if (!ch_ring->started) {
143 ret = mhi_ep_ring_start(mhi_cntrl, ch_ring,
144 (union mhi_ep_ring_ctx *)&mhi_cntrl->ch_ctx_cache[ch_id]);
146 dev_err(dev, "Failed to start ring for channel (%u)\n", ch_id);
147 ret = mhi_ep_send_cmd_comp_event(mhi_cntrl,
148 MHI_EV_CC_UNDEFINED_ERR);
150 dev_err(dev, "Error sending completion event: %d\n", ret);
156 /* Set channel state to RUNNING */
157 mhi_chan->state = MHI_CH_STATE_RUNNING;
158 tmp = le32_to_cpu(mhi_cntrl->ch_ctx_cache[ch_id].chcfg);
159 tmp &= ~CHAN_CTX_CHSTATE_MASK;
160 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_RUNNING);
161 mhi_cntrl->ch_ctx_cache[ch_id].chcfg = cpu_to_le32(tmp);
163 ret = mhi_ep_send_cmd_comp_event(mhi_cntrl, MHI_EV_CC_SUCCESS);
165 dev_err(dev, "Error sending command completion event (%u)\n",
170 mutex_unlock(&mhi_chan->lock);
173 * Create MHI device only during UL channel start. Since the MHI
174 * channels operate in a pair, we'll associate both UL and DL
175 * channels to the same device.
177 * We also need to check for mhi_dev != NULL because, the host
178 * will issue START_CHAN command during resume and we don't
179 * destroy the device during suspend.
181 if (!(ch_id % 2) && !mhi_chan->mhi_dev) {
182 ret = mhi_ep_create_device(mhi_cntrl, ch_id);
184 dev_err(dev, "Error creating device for channel (%u)\n", ch_id);
185 mhi_ep_handle_syserr(mhi_cntrl);
190 /* Finally, enable DB for the channel */
191 mhi_ep_mmio_enable_chdb(mhi_cntrl, ch_id);
194 case MHI_PKT_TYPE_STOP_CHAN_CMD:
195 dev_dbg(dev, "Received STOP command for channel (%u)\n", ch_id);
196 if (!ch_ring->started) {
197 dev_err(dev, "Channel (%u) not opened\n", ch_id);
201 mutex_lock(&mhi_chan->lock);
202 /* Disable DB for the channel */
203 mhi_ep_mmio_disable_chdb(mhi_cntrl, ch_id);
205 /* Send channel disconnect status to client drivers */
206 if (mhi_chan->xfer_cb) {
207 result.transaction_status = -ENOTCONN;
208 result.bytes_xferd = 0;
209 mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result);
212 /* Set channel state to STOP */
213 mhi_chan->state = MHI_CH_STATE_STOP;
214 tmp = le32_to_cpu(mhi_cntrl->ch_ctx_cache[ch_id].chcfg);
215 tmp &= ~CHAN_CTX_CHSTATE_MASK;
216 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_STOP);
217 mhi_cntrl->ch_ctx_cache[ch_id].chcfg = cpu_to_le32(tmp);
219 ret = mhi_ep_send_cmd_comp_event(mhi_cntrl, MHI_EV_CC_SUCCESS);
221 dev_err(dev, "Error sending command completion event (%u)\n",
226 mutex_unlock(&mhi_chan->lock);
228 case MHI_PKT_TYPE_RESET_CHAN_CMD:
229 dev_dbg(dev, "Received RESET command for channel (%u)\n", ch_id);
230 if (!ch_ring->started) {
231 dev_err(dev, "Channel (%u) not opened\n", ch_id);
235 mutex_lock(&mhi_chan->lock);
236 /* Stop and reset the transfer ring */
237 mhi_ep_ring_reset(mhi_cntrl, ch_ring);
239 /* Send channel disconnect status to client driver */
240 if (mhi_chan->xfer_cb) {
241 result.transaction_status = -ENOTCONN;
242 result.bytes_xferd = 0;
243 mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result);
246 /* Set channel state to DISABLED */
247 mhi_chan->state = MHI_CH_STATE_DISABLED;
248 tmp = le32_to_cpu(mhi_cntrl->ch_ctx_cache[ch_id].chcfg);
249 tmp &= ~CHAN_CTX_CHSTATE_MASK;
250 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_DISABLED);
251 mhi_cntrl->ch_ctx_cache[ch_id].chcfg = cpu_to_le32(tmp);
253 ret = mhi_ep_send_cmd_comp_event(mhi_cntrl, MHI_EV_CC_SUCCESS);
255 dev_err(dev, "Error sending command completion event (%u)\n",
260 mutex_unlock(&mhi_chan->lock);
263 dev_err(dev, "Invalid command received: %lu for channel (%u)\n",
264 MHI_TRE_GET_CMD_TYPE(el), ch_id);
271 mutex_unlock(&mhi_chan->lock);
276 bool mhi_ep_queue_is_empty(struct mhi_ep_device *mhi_dev, enum dma_data_direction dir)
278 struct mhi_ep_chan *mhi_chan = (dir == DMA_FROM_DEVICE) ? mhi_dev->dl_chan :
280 struct mhi_ep_cntrl *mhi_cntrl = mhi_dev->mhi_cntrl;
281 struct mhi_ep_ring *ring = &mhi_cntrl->mhi_chan[mhi_chan->chan].ring;
283 return !!(ring->rd_offset == ring->wr_offset);
285 EXPORT_SYMBOL_GPL(mhi_ep_queue_is_empty);
287 static int mhi_ep_read_channel(struct mhi_ep_cntrl *mhi_cntrl,
288 struct mhi_ep_ring *ring,
289 struct mhi_result *result,
292 struct mhi_ep_chan *mhi_chan = &mhi_cntrl->mhi_chan[ring->ch_id];
293 struct device *dev = &mhi_cntrl->mhi_dev->dev;
294 size_t tr_len, read_offset, write_offset;
295 struct mhi_ring_element *el;
296 bool tr_done = false;
305 /* Don't process the transfer ring if the channel is not in RUNNING state */
306 if (mhi_chan->state != MHI_CH_STATE_RUNNING) {
307 dev_err(dev, "Channel not available\n");
311 el = &ring->ring_cache[ring->rd_offset];
313 /* Check if there is data pending to be read from previous read operation */
314 if (mhi_chan->tre_bytes_left) {
315 dev_dbg(dev, "TRE bytes remaining: %u\n", mhi_chan->tre_bytes_left);
316 tr_len = min(buf_left, mhi_chan->tre_bytes_left);
318 mhi_chan->tre_loc = MHI_TRE_DATA_GET_PTR(el);
319 mhi_chan->tre_size = MHI_TRE_DATA_GET_LEN(el);
320 mhi_chan->tre_bytes_left = mhi_chan->tre_size;
322 tr_len = min(buf_left, mhi_chan->tre_size);
325 read_offset = mhi_chan->tre_size - mhi_chan->tre_bytes_left;
326 write_offset = len - buf_left;
327 read_addr = mhi_chan->tre_loc + read_offset;
328 write_addr = result->buf_addr + write_offset;
330 dev_dbg(dev, "Reading %zd bytes from channel (%u)\n", tr_len, ring->ch_id);
331 ret = mhi_cntrl->read_from_host(mhi_cntrl, read_addr, write_addr, tr_len);
333 dev_err(&mhi_chan->mhi_dev->dev, "Error reading from channel\n");
338 mhi_chan->tre_bytes_left -= tr_len;
341 * Once the TRE (Transfer Ring Element) of a TD (Transfer Descriptor) has been
344 * 1. Send completion event to the host based on the flags set in TRE.
345 * 2. Increment the local read offset of the transfer ring.
347 if (!mhi_chan->tre_bytes_left) {
349 * The host will split the data packet into multiple TREs if it can't fit
350 * the packet in a single TRE. In that case, CHAIN flag will be set by the
351 * host for all TREs except the last one.
353 if (MHI_TRE_DATA_GET_CHAIN(el)) {
355 * IEOB (Interrupt on End of Block) flag will be set by the host if
356 * it expects the completion event for all TREs of a TD.
358 if (MHI_TRE_DATA_GET_IEOB(el)) {
359 ret = mhi_ep_send_completion_event(mhi_cntrl, ring, el,
360 MHI_TRE_DATA_GET_LEN(el),
363 dev_err(&mhi_chan->mhi_dev->dev,
364 "Error sending transfer compl. event\n");
370 * IEOT (Interrupt on End of Transfer) flag will be set by the host
371 * for the last TRE of the TD and expects the completion event for
374 if (MHI_TRE_DATA_GET_IEOT(el)) {
375 ret = mhi_ep_send_completion_event(mhi_cntrl, ring, el,
376 MHI_TRE_DATA_GET_LEN(el),
379 dev_err(&mhi_chan->mhi_dev->dev,
380 "Error sending transfer compl. event\n");
388 mhi_ep_ring_inc_index(ring);
391 result->bytes_xferd += tr_len;
392 } while (buf_left && !tr_done);
397 static int mhi_ep_process_ch_ring(struct mhi_ep_ring *ring, struct mhi_ring_element *el)
399 struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl;
400 struct mhi_result result = {};
401 u32 len = MHI_EP_DEFAULT_MTU;
402 struct mhi_ep_chan *mhi_chan;
405 mhi_chan = &mhi_cntrl->mhi_chan[ring->ch_id];
408 * Bail out if transfer callback is not registered for the channel.
409 * This is most likely due to the client driver not loaded at this point.
411 if (!mhi_chan->xfer_cb) {
412 dev_err(&mhi_chan->mhi_dev->dev, "Client driver not available\n");
416 if (ring->ch_id % 2) {
418 result.dir = mhi_chan->dir;
419 mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result);
422 result.buf_addr = kzalloc(len, GFP_KERNEL);
423 if (!result.buf_addr)
427 ret = mhi_ep_read_channel(mhi_cntrl, ring, &result, len);
429 dev_err(&mhi_chan->mhi_dev->dev, "Failed to read channel\n");
430 kfree(result.buf_addr);
434 result.dir = mhi_chan->dir;
435 mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result);
436 result.bytes_xferd = 0;
437 memset(result.buf_addr, 0, len);
439 /* Read until the ring becomes empty */
440 } while (!mhi_ep_queue_is_empty(mhi_chan->mhi_dev, DMA_TO_DEVICE));
442 kfree(result.buf_addr);
448 /* TODO: Handle partially formed TDs */
449 int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, struct sk_buff *skb)
451 struct mhi_ep_cntrl *mhi_cntrl = mhi_dev->mhi_cntrl;
452 struct mhi_ep_chan *mhi_chan = mhi_dev->dl_chan;
453 struct device *dev = &mhi_chan->mhi_dev->dev;
454 struct mhi_ring_element *el;
455 u32 buf_left, read_offset;
456 struct mhi_ep_ring *ring;
457 enum mhi_ev_ccs code;
465 ring = &mhi_cntrl->mhi_chan[mhi_chan->chan].ring;
467 mutex_lock(&mhi_chan->lock);
470 /* Don't process the transfer ring if the channel is not in RUNNING state */
471 if (mhi_chan->state != MHI_CH_STATE_RUNNING) {
472 dev_err(dev, "Channel not available\n");
477 if (mhi_ep_queue_is_empty(mhi_dev, DMA_FROM_DEVICE)) {
478 dev_err(dev, "TRE not available!\n");
483 el = &ring->ring_cache[ring->rd_offset];
484 tre_len = MHI_TRE_DATA_GET_LEN(el);
486 tr_len = min(buf_left, tre_len);
487 read_offset = skb->len - buf_left;
488 read_addr = skb->data + read_offset;
489 write_addr = MHI_TRE_DATA_GET_PTR(el);
491 dev_dbg(dev, "Writing %zd bytes to channel (%u)\n", tr_len, ring->ch_id);
492 ret = mhi_cntrl->write_to_host(mhi_cntrl, read_addr, write_addr, tr_len);
494 dev_err(dev, "Error writing to the channel\n");
500 * For all TREs queued by the host for DL channel, only the EOT flag will be set.
501 * If the packet doesn't fit into a single TRE, send the OVERFLOW event to
502 * the host so that the host can adjust the packet boundary to next TREs. Else send
503 * the EOT event to the host indicating the packet boundary.
506 code = MHI_EV_CC_OVERFLOW;
508 code = MHI_EV_CC_EOT;
510 ret = mhi_ep_send_completion_event(mhi_cntrl, ring, el, tr_len, code);
512 dev_err(dev, "Error sending transfer completion event\n");
516 mhi_ep_ring_inc_index(ring);
519 mutex_unlock(&mhi_chan->lock);
524 mutex_unlock(&mhi_chan->lock);
528 EXPORT_SYMBOL_GPL(mhi_ep_queue_skb);
530 static int mhi_ep_cache_host_cfg(struct mhi_ep_cntrl *mhi_cntrl)
532 size_t cmd_ctx_host_size, ch_ctx_host_size, ev_ctx_host_size;
533 struct device *dev = &mhi_cntrl->mhi_dev->dev;
536 /* Update the number of event rings (NER) programmed by the host */
537 mhi_ep_mmio_update_ner(mhi_cntrl);
539 dev_dbg(dev, "Number of Event rings: %u, HW Event rings: %u\n",
540 mhi_cntrl->event_rings, mhi_cntrl->hw_event_rings);
542 ch_ctx_host_size = sizeof(struct mhi_chan_ctxt) * mhi_cntrl->max_chan;
543 ev_ctx_host_size = sizeof(struct mhi_event_ctxt) * mhi_cntrl->event_rings;
544 cmd_ctx_host_size = sizeof(struct mhi_cmd_ctxt) * NR_OF_CMD_RINGS;
546 /* Get the channel context base pointer from host */
547 mhi_ep_mmio_get_chc_base(mhi_cntrl);
549 /* Allocate and map memory for caching host channel context */
550 ret = mhi_cntrl->alloc_map(mhi_cntrl, mhi_cntrl->ch_ctx_host_pa,
551 &mhi_cntrl->ch_ctx_cache_phys,
552 (void __iomem **) &mhi_cntrl->ch_ctx_cache,
555 dev_err(dev, "Failed to allocate and map ch_ctx_cache\n");
559 /* Get the event context base pointer from host */
560 mhi_ep_mmio_get_erc_base(mhi_cntrl);
562 /* Allocate and map memory for caching host event context */
563 ret = mhi_cntrl->alloc_map(mhi_cntrl, mhi_cntrl->ev_ctx_host_pa,
564 &mhi_cntrl->ev_ctx_cache_phys,
565 (void __iomem **) &mhi_cntrl->ev_ctx_cache,
568 dev_err(dev, "Failed to allocate and map ev_ctx_cache\n");
572 /* Get the command context base pointer from host */
573 mhi_ep_mmio_get_crc_base(mhi_cntrl);
575 /* Allocate and map memory for caching host command context */
576 ret = mhi_cntrl->alloc_map(mhi_cntrl, mhi_cntrl->cmd_ctx_host_pa,
577 &mhi_cntrl->cmd_ctx_cache_phys,
578 (void __iomem **) &mhi_cntrl->cmd_ctx_cache,
581 dev_err(dev, "Failed to allocate and map cmd_ctx_cache\n");
585 /* Initialize command ring */
586 ret = mhi_ep_ring_start(mhi_cntrl, &mhi_cntrl->mhi_cmd->ring,
587 (union mhi_ep_ring_ctx *)mhi_cntrl->cmd_ctx_cache);
589 dev_err(dev, "Failed to start the command ring\n");
596 mhi_cntrl->unmap_free(mhi_cntrl, mhi_cntrl->cmd_ctx_host_pa, mhi_cntrl->cmd_ctx_cache_phys,
597 (void __iomem *) mhi_cntrl->cmd_ctx_cache, cmd_ctx_host_size);
600 mhi_cntrl->unmap_free(mhi_cntrl, mhi_cntrl->ev_ctx_host_pa, mhi_cntrl->ev_ctx_cache_phys,
601 (void __iomem *) mhi_cntrl->ev_ctx_cache, ev_ctx_host_size);
604 mhi_cntrl->unmap_free(mhi_cntrl, mhi_cntrl->ch_ctx_host_pa, mhi_cntrl->ch_ctx_cache_phys,
605 (void __iomem *) mhi_cntrl->ch_ctx_cache, ch_ctx_host_size);
610 static void mhi_ep_free_host_cfg(struct mhi_ep_cntrl *mhi_cntrl)
612 size_t cmd_ctx_host_size, ch_ctx_host_size, ev_ctx_host_size;
614 ch_ctx_host_size = sizeof(struct mhi_chan_ctxt) * mhi_cntrl->max_chan;
615 ev_ctx_host_size = sizeof(struct mhi_event_ctxt) * mhi_cntrl->event_rings;
616 cmd_ctx_host_size = sizeof(struct mhi_cmd_ctxt) * NR_OF_CMD_RINGS;
618 mhi_cntrl->unmap_free(mhi_cntrl, mhi_cntrl->cmd_ctx_host_pa, mhi_cntrl->cmd_ctx_cache_phys,
619 (void __iomem *) mhi_cntrl->cmd_ctx_cache, cmd_ctx_host_size);
621 mhi_cntrl->unmap_free(mhi_cntrl, mhi_cntrl->ev_ctx_host_pa, mhi_cntrl->ev_ctx_cache_phys,
622 (void __iomem *) mhi_cntrl->ev_ctx_cache, ev_ctx_host_size);
624 mhi_cntrl->unmap_free(mhi_cntrl, mhi_cntrl->ch_ctx_host_pa, mhi_cntrl->ch_ctx_cache_phys,
625 (void __iomem *) mhi_cntrl->ch_ctx_cache, ch_ctx_host_size);
628 static void mhi_ep_enable_int(struct mhi_ep_cntrl *mhi_cntrl)
631 * Doorbell interrupts are enabled when the corresponding channel gets started.
632 * Enabling all interrupts here triggers spurious irqs as some of the interrupts
633 * associated with hw channels always get triggered.
635 mhi_ep_mmio_enable_ctrl_interrupt(mhi_cntrl);
636 mhi_ep_mmio_enable_cmdb_interrupt(mhi_cntrl);
639 static int mhi_ep_enable(struct mhi_ep_cntrl *mhi_cntrl)
641 struct device *dev = &mhi_cntrl->mhi_dev->dev;
642 enum mhi_state state;
647 /* Wait for Host to set the M0 state */
649 msleep(M0_WAIT_DELAY_MS);
650 mhi_ep_mmio_get_mhi_state(mhi_cntrl, &state, &mhi_reset);
652 /* Clear the MHI reset if host is in reset state */
653 mhi_ep_mmio_clear_reset(mhi_cntrl);
654 dev_info(dev, "Detected Host reset while waiting for M0\n");
657 } while (state != MHI_STATE_M0 && count < M0_WAIT_COUNT);
659 if (state != MHI_STATE_M0) {
660 dev_err(dev, "Host failed to enter M0\n");
664 ret = mhi_ep_cache_host_cfg(mhi_cntrl);
666 dev_err(dev, "Failed to cache host config\n");
670 mhi_ep_mmio_set_env(mhi_cntrl, MHI_EE_AMSS);
672 /* Enable all interrupts now */
673 mhi_ep_enable_int(mhi_cntrl);
678 static void mhi_ep_cmd_ring_worker(struct work_struct *work)
680 struct mhi_ep_cntrl *mhi_cntrl = container_of(work, struct mhi_ep_cntrl, cmd_ring_work);
681 struct mhi_ep_ring *ring = &mhi_cntrl->mhi_cmd->ring;
682 struct device *dev = &mhi_cntrl->mhi_dev->dev;
683 struct mhi_ring_element *el;
686 /* Update the write offset for the ring */
687 ret = mhi_ep_update_wr_offset(ring);
689 dev_err(dev, "Error updating write offset for ring\n");
693 /* Sanity check to make sure there are elements in the ring */
694 if (ring->rd_offset == ring->wr_offset)
698 * Process command ring element till write offset. In case of an error, just try to
699 * process next element.
701 while (ring->rd_offset != ring->wr_offset) {
702 el = &ring->ring_cache[ring->rd_offset];
704 ret = mhi_ep_process_cmd_ring(ring, el);
706 dev_err(dev, "Error processing cmd ring element: %zu\n", ring->rd_offset);
708 mhi_ep_ring_inc_index(ring);
712 static void mhi_ep_ch_ring_worker(struct work_struct *work)
714 struct mhi_ep_cntrl *mhi_cntrl = container_of(work, struct mhi_ep_cntrl, ch_ring_work);
715 struct device *dev = &mhi_cntrl->mhi_dev->dev;
716 struct mhi_ep_ring_item *itr, *tmp;
717 struct mhi_ring_element *el;
718 struct mhi_ep_ring *ring;
719 struct mhi_ep_chan *chan;
724 spin_lock_irqsave(&mhi_cntrl->list_lock, flags);
725 list_splice_tail_init(&mhi_cntrl->ch_db_list, &head);
726 spin_unlock_irqrestore(&mhi_cntrl->list_lock, flags);
728 /* Process each queued channel ring. In case of an error, just process next element. */
729 list_for_each_entry_safe(itr, tmp, &head, node) {
730 list_del(&itr->node);
733 chan = &mhi_cntrl->mhi_chan[ring->ch_id];
734 mutex_lock(&chan->lock);
737 * The ring could've stopped while we waited to grab the (chan->lock), so do
738 * a sanity check before going further.
740 if (!ring->started) {
741 mutex_unlock(&chan->lock);
746 /* Update the write offset for the ring */
747 ret = mhi_ep_update_wr_offset(ring);
749 dev_err(dev, "Error updating write offset for ring\n");
750 mutex_unlock(&chan->lock);
755 /* Sanity check to make sure there are elements in the ring */
756 if (ring->rd_offset == ring->wr_offset) {
757 mutex_unlock(&chan->lock);
762 el = &ring->ring_cache[ring->rd_offset];
764 dev_dbg(dev, "Processing the ring for channel (%u)\n", ring->ch_id);
765 ret = mhi_ep_process_ch_ring(ring, el);
767 dev_err(dev, "Error processing ring for channel (%u): %d\n",
769 mutex_unlock(&chan->lock);
774 mutex_unlock(&chan->lock);
779 static void mhi_ep_state_worker(struct work_struct *work)
781 struct mhi_ep_cntrl *mhi_cntrl = container_of(work, struct mhi_ep_cntrl, state_work);
782 struct device *dev = &mhi_cntrl->mhi_dev->dev;
783 struct mhi_ep_state_transition *itr, *tmp;
788 spin_lock_irqsave(&mhi_cntrl->list_lock, flags);
789 list_splice_tail_init(&mhi_cntrl->st_transition_list, &head);
790 spin_unlock_irqrestore(&mhi_cntrl->list_lock, flags);
792 list_for_each_entry_safe(itr, tmp, &head, node) {
793 list_del(&itr->node);
794 dev_dbg(dev, "Handling MHI state transition to %s\n",
795 mhi_state_str(itr->state));
797 switch (itr->state) {
799 ret = mhi_ep_set_m0_state(mhi_cntrl);
801 dev_err(dev, "Failed to transition to M0 state\n");
804 ret = mhi_ep_set_m3_state(mhi_cntrl);
806 dev_err(dev, "Failed to transition to M3 state\n");
809 dev_err(dev, "Invalid MHI state transition: %d\n", itr->state);
816 static void mhi_ep_queue_channel_db(struct mhi_ep_cntrl *mhi_cntrl, unsigned long ch_int,
819 struct mhi_ep_ring_item *item;
820 struct mhi_ep_ring *ring;
821 bool work = !!ch_int;
825 /* First add the ring items to a local list */
826 for_each_set_bit(i, &ch_int, 32) {
827 /* Channel index varies for each register: 0, 32, 64, 96 */
828 u32 ch_id = ch_idx + i;
830 ring = &mhi_cntrl->mhi_chan[ch_id].ring;
831 item = kzalloc(sizeof(*item), GFP_ATOMIC);
836 list_add_tail(&item->node, &head);
839 /* Now, splice the local list into ch_db_list and queue the work item */
841 spin_lock(&mhi_cntrl->list_lock);
842 list_splice_tail_init(&head, &mhi_cntrl->ch_db_list);
843 spin_unlock(&mhi_cntrl->list_lock);
845 queue_work(mhi_cntrl->wq, &mhi_cntrl->ch_ring_work);
850 * Channel interrupt statuses are contained in 4 registers each of 32bit length.
851 * For checking all interrupts, we need to loop through each registers and then
852 * check for bits set.
854 static void mhi_ep_check_channel_interrupt(struct mhi_ep_cntrl *mhi_cntrl)
856 u32 ch_int, ch_idx, i;
858 /* Bail out if there is no channel doorbell interrupt */
859 if (!mhi_ep_mmio_read_chdb_status_interrupts(mhi_cntrl))
862 for (i = 0; i < MHI_MASK_ROWS_CH_DB; i++) {
863 ch_idx = i * MHI_MASK_CH_LEN;
865 /* Only process channel interrupt if the mask is enabled */
866 ch_int = mhi_cntrl->chdb[i].status & mhi_cntrl->chdb[i].mask;
868 mhi_ep_queue_channel_db(mhi_cntrl, ch_int, ch_idx);
869 mhi_ep_mmio_write(mhi_cntrl, MHI_CHDB_INT_CLEAR_n(i),
870 mhi_cntrl->chdb[i].status);
875 static void mhi_ep_process_ctrl_interrupt(struct mhi_ep_cntrl *mhi_cntrl,
876 enum mhi_state state)
878 struct mhi_ep_state_transition *item;
880 item = kzalloc(sizeof(*item), GFP_ATOMIC);
885 spin_lock(&mhi_cntrl->list_lock);
886 list_add_tail(&item->node, &mhi_cntrl->st_transition_list);
887 spin_unlock(&mhi_cntrl->list_lock);
889 queue_work(mhi_cntrl->wq, &mhi_cntrl->state_work);
893 * Interrupt handler that services interrupts raised by the host writing to
894 * MHICTRL and Command ring doorbell (CRDB) registers for state change and
895 * channel interrupts.
897 static irqreturn_t mhi_ep_irq(int irq, void *data)
899 struct mhi_ep_cntrl *mhi_cntrl = data;
900 struct device *dev = &mhi_cntrl->mhi_dev->dev;
901 enum mhi_state state;
905 /* Acknowledge the ctrl interrupt */
906 int_value = mhi_ep_mmio_read(mhi_cntrl, MHI_CTRL_INT_STATUS);
907 mhi_ep_mmio_write(mhi_cntrl, MHI_CTRL_INT_CLEAR, int_value);
909 /* Check for ctrl interrupt */
910 if (FIELD_GET(MHI_CTRL_INT_STATUS_MSK, int_value)) {
911 dev_dbg(dev, "Processing ctrl interrupt\n");
912 mhi_ep_mmio_get_mhi_state(mhi_cntrl, &state, &mhi_reset);
914 dev_info(dev, "Host triggered MHI reset!\n");
915 disable_irq_nosync(mhi_cntrl->irq);
916 schedule_work(&mhi_cntrl->reset_work);
920 mhi_ep_process_ctrl_interrupt(mhi_cntrl, state);
923 /* Check for command doorbell interrupt */
924 if (FIELD_GET(MHI_CTRL_INT_STATUS_CRDB_MSK, int_value)) {
925 dev_dbg(dev, "Processing command doorbell interrupt\n");
926 queue_work(mhi_cntrl->wq, &mhi_cntrl->cmd_ring_work);
929 /* Check for channel interrupts */
930 mhi_ep_check_channel_interrupt(mhi_cntrl);
935 static void mhi_ep_abort_transfer(struct mhi_ep_cntrl *mhi_cntrl)
937 struct mhi_ep_ring *ch_ring, *ev_ring;
938 struct mhi_result result = {};
939 struct mhi_ep_chan *mhi_chan;
942 /* Stop all the channels */
943 for (i = 0; i < mhi_cntrl->max_chan; i++) {
944 mhi_chan = &mhi_cntrl->mhi_chan[i];
945 if (!mhi_chan->ring.started)
948 mutex_lock(&mhi_chan->lock);
949 /* Send channel disconnect status to client drivers */
950 if (mhi_chan->xfer_cb) {
951 result.transaction_status = -ENOTCONN;
952 result.bytes_xferd = 0;
953 mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result);
956 mhi_chan->state = MHI_CH_STATE_DISABLED;
957 mutex_unlock(&mhi_chan->lock);
960 flush_workqueue(mhi_cntrl->wq);
962 /* Destroy devices associated with all channels */
963 device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_ep_destroy_device);
965 /* Stop and reset the transfer rings */
966 for (i = 0; i < mhi_cntrl->max_chan; i++) {
967 mhi_chan = &mhi_cntrl->mhi_chan[i];
968 if (!mhi_chan->ring.started)
971 ch_ring = &mhi_cntrl->mhi_chan[i].ring;
972 mutex_lock(&mhi_chan->lock);
973 mhi_ep_ring_reset(mhi_cntrl, ch_ring);
974 mutex_unlock(&mhi_chan->lock);
977 /* Stop and reset the event rings */
978 for (i = 0; i < mhi_cntrl->event_rings; i++) {
979 ev_ring = &mhi_cntrl->mhi_event[i].ring;
980 if (!ev_ring->started)
983 mutex_lock(&mhi_cntrl->event_lock);
984 mhi_ep_ring_reset(mhi_cntrl, ev_ring);
985 mutex_unlock(&mhi_cntrl->event_lock);
988 /* Stop and reset the command ring */
989 mhi_ep_ring_reset(mhi_cntrl, &mhi_cntrl->mhi_cmd->ring);
991 mhi_ep_free_host_cfg(mhi_cntrl);
992 mhi_ep_mmio_mask_interrupts(mhi_cntrl);
994 mhi_cntrl->enabled = false;
997 static void mhi_ep_reset_worker(struct work_struct *work)
999 struct mhi_ep_cntrl *mhi_cntrl = container_of(work, struct mhi_ep_cntrl, reset_work);
1000 enum mhi_state cur_state;
1002 mhi_ep_power_down(mhi_cntrl);
1004 mutex_lock(&mhi_cntrl->state_lock);
1006 /* Reset MMIO to signal host that the MHI_RESET is completed in endpoint */
1007 mhi_ep_mmio_reset(mhi_cntrl);
1008 cur_state = mhi_cntrl->mhi_state;
1011 * Only proceed further if the reset is due to SYS_ERR. The host will
1012 * issue reset during shutdown also and we don't need to do re-init in
1015 if (cur_state == MHI_STATE_SYS_ERR)
1016 mhi_ep_power_up(mhi_cntrl);
1018 mutex_unlock(&mhi_cntrl->state_lock);
1022 * We don't need to do anything special other than setting the MHI SYS_ERR
1023 * state. The host will reset all contexts and issue MHI RESET so that we
1024 * could also recover from error state.
1026 void mhi_ep_handle_syserr(struct mhi_ep_cntrl *mhi_cntrl)
1028 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1031 ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR);
1035 /* Signal host that the device went to SYS_ERR state */
1036 ret = mhi_ep_send_state_change_event(mhi_cntrl, MHI_STATE_SYS_ERR);
1038 dev_err(dev, "Failed sending SYS_ERR state change event: %d\n", ret);
1041 int mhi_ep_power_up(struct mhi_ep_cntrl *mhi_cntrl)
1043 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1047 * Mask all interrupts until the state machine is ready. Interrupts will
1048 * be enabled later with mhi_ep_enable().
1050 mhi_ep_mmio_mask_interrupts(mhi_cntrl);
1051 mhi_ep_mmio_init(mhi_cntrl);
1053 mhi_cntrl->mhi_event = kzalloc(mhi_cntrl->event_rings * (sizeof(*mhi_cntrl->mhi_event)),
1055 if (!mhi_cntrl->mhi_event)
1058 /* Initialize command, channel and event rings */
1059 mhi_ep_ring_init(&mhi_cntrl->mhi_cmd->ring, RING_TYPE_CMD, 0);
1060 for (i = 0; i < mhi_cntrl->max_chan; i++)
1061 mhi_ep_ring_init(&mhi_cntrl->mhi_chan[i].ring, RING_TYPE_CH, i);
1062 for (i = 0; i < mhi_cntrl->event_rings; i++)
1063 mhi_ep_ring_init(&mhi_cntrl->mhi_event[i].ring, RING_TYPE_ER, i);
1065 mhi_cntrl->mhi_state = MHI_STATE_RESET;
1067 /* Set AMSS EE before signaling ready state */
1068 mhi_ep_mmio_set_env(mhi_cntrl, MHI_EE_AMSS);
1070 /* All set, notify the host that we are ready */
1071 ret = mhi_ep_set_ready_state(mhi_cntrl);
1073 goto err_free_event;
1075 dev_dbg(dev, "READY state notification sent to the host\n");
1077 ret = mhi_ep_enable(mhi_cntrl);
1079 dev_err(dev, "Failed to enable MHI endpoint\n");
1080 goto err_free_event;
1083 enable_irq(mhi_cntrl->irq);
1084 mhi_cntrl->enabled = true;
1089 kfree(mhi_cntrl->mhi_event);
1093 EXPORT_SYMBOL_GPL(mhi_ep_power_up);
1095 void mhi_ep_power_down(struct mhi_ep_cntrl *mhi_cntrl)
1097 if (mhi_cntrl->enabled) {
1098 mhi_ep_abort_transfer(mhi_cntrl);
1099 kfree(mhi_cntrl->mhi_event);
1100 disable_irq(mhi_cntrl->irq);
1103 EXPORT_SYMBOL_GPL(mhi_ep_power_down);
1105 void mhi_ep_suspend_channels(struct mhi_ep_cntrl *mhi_cntrl)
1107 struct mhi_ep_chan *mhi_chan;
1111 for (i = 0; i < mhi_cntrl->max_chan; i++) {
1112 mhi_chan = &mhi_cntrl->mhi_chan[i];
1114 if (!mhi_chan->mhi_dev)
1117 mutex_lock(&mhi_chan->lock);
1118 /* Skip if the channel is not currently running */
1119 tmp = le32_to_cpu(mhi_cntrl->ch_ctx_cache[i].chcfg);
1120 if (FIELD_GET(CHAN_CTX_CHSTATE_MASK, tmp) != MHI_CH_STATE_RUNNING) {
1121 mutex_unlock(&mhi_chan->lock);
1125 dev_dbg(&mhi_chan->mhi_dev->dev, "Suspending channel\n");
1126 /* Set channel state to SUSPENDED */
1127 mhi_chan->state = MHI_CH_STATE_SUSPENDED;
1128 tmp &= ~CHAN_CTX_CHSTATE_MASK;
1129 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_SUSPENDED);
1130 mhi_cntrl->ch_ctx_cache[i].chcfg = cpu_to_le32(tmp);
1131 mutex_unlock(&mhi_chan->lock);
1135 void mhi_ep_resume_channels(struct mhi_ep_cntrl *mhi_cntrl)
1137 struct mhi_ep_chan *mhi_chan;
1141 for (i = 0; i < mhi_cntrl->max_chan; i++) {
1142 mhi_chan = &mhi_cntrl->mhi_chan[i];
1144 if (!mhi_chan->mhi_dev)
1147 mutex_lock(&mhi_chan->lock);
1148 /* Skip if the channel is not currently suspended */
1149 tmp = le32_to_cpu(mhi_cntrl->ch_ctx_cache[i].chcfg);
1150 if (FIELD_GET(CHAN_CTX_CHSTATE_MASK, tmp) != MHI_CH_STATE_SUSPENDED) {
1151 mutex_unlock(&mhi_chan->lock);
1155 dev_dbg(&mhi_chan->mhi_dev->dev, "Resuming channel\n");
1156 /* Set channel state to RUNNING */
1157 mhi_chan->state = MHI_CH_STATE_RUNNING;
1158 tmp &= ~CHAN_CTX_CHSTATE_MASK;
1159 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_RUNNING);
1160 mhi_cntrl->ch_ctx_cache[i].chcfg = cpu_to_le32(tmp);
1161 mutex_unlock(&mhi_chan->lock);
1165 static void mhi_ep_release_device(struct device *dev)
1167 struct mhi_ep_device *mhi_dev = to_mhi_ep_device(dev);
1169 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER)
1170 mhi_dev->mhi_cntrl->mhi_dev = NULL;
1173 * We need to set the mhi_chan->mhi_dev to NULL here since the MHI
1174 * devices for the channels will only get created in mhi_ep_create_device()
1175 * if the mhi_dev associated with it is NULL.
1177 if (mhi_dev->ul_chan)
1178 mhi_dev->ul_chan->mhi_dev = NULL;
1180 if (mhi_dev->dl_chan)
1181 mhi_dev->dl_chan->mhi_dev = NULL;
1186 static struct mhi_ep_device *mhi_ep_alloc_device(struct mhi_ep_cntrl *mhi_cntrl,
1187 enum mhi_device_type dev_type)
1189 struct mhi_ep_device *mhi_dev;
1192 mhi_dev = kzalloc(sizeof(*mhi_dev), GFP_KERNEL);
1194 return ERR_PTR(-ENOMEM);
1196 dev = &mhi_dev->dev;
1197 device_initialize(dev);
1198 dev->bus = &mhi_ep_bus_type;
1199 dev->release = mhi_ep_release_device;
1201 /* Controller device is always allocated first */
1202 if (dev_type == MHI_DEVICE_CONTROLLER)
1203 /* for MHI controller device, parent is the bus device (e.g. PCI EPF) */
1204 dev->parent = mhi_cntrl->cntrl_dev;
1206 /* for MHI client devices, parent is the MHI controller device */
1207 dev->parent = &mhi_cntrl->mhi_dev->dev;
1209 mhi_dev->mhi_cntrl = mhi_cntrl;
1210 mhi_dev->dev_type = dev_type;
1216 * MHI channels are always defined in pairs with UL as the even numbered
1217 * channel and DL as odd numbered one. This function gets UL channel (primary)
1218 * as the ch_id and always looks after the next entry in channel list for
1219 * the corresponding DL channel (secondary).
1221 static int mhi_ep_create_device(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id)
1223 struct mhi_ep_chan *mhi_chan = &mhi_cntrl->mhi_chan[ch_id];
1224 struct device *dev = mhi_cntrl->cntrl_dev;
1225 struct mhi_ep_device *mhi_dev;
1228 /* Check if the channel name is same for both UL and DL */
1229 if (strcmp(mhi_chan->name, mhi_chan[1].name)) {
1230 dev_err(dev, "UL and DL channel names are not same: (%s) != (%s)\n",
1231 mhi_chan->name, mhi_chan[1].name);
1235 mhi_dev = mhi_ep_alloc_device(mhi_cntrl, MHI_DEVICE_XFER);
1236 if (IS_ERR(mhi_dev))
1237 return PTR_ERR(mhi_dev);
1239 /* Configure primary channel */
1240 mhi_dev->ul_chan = mhi_chan;
1241 get_device(&mhi_dev->dev);
1242 mhi_chan->mhi_dev = mhi_dev;
1244 /* Configure secondary channel as well */
1246 mhi_dev->dl_chan = mhi_chan;
1247 get_device(&mhi_dev->dev);
1248 mhi_chan->mhi_dev = mhi_dev;
1250 /* Channel name is same for both UL and DL */
1251 mhi_dev->name = mhi_chan->name;
1252 ret = dev_set_name(&mhi_dev->dev, "%s_%s",
1253 dev_name(&mhi_cntrl->mhi_dev->dev),
1256 put_device(&mhi_dev->dev);
1260 ret = device_add(&mhi_dev->dev);
1262 put_device(&mhi_dev->dev);
1267 static int mhi_ep_destroy_device(struct device *dev, void *data)
1269 struct mhi_ep_device *mhi_dev;
1270 struct mhi_ep_cntrl *mhi_cntrl;
1271 struct mhi_ep_chan *ul_chan, *dl_chan;
1273 if (dev->bus != &mhi_ep_bus_type)
1276 mhi_dev = to_mhi_ep_device(dev);
1277 mhi_cntrl = mhi_dev->mhi_cntrl;
1279 /* Only destroy devices created for channels */
1280 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER)
1283 ul_chan = mhi_dev->ul_chan;
1284 dl_chan = mhi_dev->dl_chan;
1287 put_device(&ul_chan->mhi_dev->dev);
1290 put_device(&dl_chan->mhi_dev->dev);
1292 dev_dbg(&mhi_cntrl->mhi_dev->dev, "Destroying device for chan:%s\n",
1295 /* Notify the client and remove the device from MHI bus */
1302 static int mhi_ep_chan_init(struct mhi_ep_cntrl *mhi_cntrl,
1303 const struct mhi_ep_cntrl_config *config)
1305 const struct mhi_ep_channel_config *ch_cfg;
1306 struct device *dev = mhi_cntrl->cntrl_dev;
1310 mhi_cntrl->max_chan = config->max_channels;
1313 * Allocate max_channels supported by the MHI endpoint and populate
1314 * only the defined channels
1316 mhi_cntrl->mhi_chan = kcalloc(mhi_cntrl->max_chan, sizeof(*mhi_cntrl->mhi_chan),
1318 if (!mhi_cntrl->mhi_chan)
1321 for (i = 0; i < config->num_channels; i++) {
1322 struct mhi_ep_chan *mhi_chan;
1324 ch_cfg = &config->ch_cfg[i];
1327 if (chan >= mhi_cntrl->max_chan) {
1328 dev_err(dev, "Channel (%u) exceeds maximum available channels (%u)\n",
1329 chan, mhi_cntrl->max_chan);
1330 goto error_chan_cfg;
1333 /* Bi-directional and direction less channels are not supported */
1334 if (ch_cfg->dir == DMA_BIDIRECTIONAL || ch_cfg->dir == DMA_NONE) {
1335 dev_err(dev, "Invalid direction (%u) for channel (%u)\n",
1337 goto error_chan_cfg;
1340 mhi_chan = &mhi_cntrl->mhi_chan[chan];
1341 mhi_chan->name = ch_cfg->name;
1342 mhi_chan->chan = chan;
1343 mhi_chan->dir = ch_cfg->dir;
1344 mutex_init(&mhi_chan->lock);
1350 kfree(mhi_cntrl->mhi_chan);
1356 * Allocate channel and command rings here. Event rings will be allocated
1357 * in mhi_ep_power_up() as the config comes from the host.
1359 int mhi_ep_register_controller(struct mhi_ep_cntrl *mhi_cntrl,
1360 const struct mhi_ep_cntrl_config *config)
1362 struct mhi_ep_device *mhi_dev;
1365 if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->mmio || !mhi_cntrl->irq)
1368 ret = mhi_ep_chan_init(mhi_cntrl, config);
1372 mhi_cntrl->mhi_cmd = kcalloc(NR_OF_CMD_RINGS, sizeof(*mhi_cntrl->mhi_cmd), GFP_KERNEL);
1373 if (!mhi_cntrl->mhi_cmd) {
1378 INIT_WORK(&mhi_cntrl->state_work, mhi_ep_state_worker);
1379 INIT_WORK(&mhi_cntrl->reset_work, mhi_ep_reset_worker);
1380 INIT_WORK(&mhi_cntrl->cmd_ring_work, mhi_ep_cmd_ring_worker);
1381 INIT_WORK(&mhi_cntrl->ch_ring_work, mhi_ep_ch_ring_worker);
1383 mhi_cntrl->wq = alloc_workqueue("mhi_ep_wq", 0, 0);
1384 if (!mhi_cntrl->wq) {
1389 INIT_LIST_HEAD(&mhi_cntrl->st_transition_list);
1390 INIT_LIST_HEAD(&mhi_cntrl->ch_db_list);
1391 spin_lock_init(&mhi_cntrl->list_lock);
1392 mutex_init(&mhi_cntrl->state_lock);
1393 mutex_init(&mhi_cntrl->event_lock);
1395 /* Set MHI version and AMSS EE before enumeration */
1396 mhi_ep_mmio_write(mhi_cntrl, EP_MHIVER, config->mhi_version);
1397 mhi_ep_mmio_set_env(mhi_cntrl, MHI_EE_AMSS);
1399 /* Set controller index */
1400 ret = ida_alloc(&mhi_ep_cntrl_ida, GFP_KERNEL);
1402 goto err_destroy_wq;
1404 mhi_cntrl->index = ret;
1406 irq_set_status_flags(mhi_cntrl->irq, IRQ_NOAUTOEN);
1407 ret = request_irq(mhi_cntrl->irq, mhi_ep_irq, IRQF_TRIGGER_HIGH,
1408 "doorbell_irq", mhi_cntrl);
1410 dev_err(mhi_cntrl->cntrl_dev, "Failed to request Doorbell IRQ\n");
1414 /* Allocate the controller device */
1415 mhi_dev = mhi_ep_alloc_device(mhi_cntrl, MHI_DEVICE_CONTROLLER);
1416 if (IS_ERR(mhi_dev)) {
1417 dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate controller device\n");
1418 ret = PTR_ERR(mhi_dev);
1422 ret = dev_set_name(&mhi_dev->dev, "mhi_ep%u", mhi_cntrl->index);
1426 mhi_dev->name = dev_name(&mhi_dev->dev);
1427 mhi_cntrl->mhi_dev = mhi_dev;
1429 ret = device_add(&mhi_dev->dev);
1433 dev_dbg(&mhi_dev->dev, "MHI EP Controller registered\n");
1438 put_device(&mhi_dev->dev);
1440 free_irq(mhi_cntrl->irq, mhi_cntrl);
1442 ida_free(&mhi_ep_cntrl_ida, mhi_cntrl->index);
1444 destroy_workqueue(mhi_cntrl->wq);
1446 kfree(mhi_cntrl->mhi_cmd);
1448 kfree(mhi_cntrl->mhi_chan);
1452 EXPORT_SYMBOL_GPL(mhi_ep_register_controller);
1455 * It is expected that the controller drivers will power down the MHI EP stack
1456 * using "mhi_ep_power_down()" before calling this function to unregister themselves.
1458 void mhi_ep_unregister_controller(struct mhi_ep_cntrl *mhi_cntrl)
1460 struct mhi_ep_device *mhi_dev = mhi_cntrl->mhi_dev;
1462 destroy_workqueue(mhi_cntrl->wq);
1464 free_irq(mhi_cntrl->irq, mhi_cntrl);
1466 kfree(mhi_cntrl->mhi_cmd);
1467 kfree(mhi_cntrl->mhi_chan);
1469 device_del(&mhi_dev->dev);
1470 put_device(&mhi_dev->dev);
1472 ida_free(&mhi_ep_cntrl_ida, mhi_cntrl->index);
1474 EXPORT_SYMBOL_GPL(mhi_ep_unregister_controller);
1476 static int mhi_ep_driver_probe(struct device *dev)
1478 struct mhi_ep_device *mhi_dev = to_mhi_ep_device(dev);
1479 struct mhi_ep_driver *mhi_drv = to_mhi_ep_driver(dev->driver);
1480 struct mhi_ep_chan *ul_chan = mhi_dev->ul_chan;
1481 struct mhi_ep_chan *dl_chan = mhi_dev->dl_chan;
1483 ul_chan->xfer_cb = mhi_drv->ul_xfer_cb;
1484 dl_chan->xfer_cb = mhi_drv->dl_xfer_cb;
1486 return mhi_drv->probe(mhi_dev, mhi_dev->id);
1489 static int mhi_ep_driver_remove(struct device *dev)
1491 struct mhi_ep_device *mhi_dev = to_mhi_ep_device(dev);
1492 struct mhi_ep_driver *mhi_drv = to_mhi_ep_driver(dev->driver);
1493 struct mhi_result result = {};
1494 struct mhi_ep_chan *mhi_chan;
1497 /* Skip if it is a controller device */
1498 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER)
1501 /* Disconnect the channels associated with the driver */
1502 for (dir = 0; dir < 2; dir++) {
1503 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan;
1508 mutex_lock(&mhi_chan->lock);
1509 /* Send channel disconnect status to the client driver */
1510 if (mhi_chan->xfer_cb) {
1511 result.transaction_status = -ENOTCONN;
1512 result.bytes_xferd = 0;
1513 mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result);
1516 mhi_chan->state = MHI_CH_STATE_DISABLED;
1517 mhi_chan->xfer_cb = NULL;
1518 mutex_unlock(&mhi_chan->lock);
1521 /* Remove the client driver now */
1522 mhi_drv->remove(mhi_dev);
1527 int __mhi_ep_driver_register(struct mhi_ep_driver *mhi_drv, struct module *owner)
1529 struct device_driver *driver = &mhi_drv->driver;
1531 if (!mhi_drv->probe || !mhi_drv->remove)
1534 /* Client drivers should have callbacks defined for both channels */
1535 if (!mhi_drv->ul_xfer_cb || !mhi_drv->dl_xfer_cb)
1538 driver->bus = &mhi_ep_bus_type;
1539 driver->owner = owner;
1540 driver->probe = mhi_ep_driver_probe;
1541 driver->remove = mhi_ep_driver_remove;
1543 return driver_register(driver);
1545 EXPORT_SYMBOL_GPL(__mhi_ep_driver_register);
1547 void mhi_ep_driver_unregister(struct mhi_ep_driver *mhi_drv)
1549 driver_unregister(&mhi_drv->driver);
1551 EXPORT_SYMBOL_GPL(mhi_ep_driver_unregister);
1553 static int mhi_ep_uevent(struct device *dev, struct kobj_uevent_env *env)
1555 struct mhi_ep_device *mhi_dev = to_mhi_ep_device(dev);
1557 return add_uevent_var(env, "MODALIAS=" MHI_EP_DEVICE_MODALIAS_FMT,
1561 static int mhi_ep_match(struct device *dev, struct device_driver *drv)
1563 struct mhi_ep_device *mhi_dev = to_mhi_ep_device(dev);
1564 struct mhi_ep_driver *mhi_drv = to_mhi_ep_driver(drv);
1565 const struct mhi_device_id *id;
1568 * If the device is a controller type then there is no client driver
1569 * associated with it
1571 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER)
1574 for (id = mhi_drv->id_table; id->chan[0]; id++)
1575 if (!strcmp(mhi_dev->name, id->chan)) {
1583 struct bus_type mhi_ep_bus_type = {
1585 .dev_name = "mhi_ep",
1586 .match = mhi_ep_match,
1587 .uevent = mhi_ep_uevent,
1590 static int __init mhi_ep_init(void)
1592 return bus_register(&mhi_ep_bus_type);
1595 static void __exit mhi_ep_exit(void)
1597 bus_unregister(&mhi_ep_bus_type);
1600 postcore_initcall(mhi_ep_init);
1601 module_exit(mhi_ep_exit);
1603 MODULE_LICENSE("GPL v2");
1604 MODULE_DESCRIPTION("MHI Bus Endpoint stack");
1605 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");