2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/errno.h>
25 #include <linux/genhd.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/kdev_t.h>
30 #include <linux/kthread.h>
31 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/types.h>
40 #include <linux/version.h>
42 #define NVME_Q_DEPTH 1024
43 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
44 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
45 #define NVME_MINORS 64
46 #define IO_TIMEOUT (5 * HZ)
47 #define ADMIN_TIMEOUT (60 * HZ)
49 static int nvme_major;
50 module_param(nvme_major, int, 0);
52 static int use_threaded_interrupts;
53 module_param(use_threaded_interrupts, int, 0);
55 static DEFINE_SPINLOCK(dev_list_lock);
56 static LIST_HEAD(dev_list);
57 static struct task_struct *nvme_thread;
60 * Represents an NVM Express device. Each nvme_dev is a PCI function.
63 struct list_head node;
64 struct nvme_queue **queues;
66 struct pci_dev *pci_dev;
67 struct dma_pool *prp_page_pool;
68 struct dma_pool *prp_small_pool;
72 struct msix_entry *entry;
73 struct nvme_bar __iomem *bar;
74 struct list_head namespaces;
81 * An NVM Express namespace is equivalent to a SCSI LUN
84 struct list_head list;
87 struct request_queue *queue;
95 * An NVM Express queue. Each device has at least two (one for admin
96 * commands and one for I/O commands).
99 struct device *q_dmadev;
100 struct nvme_dev *dev;
102 struct nvme_command *sq_cmds;
103 volatile struct nvme_completion *cqes;
104 dma_addr_t sq_dma_addr;
105 dma_addr_t cq_dma_addr;
106 wait_queue_head_t sq_full;
107 wait_queue_t sq_cong_wait;
108 struct bio_list sq_cong;
116 unsigned long cmdid_data[];
120 * Check we didin't inadvertently grow the command struct
122 static inline void _nvme_check_size(void)
124 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
125 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
131 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
132 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
135 struct nvme_cmd_info {
137 unsigned long timeout;
140 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
142 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
146 * alloc_cmdid() - Allocate a Command ID
147 * @nvmeq: The queue that will be used for this command
148 * @ctx: A pointer that will be passed to the handler
149 * @handler: The ID of the handler to call
151 * Allocate a Command ID for a queue. The data passed in will
152 * be passed to the completion handler. This is implemented by using
153 * the bottom two bits of the ctx pointer to store the handler ID.
154 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
155 * We can change this if it becomes a problem.
157 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
160 int depth = nvmeq->q_depth - 1;
161 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
164 BUG_ON((unsigned long)ctx & 3);
167 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
170 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
172 info[cmdid].ctx = (unsigned long)ctx | handler;
173 info[cmdid].timeout = jiffies + timeout;
177 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
178 int handler, unsigned timeout)
181 wait_event_killable(nvmeq->sq_full,
182 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
183 return (cmdid < 0) ? -EINTR : cmdid;
187 * If you need more than four handlers, you'll need to change how
188 * alloc_cmdid and nvme_process_cq work. Consider using a special
189 * CMD_CTX value instead, if that works for your situation.
192 sync_completion_id = 0,
196 /* Special values must be a multiple of 4, and less than 0x1000 */
197 #define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id)
198 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
199 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
200 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
201 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
203 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
206 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
208 if (cmdid >= nvmeq->q_depth)
209 return CMD_CTX_INVALID;
210 data = info[cmdid].ctx;
211 info[cmdid].ctx = CMD_CTX_COMPLETED;
212 clear_bit(cmdid, nvmeq->cmdid_data);
213 wake_up(&nvmeq->sq_full);
217 static unsigned long cancel_cmdid(struct nvme_queue *nvmeq, int cmdid)
220 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
221 data = info[cmdid].ctx;
222 info[cmdid].ctx = CMD_CTX_CANCELLED;
226 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
228 return ns->dev->queues[get_cpu() + 1];
231 static void put_nvmeq(struct nvme_queue *nvmeq)
237 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
238 * @nvmeq: The queue to use
239 * @cmd: The command to send
241 * Safe to use from interrupt context
243 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
247 spin_lock_irqsave(&nvmeq->q_lock, flags);
248 tail = nvmeq->sq_tail;
249 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
250 if (++tail == nvmeq->q_depth)
252 writel(tail, nvmeq->q_db);
253 nvmeq->sq_tail = tail;
254 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
261 dma_addr_t first_dma;
265 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
267 const int last_prp = PAGE_SIZE / 8 - 1;
274 prp_dma = prps->first_dma;
276 if (prps->npages == 0)
277 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
278 for (i = 0; i < prps->npages; i++) {
279 __le64 *prp_list = prps->list[i];
280 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
281 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
282 prp_dma = next_prp_dma;
290 struct nvme_prps *prps;
291 struct scatterlist sg[0];
294 /* XXX: use a mempool */
295 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
297 return kzalloc(sizeof(struct nvme_bio) +
298 sizeof(struct scatterlist) * nseg, gfp);
301 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
303 nvme_free_prps(nvmeq->dev, nbio->prps);
307 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
308 struct nvme_completion *cqe)
310 struct nvme_bio *nbio = ctx;
311 struct bio *bio = nbio->bio;
312 u16 status = le16_to_cpup(&cqe->status) >> 1;
314 dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
315 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
316 free_nbio(nvmeq, nbio);
318 bio_endio(bio, -EIO);
319 } else if (bio->bi_vcnt > bio->bi_idx) {
320 bio_list_add(&nvmeq->sq_cong, bio);
321 wake_up_process(nvme_thread);
327 /* length is in bytes */
328 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
329 struct nvme_common_command *cmd,
330 struct scatterlist *sg, int length)
332 struct dma_pool *pool;
333 int dma_len = sg_dma_len(sg);
334 u64 dma_addr = sg_dma_address(sg);
335 int offset = offset_in_page(dma_addr);
338 int nprps, npages, i, prp_page;
339 struct nvme_prps *prps = NULL;
341 cmd->prp1 = cpu_to_le64(dma_addr);
342 length -= (PAGE_SIZE - offset);
346 dma_len -= (PAGE_SIZE - offset);
348 dma_addr += (PAGE_SIZE - offset);
351 dma_addr = sg_dma_address(sg);
352 dma_len = sg_dma_len(sg);
355 if (length <= PAGE_SIZE) {
356 cmd->prp2 = cpu_to_le64(dma_addr);
360 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
361 npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
362 prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
364 if (nprps <= (256 / 8)) {
365 pool = dev->prp_small_pool;
368 pool = dev->prp_page_pool;
369 prps->npages = npages;
372 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
373 prps->list[prp_page++] = prp_list;
374 prps->first_dma = prp_dma;
375 cmd->prp2 = cpu_to_le64(prp_dma);
378 if (i == PAGE_SIZE / 8) {
379 __le64 *old_prp_list = prp_list;
380 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
381 prps->list[prp_page++] = prp_list;
382 prp_list[0] = old_prp_list[i - 1];
383 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
386 prp_list[i++] = cpu_to_le64(dma_addr);
387 dma_len -= PAGE_SIZE;
388 dma_addr += PAGE_SIZE;
396 dma_addr = sg_dma_address(sg);
397 dma_len = sg_dma_len(sg);
403 /* NVMe scatterlists require no holes in the virtual address */
404 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
405 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
407 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
408 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
410 struct bio_vec *bvec, *bvprv = NULL;
411 struct scatterlist *sg = NULL;
412 int i, old_idx, length = 0, nsegs = 0;
414 sg_init_table(nbio->sg, psegs);
415 old_idx = bio->bi_idx;
416 bio_for_each_segment(bvec, bio, i) {
417 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
418 sg->length += bvec->bv_len;
420 if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
422 sg = sg ? sg + 1 : nbio->sg;
423 sg_set_page(sg, bvec->bv_page, bvec->bv_len,
427 length += bvec->bv_len;
433 if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
434 bio->bi_idx = old_idx;
440 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
443 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
445 memset(cmnd, 0, sizeof(*cmnd));
446 cmnd->common.opcode = nvme_cmd_flush;
447 cmnd->common.command_id = cmdid;
448 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
450 if (++nvmeq->sq_tail == nvmeq->q_depth)
452 writel(nvmeq->sq_tail, nvmeq->q_db);
457 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
459 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
460 sync_completion_id, IO_TIMEOUT);
461 if (unlikely(cmdid < 0))
464 return nvme_submit_flush(nvmeq, ns, cmdid);
467 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
470 struct nvme_command *cmnd;
471 struct nvme_bio *nbio;
472 enum dma_data_direction dma_dir;
473 int cmdid, length, result = -ENOMEM;
476 int psegs = bio_phys_segments(ns->queue, bio);
478 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
479 result = nvme_submit_flush_data(nvmeq, ns);
484 nbio = alloc_nbio(psegs, GFP_ATOMIC);
490 cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
491 if (unlikely(cmdid < 0))
494 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
495 return nvme_submit_flush(nvmeq, ns, cmdid);
498 if (bio->bi_rw & REQ_FUA)
499 control |= NVME_RW_FUA;
500 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
501 control |= NVME_RW_LR;
504 if (bio->bi_rw & REQ_RAHEAD)
505 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
507 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
509 memset(cmnd, 0, sizeof(*cmnd));
510 if (bio_data_dir(bio)) {
511 cmnd->rw.opcode = nvme_cmd_write;
512 dma_dir = DMA_TO_DEVICE;
514 cmnd->rw.opcode = nvme_cmd_read;
515 dma_dir = DMA_FROM_DEVICE;
518 result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
523 cmnd->rw.command_id = cmdid;
524 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
525 nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
527 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
528 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
529 cmnd->rw.control = cpu_to_le16(control);
530 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
532 bio->bi_sector += length >> 9;
534 if (++nvmeq->sq_tail == nvmeq->q_depth)
536 writel(nvmeq->sq_tail, nvmeq->q_db);
541 free_nbio(nvmeq, nbio);
547 * NB: return value of non-zero would mean that we were a stacking driver.
548 * make_request must always succeed.
550 static int nvme_make_request(struct request_queue *q, struct bio *bio)
552 struct nvme_ns *ns = q->queuedata;
553 struct nvme_queue *nvmeq = get_nvmeq(ns);
556 spin_lock_irq(&nvmeq->q_lock);
557 if (bio_list_empty(&nvmeq->sq_cong))
558 result = nvme_submit_bio_queue(nvmeq, ns, bio);
559 if (unlikely(result)) {
560 if (bio_list_empty(&nvmeq->sq_cong))
561 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
562 bio_list_add(&nvmeq->sq_cong, bio);
565 spin_unlock_irq(&nvmeq->q_lock);
571 struct sync_cmd_info {
572 struct task_struct *task;
577 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
578 struct nvme_completion *cqe)
580 struct sync_cmd_info *cmdinfo = ctx;
581 if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
583 if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
585 if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
586 dev_warn(nvmeq->q_dmadev,
587 "completed id %d twice on queue %d\n",
588 cqe->command_id, le16_to_cpup(&cqe->sq_id));
591 if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
592 dev_warn(nvmeq->q_dmadev,
593 "invalid id %d completed on queue %d\n",
594 cqe->command_id, le16_to_cpup(&cqe->sq_id));
597 cmdinfo->result = le32_to_cpup(&cqe->result);
598 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
599 wake_up_process(cmdinfo->task);
602 typedef void (*completion_fn)(struct nvme_queue *, void *,
603 struct nvme_completion *);
605 static const completion_fn nvme_completions[4] = {
606 [sync_completion_id] = sync_completion,
607 [bio_completion_id] = bio_completion,
610 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
614 head = nvmeq->cq_head;
615 phase = nvmeq->cq_phase;
620 unsigned char handler;
621 struct nvme_completion cqe = nvmeq->cqes[head];
622 if ((le16_to_cpu(cqe.status) & 1) != phase)
624 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
625 if (++head == nvmeq->q_depth) {
630 data = free_cmdid(nvmeq, cqe.command_id);
632 ptr = (void *)(data & ~3UL);
633 nvme_completions[handler](nvmeq, ptr, &cqe);
636 /* If the controller ignores the cq head doorbell and continuously
637 * writes to the queue, it is theoretically possible to wrap around
638 * the queue twice and mistakenly return IRQ_NONE. Linux only
639 * requires that 0.1% of your interrupts are handled, so this isn't
642 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
645 writel(head, nvmeq->q_db + 1);
646 nvmeq->cq_head = head;
647 nvmeq->cq_phase = phase;
652 static irqreturn_t nvme_irq(int irq, void *data)
655 struct nvme_queue *nvmeq = data;
656 spin_lock(&nvmeq->q_lock);
657 result = nvme_process_cq(nvmeq);
658 spin_unlock(&nvmeq->q_lock);
662 static irqreturn_t nvme_irq_check(int irq, void *data)
664 struct nvme_queue *nvmeq = data;
665 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
666 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
668 return IRQ_WAKE_THREAD;
671 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
673 spin_lock_irq(&nvmeq->q_lock);
674 cancel_cmdid(nvmeq, cmdid);
675 spin_unlock_irq(&nvmeq->q_lock);
679 * Returns 0 on success. If the result is negative, it's a Linux error code;
680 * if the result is positive, it's an NVM Express status code
682 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
683 struct nvme_command *cmd, u32 *result, unsigned timeout)
686 struct sync_cmd_info cmdinfo;
688 cmdinfo.task = current;
689 cmdinfo.status = -EINTR;
691 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
695 cmd->common.command_id = cmdid;
697 set_current_state(TASK_KILLABLE);
698 nvme_submit_cmd(nvmeq, cmd);
701 if (cmdinfo.status == -EINTR) {
702 nvme_abort_command(nvmeq, cmdid);
707 *result = cmdinfo.result;
709 return cmdinfo.status;
712 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
715 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
718 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
721 struct nvme_command c;
723 memset(&c, 0, sizeof(c));
724 c.delete_queue.opcode = opcode;
725 c.delete_queue.qid = cpu_to_le16(id);
727 status = nvme_submit_admin_cmd(dev, &c, NULL);
733 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
734 struct nvme_queue *nvmeq)
737 struct nvme_command c;
738 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
740 memset(&c, 0, sizeof(c));
741 c.create_cq.opcode = nvme_admin_create_cq;
742 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
743 c.create_cq.cqid = cpu_to_le16(qid);
744 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
745 c.create_cq.cq_flags = cpu_to_le16(flags);
746 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
748 status = nvme_submit_admin_cmd(dev, &c, NULL);
754 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
755 struct nvme_queue *nvmeq)
758 struct nvme_command c;
759 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
761 memset(&c, 0, sizeof(c));
762 c.create_sq.opcode = nvme_admin_create_sq;
763 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
764 c.create_sq.sqid = cpu_to_le16(qid);
765 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
766 c.create_sq.sq_flags = cpu_to_le16(flags);
767 c.create_sq.cqid = cpu_to_le16(qid);
769 status = nvme_submit_admin_cmd(dev, &c, NULL);
775 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
777 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
780 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
782 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
785 static void nvme_free_queue(struct nvme_dev *dev, int qid)
787 struct nvme_queue *nvmeq = dev->queues[qid];
788 int vector = dev->entry[nvmeq->cq_vector].vector;
790 irq_set_affinity_hint(vector, NULL);
791 free_irq(vector, nvmeq);
793 /* Don't tell the adapter to delete the admin queue */
795 adapter_delete_sq(dev, qid);
796 adapter_delete_cq(dev, qid);
799 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
800 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
801 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
802 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
806 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
807 int depth, int vector)
809 struct device *dmadev = &dev->pci_dev->dev;
810 unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
811 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
815 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
816 &nvmeq->cq_dma_addr, GFP_KERNEL);
819 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
821 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
822 &nvmeq->sq_dma_addr, GFP_KERNEL);
826 nvmeq->q_dmadev = dmadev;
828 spin_lock_init(&nvmeq->q_lock);
831 init_waitqueue_head(&nvmeq->sq_full);
832 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
833 bio_list_init(&nvmeq->sq_cong);
834 nvmeq->q_db = &dev->dbs[qid * 2];
835 nvmeq->q_depth = depth;
836 nvmeq->cq_vector = vector;
841 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
848 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
851 if (use_threaded_interrupts)
852 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
853 nvme_irq_check, nvme_irq,
854 IRQF_DISABLED | IRQF_SHARED,
856 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
857 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
860 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
861 int qid, int cq_size, int vector)
864 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
869 result = adapter_alloc_cq(dev, qid, nvmeq);
873 result = adapter_alloc_sq(dev, qid, nvmeq);
877 result = queue_request_irq(dev, nvmeq, "nvme");
884 adapter_delete_sq(dev, qid);
886 adapter_delete_cq(dev, qid);
888 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
889 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
890 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
891 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
896 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
901 unsigned long timeout;
902 struct nvme_queue *nvmeq;
904 dev->dbs = ((void __iomem *)dev->bar) + 4096;
906 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
910 aqa = nvmeq->q_depth - 1;
913 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
914 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
915 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
916 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
918 writel(0, &dev->bar->cc);
919 writel(aqa, &dev->bar->aqa);
920 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
921 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
922 writel(dev->ctrl_config, &dev->bar->cc);
924 cap = readq(&dev->bar->cap);
925 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
927 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
929 if (fatal_signal_pending(current))
931 if (time_after(jiffies, timeout)) {
932 dev_err(&dev->pci_dev->dev,
933 "Device not ready; aborting initialisation\n");
938 result = queue_request_irq(dev, nvmeq, "nvme admin");
939 dev->queues[0] = nvmeq;
943 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
944 unsigned long addr, unsigned length,
945 struct scatterlist **sgp)
947 int i, err, count, nents, offset;
948 struct scatterlist *sg;
956 offset = offset_in_page(addr);
957 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
958 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
960 err = get_user_pages_fast(addr, count, 1, pages);
967 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
968 sg_init_table(sg, count);
969 sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
970 length -= (PAGE_SIZE - offset);
971 for (i = 1; i < count; i++) {
972 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
977 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
978 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
987 for (i = 0; i < count; i++)
993 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
994 unsigned long addr, int length,
995 struct scatterlist *sg, int nents)
999 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
1000 dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
1002 for (i = 0; i < count; i++)
1003 put_page(sg_page(&sg[i]));
1006 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
1007 unsigned long addr, unsigned length,
1008 struct nvme_command *cmd)
1011 struct scatterlist *sg;
1012 struct nvme_prps *prps;
1014 nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
1017 prps = nvme_setup_prps(dev, &cmd->common, sg, length);
1018 err = nvme_submit_admin_cmd(dev, cmd, NULL);
1019 nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
1020 nvme_free_prps(dev, prps);
1021 return err ? -EIO : 0;
1024 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
1026 struct nvme_command c;
1028 memset(&c, 0, sizeof(c));
1029 c.identify.opcode = nvme_admin_identify;
1030 c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
1031 c.identify.cns = cpu_to_le32(cns);
1033 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1036 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
1038 struct nvme_command c;
1040 memset(&c, 0, sizeof(c));
1041 c.features.opcode = nvme_admin_get_features;
1042 c.features.nsid = cpu_to_le32(ns->ns_id);
1043 c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1045 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1048 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1050 struct nvme_dev *dev = ns->dev;
1051 struct nvme_queue *nvmeq;
1052 struct nvme_user_io io;
1053 struct nvme_command c;
1056 struct scatterlist *sg;
1057 struct nvme_prps *prps;
1059 if (copy_from_user(&io, uio, sizeof(io)))
1061 length = (io.nblocks + 1) << ns->lba_shift;
1063 switch (io.opcode) {
1064 case nvme_cmd_write:
1066 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr,
1075 memset(&c, 0, sizeof(c));
1076 c.rw.opcode = io.opcode;
1077 c.rw.flags = io.flags;
1078 c.rw.nsid = cpu_to_le32(ns->ns_id);
1079 c.rw.slba = cpu_to_le64(io.slba);
1080 c.rw.length = cpu_to_le16(io.nblocks);
1081 c.rw.control = cpu_to_le16(io.control);
1082 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1083 c.rw.reftag = io.reftag;
1084 c.rw.apptag = io.apptag;
1085 c.rw.appmask = io.appmask;
1087 prps = nvme_setup_prps(dev, &c.common, sg, length);
1089 nvmeq = get_nvmeq(ns);
1091 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1092 * disabled. We may be preempted at any point, and be rescheduled
1093 * to a different CPU. That will cause cacheline bouncing, but no
1094 * additional races since q_lock already protects against other CPUs.
1097 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, IO_TIMEOUT);
1099 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1100 nvme_free_prps(dev, prps);
1104 static int nvme_download_firmware(struct nvme_ns *ns,
1105 struct nvme_dlfw __user *udlfw)
1107 struct nvme_dev *dev = ns->dev;
1108 struct nvme_dlfw dlfw;
1109 struct nvme_command c;
1111 struct scatterlist *sg;
1112 struct nvme_prps *prps;
1114 if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1116 if (dlfw.length >= (1 << 30))
1119 nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1123 memset(&c, 0, sizeof(c));
1124 c.dlfw.opcode = nvme_admin_download_fw;
1125 c.dlfw.numd = cpu_to_le32(dlfw.length);
1126 c.dlfw.offset = cpu_to_le32(dlfw.offset);
1127 prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
1129 status = nvme_submit_admin_cmd(dev, &c, NULL);
1130 nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1131 nvme_free_prps(dev, prps);
1135 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1137 struct nvme_dev *dev = ns->dev;
1138 struct nvme_command c;
1140 memset(&c, 0, sizeof(c));
1141 c.common.opcode = nvme_admin_activate_fw;
1142 c.common.rsvd10[0] = cpu_to_le32(arg);
1144 return nvme_submit_admin_cmd(dev, &c, NULL);
1147 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1150 struct nvme_ns *ns = bdev->bd_disk->private_data;
1153 case NVME_IOCTL_IDENTIFY_NS:
1154 return nvme_identify(ns, arg, 0);
1155 case NVME_IOCTL_IDENTIFY_CTRL:
1156 return nvme_identify(ns, arg, 1);
1157 case NVME_IOCTL_GET_RANGE_TYPE:
1158 return nvme_get_range_type(ns, arg);
1159 case NVME_IOCTL_SUBMIT_IO:
1160 return nvme_submit_io(ns, (void __user *)arg);
1161 case NVME_IOCTL_DOWNLOAD_FW:
1162 return nvme_download_firmware(ns, (void __user *)arg);
1163 case NVME_IOCTL_ACTIVATE_FW:
1164 return nvme_activate_firmware(ns, arg);
1170 static const struct block_device_operations nvme_fops = {
1171 .owner = THIS_MODULE,
1172 .ioctl = nvme_ioctl,
1173 .compat_ioctl = nvme_ioctl,
1176 static void nvme_timeout_ios(struct nvme_queue *nvmeq)
1178 int depth = nvmeq->q_depth - 1;
1179 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1180 unsigned long now = jiffies;
1183 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1186 unsigned char handler;
1187 static struct nvme_completion cqe = { .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, };
1189 if (!time_after(now, info[cmdid].timeout))
1191 dev_warn(nvmeq->q_dmadev, "Timing out I/O %d\n", cmdid);
1192 data = cancel_cmdid(nvmeq, cmdid);
1194 ptr = (void *)(data & ~3UL);
1195 nvme_completions[handler](nvmeq, ptr, &cqe);
1199 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1201 while (bio_list_peek(&nvmeq->sq_cong)) {
1202 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1203 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1204 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1205 bio_list_add_head(&nvmeq->sq_cong, bio);
1208 if (bio_list_empty(&nvmeq->sq_cong))
1209 remove_wait_queue(&nvmeq->sq_full,
1210 &nvmeq->sq_cong_wait);
1214 static int nvme_kthread(void *data)
1216 struct nvme_dev *dev;
1218 while (!kthread_should_stop()) {
1219 __set_current_state(TASK_RUNNING);
1220 spin_lock(&dev_list_lock);
1221 list_for_each_entry(dev, &dev_list, node) {
1223 for (i = 0; i < dev->queue_count; i++) {
1224 struct nvme_queue *nvmeq = dev->queues[i];
1227 spin_lock_irq(&nvmeq->q_lock);
1228 if (nvme_process_cq(nvmeq))
1229 printk("process_cq did something\n");
1230 nvme_timeout_ios(nvmeq);
1231 nvme_resubmit_bios(nvmeq);
1232 spin_unlock_irq(&nvmeq->q_lock);
1235 spin_unlock(&dev_list_lock);
1236 set_current_state(TASK_INTERRUPTIBLE);
1237 schedule_timeout(HZ);
1242 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1243 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1246 struct gendisk *disk;
1249 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1252 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1255 ns->queue = blk_alloc_queue(GFP_KERNEL);
1258 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1259 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1260 blk_queue_make_request(ns->queue, nvme_make_request);
1262 ns->queue->queuedata = ns;
1264 disk = alloc_disk(NVME_MINORS);
1266 goto out_free_queue;
1269 lbaf = id->flbas & 0xf;
1270 ns->lba_shift = id->lbaf[lbaf].ds;
1272 disk->major = nvme_major;
1273 disk->minors = NVME_MINORS;
1274 disk->first_minor = NVME_MINORS * index;
1275 disk->fops = &nvme_fops;
1276 disk->private_data = ns;
1277 disk->queue = ns->queue;
1278 disk->driverfs_dev = &dev->pci_dev->dev;
1279 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1280 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1285 blk_cleanup_queue(ns->queue);
1291 static void nvme_ns_free(struct nvme_ns *ns)
1294 blk_cleanup_queue(ns->queue);
1298 static int set_queue_count(struct nvme_dev *dev, int count)
1302 struct nvme_command c;
1303 u32 q_count = (count - 1) | ((count - 1) << 16);
1305 memset(&c, 0, sizeof(c));
1306 c.features.opcode = nvme_admin_get_features;
1307 c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1308 c.features.dword11 = cpu_to_le32(q_count);
1310 status = nvme_submit_admin_cmd(dev, &c, &result);
1313 return min(result & 0xffff, result >> 16) + 1;
1316 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1318 int result, cpu, i, nr_io_queues;
1320 nr_io_queues = num_online_cpus();
1321 result = set_queue_count(dev, nr_io_queues);
1324 if (result < nr_io_queues)
1325 nr_io_queues = result;
1327 /* Deregister the admin queue's interrupt */
1328 free_irq(dev->entry[0].vector, dev->queues[0]);
1330 for (i = 0; i < nr_io_queues; i++)
1331 dev->entry[i].entry = i;
1333 result = pci_enable_msix(dev->pci_dev, dev->entry,
1337 } else if (result > 0) {
1338 nr_io_queues = result;
1346 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1347 /* XXX: handle failure here */
1349 cpu = cpumask_first(cpu_online_mask);
1350 for (i = 0; i < nr_io_queues; i++) {
1351 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1352 cpu = cpumask_next(cpu, cpu_online_mask);
1355 for (i = 0; i < nr_io_queues; i++) {
1356 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1358 if (!dev->queues[i + 1])
1363 for (; i < num_possible_cpus(); i++) {
1364 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1365 dev->queues[i + 1] = dev->queues[target + 1];
1371 static void nvme_free_queues(struct nvme_dev *dev)
1375 for (i = dev->queue_count - 1; i >= 0; i--)
1376 nvme_free_queue(dev, i);
1379 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1382 struct nvme_ns *ns, *next;
1383 struct nvme_id_ctrl *ctrl;
1385 dma_addr_t dma_addr;
1386 struct nvme_command cid, crt;
1388 res = nvme_setup_io_queues(dev);
1392 /* XXX: Switch to a SG list once prp2 works */
1393 id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1396 memset(&cid, 0, sizeof(cid));
1397 cid.identify.opcode = nvme_admin_identify;
1398 cid.identify.nsid = 0;
1399 cid.identify.prp1 = cpu_to_le64(dma_addr);
1400 cid.identify.cns = cpu_to_le32(1);
1402 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1409 nn = le32_to_cpup(&ctrl->nn);
1410 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1411 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1412 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1414 cid.identify.cns = 0;
1415 memset(&crt, 0, sizeof(crt));
1416 crt.features.opcode = nvme_admin_get_features;
1417 crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1418 crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1420 for (i = 0; i <= nn; i++) {
1421 cid.identify.nsid = cpu_to_le32(i);
1422 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1426 if (((struct nvme_id_ns *)id)->ncap == 0)
1429 crt.features.nsid = cpu_to_le32(i);
1430 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1434 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1436 list_add_tail(&ns->list, &dev->namespaces);
1438 list_for_each_entry(ns, &dev->namespaces, list)
1441 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1445 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1446 list_del(&ns->list);
1450 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1454 static int nvme_dev_remove(struct nvme_dev *dev)
1456 struct nvme_ns *ns, *next;
1458 spin_lock(&dev_list_lock);
1459 list_del(&dev->node);
1460 spin_unlock(&dev_list_lock);
1462 /* TODO: wait all I/O finished or cancel them */
1464 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1465 list_del(&ns->list);
1466 del_gendisk(ns->disk);
1470 nvme_free_queues(dev);
1475 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1477 struct device *dmadev = &dev->pci_dev->dev;
1478 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1479 PAGE_SIZE, PAGE_SIZE, 0);
1480 if (!dev->prp_page_pool)
1483 /* Optimisation for I/Os between 4k and 128k */
1484 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1486 if (!dev->prp_small_pool) {
1487 dma_pool_destroy(dev->prp_page_pool);
1493 static void nvme_release_prp_pools(struct nvme_dev *dev)
1495 dma_pool_destroy(dev->prp_page_pool);
1496 dma_pool_destroy(dev->prp_small_pool);
1499 /* XXX: Use an ida or something to let remove / add work correctly */
1500 static void nvme_set_instance(struct nvme_dev *dev)
1502 static int instance;
1503 dev->instance = instance++;
1506 static void nvme_release_instance(struct nvme_dev *dev)
1510 static int __devinit nvme_probe(struct pci_dev *pdev,
1511 const struct pci_device_id *id)
1513 int bars, result = -ENOMEM;
1514 struct nvme_dev *dev;
1516 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1519 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1523 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1528 if (pci_enable_device_mem(pdev))
1530 pci_set_master(pdev);
1531 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1532 if (pci_request_selected_regions(pdev, bars, "nvme"))
1535 INIT_LIST_HEAD(&dev->namespaces);
1536 dev->pci_dev = pdev;
1537 pci_set_drvdata(pdev, dev);
1538 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1539 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1540 nvme_set_instance(dev);
1541 dev->entry[0].vector = pdev->irq;
1543 result = nvme_setup_prp_pools(dev);
1547 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1553 result = nvme_configure_admin_queue(dev);
1558 spin_lock(&dev_list_lock);
1559 list_add(&dev->node, &dev_list);
1560 spin_unlock(&dev_list_lock);
1562 result = nvme_dev_add(dev);
1569 spin_lock(&dev_list_lock);
1570 list_del(&dev->node);
1571 spin_unlock(&dev_list_lock);
1573 nvme_free_queues(dev);
1577 pci_disable_msix(pdev);
1578 nvme_release_instance(dev);
1579 nvme_release_prp_pools(dev);
1581 pci_disable_device(pdev);
1582 pci_release_regions(pdev);
1590 static void __devexit nvme_remove(struct pci_dev *pdev)
1592 struct nvme_dev *dev = pci_get_drvdata(pdev);
1593 nvme_dev_remove(dev);
1594 pci_disable_msix(pdev);
1596 nvme_release_instance(dev);
1597 nvme_release_prp_pools(dev);
1598 pci_disable_device(pdev);
1599 pci_release_regions(pdev);
1605 /* These functions are yet to be implemented */
1606 #define nvme_error_detected NULL
1607 #define nvme_dump_registers NULL
1608 #define nvme_link_reset NULL
1609 #define nvme_slot_reset NULL
1610 #define nvme_error_resume NULL
1611 #define nvme_suspend NULL
1612 #define nvme_resume NULL
1614 static struct pci_error_handlers nvme_err_handler = {
1615 .error_detected = nvme_error_detected,
1616 .mmio_enabled = nvme_dump_registers,
1617 .link_reset = nvme_link_reset,
1618 .slot_reset = nvme_slot_reset,
1619 .resume = nvme_error_resume,
1622 /* Move to pci_ids.h later */
1623 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1625 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1626 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1629 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1631 static struct pci_driver nvme_driver = {
1633 .id_table = nvme_id_table,
1634 .probe = nvme_probe,
1635 .remove = __devexit_p(nvme_remove),
1636 .suspend = nvme_suspend,
1637 .resume = nvme_resume,
1638 .err_handler = &nvme_err_handler,
1641 static int __init nvme_init(void)
1643 int result = -EBUSY;
1645 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1646 if (IS_ERR(nvme_thread))
1647 return PTR_ERR(nvme_thread);
1649 nvme_major = register_blkdev(nvme_major, "nvme");
1650 if (nvme_major <= 0)
1653 result = pci_register_driver(&nvme_driver);
1655 goto unregister_blkdev;
1659 unregister_blkdev(nvme_major, "nvme");
1661 kthread_stop(nvme_thread);
1665 static void __exit nvme_exit(void)
1667 pci_unregister_driver(&nvme_driver);
1668 unregister_blkdev(nvme_major, "nvme");
1669 kthread_stop(nvme_thread);
1672 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1673 MODULE_LICENSE("GPL");
1674 MODULE_VERSION("0.5");
1675 module_init(nvme_init);
1676 module_exit(nvme_exit);