drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kernel.h>
  30 #include <linux/mm.h>
  31 #include <linux/module.h>
  32 #include <linux/moduleparam.h>
  33 #include <linux/pci.h>
  34 #include <linux/poison.h>
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/types.h>
  38 #include <linux/version.h>
  39
  40 #define NVME_Q_DEPTH 1024
  41 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  42 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  43 #define NVME_MINORS 64
  44 #define IO_TIMEOUT      (5 * HZ)
  45 #define ADMIN_TIMEOUT   (60 * HZ)
  46
  47 static int nvme_major;
  48 module_param(nvme_major, int, 0);
  49
  50 static int use_threaded_interrupts;
  51 module_param(use_threaded_interrupts, int, 0);
  52
  53 /*
  54  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  55  */
  56 struct nvme_dev {
  57         struct nvme_queue **queues;
  58         u32 __iomem *dbs;
  59         struct pci_dev *pci_dev;
  60         int instance;
  61         int queue_count;
  62         u32 ctrl_config;
  63         struct msix_entry *entry;
  64         struct nvme_bar __iomem *bar;
  65         struct list_head namespaces;
  66         char serial[20];
  67         char model[40];
  68         char firmware_rev[8];
  69 };
  70
  71 /*
  72  * An NVM Express namespace is equivalent to a SCSI LUN
  73  */
  74 struct nvme_ns {
  75         struct list_head list;
  76
  77         struct nvme_dev *dev;
  78         struct request_queue *queue;
  79         struct gendisk *disk;
  80
  81         int ns_id;
  82         int lba_shift;
  83 };
  84
  85 /*
  86  * An NVM Express queue.  Each device has at least two (one for admin
  87  * commands and one for I/O commands).
  88  */
  89 struct nvme_queue {
  90         struct device *q_dmadev;
  91         spinlock_t q_lock;
  92         struct nvme_command *sq_cmds;
  93         volatile struct nvme_completion *cqes;
  94         dma_addr_t sq_dma_addr;
  95         dma_addr_t cq_dma_addr;
  96         wait_queue_head_t sq_full;
  97         struct bio_list sq_cong;
  98         u32 __iomem *q_db;
  99         u16 q_depth;
 100         u16 cq_vector;
 101         u16 sq_head;
 102         u16 sq_tail;
 103         u16 cq_head;
 104         u16 cq_phase;
 105         unsigned long cmdid_data[];
 106 };
 107
 108 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio);
 109
 110 /*
 111  * Check we didin't inadvertently grow the command struct
 112  */
 113 static inline void _nvme_check_size(void)
 114 {
 115         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 116         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 117         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 118         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 119         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 120         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 121         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 122         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 123         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 124 }
 125
 126 struct nvme_cmd_info {
 127         unsigned long ctx;
 128         unsigned long timeout;
 129 };
 130
 131 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 132 {
 133         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 134 }
 135
 136 /**
 137  * alloc_cmdid - Allocate a Command ID
 138  * @param nvmeq The queue that will be used for this command
 139  * @param ctx A pointer that will be passed to the handler
 140  * @param handler The ID of the handler to call
 141  *
 142  * Allocate a Command ID for a queue.  The data passed in will
 143  * be passed to the completion handler.  This is implemented by using
 144  * the bottom two bits of the ctx pointer to store the handler ID.
 145  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 146  * We can change this if it becomes a problem.
 147  */
 148 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 149                                                         unsigned timeout)
 150 {
 151         int depth = nvmeq->q_depth;
 152         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 153         int cmdid;
 154
 155         BUG_ON((unsigned long)ctx & 3);
 156
 157         do {
 158                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 159                 if (cmdid >= depth)
 160                         return -EBUSY;
 161         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 162
 163         info[cmdid].ctx = (unsigned long)ctx | handler;
 164         info[cmdid].timeout = jiffies + timeout;
 165         return cmdid;
 166 }
 167
 168 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 169                                                 int handler, unsigned timeout)
 170 {
 171         int cmdid;
 172         wait_event_killable(nvmeq->sq_full,
 173                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 174         return (cmdid < 0) ? -EINTR : cmdid;
 175 }
 176
 177 /* If you need more than four handlers, you'll need to change how
 178  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 179  * CMD_CTX value instead, if that works for your situation.
 180  */
 181 enum {
 182         sync_completion_id = 0,
 183         bio_completion_id,
 184 };
 185
 186 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 187 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 188 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 189 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 190
 191 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 192 {
 193         unsigned long data;
 194         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 195
 196         if (cmdid >= nvmeq->q_depth)
 197                 return CMD_CTX_INVALID;
 198         data = info[cmdid].ctx;
 199         info[cmdid].ctx = CMD_CTX_COMPLETED;
 200         clear_bit(cmdid, nvmeq->cmdid_data);
 201         wake_up(&nvmeq->sq_full);
 202         return data;
 203 }
 204
 205 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 206 {
 207         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 208         info[cmdid].ctx = CMD_CTX_CANCELLED;
 209 }
 210
 211 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 212 {
 213         int qid, cpu = get_cpu();
 214         if (cpu < ns->dev->queue_count)
 215                 qid = cpu + 1;
 216         else
 217                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 218         return ns->dev->queues[qid];
 219 }
 220
 221 static void put_nvmeq(struct nvme_queue *nvmeq)
 222 {
 223         put_cpu();
 224 }
 225
 226 /**
 227  * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
 228  * @nvmeq: The queue to use
 229  * @cmd: The command to send
 230  *
 231  * Safe to use from interrupt context
 232  */
 233 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 234 {
 235         unsigned long flags;
 236         u16 tail;
 237         /* XXX: Need to check tail isn't going to overrun head */
 238         spin_lock_irqsave(&nvmeq->q_lock, flags);
 239         tail = nvmeq->sq_tail;
 240         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 241         writel(tail, nvmeq->q_db);
 242         if (++tail == nvmeq->q_depth)
 243                 tail = 0;
 244         nvmeq->sq_tail = tail;
 245         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 246
 247         return 0;
 248 }
 249
 250 struct nvme_req_info {
 251         struct bio *bio;
 252         int nents;
 253         struct scatterlist sg[0];
 254 };
 255
 256 /* XXX: use a mempool */
 257 static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp)
 258 {
 259         return kmalloc(sizeof(struct nvme_req_info) +
 260                         sizeof(struct scatterlist) * nseg, gfp);
 261 }
 262
 263 static void free_info(struct nvme_req_info *info)
 264 {
 265         kfree(info);
 266 }
 267
 268 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 269                                                 struct nvme_completion *cqe)
 270 {
 271         struct nvme_req_info *info = ctx;
 272         struct bio *bio = info->bio;
 273         u16 status = le16_to_cpup(&cqe->status) >> 1;
 274
 275         dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents,
 276                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 277         free_info(info);
 278         bio_endio(bio, status ? -EIO : 0);
 279         bio = bio_list_pop(&nvmeq->sq_cong);
 280         if (bio)
 281                 nvme_resubmit_bio(nvmeq, bio);
 282 }
 283
 284 /* length is in bytes */
 285 static void nvme_setup_prps(struct nvme_common_command *cmd,
 286                                         struct scatterlist *sg, int length)
 287 {
 288         int dma_len = sg_dma_len(sg);
 289         u64 dma_addr = sg_dma_address(sg);
 290         int offset = offset_in_page(dma_addr);
 291
 292         cmd->prp1 = cpu_to_le64(dma_addr);
 293         length -= (PAGE_SIZE - offset);
 294         if (length <= 0)
 295                 return;
 296
 297         dma_len -= (PAGE_SIZE - offset);
 298         if (dma_len) {
 299                 dma_addr += (PAGE_SIZE - offset);
 300         } else {
 301                 sg = sg_next(sg);
 302                 dma_addr = sg_dma_address(sg);
 303                 dma_len = sg_dma_len(sg);
 304         }
 305
 306         if (length <= PAGE_SIZE) {
 307                 cmd->prp2 = cpu_to_le64(dma_addr);
 308                 return;
 309         }
 310
 311         /* XXX: support PRP lists */
 312 }
 313
 314 static int nvme_map_bio(struct device *dev, struct nvme_req_info *info,
 315                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 316 {
 317         struct bio_vec *bvec;
 318         struct scatterlist *sg = info->sg;
 319         int i, nsegs;
 320
 321         sg_init_table(sg, psegs);
 322         bio_for_each_segment(bvec, bio, i) {
 323                 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
 324                 sg++;
 325                 /* XXX: handle non-mergable here */
 326                 nsegs++;
 327         }
 328         info->nents = nsegs;
 329
 330         return dma_map_sg(dev, info->sg, info->nents, dma_dir);
 331 }
 332
 333 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 334                                                                 struct bio *bio)
 335 {
 336         struct nvme_command *cmnd;
 337         struct nvme_req_info *info;
 338         enum dma_data_direction dma_dir;
 339         int cmdid;
 340         u16 control;
 341         u32 dsmgmt;
 342         unsigned long flags;
 343         int psegs = bio_phys_segments(ns->queue, bio);
 344
 345         info = alloc_info(psegs, GFP_NOIO);
 346         if (!info)
 347                 goto congestion;
 348         info->bio = bio;
 349
 350         cmdid = alloc_cmdid(nvmeq, info, bio_completion_id, IO_TIMEOUT);
 351         if (unlikely(cmdid < 0))
 352                 goto free_info;
 353
 354         control = 0;
 355         if (bio->bi_rw & REQ_FUA)
 356                 control |= NVME_RW_FUA;
 357         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 358                 control |= NVME_RW_LR;
 359
 360         dsmgmt = 0;
 361         if (bio->bi_rw & REQ_RAHEAD)
 362                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 363
 364         spin_lock_irqsave(&nvmeq->q_lock, flags);
 365         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 366
 367         memset(cmnd, 0, sizeof(*cmnd));
 368         if (bio_data_dir(bio)) {
 369                 cmnd->rw.opcode = nvme_cmd_write;
 370                 dma_dir = DMA_TO_DEVICE;
 371         } else {
 372                 cmnd->rw.opcode = nvme_cmd_read;
 373                 dma_dir = DMA_FROM_DEVICE;
 374         }
 375
 376         nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs);
 377
 378         cmnd->rw.flags = 1;
 379         cmnd->rw.command_id = cmdid;
 380         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 381         nvme_setup_prps(&cmnd->common, info->sg, bio->bi_size);
 382         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 383         cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
 384         cmnd->rw.control = cpu_to_le16(control);
 385         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 386
 387         writel(nvmeq->sq_tail, nvmeq->q_db);
 388         if (++nvmeq->sq_tail == nvmeq->q_depth)
 389                 nvmeq->sq_tail = 0;
 390
 391         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 392
 393         return 0;
 394
 395  free_info:
 396         free_info(info);
 397  congestion:
 398         return -EBUSY;
 399 }
 400
 401 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio)
 402 {
 403         struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
 404         if (nvme_submit_bio_queue(nvmeq, ns, bio))
 405                 bio_list_add_head(&nvmeq->sq_cong, bio);
 406         else if (bio_list_empty(&nvmeq->sq_cong))
 407                 blk_clear_queue_congested(ns->queue, rw_is_sync(bio->bi_rw));
 408         /* XXX: Need to duplicate the logic from __freed_request here */
 409 }
 410
 411 /*
 412  * NB: return value of non-zero would mean that we were a stacking driver.
 413  * make_request must always succeed.
 414  */
 415 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 416 {
 417         struct nvme_ns *ns = q->queuedata;
 418         struct nvme_queue *nvmeq = get_nvmeq(ns);
 419
 420         if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
 421                 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
 422                 spin_lock_irq(&nvmeq->q_lock);
 423                 bio_list_add(&nvmeq->sq_cong, bio);
 424                 spin_unlock_irq(&nvmeq->q_lock);
 425         }
 426         put_nvmeq(nvmeq);
 427
 428         return 0;
 429 }
 430
 431 struct sync_cmd_info {
 432         struct task_struct *task;
 433         u32 result;
 434         int status;
 435 };
 436
 437 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 438                                                 struct nvme_completion *cqe)
 439 {
 440         struct sync_cmd_info *cmdinfo = ctx;
 441         if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
 442                 return;
 443         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 444                 dev_warn(nvmeq->q_dmadev,
 445                                 "completed id %d twice on queue %d\n",
 446                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 447                 return;
 448         }
 449         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 450                 dev_warn(nvmeq->q_dmadev,
 451                                 "invalid id %d completed on queue %d\n",
 452                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 453                 return;
 454         }
 455         cmdinfo->result = le32_to_cpup(&cqe->result);
 456         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 457         wake_up_process(cmdinfo->task);
 458 }
 459
 460 typedef void (*completion_fn)(struct nvme_queue *, void *,
 461                                                 struct nvme_completion *);
 462
 463 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 464 {
 465         u16 head, phase;
 466
 467         static const completion_fn completions[4] = {
 468                 [sync_completion_id] = sync_completion,
 469                 [bio_completion_id]  = bio_completion,
 470         };
 471
 472         head = nvmeq->cq_head;
 473         phase = nvmeq->cq_phase;
 474
 475         for (;;) {
 476                 unsigned long data;
 477                 void *ptr;
 478                 unsigned char handler;
 479                 struct nvme_completion cqe = nvmeq->cqes[head];
 480                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 481                         break;
 482                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 483                 if (++head == nvmeq->q_depth) {
 484                         head = 0;
 485                         phase = !phase;
 486                 }
 487
 488                 data = free_cmdid(nvmeq, cqe.command_id);
 489                 handler = data & 3;
 490                 ptr = (void *)(data & ~3UL);
 491                 completions[handler](nvmeq, ptr, &cqe);
 492         }
 493
 494         /* If the controller ignores the cq head doorbell and continuously
 495          * writes to the queue, it is theoretically possible to wrap around
 496          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 497          * requires that 0.1% of your interrupts are handled, so this isn't
 498          * a big problem.
 499          */
 500         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 501                 return IRQ_NONE;
 502
 503         writel(head, nvmeq->q_db + 1);
 504         nvmeq->cq_head = head;
 505         nvmeq->cq_phase = phase;
 506
 507         return IRQ_HANDLED;
 508 }
 509
 510 static irqreturn_t nvme_irq(int irq, void *data)
 511 {
 512         irqreturn_t result;
 513         struct nvme_queue *nvmeq = data;
 514         spin_lock(&nvmeq->q_lock);
 515         result = nvme_process_cq(nvmeq);
 516         spin_unlock(&nvmeq->q_lock);
 517         return result;
 518 }
 519
 520 static irqreturn_t nvme_irq_check(int irq, void *data)
 521 {
 522         struct nvme_queue *nvmeq = data;
 523         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 524         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 525                 return IRQ_NONE;
 526         return IRQ_WAKE_THREAD;
 527 }
 528
 529 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 530 {
 531         spin_lock_irq(&nvmeq->q_lock);
 532         cancel_cmdid_data(nvmeq, cmdid);
 533         spin_unlock_irq(&nvmeq->q_lock);
 534 }
 535
 536 /*
 537  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 538  * if the result is positive, it's an NVM Express status code
 539  */
 540 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 541                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 542 {
 543         int cmdid;
 544         struct sync_cmd_info cmdinfo;
 545
 546         cmdinfo.task = current;
 547         cmdinfo.status = -EINTR;
 548
 549         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 550                                                                 timeout);
 551         if (cmdid < 0)
 552                 return cmdid;
 553         cmd->common.command_id = cmdid;
 554
 555         set_current_state(TASK_KILLABLE);
 556         nvme_submit_cmd(nvmeq, cmd);
 557         schedule();
 558
 559         if (cmdinfo.status == -EINTR) {
 560                 nvme_abort_command(nvmeq, cmdid);
 561                 return -EINTR;
 562         }
 563
 564         if (result)
 565                 *result = cmdinfo.result;
 566
 567         return cmdinfo.status;
 568 }
 569
 570 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 571                                                                 u32 *result)
 572 {
 573         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 574 }
 575
 576 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 577 {
 578         int status;
 579         struct nvme_command c;
 580
 581         memset(&c, 0, sizeof(c));
 582         c.delete_queue.opcode = opcode;
 583         c.delete_queue.qid = cpu_to_le16(id);
 584
 585         status = nvme_submit_admin_cmd(dev, &c, NULL);
 586         if (status)
 587                 return -EIO;
 588         return 0;
 589 }
 590
 591 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 592                                                 struct nvme_queue *nvmeq)
 593 {
 594         int status;
 595         struct nvme_command c;
 596         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 597
 598         memset(&c, 0, sizeof(c));
 599         c.create_cq.opcode = nvme_admin_create_cq;
 600         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 601         c.create_cq.cqid = cpu_to_le16(qid);
 602         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 603         c.create_cq.cq_flags = cpu_to_le16(flags);
 604         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 605
 606         status = nvme_submit_admin_cmd(dev, &c, NULL);
 607         if (status)
 608                 return -EIO;
 609         return 0;
 610 }
 611
 612 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 613                                                 struct nvme_queue *nvmeq)
 614 {
 615         int status;
 616         struct nvme_command c;
 617         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 618
 619         memset(&c, 0, sizeof(c));
 620         c.create_sq.opcode = nvme_admin_create_sq;
 621         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 622         c.create_sq.sqid = cpu_to_le16(qid);
 623         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 624         c.create_sq.sq_flags = cpu_to_le16(flags);
 625         c.create_sq.cqid = cpu_to_le16(qid);
 626
 627         status = nvme_submit_admin_cmd(dev, &c, NULL);
 628         if (status)
 629                 return -EIO;
 630         return 0;
 631 }
 632
 633 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 634 {
 635         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 636 }
 637
 638 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 639 {
 640         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 641 }
 642
 643 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 644 {
 645         struct nvme_queue *nvmeq = dev->queues[qid];
 646
 647         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 648
 649         /* Don't tell the adapter to delete the admin queue */
 650         if (qid) {
 651                 adapter_delete_sq(dev, qid);
 652                 adapter_delete_cq(dev, qid);
 653         }
 654
 655         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 656                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 657         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 658                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 659         kfree(nvmeq);
 660 }
 661
 662 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 663                                                         int depth, int vector)
 664 {
 665         struct device *dmadev = &dev->pci_dev->dev;
 666         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 667         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 668         if (!nvmeq)
 669                 return NULL;
 670
 671         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 672                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 673         if (!nvmeq->cqes)
 674                 goto free_nvmeq;
 675         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 676
 677         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 678                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 679         if (!nvmeq->sq_cmds)
 680                 goto free_cqdma;
 681
 682         nvmeq->q_dmadev = dmadev;
 683         spin_lock_init(&nvmeq->q_lock);
 684         nvmeq->cq_head = 0;
 685         nvmeq->cq_phase = 1;
 686         init_waitqueue_head(&nvmeq->sq_full);
 687         bio_list_init(&nvmeq->sq_cong);
 688         nvmeq->q_db = &dev->dbs[qid * 2];
 689         nvmeq->q_depth = depth;
 690         nvmeq->cq_vector = vector;
 691
 692         return nvmeq;
 693
 694  free_cqdma:
 695         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 696                                                         nvmeq->cq_dma_addr);
 697  free_nvmeq:
 698         kfree(nvmeq);
 699         return NULL;
 700 }
 701
 702 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 703                                                         const char *name)
 704 {
 705         if (use_threaded_interrupts)
 706                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 707                                         nvme_irq_check, nvme_irq,
 708                                         IRQF_DISABLED | IRQF_SHARED,
 709                                         name, nvmeq);
 710         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 711                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 712 }
 713
 714 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 715                                         int qid, int cq_size, int vector)
 716 {
 717         int result;
 718         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 719
 720         if (!nvmeq)
 721                 return NULL;
 722
 723         result = adapter_alloc_cq(dev, qid, nvmeq);
 724         if (result < 0)
 725                 goto free_nvmeq;
 726
 727         result = adapter_alloc_sq(dev, qid, nvmeq);
 728         if (result < 0)
 729                 goto release_cq;
 730
 731         result = queue_request_irq(dev, nvmeq, "nvme");
 732         if (result < 0)
 733                 goto release_sq;
 734
 735         return nvmeq;
 736
 737  release_sq:
 738         adapter_delete_sq(dev, qid);
 739  release_cq:
 740         adapter_delete_cq(dev, qid);
 741  free_nvmeq:
 742         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 743                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 744         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 745                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 746         kfree(nvmeq);
 747         return NULL;
 748 }
 749
 750 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 751 {
 752         int result;
 753         u32 aqa;
 754         struct nvme_queue *nvmeq;
 755
 756         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 757
 758         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 759         if (!nvmeq)
 760                 return -ENOMEM;
 761
 762         aqa = nvmeq->q_depth - 1;
 763         aqa |= aqa << 16;
 764
 765         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 766         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 767         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 768
 769         writel(0, &dev->bar->cc);
 770         writel(aqa, &dev->bar->aqa);
 771         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 772         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 773         writel(dev->ctrl_config, &dev->bar->cc);
 774
 775         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 776                 msleep(100);
 777                 if (fatal_signal_pending(current))
 778                         return -EINTR;
 779         }
 780
 781         result = queue_request_irq(dev, nvmeq, "nvme admin");
 782         dev->queues[0] = nvmeq;
 783         return result;
 784 }
 785
 786 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 787                                 unsigned long addr, unsigned length,
 788                                 struct scatterlist **sgp)
 789 {
 790         int i, err, count, nents, offset;
 791         struct scatterlist *sg;
 792         struct page **pages;
 793
 794         if (addr & 3)
 795                 return -EINVAL;
 796         if (!length)
 797                 return -EINVAL;
 798
 799         offset = offset_in_page(addr);
 800         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 801         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 802
 803         err = get_user_pages_fast(addr, count, 1, pages);
 804         if (err < count) {
 805                 count = err;
 806                 err = -EFAULT;
 807                 goto put_pages;
 808         }
 809
 810         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 811         sg_init_table(sg, count);
 812         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 813         length -= (PAGE_SIZE - offset);
 814         for (i = 1; i < count; i++) {
 815                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 816                 length -= PAGE_SIZE;
 817         }
 818
 819         err = -ENOMEM;
 820         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 821                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 822         if (!nents)
 823                 goto put_pages;
 824
 825         kfree(pages);
 826         *sgp = sg;
 827         return nents;
 828
 829  put_pages:
 830         for (i = 0; i < count; i++)
 831                 put_page(pages[i]);
 832         kfree(pages);
 833         return err;
 834 }
 835
 836 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 837                                 unsigned long addr, int length,
 838                                 struct scatterlist *sg, int nents)
 839 {
 840         int i, count;
 841
 842         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 843         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 844
 845         for (i = 0; i < count; i++)
 846                 put_page(sg_page(&sg[i]));
 847 }
 848
 849 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 850                                         unsigned long addr, unsigned length,
 851                                         struct nvme_command *cmd)
 852 {
 853         int err, nents;
 854         struct scatterlist *sg;
 855
 856         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
 857         if (nents < 0)
 858                 return nents;
 859         nvme_setup_prps(&cmd->common, sg, length);
 860         err = nvme_submit_admin_cmd(dev, cmd, NULL);
 861         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
 862         return err ? -EIO : 0;
 863 }
 864
 865 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
 866 {
 867         struct nvme_command c;
 868
 869         memset(&c, 0, sizeof(c));
 870         c.identify.opcode = nvme_admin_identify;
 871         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
 872         c.identify.cns = cpu_to_le32(cns);
 873
 874         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 875 }
 876
 877 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
 878 {
 879         struct nvme_command c;
 880
 881         memset(&c, 0, sizeof(c));
 882         c.features.opcode = nvme_admin_get_features;
 883         c.features.nsid = cpu_to_le32(ns->ns_id);
 884         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
 885
 886         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 887 }
 888
 889 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
 890 {
 891         struct nvme_dev *dev = ns->dev;
 892         struct nvme_queue *nvmeq;
 893         struct nvme_user_io io;
 894         struct nvme_command c;
 895         unsigned length;
 896         u32 result;
 897         int nents, status;
 898         struct scatterlist *sg;
 899
 900         if (copy_from_user(&io, uio, sizeof(io)))
 901                 return -EFAULT;
 902         length = io.nblocks << io.block_shift;
 903         nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
 904         if (nents < 0)
 905                 return nents;
 906
 907         memset(&c, 0, sizeof(c));
 908         c.rw.opcode = io.opcode;
 909         c.rw.flags = io.flags;
 910         c.rw.nsid = cpu_to_le32(io.nsid);
 911         c.rw.slba = cpu_to_le64(io.slba);
 912         c.rw.length = cpu_to_le16(io.nblocks - 1);
 913         c.rw.control = cpu_to_le16(io.control);
 914         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
 915         c.rw.reftag = cpu_to_le32(io.reftag);   /* XXX: endian? */
 916         c.rw.apptag = cpu_to_le16(io.apptag);
 917         c.rw.appmask = cpu_to_le16(io.appmask);
 918         /* XXX: metadata */
 919         nvme_setup_prps(&c.common, sg, length);
 920
 921         nvmeq = get_nvmeq(ns);
 922         /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
 923          * disabled.  We may be preempted at any point, and be rescheduled
 924          * to a different CPU.  That will cause cacheline bouncing, but no
 925          * additional races since q_lock already protects against other CPUs.
 926          */
 927         put_nvmeq(nvmeq);
 928         status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
 929
 930         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
 931         put_user(result, &uio->result);
 932         return status;
 933 }
 934
 935 static int nvme_download_firmware(struct nvme_ns *ns,
 936                                                 struct nvme_dlfw __user *udlfw)
 937 {
 938         struct nvme_dev *dev = ns->dev;
 939         struct nvme_dlfw dlfw;
 940         struct nvme_command c;
 941         int nents, status;
 942         struct scatterlist *sg;
 943
 944         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
 945                 return -EFAULT;
 946         if (dlfw.length >= (1 << 30))
 947                 return -EINVAL;
 948
 949         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
 950         if (nents < 0)
 951                 return nents;
 952
 953         memset(&c, 0, sizeof(c));
 954         c.dlfw.opcode = nvme_admin_download_fw;
 955         c.dlfw.numd = cpu_to_le32(dlfw.length);
 956         c.dlfw.offset = cpu_to_le32(dlfw.offset);
 957         nvme_setup_prps(&c.common, sg, dlfw.length * 4);
 958
 959         status = nvme_submit_admin_cmd(dev, &c, NULL);
 960         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
 961         return status;
 962 }
 963
 964 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
 965 {
 966         struct nvme_dev *dev = ns->dev;
 967         struct nvme_command c;
 968
 969         memset(&c, 0, sizeof(c));
 970         c.common.opcode = nvme_admin_activate_fw;
 971         c.common.rsvd10[0] = cpu_to_le32(arg);
 972
 973         return nvme_submit_admin_cmd(dev, &c, NULL);
 974 }
 975
 976 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
 977                                                         unsigned long arg)
 978 {
 979         struct nvme_ns *ns = bdev->bd_disk->private_data;
 980
 981         switch (cmd) {
 982         case NVME_IOCTL_IDENTIFY_NS:
 983                 return nvme_identify(ns, arg, 0);
 984         case NVME_IOCTL_IDENTIFY_CTRL:
 985                 return nvme_identify(ns, arg, 1);
 986         case NVME_IOCTL_GET_RANGE_TYPE:
 987                 return nvme_get_range_type(ns, arg);
 988         case NVME_IOCTL_SUBMIT_IO:
 989                 return nvme_submit_io(ns, (void __user *)arg);
 990         case NVME_IOCTL_DOWNLOAD_FW:
 991                 return nvme_download_firmware(ns, (void __user *)arg);
 992         case NVME_IOCTL_ACTIVATE_FW:
 993                 return nvme_activate_firmware(ns, arg);
 994         default:
 995                 return -ENOTTY;
 996         }
 997 }
 998
 999 static const struct block_device_operations nvme_fops = {
1000         .owner          = THIS_MODULE,
1001         .ioctl          = nvme_ioctl,
1002 };
1003
1004 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1005                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1006 {
1007         struct nvme_ns *ns;
1008         struct gendisk *disk;
1009         int lbaf;
1010
1011         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1012                 return NULL;
1013
1014         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1015         if (!ns)
1016                 return NULL;
1017         ns->queue = blk_alloc_queue(GFP_KERNEL);
1018         if (!ns->queue)
1019                 goto out_free_ns;
1020         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1021                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1022         blk_queue_make_request(ns->queue, nvme_make_request);
1023         ns->dev = dev;
1024         ns->queue->queuedata = ns;
1025
1026         disk = alloc_disk(NVME_MINORS);
1027         if (!disk)
1028                 goto out_free_queue;
1029         ns->ns_id = index;
1030         ns->disk = disk;
1031         lbaf = id->flbas & 0xf;
1032         ns->lba_shift = id->lbaf[lbaf].ds;
1033
1034         disk->major = nvme_major;
1035         disk->minors = NVME_MINORS;
1036         disk->first_minor = NVME_MINORS * index;
1037         disk->fops = &nvme_fops;
1038         disk->private_data = ns;
1039         disk->queue = ns->queue;
1040         disk->driverfs_dev = &dev->pci_dev->dev;
1041         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1042         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1043
1044         return ns;
1045
1046  out_free_queue:
1047         blk_cleanup_queue(ns->queue);
1048  out_free_ns:
1049         kfree(ns);
1050         return NULL;
1051 }
1052
1053 static void nvme_ns_free(struct nvme_ns *ns)
1054 {
1055         put_disk(ns->disk);
1056         blk_cleanup_queue(ns->queue);
1057         kfree(ns);
1058 }
1059
1060 static int set_queue_count(struct nvme_dev *dev, int count)
1061 {
1062         int status;
1063         u32 result;
1064         struct nvme_command c;
1065         u32 q_count = (count - 1) | ((count - 1) << 16);
1066
1067         memset(&c, 0, sizeof(c));
1068         c.features.opcode = nvme_admin_get_features;
1069         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1070         c.features.dword11 = cpu_to_le32(q_count);
1071
1072         status = nvme_submit_admin_cmd(dev, &c, &result);
1073         if (status)
1074                 return -EIO;
1075         return min(result & 0xffff, result >> 16) + 1;
1076 }
1077
1078 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1079 {
1080         int result, cpu, i, nr_queues;
1081
1082         nr_queues = num_online_cpus();
1083         result = set_queue_count(dev, nr_queues);
1084         if (result < 0)
1085                 return result;
1086         if (result < nr_queues)
1087                 nr_queues = result;
1088
1089         /* Deregister the admin queue's interrupt */
1090         free_irq(dev->entry[0].vector, dev->queues[0]);
1091
1092         for (i = 0; i < nr_queues; i++)
1093                 dev->entry[i].entry = i;
1094         for (;;) {
1095                 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1096                 if (result == 0) {
1097                         break;
1098                 } else if (result > 0) {
1099                         nr_queues = result;
1100                         continue;
1101                 } else {
1102                         nr_queues = 1;
1103                         break;
1104                 }
1105         }
1106
1107         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1108         /* XXX: handle failure here */
1109
1110         cpu = cpumask_first(cpu_online_mask);
1111         for (i = 0; i < nr_queues; i++) {
1112                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1113                 cpu = cpumask_next(cpu, cpu_online_mask);
1114         }
1115
1116         for (i = 0; i < nr_queues; i++) {
1117                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1118                                                         NVME_Q_DEPTH, i);
1119                 if (!dev->queues[i + 1])
1120                         return -ENOMEM;
1121                 dev->queue_count++;
1122         }
1123
1124         return 0;
1125 }
1126
1127 static void nvme_free_queues(struct nvme_dev *dev)
1128 {
1129         int i;
1130
1131         for (i = dev->queue_count - 1; i >= 0; i--)
1132                 nvme_free_queue(dev, i);
1133 }
1134
1135 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1136 {
1137         int res, nn, i;
1138         struct nvme_ns *ns, *next;
1139         struct nvme_id_ctrl *ctrl;
1140         void *id;
1141         dma_addr_t dma_addr;
1142         struct nvme_command cid, crt;
1143
1144         res = nvme_setup_io_queues(dev);
1145         if (res)
1146                 return res;
1147
1148         /* XXX: Switch to a SG list once prp2 works */
1149         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1150                                                                 GFP_KERNEL);
1151
1152         memset(&cid, 0, sizeof(cid));
1153         cid.identify.opcode = nvme_admin_identify;
1154         cid.identify.nsid = 0;
1155         cid.identify.prp1 = cpu_to_le64(dma_addr);
1156         cid.identify.cns = cpu_to_le32(1);
1157
1158         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1159         if (res) {
1160                 res = -EIO;
1161                 goto out_free;
1162         }
1163
1164         ctrl = id;
1165         nn = le32_to_cpup(&ctrl->nn);
1166         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1167         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1168         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1169
1170         cid.identify.cns = 0;
1171         memset(&crt, 0, sizeof(crt));
1172         crt.features.opcode = nvme_admin_get_features;
1173         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1174         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1175
1176         for (i = 0; i < nn; i++) {
1177                 cid.identify.nsid = cpu_to_le32(i);
1178                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1179                 if (res)
1180                         continue;
1181
1182                 if (((struct nvme_id_ns *)id)->ncap == 0)
1183                         continue;
1184
1185                 crt.features.nsid = cpu_to_le32(i);
1186                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1187                 if (res)
1188                         continue;
1189
1190                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1191                 if (ns)
1192                         list_add_tail(&ns->list, &dev->namespaces);
1193         }
1194         list_for_each_entry(ns, &dev->namespaces, list)
1195                 add_disk(ns->disk);
1196
1197         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1198         return 0;
1199
1200  out_free:
1201         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1202                 list_del(&ns->list);
1203                 nvme_ns_free(ns);
1204         }
1205
1206         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1207         return res;
1208 }
1209
1210 static int nvme_dev_remove(struct nvme_dev *dev)
1211 {
1212         struct nvme_ns *ns, *next;
1213
1214         /* TODO: wait all I/O finished or cancel them */
1215
1216         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1217                 list_del(&ns->list);
1218                 del_gendisk(ns->disk);
1219                 nvme_ns_free(ns);
1220         }
1221
1222         nvme_free_queues(dev);
1223
1224         return 0;
1225 }
1226
1227 /* XXX: Use an ida or something to let remove / add work correctly */
1228 static void nvme_set_instance(struct nvme_dev *dev)
1229 {
1230         static int instance;
1231         dev->instance = instance++;
1232 }
1233
1234 static void nvme_release_instance(struct nvme_dev *dev)
1235 {
1236 }
1237
1238 static int __devinit nvme_probe(struct pci_dev *pdev,
1239                                                 const struct pci_device_id *id)
1240 {
1241         int bars, result = -ENOMEM;
1242         struct nvme_dev *dev;
1243
1244         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1245         if (!dev)
1246                 return -ENOMEM;
1247         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1248                                                                 GFP_KERNEL);
1249         if (!dev->entry)
1250                 goto free;
1251         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1252                                                                 GFP_KERNEL);
1253         if (!dev->queues)
1254                 goto free;
1255
1256         if (pci_enable_device_mem(pdev))
1257                 goto free;
1258         pci_set_master(pdev);
1259         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1260         if (pci_request_selected_regions(pdev, bars, "nvme"))
1261                 goto disable;
1262
1263         INIT_LIST_HEAD(&dev->namespaces);
1264         dev->pci_dev = pdev;
1265         pci_set_drvdata(pdev, dev);
1266         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1267         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1268         nvme_set_instance(dev);
1269         dev->entry[0].vector = pdev->irq;
1270
1271         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1272         if (!dev->bar) {
1273                 result = -ENOMEM;
1274                 goto disable_msix;
1275         }
1276
1277         result = nvme_configure_admin_queue(dev);
1278         if (result)
1279                 goto unmap;
1280         dev->queue_count++;
1281
1282         result = nvme_dev_add(dev);
1283         if (result)
1284                 goto delete;
1285         return 0;
1286
1287  delete:
1288         nvme_free_queues(dev);
1289  unmap:
1290         iounmap(dev->bar);
1291  disable_msix:
1292         pci_disable_msix(pdev);
1293         nvme_release_instance(dev);
1294  disable:
1295         pci_disable_device(pdev);
1296         pci_release_regions(pdev);
1297  free:
1298         kfree(dev->queues);
1299         kfree(dev->entry);
1300         kfree(dev);
1301         return result;
1302 }
1303
1304 static void __devexit nvme_remove(struct pci_dev *pdev)
1305 {
1306         struct nvme_dev *dev = pci_get_drvdata(pdev);
1307         nvme_dev_remove(dev);
1308         pci_disable_msix(pdev);
1309         iounmap(dev->bar);
1310         nvme_release_instance(dev);
1311         pci_disable_device(pdev);
1312         pci_release_regions(pdev);
1313         kfree(dev->queues);
1314         kfree(dev->entry);
1315         kfree(dev);
1316 }
1317
1318 /* These functions are yet to be implemented */
1319 #define nvme_error_detected NULL
1320 #define nvme_dump_registers NULL
1321 #define nvme_link_reset NULL
1322 #define nvme_slot_reset NULL
1323 #define nvme_error_resume NULL
1324 #define nvme_suspend NULL
1325 #define nvme_resume NULL
1326
1327 static struct pci_error_handlers nvme_err_handler = {
1328         .error_detected = nvme_error_detected,
1329         .mmio_enabled   = nvme_dump_registers,
1330         .link_reset     = nvme_link_reset,
1331         .slot_reset     = nvme_slot_reset,
1332         .resume         = nvme_error_resume,
1333 };
1334
1335 /* Move to pci_ids.h later */
1336 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1337
1338 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1339         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1340         { 0, }
1341 };
1342 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1343
1344 static struct pci_driver nvme_driver = {
1345         .name           = "nvme",
1346         .id_table       = nvme_id_table,
1347         .probe          = nvme_probe,
1348         .remove         = __devexit_p(nvme_remove),
1349         .suspend        = nvme_suspend,
1350         .resume         = nvme_resume,
1351         .err_handler    = &nvme_err_handler,
1352 };
1353
1354 static int __init nvme_init(void)
1355 {
1356         int result;
1357
1358         nvme_major = register_blkdev(nvme_major, "nvme");
1359         if (nvme_major <= 0)
1360                 return -EBUSY;
1361
1362         result = pci_register_driver(&nvme_driver);
1363         if (!result)
1364                 return 0;
1365
1366         unregister_blkdev(nvme_major, "nvme");
1367         return result;
1368 }
1369
1370 static void __exit nvme_exit(void)
1371 {
1372         pci_unregister_driver(&nvme_driver);
1373         unregister_blkdev(nvme_major, "nvme");
1374 }
1375
1376 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1377 MODULE_LICENSE("GPL");
1378 MODULE_VERSION("0.2");
1379 module_init(nvme_init);
1380 module_exit(nvme_exit);